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gpu: nvgpu: add support for t19x tsg/channel
Required modifications to add t19x channel specific info and handle t19x tsg requests. Bug 1842197 Change-Id: I0f8bcce20edea8f2f9a01e5bf5a9e4181af54875 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master/r/1511144 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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@@ -30,6 +30,9 @@
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#include "ioctl_tsg.h"
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#include "ioctl_channel.h"
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#include "os_linux.h"
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#ifdef CONFIG_TEGRA_19x_GPU
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#include "tsg_t19x.h"
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#endif
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struct tsg_private {
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struct gk20a *g;
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@@ -469,9 +472,13 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
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}
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default:
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#ifdef CONFIG_TEGRA_19x_GPU
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err = t19x_tsg_ioctl_handler(g, tsg, cmd, buf);
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#else
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nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x",
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cmd);
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err = -ENOTTY;
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#endif
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break;
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}
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@@ -858,6 +858,10 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
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ch->obj_class = 0;
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ch->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW;
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ch->timeslice_us = g->timeslice_low_priority_us;
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#ifdef CONFIG_TEGRA_19x_GPU
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memset(&ch->t19x, 0, sizeof(struct channel_t19x));
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#endif
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/* The channel is *not* runnable at this point. It still needs to have
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* an address space bound and allocate a gpfifo and grctx. */
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@@ -36,6 +36,9 @@ struct fifo_profile_gk20a;
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#include "mm_gk20a.h"
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#include "gr_gk20a.h"
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#include "fence_gk20a.h"
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#ifdef CONFIG_TEGRA_19x_GPU
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#include "channel_t19x.h"
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#endif
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struct notification {
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struct {
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@@ -276,6 +279,9 @@ struct channel_gk20a {
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u32 runlist_id;
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bool is_privileged_channel;
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#ifdef CONFIG_TEGRA_19x_GPU
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struct channel_t19x t19x;
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#endif
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};
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static inline struct channel_gk20a *
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@@ -970,11 +970,18 @@ struct nvgpu_gpu_set_event_filter_args {
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#define NVGPU_IOCTL_TSG_GET_TIMESLICE \
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_IOR(NVGPU_TSG_IOCTL_MAGIC, 10, struct nvgpu_timeslice_args)
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#ifdef CONFIG_TEGRA_19x_GPU
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#define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \
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NVGPU_TSG_IOCTL_MAX_ARG
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#define NVGPU_TSG_IOCTL_LAST \
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_IOC_NR(NVGPU_TSG_IOCTL_MAX)
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#else
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#define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \
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sizeof(struct nvgpu_event_id_ctrl_args)
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#define NVGPU_TSG_IOCTL_LAST \
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_IOC_NR(NVGPU_IOCTL_TSG_GET_TIMESLICE)
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#endif
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/*
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* /dev/nvhost-dbg-gpu device
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