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gpu: nvgpu: Remove GP10b support
Starting 6.0.2.0, deprecate support for GP10b. Delete GP10b specific things such as platform data, ucodes, regops allowlist, cg/pg register list. Per unit specific gp10b code cleanup will be done later. Bug 3431142 Change-Id: I4d5fd9ad8c6ee53845df3b6b2298af64d76e86c3 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2630946 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
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commit
3b1bbc7259
@@ -75,8 +75,6 @@ init:
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owner: Philip E
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owner: Philip E
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sources: [ hal/init/hal_gm20b.c,
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sources: [ hal/init/hal_gm20b.c,
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hal/init/hal_gm20b.h,
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hal/init/hal_gm20b.h,
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hal/init/hal_gp10b.c,
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hal/init/hal_gp10b.h,
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hal/init/hal_tu104.c,
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hal/init/hal_tu104.c,
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hal/init/hal_tu104.h,
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hal/init/hal_tu104.h,
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hal/init/hal_ga100.c,
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hal/init/hal_ga100.c,
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@@ -89,8 +87,6 @@ init:
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hal/init/hal_ga10b_litter.h,
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hal/init/hal_ga10b_litter.h,
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hal/init/hal_gm20b_litter.c,
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hal/init/hal_gm20b_litter.c,
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hal/init/hal_gm20b_litter.h,
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hal/init/hal_gm20b_litter.h,
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hal/init/hal_gp10b_litter.c,
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hal/init/hal_gp10b_litter.h,
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hal/init/hal_tu104_litter.c,
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hal/init/hal_tu104_litter.c,
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hal/init/hal_tu104_litter.h ]
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hal/init/hal_tu104_litter.h ]
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@@ -142,8 +138,6 @@ cg:
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owner: Seema K
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owner: Seema K
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sources: [ hal/power_features/cg/gm20b_gating_reglist.c,
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sources: [ hal/power_features/cg/gm20b_gating_reglist.c,
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hal/power_features/cg/gm20b_gating_reglist.h,
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hal/power_features/cg/gm20b_gating_reglist.h,
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hal/power_features/cg/gp10b_gating_reglist.c,
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hal/power_features/cg/gp10b_gating_reglist.h,
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hal/power_features/cg/tu104_gating_reglist.c,
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hal/power_features/cg/tu104_gating_reglist.c,
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hal/power_features/cg/tu104_gating_reglist.h,
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hal/power_features/cg/tu104_gating_reglist.h,
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hal/power_features/cg/ga10b_gating_reglist.c,
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hal/power_features/cg/ga10b_gating_reglist.c,
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@@ -748,8 +742,6 @@ regops:
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owner: Deepak N
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owner: Deepak N
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sources: [ hal/regops/regops_gm20b.c,
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sources: [ hal/regops/regops_gm20b.c,
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hal/regops/regops_gm20b.h,
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hal/regops/regops_gm20b.h,
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hal/regops/regops_gp10b.c,
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hal/regops/regops_gp10b.h,
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hal/regops/regops_gv11b.c,
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hal/regops/regops_gv11b.c,
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hal/regops/regops_gv11b.h,
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hal/regops/regops_gv11b.h,
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hal/regops/regops_tu104.c,
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hal/regops/regops_tu104.c,
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@@ -364,7 +364,6 @@ nvgpu-y += \
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hal/init/hal_init.o \
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hal/init/hal_init.o \
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hal/perf/perf_gv11b.o \
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hal/perf/perf_gv11b.o \
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hal/perf/perf_tu104.o \
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hal/perf/perf_tu104.o \
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hal/power_features/cg/gp10b_gating_reglist.o \
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hal/power_features/cg/gv11b_gating_reglist.o \
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hal/power_features/cg/gv11b_gating_reglist.o \
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hal/regops/regops_gv11b.o \
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hal/regops/regops_gv11b.o \
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hal/regops/allowlist_gv11b.o \
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hal/regops/allowlist_gv11b.o \
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@@ -782,8 +781,6 @@ nvgpu-y += \
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nvgpu-$(CONFIG_NVGPU_HAL_NON_FUSA) += \
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nvgpu-$(CONFIG_NVGPU_HAL_NON_FUSA) += \
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hal/ce/ce_tu104.o \
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hal/ce/ce_tu104.o \
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hal/clk/clk_gm20b.o \
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hal/clk/clk_gm20b.o \
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hal/init/hal_gp10b.o \
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hal/init/hal_gp10b_litter.o \
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hal/init/hal_gm20b.o \
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hal/init/hal_gm20b.o \
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hal/init/hal_gm20b_litter.o \
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hal/init/hal_gm20b_litter.o \
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hal/fifo/engine_status_gm20b.o \
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hal/fifo/engine_status_gm20b.o \
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@@ -815,7 +812,6 @@ nvgpu-$(CONFIG_NVGPU_HAL_NON_FUSA) += \
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hal/power_features/cg/gm20b_gating_reglist.o \
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hal/power_features/cg/gm20b_gating_reglist.o \
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hal/priv_ring/priv_ring_gm20b.o \
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hal/priv_ring/priv_ring_gm20b.o \
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hal/regops/regops_gm20b.o \
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hal/regops/regops_gm20b.o \
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hal/regops/regops_gp10b.o \
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hal/regops/regops_tu104.o \
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hal/regops/regops_tu104.o \
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hal/regops/allowlist_tu104.o \
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hal/regops/allowlist_tu104.o \
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hal/therm/therm_gm20b.o \
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hal/therm/therm_gm20b.o \
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@@ -280,9 +280,7 @@ srcs += hal/mm/mm_gv11b_fusa.c \
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# Source files below are not guaranteed to be functionaly safe (FuSa) and are
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# Source files below are not guaranteed to be functionaly safe (FuSa) and are
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# only included in the normal build.
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# only included in the normal build.
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ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
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ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
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srcs += hal/init/hal_gp10b.c \
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srcs += hal/init/hal_gm20b.c \
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hal/init/hal_gp10b_litter.c \
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hal/init/hal_gm20b.c \
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hal/init/hal_gm20b_litter.c \
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hal/init/hal_gm20b_litter.c \
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hal/mm/cache/flush_gk20a.c \
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hal/mm/cache/flush_gk20a.c \
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hal/mm/mm_gm20b.c \
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hal/mm/mm_gm20b.c \
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@@ -306,7 +304,6 @@ srcs += hal/init/hal_gp10b.c \
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hal/gr/falcon/gr_falcon_gm20b.c \
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hal/gr/falcon/gr_falcon_gm20b.c \
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hal/priv_ring/priv_ring_gm20b.c \
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hal/priv_ring/priv_ring_gm20b.c \
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hal/power_features/cg/gm20b_gating_reglist.c \
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hal/power_features/cg/gm20b_gating_reglist.c \
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hal/power_features/cg/gp10b_gating_reglist.c \
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hal/ce/ce2_gk20a.c \
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hal/ce/ce2_gk20a.c \
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hal/therm/therm_gm20b.c \
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hal/therm/therm_gm20b.c \
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hal/therm/therm_gp10b.c \
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hal/therm/therm_gp10b.c \
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@@ -416,7 +413,6 @@ srcs += common/debugger.c \
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hal/gr/gr/gr_tu104.c
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hal/gr/gr/gr_tu104.c
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ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
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ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
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srcs += hal/regops/regops_gm20b.c \
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srcs += hal/regops/regops_gm20b.c \
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hal/regops/regops_gp10b.c \
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hal/regops/regops_tu104.c \
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hal/regops/regops_tu104.c \
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hal/regops/regops_ga10b.c \
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hal/regops/regops_ga10b.c \
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hal/regops/allowlist_tu104.c \
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hal/regops/allowlist_tu104.c \
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File diff suppressed because it is too large
Load Diff
@@ -1,30 +0,0 @@
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/*
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* GP10B Tegra HAL interface
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_HAL_GP10B_H
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#define NVGPU_HAL_GP10B_H
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struct gk20a;
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int gp10b_init_hal(struct gk20a *g);
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#endif /* NVGPU_HAL_GP10B_H */
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@@ -1,153 +0,0 @@
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/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/class.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
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#include "hal_gp10b_litter.h"
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u32 gp10b_get_litter_value(struct gk20a *g, int value)
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{
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u32 ret = 0;
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switch (value) {
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case GPU_LIT_NUM_GPCS:
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ret = proj_scal_litter_num_gpcs_v();
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break;
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case GPU_LIT_NUM_PES_PER_GPC:
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ret = proj_scal_litter_num_pes_per_gpc_v();
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break;
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case GPU_LIT_NUM_ZCULL_BANKS:
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ret = proj_scal_litter_num_zcull_banks_v();
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break;
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case GPU_LIT_NUM_TPC_PER_GPC:
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ret = proj_scal_litter_num_tpc_per_gpc_v();
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break;
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case GPU_LIT_NUM_SM_PER_TPC:
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ret = proj_scal_litter_num_sm_per_tpc_v();
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break;
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case GPU_LIT_NUM_FBPS:
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ret = proj_scal_litter_num_fbps_v();
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break;
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case GPU_LIT_GPC_BASE:
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ret = proj_gpc_base_v();
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break;
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case GPU_LIT_GPC_STRIDE:
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ret = proj_gpc_stride_v();
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break;
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case GPU_LIT_GPC_SHARED_BASE:
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ret = proj_gpc_shared_base_v();
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break;
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case GPU_LIT_GPC_ADDR_WIDTH:
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ret = 15U; /* refer *_PGRAPH_Memory_Map.xlsx */
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break;
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case GPU_LIT_TPC_ADDR_WIDTH:
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ret = 11U; /* refer *_PGRAPH_Memory_Map.xlsx */
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break;
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case GPU_LIT_TPC_IN_GPC_BASE:
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ret = proj_tpc_in_gpc_base_v();
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break;
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case GPU_LIT_TPC_IN_GPC_STRIDE:
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ret = proj_tpc_in_gpc_stride_v();
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break;
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case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
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ret = proj_tpc_in_gpc_shared_base_v();
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break;
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case GPU_LIT_PPC_IN_GPC_BASE:
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ret = proj_ppc_in_gpc_base_v();
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break;
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case GPU_LIT_PPC_IN_GPC_STRIDE:
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ret = proj_ppc_in_gpc_stride_v();
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break;
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case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
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ret = proj_ppc_in_gpc_shared_base_v();
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break;
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case GPU_LIT_ROP_BASE:
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ret = proj_rop_base_v();
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break;
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case GPU_LIT_ROP_STRIDE:
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ret = proj_rop_stride_v();
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break;
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case GPU_LIT_ROP_SHARED_BASE:
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ret = proj_rop_shared_base_v();
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break;
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case GPU_LIT_HOST_NUM_ENGINES:
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ret = proj_host_num_engines_v();
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break;
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case GPU_LIT_HOST_NUM_PBDMA:
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ret = proj_host_num_pbdma_v();
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break;
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case GPU_LIT_LTC_STRIDE:
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ret = proj_ltc_stride_v();
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break;
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case GPU_LIT_LTS_STRIDE:
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ret = proj_lts_stride_v();
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break;
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/* Even though GP10B doesn't have an FBPA unit, the HW reports one,
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* and the microcode as a result leaves space in the context buffer
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* for one, so make sure SW accounts for this also.
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*/
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case GPU_LIT_NUM_FBPAS:
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ret = proj_scal_litter_num_fbpas_v();
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break;
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/* Hardcode FBPA values other than NUM_FBPAS to 0. */
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case GPU_LIT_FBPA_STRIDE:
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case GPU_LIT_FBPA_BASE:
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case GPU_LIT_FBPA_SHARED_BASE:
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ret = 0;
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break;
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#ifdef CONFIG_NVGPU_GRAPHICS
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case GPU_LIT_TWOD_CLASS:
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ret = FERMI_TWOD_A;
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break;
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case GPU_LIT_THREED_CLASS:
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ret = PASCAL_A;
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break;
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#endif
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#ifdef CONFIG_NVGPU_NON_FUSA
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case GPU_LIT_COMPUTE_CLASS:
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ret = PASCAL_COMPUTE_A;
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break;
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#endif
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case GPU_LIT_GPFIFO_CLASS:
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ret = PASCAL_CHANNEL_GPFIFO_A;
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break;
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case GPU_LIT_I2M_CLASS:
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ret = KEPLER_INLINE_TO_MEMORY_B;
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break;
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case GPU_LIT_DMA_COPY_CLASS:
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ret = PASCAL_DMA_COPY_A;
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break;
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case GPU_LIT_GPC_PRIV_STRIDE:
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ret = proj_gpc_priv_stride_v();
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break;
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default:
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nvgpu_err(g, "Missing definition %d", value);
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BUG();
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break;
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}
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return ret;
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}
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@@ -1,28 +0,0 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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|
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* copy of this software and associated documentation files (the "Software"),
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|
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
|
|
||||||
* The above copyright notice and this permission notice shall be included in
|
|
||||||
* all copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
||||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
||||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
||||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
||||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
||||||
* DEALINGS IN THE SOFTWARE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef NVGPU_HAL_GP10B_LITTER_H
|
|
||||||
#define NVGPU_HAL_GP10B_LITTER_H
|
|
||||||
|
|
||||||
u32 gp10b_get_litter_value(struct gk20a *g, int value);
|
|
||||||
|
|
||||||
#endif /* NVGPU_HAL_GP10B_LITTER_H */
|
|
||||||
@@ -30,7 +30,6 @@
|
|||||||
#include <nvgpu/static_analysis.h>
|
#include <nvgpu/static_analysis.h>
|
||||||
|
|
||||||
#include "hal_gm20b.h"
|
#include "hal_gm20b.h"
|
||||||
#include "hal_gp10b.h"
|
|
||||||
#include "hal_gv11b.h"
|
#include "hal_gv11b.h"
|
||||||
#include "hal_ga10b.h"
|
#include "hal_ga10b.h"
|
||||||
#ifdef CONFIG_NVGPU_DGPU
|
#ifdef CONFIG_NVGPU_DGPU
|
||||||
@@ -63,11 +62,6 @@ int nvgpu_init_hal(struct gk20a *g)
|
|||||||
err = -ENODEV;
|
err = -ENODEV;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case NVGPU_GPUID_GP10B:
|
|
||||||
if (gp10b_init_hal(g) != 0) {
|
|
||||||
err = -ENODEV;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
#endif
|
#endif
|
||||||
case NVGPU_GPUID_GA10B:
|
case NVGPU_GPUID_GA10B:
|
||||||
if (ga10b_init_hal(g) != 0) {
|
if (ga10b_init_hal(g) != 0) {
|
||||||
|
|||||||
@@ -1,800 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
|
|
||||||
*
|
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
||||||
* copy of this software and associated documentation files (the "Software"),
|
|
||||||
* to deal in the Software without restriction, including without limitation
|
|
||||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
||||||
* and/or sell copies of the Software, and to permit persons to whom the
|
|
||||||
* Software is furnished to do so, subject to the following conditions:
|
|
||||||
*
|
|
||||||
* The above copyright notice and this permission notice shall be included in
|
|
||||||
* all copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
||||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
||||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
||||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
||||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
||||||
* DEALINGS IN THE SOFTWARE.
|
|
||||||
*
|
|
||||||
* This file is autogenerated. Do not edit.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <nvgpu/types.h>
|
|
||||||
#include <nvgpu/io.h>
|
|
||||||
#include <nvgpu/enabled.h>
|
|
||||||
#include <nvgpu/utils.h>
|
|
||||||
#include <nvgpu/static_analysis.h>
|
|
||||||
|
|
||||||
#include "gating_reglist.h"
|
|
||||||
#include "gp10b_gating_reglist.h"
|
|
||||||
|
|
||||||
#define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc))
|
|
||||||
|
|
||||||
/* slcg bus */
|
|
||||||
static const struct gating_desc gp10b_slcg_bus[] = {
|
|
||||||
{.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* slcg ce2 */
|
|
||||||
static const struct gating_desc gp10b_slcg_ce2[] = {
|
|
||||||
{.addr = 0x00104204U, .prod = 0x00000040U, .disable = 0x000007feU},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* slcg chiplet */
|
|
||||||
static const struct gating_desc gp10b_slcg_chiplet[] = {
|
|
||||||
{.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U},
|
|
||||||
{.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U},
|
|
||||||
{.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U},
|
|
||||||
{.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* slcg fb */
|
|
||||||
static const struct gating_desc gp10b_slcg_fb[] = {
|
|
||||||
{.addr = 0x00100d14U, .prod = 0x00000000U, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* slcg fifo */
|
|
||||||
static const struct gating_desc gp10b_slcg_fifo[] = {
|
|
||||||
{.addr = 0x000026acU, .prod = 0x00000f40U, .disable = 0x0001fffeU},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* slcg gr */
|
|
||||||
static const struct gating_desc gp10b_slcg_gr[] = {
|
|
||||||
{.addr = 0x004041f4U, .prod = 0x00000002U, .disable = 0x03fffffeU},
|
|
||||||
{.addr = 0x0040917cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
|
|
||||||
{.addr = 0x00409894U, .prod = 0x00000040U, .disable = 0x03fffffeU},
|
|
||||||
{.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU},
|
|
||||||
{.addr = 0x00406004U, .prod = 0x00000200U, .disable = 0x0001fffeU},
|
|
||||||
{.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU},
|
|
||||||
{.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU},
|
|
||||||
{.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x000001feU},
|
|
||||||
{.addr = 0x0041a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
|
|
||||||
{.addr = 0x0041a894U, .prod = 0x00000040U, .disable = 0x03fffffeU},
|
|
||||||
{.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU},
|
|
||||||
{.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU},
|
|
||||||
{.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU},
|
|
||||||
{.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x0000003eU},
|
|
||||||
{.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U},
|
|
||||||
{.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
|
|
||||||
{.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU},
|
|
||||||
{.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU},
|
|
||||||
{.addr = 0x00418c74U, .prod = 0xffffffc0U, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x00418cf4U, .prod = 0xfffffffcU, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU},
|
|
||||||
{.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU},
|
|
||||||
{.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x0000ffffU},
|
|
||||||
{.addr = 0x00419a44U, .prod = 0x00000000U, .disable = 0x0000000eU},
|
|
||||||
{.addr = 0x00419a4cU, .prod = 0x00000000U, .disable = 0x000001feU},
|
|
||||||
{.addr = 0x00419a54U, .prod = 0x00000000U, .disable = 0x0000003eU},
|
|
||||||
{.addr = 0x00419a5cU, .prod = 0x00000000U, .disable = 0x0000000eU},
|
|
||||||
{.addr = 0x00419a64U, .prod = 0x00000000U, .disable = 0x000001feU},
|
|
||||||
{.addr = 0x00419a6cU, .prod = 0x00000000U, .disable = 0x0000000eU},
|
|
||||||
{.addr = 0x00419a74U, .prod = 0x00000000U, .disable = 0x0000000eU},
|
|
||||||
{.addr = 0x00419a7cU, .prod = 0x00000000U, .disable = 0x0000003eU},
|
|
||||||
{.addr = 0x00419a84U, .prod = 0x00000000U, .disable = 0x0000000eU},
|
|
||||||
{.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU},
|
|
||||||
{.addr = 0x00419cd8U, .prod = 0x00000000U, .disable = 0x001ffffeU},
|
|
||||||
{.addr = 0x00419ce0U, .prod = 0x00000000U, .disable = 0x001ffffeU},
|
|
||||||
{.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU},
|
|
||||||
{.addr = 0x00419fd4U, .prod = 0x00000000U, .disable = 0x0003fffeU},
|
|
||||||
{.addr = 0x00419fdcU, .prod = 0xffedff00U, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x00419fe4U, .prod = 0x00001b00U, .disable = 0x00001ffeU},
|
|
||||||
{.addr = 0x00419ff4U, .prod = 0x00000000U, .disable = 0x00003ffeU},
|
|
||||||
{.addr = 0x00419ffcU, .prod = 0x00000000U, .disable = 0x0001fffeU},
|
|
||||||
{.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU},
|
|
||||||
{.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU},
|
|
||||||
{.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU},
|
|
||||||
{.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x0000ffffU},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* slcg ltc */
|
|
||||||
static const struct gating_desc gp10b_slcg_ltc[] = {
|
|
||||||
{.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU},
|
|
||||||
{.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* slcg perf */
|
|
||||||
static const struct gating_desc gp10b_slcg_perf[] = {
|
|
||||||
{.addr = 0x001be018U, .prod = 0x000001ffU, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x001bc018U, .prod = 0x000001ffU, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x001b8018U, .prod = 0x000001ffU, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x001b4124U, .prod = 0x00000001U, .disable = 0x00000000U},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* slcg PriRing */
|
|
||||||
static const struct gating_desc gp10b_slcg_priring[] = {
|
|
||||||
{.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* slcg pmu */
|
|
||||||
static const struct gating_desc gp10b_slcg_pmu[] = {
|
|
||||||
{.addr = 0x0010a134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
|
|
||||||
{.addr = 0x0010aa74U, .prod = 0x00004000U, .disable = 0x00007ffeU},
|
|
||||||
{.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* therm gr */
|
|
||||||
static const struct gating_desc gp10b_slcg_therm[] = {
|
|
||||||
{.addr = 0x000206b8U, .prod = 0x00000000U, .disable = 0x0000000fU},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* slcg Xbar */
|
|
||||||
static const struct gating_desc gp10b_slcg_xbar[] = {
|
|
||||||
{.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
|
|
||||||
{.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* blcg bus */
|
|
||||||
static const struct gating_desc gp10b_blcg_bus[] = {
|
|
||||||
{.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* blcg ce */
|
|
||||||
static const struct gating_desc gp10b_blcg_ce[] = {
|
|
||||||
{.addr = 0x00104200U, .prod = 0x00008242U, .disable = 0x00000000U},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* blcg fb */
|
|
||||||
static const struct gating_desc gp10b_blcg_fb[] = {
|
|
||||||
{.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
/* fix priv error */
|
|
||||||
/*{.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},*/
|
|
||||||
{.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* blcg fifo */
|
|
||||||
static const struct gating_desc gp10b_blcg_fifo[] = {
|
|
||||||
{.addr = 0x000026a4U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* blcg gr */
|
|
||||||
static const struct gating_desc gp10b_blcg_gr[] = {
|
|
||||||
{.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00408040U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U},
|
|
||||||
/* fix priv error */
|
|
||||||
/*{.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U},*/
|
|
||||||
{.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418e0cU, .prod = 0x00008444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419a40U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419a48U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419a50U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419a58U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419a60U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419a68U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419a70U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419a78U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419a80U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419868U, .prod = 0x00008242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419cd4U, .prod = 0x00000002U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419cdcU, .prod = 0x00000002U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419fd0U, .prod = 0x0000c044U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419fd8U, .prod = 0x0000c046U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419fe0U, .prod = 0x0000c044U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419fe8U, .prod = 0x0000c042U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419ff0U, .prod = 0x0000c045U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419ff8U, .prod = 0x00000002U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00419f90U, .prod = 0x00000002U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00408810U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x00408a80U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x004089a8U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* blcg ltc */
|
|
||||||
static const struct gating_desc gp10b_blcg_ltc[] = {
|
|
||||||
{.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* blcg pmu */
|
|
||||||
static const struct gating_desc gp10b_blcg_pmu[] = {
|
|
||||||
{.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* blcg Xbar */
|
|
||||||
static const struct gating_desc gp10b_blcg_xbar[] = {
|
|
||||||
{.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U},
|
|
||||||
{.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* inline functions */
|
|
||||||
void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_bus)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_bus[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_bus[i].prod :
|
|
||||||
gp10b_slcg_bus[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_bus_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_bus));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_bus_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_bus;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_ce2)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_ce2[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_ce2[i].prod :
|
|
||||||
gp10b_slcg_ce2[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_ce2_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_ce2));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_ce2_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_ce2;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_chiplet)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_chiplet[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_chiplet[i].prod :
|
|
||||||
gp10b_slcg_chiplet[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_chiplet_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_chiplet));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_chiplet_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_chiplet;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_slcg_fb_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_fb)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_fb[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_fb[i].prod :
|
|
||||||
gp10b_slcg_fb[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_fb_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_fb));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_fb_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_fb;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_fifo)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_fifo[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_fifo[i].prod :
|
|
||||||
gp10b_slcg_fifo[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_fifo_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_fifo));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_fifo_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_fifo;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_slcg_gr_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_gr)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_gr[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_gr[i].prod :
|
|
||||||
gp10b_slcg_gr[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_gr_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_gr));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_gr_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_gr;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_slcg_ltc_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_ltc)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_ltc[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_ltc[i].prod :
|
|
||||||
gp10b_slcg_ltc[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_ltc_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_ltc));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_ltc_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_ltc;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_slcg_perf_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_perf)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_perf[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_perf[i].prod :
|
|
||||||
gp10b_slcg_perf[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_perf_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_perf));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_perf_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_perf;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_slcg_priring_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_priring)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_priring[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_priring[i].prod :
|
|
||||||
gp10b_slcg_priring[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_priring_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_priring));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_priring_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_priring;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_pmu)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_pmu[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_pmu[i].prod :
|
|
||||||
gp10b_slcg_pmu[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_pmu_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_pmu));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_pmu_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_pmu;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_slcg_therm_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_therm)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_therm[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_therm[i].prod :
|
|
||||||
gp10b_slcg_therm[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_therm_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_therm));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_therm_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_therm;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_slcg_xbar)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_slcg_xbar[i].addr;
|
|
||||||
u32 val = prod ? gp10b_slcg_xbar[i].prod :
|
|
||||||
gp10b_slcg_xbar[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_slcg_xbar_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_slcg_xbar));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_slcg_xbar_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_slcg_xbar;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_blcg_bus_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_blcg_bus)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_blcg_bus[i].addr;
|
|
||||||
u32 val = prod ? gp10b_blcg_bus[i].prod :
|
|
||||||
gp10b_blcg_bus[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_blcg_bus_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_blcg_bus));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_blcg_bus_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_blcg_bus;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_blcg_ce_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_blcg_ce)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_blcg_ce[i].addr;
|
|
||||||
u32 val = prod ? gp10b_blcg_ce[i].prod :
|
|
||||||
gp10b_blcg_ce[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_blcg_ce_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_blcg_ce));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_blcg_ce_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_blcg_ce;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_blcg_fb_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_blcg_fb)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_blcg_fb[i].addr;
|
|
||||||
u32 val = prod ? gp10b_blcg_fb[i].prod :
|
|
||||||
gp10b_blcg_fb[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_blcg_fb_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_blcg_fb));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_blcg_fb_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_blcg_fb;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_blcg_fifo)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_blcg_fifo[i].addr;
|
|
||||||
u32 val = prod ? gp10b_blcg_fifo[i].prod :
|
|
||||||
gp10b_blcg_fifo[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_blcg_fifo_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_blcg_fifo));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_blcg_fifo_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_blcg_fifo;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_blcg_gr_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_blcg_gr)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_blcg_gr[i].addr;
|
|
||||||
u32 val = prod ? gp10b_blcg_gr[i].prod :
|
|
||||||
gp10b_blcg_gr[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_blcg_gr_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_blcg_gr));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_blcg_gr_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_blcg_gr;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_blcg_ltc)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_blcg_ltc[i].addr;
|
|
||||||
u32 val = prod ? gp10b_blcg_ltc[i].prod :
|
|
||||||
gp10b_blcg_ltc[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_blcg_ltc_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_blcg_ltc));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_blcg_ltc_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_blcg_ltc;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_blcg_pmu)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_blcg_pmu[i].addr;
|
|
||||||
u32 val = prod ? gp10b_blcg_pmu[i].prod :
|
|
||||||
gp10b_blcg_pmu[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_blcg_pmu_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_blcg_pmu));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_blcg_pmu_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_blcg_pmu;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod)
|
|
||||||
{
|
|
||||||
u32 i;
|
|
||||||
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(gp10b_blcg_xbar)
|
|
||||||
/ GATING_DESC_SIZE);
|
|
||||||
|
|
||||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
|
||||||
for (i = 0; i < size; i++) {
|
|
||||||
u32 reg = gp10b_blcg_xbar[i].addr;
|
|
||||||
u32 val = prod ? gp10b_blcg_xbar[i].prod :
|
|
||||||
gp10b_blcg_xbar[i].disable;
|
|
||||||
nvgpu_writel(g, reg, val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 gp10b_blcg_xbar_gating_prod_size(void)
|
|
||||||
{
|
|
||||||
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(gp10b_blcg_xbar));
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct gating_desc *gp10b_blcg_xbar_get_gating_prod(void)
|
|
||||||
{
|
|
||||||
return gp10b_blcg_xbar;
|
|
||||||
}
|
|
||||||
@@ -1,133 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
|
|
||||||
*
|
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
||||||
* copy of this software and associated documentation files (the "Software"),
|
|
||||||
* to deal in the Software without restriction, including without limitation
|
|
||||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
||||||
* and/or sell copies of the Software, and to permit persons to whom the
|
|
||||||
* Software is furnished to do so, subject to the following conditions:
|
|
||||||
*
|
|
||||||
* The above copyright notice and this permission notice shall be included in
|
|
||||||
* all copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
||||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
||||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
||||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
||||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
||||||
* DEALINGS IN THE SOFTWARE.
|
|
||||||
*
|
|
||||||
* This file is autogenerated. Do not edit.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef NVGPU_CG_GP10B_GATING_REGLIST_H
|
|
||||||
#define NVGPU_CG_GP10B_GATING_REGLIST_H
|
|
||||||
|
|
||||||
#include <nvgpu/types.h>
|
|
||||||
|
|
||||||
struct gating_desc;
|
|
||||||
struct gk20a;
|
|
||||||
|
|
||||||
void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_bus_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_bus_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_ce2_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_ce2_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_chiplet_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_chiplet_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_slcg_fb_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_fb_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_fb_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_fifo_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_fifo_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_slcg_gr_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_gr_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_gr_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_slcg_ltc_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_ltc_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_ltc_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_slcg_perf_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_perf_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_perf_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_slcg_priring_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_priring_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_priring_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_pmu_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_pmu_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_slcg_therm_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_therm_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_therm_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_slcg_xbar_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_slcg_xbar_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_blcg_bus_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_blcg_bus_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_blcg_bus_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_blcg_ce_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_blcg_ce_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_blcg_ce_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_blcg_fb_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_blcg_fb_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_blcg_fb_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_blcg_fifo_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_blcg_fifo_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_blcg_gr_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_blcg_gr_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_blcg_gr_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_blcg_ltc_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_blcg_ltc_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_blcg_pmu_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_blcg_pmu_get_gating_prod(void);
|
|
||||||
|
|
||||||
void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
|
|
||||||
bool prod);
|
|
||||||
u32 gp10b_blcg_xbar_gating_prod_size(void);
|
|
||||||
const struct gating_desc *gp10b_blcg_xbar_get_gating_prod(void);
|
|
||||||
|
|
||||||
#endif /* NVGPU_CG_GP10B_GATING_REGLIST_H */
|
|
||||||
@@ -1,422 +0,0 @@
|
|||||||
/*
|
|
||||||
* Tegra GK20A GPU Debugger Driver Register Ops
|
|
||||||
*
|
|
||||||
* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
|
|
||||||
*
|
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
||||||
* copy of this software and associated documentation files (the "Software"),
|
|
||||||
* to deal in the Software without restriction, including without limitation
|
|
||||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
||||||
* and/or sell copies of the Software, and to permit persons to whom the
|
|
||||||
* Software is furnished to do so, subject to the following conditions:
|
|
||||||
*
|
|
||||||
* The above copyright notice and this permission notice shall be included in
|
|
||||||
* all copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
||||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
||||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
||||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
||||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
||||||
* DEALINGS IN THE SOFTWARE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <nvgpu/gk20a.h>
|
|
||||||
#include <nvgpu/regops.h>
|
|
||||||
|
|
||||||
#include "regops_gp10b.h"
|
|
||||||
|
|
||||||
static const struct regop_offset_range gp10b_global_whitelist_ranges[] = {
|
|
||||||
{ 0x000004f0, 1},
|
|
||||||
{ 0x00001a00, 3},
|
|
||||||
{ 0x00002800, 128},
|
|
||||||
{ 0x00009400, 1},
|
|
||||||
{ 0x00009410, 1},
|
|
||||||
{ 0x00009480, 1},
|
|
||||||
{ 0x00020200, 24},
|
|
||||||
{ 0x00021c00, 4},
|
|
||||||
{ 0x00021c14, 3},
|
|
||||||
{ 0x00021c24, 1},
|
|
||||||
{ 0x00021c2c, 69},
|
|
||||||
{ 0x00021d44, 1},
|
|
||||||
{ 0x00021d4c, 1},
|
|
||||||
{ 0x00021d54, 1},
|
|
||||||
{ 0x00021d5c, 1},
|
|
||||||
{ 0x00021d64, 2},
|
|
||||||
{ 0x00021d70, 16},
|
|
||||||
{ 0x00022430, 7},
|
|
||||||
{ 0x00022450, 1},
|
|
||||||
{ 0x0002245c, 1},
|
|
||||||
{ 0x00070000, 5},
|
|
||||||
{ 0x000884e0, 1},
|
|
||||||
{ 0x0008e00c, 1},
|
|
||||||
{ 0x00100c18, 3},
|
|
||||||
{ 0x00100c84, 1},
|
|
||||||
{ 0x00104038, 1},
|
|
||||||
{ 0x0010a0a8, 1},
|
|
||||||
{ 0x0010a4f0, 1},
|
|
||||||
{ 0x0010e490, 1},
|
|
||||||
{ 0x0013cc14, 1},
|
|
||||||
{ 0x00140028, 1},
|
|
||||||
{ 0x00140280, 1},
|
|
||||||
{ 0x001402a0, 1},
|
|
||||||
{ 0x00140350, 1},
|
|
||||||
{ 0x00140480, 1},
|
|
||||||
{ 0x001404a0, 1},
|
|
||||||
{ 0x00140550, 1},
|
|
||||||
{ 0x00142028, 1},
|
|
||||||
{ 0x00142280, 1},
|
|
||||||
{ 0x001422a0, 1},
|
|
||||||
{ 0x00142350, 1},
|
|
||||||
{ 0x00142480, 1},
|
|
||||||
{ 0x001424a0, 1},
|
|
||||||
{ 0x00142550, 1},
|
|
||||||
{ 0x0017e028, 1},
|
|
||||||
{ 0x0017e280, 1},
|
|
||||||
{ 0x0017e294, 1},
|
|
||||||
{ 0x0017e29c, 2},
|
|
||||||
{ 0x0017e2ac, 1},
|
|
||||||
{ 0x0017e350, 1},
|
|
||||||
{ 0x0017e39c, 1},
|
|
||||||
{ 0x0017e480, 1},
|
|
||||||
{ 0x0017e4a0, 1},
|
|
||||||
{ 0x0017e550, 1},
|
|
||||||
{ 0x00180040, 41},
|
|
||||||
{ 0x001800ec, 10},
|
|
||||||
{ 0x00180240, 41},
|
|
||||||
{ 0x001802ec, 10},
|
|
||||||
{ 0x00180440, 41},
|
|
||||||
{ 0x001804ec, 10},
|
|
||||||
{ 0x00180640, 41},
|
|
||||||
{ 0x001806ec, 10},
|
|
||||||
{ 0x00180840, 41},
|
|
||||||
{ 0x001808ec, 10},
|
|
||||||
{ 0x00180a40, 41},
|
|
||||||
{ 0x00180aec, 10},
|
|
||||||
{ 0x00180c40, 41},
|
|
||||||
{ 0x00180cec, 10},
|
|
||||||
{ 0x00180e40, 41},
|
|
||||||
{ 0x00180eec, 10},
|
|
||||||
{ 0x001a0040, 41},
|
|
||||||
{ 0x001a00ec, 10},
|
|
||||||
{ 0x001a0240, 41},
|
|
||||||
{ 0x001a02ec, 10},
|
|
||||||
{ 0x001a0440, 41},
|
|
||||||
{ 0x001a04ec, 10},
|
|
||||||
{ 0x001a0640, 41},
|
|
||||||
{ 0x001a06ec, 10},
|
|
||||||
{ 0x001a0840, 41},
|
|
||||||
{ 0x001a08ec, 10},
|
|
||||||
{ 0x001a0a40, 41},
|
|
||||||
{ 0x001a0aec, 10},
|
|
||||||
{ 0x001a0c40, 41},
|
|
||||||
{ 0x001a0cec, 10},
|
|
||||||
{ 0x001a0e40, 41},
|
|
||||||
{ 0x001a0eec, 10},
|
|
||||||
{ 0x001b0040, 41},
|
|
||||||
{ 0x001b00ec, 10},
|
|
||||||
{ 0x001b0240, 41},
|
|
||||||
{ 0x001b02ec, 10},
|
|
||||||
{ 0x001b0440, 41},
|
|
||||||
{ 0x001b04ec, 10},
|
|
||||||
{ 0x001b0640, 41},
|
|
||||||
{ 0x001b06ec, 10},
|
|
||||||
{ 0x001b0840, 41},
|
|
||||||
{ 0x001b08ec, 10},
|
|
||||||
{ 0x001b0a40, 41},
|
|
||||||
{ 0x001b0aec, 10},
|
|
||||||
{ 0x001b0c40, 41},
|
|
||||||
{ 0x001b0cec, 10},
|
|
||||||
{ 0x001b0e40, 41},
|
|
||||||
{ 0x001b0eec, 10},
|
|
||||||
{ 0x001b4000, 1},
|
|
||||||
{ 0x001b4008, 1},
|
|
||||||
{ 0x001b4010, 3},
|
|
||||||
{ 0x001b4020, 3},
|
|
||||||
{ 0x001b4030, 3},
|
|
||||||
{ 0x001b4040, 3},
|
|
||||||
{ 0x001b4050, 3},
|
|
||||||
{ 0x001b4060, 4},
|
|
||||||
{ 0x001b4074, 7},
|
|
||||||
{ 0x001b4094, 3},
|
|
||||||
{ 0x001b40a4, 1},
|
|
||||||
{ 0x001b4100, 6},
|
|
||||||
{ 0x001b4124, 2},
|
|
||||||
{ 0x001b8000, 1},
|
|
||||||
{ 0x001b8008, 1},
|
|
||||||
{ 0x001b8010, 3},
|
|
||||||
{ 0x001bc000, 1},
|
|
||||||
{ 0x001bc008, 1},
|
|
||||||
{ 0x001bc010, 3},
|
|
||||||
{ 0x001be000, 1},
|
|
||||||
{ 0x001be008, 1},
|
|
||||||
{ 0x001be010, 3},
|
|
||||||
{ 0x00400500, 1},
|
|
||||||
{ 0x0040415c, 1},
|
|
||||||
{ 0x00404468, 1},
|
|
||||||
{ 0x00404498, 1},
|
|
||||||
{ 0x00405800, 1},
|
|
||||||
{ 0x00405840, 2},
|
|
||||||
{ 0x00405850, 1},
|
|
||||||
{ 0x00405908, 1},
|
|
||||||
{ 0x00405b40, 1},
|
|
||||||
{ 0x00405b50, 1},
|
|
||||||
{ 0x00406024, 5},
|
|
||||||
{ 0x00407010, 1},
|
|
||||||
{ 0x00407808, 1},
|
|
||||||
{ 0x0040803c, 1},
|
|
||||||
{ 0x00408804, 1},
|
|
||||||
{ 0x0040880c, 1},
|
|
||||||
{ 0x00408900, 2},
|
|
||||||
{ 0x00408910, 1},
|
|
||||||
{ 0x00408944, 1},
|
|
||||||
{ 0x00408984, 1},
|
|
||||||
{ 0x004090a8, 1},
|
|
||||||
{ 0x004098a0, 1},
|
|
||||||
{ 0x00409b00, 1},
|
|
||||||
{ 0x0041000c, 1},
|
|
||||||
{ 0x00410110, 1},
|
|
||||||
{ 0x00410184, 1},
|
|
||||||
{ 0x0041040c, 1},
|
|
||||||
{ 0x00410510, 1},
|
|
||||||
{ 0x00410584, 1},
|
|
||||||
{ 0x00418000, 1},
|
|
||||||
{ 0x00418008, 1},
|
|
||||||
{ 0x00418380, 2},
|
|
||||||
{ 0x00418400, 2},
|
|
||||||
{ 0x004184a0, 1},
|
|
||||||
{ 0x00418604, 1},
|
|
||||||
{ 0x00418680, 1},
|
|
||||||
{ 0x00418704, 1},
|
|
||||||
{ 0x00418714, 1},
|
|
||||||
{ 0x00418800, 1},
|
|
||||||
{ 0x0041881c, 1},
|
|
||||||
{ 0x00418830, 1},
|
|
||||||
{ 0x00418884, 1},
|
|
||||||
{ 0x004188b0, 1},
|
|
||||||
{ 0x004188c8, 3},
|
|
||||||
{ 0x004188fc, 1},
|
|
||||||
{ 0x00418b04, 1},
|
|
||||||
{ 0x00418c04, 1},
|
|
||||||
{ 0x00418c10, 8},
|
|
||||||
{ 0x00418c88, 1},
|
|
||||||
{ 0x00418d00, 1},
|
|
||||||
{ 0x00418e00, 1},
|
|
||||||
{ 0x00418e08, 1},
|
|
||||||
{ 0x00418e34, 1},
|
|
||||||
{ 0x00418e40, 4},
|
|
||||||
{ 0x00418e58, 16},
|
|
||||||
{ 0x00418f08, 1},
|
|
||||||
{ 0x00419000, 1},
|
|
||||||
{ 0x0041900c, 1},
|
|
||||||
{ 0x00419018, 1},
|
|
||||||
{ 0x00419854, 1},
|
|
||||||
{ 0x00419864, 1},
|
|
||||||
{ 0x00419a04, 2},
|
|
||||||
{ 0x00419a14, 1},
|
|
||||||
{ 0x00419ab0, 1},
|
|
||||||
{ 0x00419ab8, 3},
|
|
||||||
{ 0x00419c0c, 1},
|
|
||||||
{ 0x00419c8c, 2},
|
|
||||||
{ 0x00419d00, 1},
|
|
||||||
{ 0x00419d08, 2},
|
|
||||||
{ 0x00419e00, 11},
|
|
||||||
{ 0x00419e34, 2},
|
|
||||||
{ 0x00419e44, 11},
|
|
||||||
{ 0x00419e74, 10},
|
|
||||||
{ 0x00419ea4, 1},
|
|
||||||
{ 0x00419eac, 2},
|
|
||||||
{ 0x00419ee8, 1},
|
|
||||||
{ 0x00419ef0, 28},
|
|
||||||
{ 0x00419f70, 1},
|
|
||||||
{ 0x00419f78, 2},
|
|
||||||
{ 0x00419f98, 2},
|
|
||||||
{ 0x00419fdc, 1},
|
|
||||||
{ 0x0041a02c, 2},
|
|
||||||
{ 0x0041a0a0, 1},
|
|
||||||
{ 0x0041a0a8, 1},
|
|
||||||
{ 0x0041a890, 2},
|
|
||||||
{ 0x0041a8a0, 3},
|
|
||||||
{ 0x0041a8b0, 2},
|
|
||||||
{ 0x0041b014, 1},
|
|
||||||
{ 0x0041b0a0, 1},
|
|
||||||
{ 0x0041b0cc, 1},
|
|
||||||
{ 0x0041b1dc, 1},
|
|
||||||
{ 0x0041be0c, 3},
|
|
||||||
{ 0x0041bea0, 1},
|
|
||||||
{ 0x0041becc, 1},
|
|
||||||
{ 0x0041bfdc, 1},
|
|
||||||
{ 0x0041c054, 1},
|
|
||||||
{ 0x0041c2b0, 1},
|
|
||||||
{ 0x0041c2b8, 3},
|
|
||||||
{ 0x0041c40c, 1},
|
|
||||||
{ 0x0041c48c, 2},
|
|
||||||
{ 0x0041c500, 1},
|
|
||||||
{ 0x0041c508, 2},
|
|
||||||
{ 0x0041c600, 11},
|
|
||||||
{ 0x0041c634, 2},
|
|
||||||
{ 0x0041c644, 11},
|
|
||||||
{ 0x0041c674, 10},
|
|
||||||
{ 0x0041c6a4, 1},
|
|
||||||
{ 0x0041c6ac, 2},
|
|
||||||
{ 0x0041c6e8, 1},
|
|
||||||
{ 0x0041c6f0, 28},
|
|
||||||
{ 0x0041c770, 1},
|
|
||||||
{ 0x0041c778, 2},
|
|
||||||
{ 0x0041c798, 2},
|
|
||||||
{ 0x0041c7dc, 1},
|
|
||||||
{ 0x0041c854, 1},
|
|
||||||
{ 0x0041cab0, 1},
|
|
||||||
{ 0x0041cab8, 3},
|
|
||||||
{ 0x0041cc0c, 1},
|
|
||||||
{ 0x0041cc8c, 2},
|
|
||||||
{ 0x0041cd00, 1},
|
|
||||||
{ 0x0041cd08, 2},
|
|
||||||
{ 0x0041ce00, 11},
|
|
||||||
{ 0x0041ce34, 2},
|
|
||||||
{ 0x0041ce44, 11},
|
|
||||||
{ 0x0041ce74, 10},
|
|
||||||
{ 0x0041cea4, 1},
|
|
||||||
{ 0x0041ceac, 2},
|
|
||||||
{ 0x0041cee8, 1},
|
|
||||||
{ 0x0041cef0, 28},
|
|
||||||
{ 0x0041cf70, 1},
|
|
||||||
{ 0x0041cf78, 2},
|
|
||||||
{ 0x0041cf98, 2},
|
|
||||||
{ 0x0041cfdc, 1},
|
|
||||||
{ 0x00500384, 1},
|
|
||||||
{ 0x005004a0, 1},
|
|
||||||
{ 0x00500604, 1},
|
|
||||||
{ 0x00500680, 1},
|
|
||||||
{ 0x00500714, 1},
|
|
||||||
{ 0x0050081c, 1},
|
|
||||||
{ 0x00500884, 1},
|
|
||||||
{ 0x005008b0, 1},
|
|
||||||
{ 0x005008c8, 3},
|
|
||||||
{ 0x005008fc, 1},
|
|
||||||
{ 0x00500b04, 1},
|
|
||||||
{ 0x00500c04, 1},
|
|
||||||
{ 0x00500c10, 8},
|
|
||||||
{ 0x00500c88, 1},
|
|
||||||
{ 0x00500d00, 1},
|
|
||||||
{ 0x00500e08, 1},
|
|
||||||
{ 0x00500f08, 1},
|
|
||||||
{ 0x00501000, 1},
|
|
||||||
{ 0x0050100c, 1},
|
|
||||||
{ 0x00501018, 1},
|
|
||||||
{ 0x00501854, 1},
|
|
||||||
{ 0x00501ab0, 1},
|
|
||||||
{ 0x00501ab8, 3},
|
|
||||||
{ 0x00501c0c, 1},
|
|
||||||
{ 0x00501c8c, 2},
|
|
||||||
{ 0x00501d00, 1},
|
|
||||||
{ 0x00501d08, 2},
|
|
||||||
{ 0x00501e00, 11},
|
|
||||||
{ 0x00501e34, 2},
|
|
||||||
{ 0x00501e44, 11},
|
|
||||||
{ 0x00501e74, 10},
|
|
||||||
{ 0x00501ea4, 1},
|
|
||||||
{ 0x00501eac, 2},
|
|
||||||
{ 0x00501ee8, 1},
|
|
||||||
{ 0x00501ef0, 28},
|
|
||||||
{ 0x00501f70, 1},
|
|
||||||
{ 0x00501f78, 2},
|
|
||||||
{ 0x00501f98, 2},
|
|
||||||
{ 0x00501fdc, 1},
|
|
||||||
{ 0x0050202c, 2},
|
|
||||||
{ 0x005020a0, 1},
|
|
||||||
{ 0x005020a8, 1},
|
|
||||||
{ 0x00502890, 2},
|
|
||||||
{ 0x005028a0, 3},
|
|
||||||
{ 0x005028b0, 2},
|
|
||||||
{ 0x00503014, 1},
|
|
||||||
{ 0x005030a0, 1},
|
|
||||||
{ 0x005030cc, 1},
|
|
||||||
{ 0x005031dc, 1},
|
|
||||||
{ 0x00503e14, 1},
|
|
||||||
{ 0x00503ea0, 1},
|
|
||||||
{ 0x00503ecc, 1},
|
|
||||||
{ 0x00503fdc, 1},
|
|
||||||
{ 0x00504054, 1},
|
|
||||||
{ 0x005042b0, 1},
|
|
||||||
{ 0x005042b8, 3},
|
|
||||||
{ 0x0050440c, 1},
|
|
||||||
{ 0x0050448c, 2},
|
|
||||||
{ 0x00504500, 1},
|
|
||||||
{ 0x00504508, 2},
|
|
||||||
{ 0x00504600, 11},
|
|
||||||
{ 0x00504634, 2},
|
|
||||||
{ 0x00504644, 11},
|
|
||||||
{ 0x00504674, 10},
|
|
||||||
{ 0x005046a4, 1},
|
|
||||||
{ 0x005046ac, 2},
|
|
||||||
{ 0x005046e8, 1},
|
|
||||||
{ 0x005046f0, 28},
|
|
||||||
{ 0x00504770, 1},
|
|
||||||
{ 0x00504778, 2},
|
|
||||||
{ 0x00504798, 2},
|
|
||||||
{ 0x005047dc, 1},
|
|
||||||
{ 0x00504854, 1},
|
|
||||||
{ 0x00504ab0, 1},
|
|
||||||
{ 0x00504ab8, 3},
|
|
||||||
{ 0x00504c0c, 1},
|
|
||||||
{ 0x00504c8c, 2},
|
|
||||||
{ 0x00504d00, 1},
|
|
||||||
{ 0x00504d08, 2},
|
|
||||||
{ 0x00504e00, 11},
|
|
||||||
{ 0x00504e34, 2},
|
|
||||||
{ 0x00504e44, 11},
|
|
||||||
{ 0x00504e74, 10},
|
|
||||||
{ 0x00504ea4, 1},
|
|
||||||
{ 0x00504eac, 2},
|
|
||||||
{ 0x00504ee8, 1},
|
|
||||||
{ 0x00504ef0, 28},
|
|
||||||
{ 0x00504f70, 1},
|
|
||||||
{ 0x00504f78, 2},
|
|
||||||
{ 0x00504f98, 2},
|
|
||||||
{ 0x00504fdc, 1},
|
|
||||||
{ 0x00900100, 1},
|
|
||||||
{ 0x009a0100, 1},
|
|
||||||
};
|
|
||||||
|
|
||||||
static const u64 gp10b_global_whitelist_ranges_count =
|
|
||||||
ARRAY_SIZE(gp10b_global_whitelist_ranges);
|
|
||||||
|
|
||||||
/* context */
|
|
||||||
|
|
||||||
/* runcontrol */
|
|
||||||
static const u32 gp10b_runcontrol_whitelist[] = {
|
|
||||||
};
|
|
||||||
static const u64 gp10b_runcontrol_whitelist_count =
|
|
||||||
ARRAY_SIZE(gp10b_runcontrol_whitelist);
|
|
||||||
|
|
||||||
const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void)
|
|
||||||
{
|
|
||||||
return gp10b_global_whitelist_ranges;
|
|
||||||
}
|
|
||||||
|
|
||||||
u64 gp10b_get_global_whitelist_ranges_count(void)
|
|
||||||
{
|
|
||||||
return gp10b_global_whitelist_ranges_count;
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void)
|
|
||||||
{
|
|
||||||
return gp10b_global_whitelist_ranges;
|
|
||||||
}
|
|
||||||
|
|
||||||
u64 gp10b_get_context_whitelist_ranges_count(void)
|
|
||||||
{
|
|
||||||
return gp10b_global_whitelist_ranges_count;
|
|
||||||
}
|
|
||||||
|
|
||||||
const u32 *gp10b_get_runcontrol_whitelist(void)
|
|
||||||
{
|
|
||||||
return gp10b_runcontrol_whitelist;
|
|
||||||
}
|
|
||||||
|
|
||||||
u64 gp10b_get_runcontrol_whitelist_count(void)
|
|
||||||
{
|
|
||||||
return gp10b_runcontrol_whitelist_count;
|
|
||||||
}
|
|
||||||
@@ -1,40 +0,0 @@
|
|||||||
/*
|
|
||||||
*
|
|
||||||
* Tegra GP10B GPU Debugger Driver Register Ops
|
|
||||||
*
|
|
||||||
* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
|
|
||||||
*
|
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
||||||
* copy of this software and associated documentation files (the "Software"),
|
|
||||||
* to deal in the Software without restriction, including without limitation
|
|
||||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
||||||
* and/or sell copies of the Software, and to permit persons to whom the
|
|
||||||
* Software is furnished to do so, subject to the following conditions:
|
|
||||||
*
|
|
||||||
* The above copyright notice and this permission notice shall be included in
|
|
||||||
* all copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
||||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
||||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
||||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
||||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
||||||
* DEALINGS IN THE SOFTWARE.
|
|
||||||
*/
|
|
||||||
#ifndef NVGPU_REGOPS_GP10B_H
|
|
||||||
#define NVGPU_REGOPS_GP10B_H
|
|
||||||
|
|
||||||
#ifdef CONFIG_NVGPU_DEBUGGER
|
|
||||||
|
|
||||||
const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void);
|
|
||||||
u64 gp10b_get_global_whitelist_ranges_count(void);
|
|
||||||
const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void);
|
|
||||||
u64 gp10b_get_context_whitelist_ranges_count(void);
|
|
||||||
const u32 *gp10b_get_runcontrol_whitelist(void);
|
|
||||||
u64 gp10b_get_runcontrol_whitelist_count(void);
|
|
||||||
const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void);
|
|
||||||
u64 gp10b_get_runcontrol_whitelist_ranges_count(void);
|
|
||||||
|
|
||||||
#endif /* CONFIG_NVGPU_DEBUGGER */
|
|
||||||
#endif /* NVGPU_REGOPS_GP10B_H */
|
|
||||||
@@ -672,14 +672,6 @@ static struct of_device_id tegra_gk20a_of_match[] = {
|
|||||||
#ifdef CONFIG_TEGRA_GK20A
|
#ifdef CONFIG_TEGRA_GK20A
|
||||||
{ .compatible = "nvidia,tegra210-gm20b",
|
{ .compatible = "nvidia,tegra210-gm20b",
|
||||||
.data = &gm20b_tegra_platform },
|
.data = &gm20b_tegra_platform },
|
||||||
{ .compatible = "nvidia,tegra186-gp10b",
|
|
||||||
.data = &gp10b_tegra_platform },
|
|
||||||
/*
|
|
||||||
* Upstream device trees use nvidia,gp10b instead of
|
|
||||||
* nvidia,tegra186-gp10b used in downstream.
|
|
||||||
*/
|
|
||||||
{ .compatible = "nvidia,gp10b",
|
|
||||||
.data = &gp10b_tegra_platform },
|
|
||||||
{ .compatible = "nvidia,gv11b",
|
{ .compatible = "nvidia,gv11b",
|
||||||
.data = &gv11b_tegra_platform },
|
.data = &gv11b_tegra_platform },
|
||||||
#ifdef CONFIG_NVGPU_GR_VIRTUALIZATION
|
#ifdef CONFIG_NVGPU_GR_VIRTUALIZATION
|
||||||
|
|||||||
@@ -343,7 +343,6 @@ static inline struct gk20a_platform *gk20a_get_platform(
|
|||||||
|
|
||||||
#ifdef CONFIG_TEGRA_GK20A
|
#ifdef CONFIG_TEGRA_GK20A
|
||||||
extern struct gk20a_platform gm20b_tegra_platform;
|
extern struct gk20a_platform gm20b_tegra_platform;
|
||||||
extern struct gk20a_platform gp10b_tegra_platform;
|
|
||||||
extern struct gk20a_platform gv11b_tegra_platform;
|
extern struct gk20a_platform gv11b_tegra_platform;
|
||||||
#ifdef CONFIG_NVGPU_GR_VIRTUALIZATION
|
#ifdef CONFIG_NVGPU_GR_VIRTUALIZATION
|
||||||
extern struct gk20a_platform gv11b_vgpu_tegra_platform;
|
extern struct gk20a_platform gv11b_vgpu_tegra_platform;
|
||||||
|
|||||||
@@ -178,104 +178,6 @@ void gp10b_tegra_scale_init(struct device *dev)
|
|||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
static void gp10b_tegra_scale_exit(struct device *dev)
|
|
||||||
{
|
|
||||||
#ifdef CONFIG_TEGRA_BWMGR
|
|
||||||
struct gk20a_platform *platform = gk20a_get_platform(dev);
|
|
||||||
struct gk20a_scale_profile *profile = platform->g->scale_profile;
|
|
||||||
|
|
||||||
if (profile && profile->private_data)
|
|
||||||
tegra_bwmgr_unregister(
|
|
||||||
(struct tegra_bwmgr_client *)profile->private_data);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
static int gp10b_tegra_probe(struct device *dev)
|
|
||||||
{
|
|
||||||
struct gk20a_platform *platform = dev_get_drvdata(dev);
|
|
||||||
struct device_node *of_chosen;
|
|
||||||
bool joint_xpu_rail = false;
|
|
||||||
struct gk20a *g = platform->g;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
#ifdef CONFIG_TEGRA_GK20A_NVHOST
|
|
||||||
ret = nvgpu_get_nvhost_dev(platform->g);
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
platform->disable_bigpage = !iommu_get_domain_for_dev(dev) &&
|
|
||||||
(NVGPU_CPU_PAGE_SIZE < SZ_64K);
|
|
||||||
|
|
||||||
#ifdef CONFIG_OF
|
|
||||||
of_chosen = of_find_node_by_path("/chosen");
|
|
||||||
if (!of_chosen)
|
|
||||||
return -ENODEV;
|
|
||||||
|
|
||||||
joint_xpu_rail = of_property_read_bool(of_chosen,
|
|
||||||
"nvidia,tegra-joint_xpu_rail");
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if (joint_xpu_rail) {
|
|
||||||
nvgpu_log_info(g, "XPU rails are joint\n");
|
|
||||||
platform->can_railgate_init = false;
|
|
||||||
nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, false);
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = gp10b_tegra_get_clocks(dev);
|
|
||||||
if (ret != 0) {
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
nvgpu_linux_init_clk_support(platform->g);
|
|
||||||
|
|
||||||
nvgpu_mutex_init(&platform->clk_get_freq_lock);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int gp10b_tegra_late_probe(struct device *dev)
|
|
||||||
{
|
|
||||||
struct gk20a_platform *platform = dev_get_drvdata(dev);
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
ret = gk20a_tegra_init_secure_alloc(platform);
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int gp10b_tegra_remove(struct device *dev)
|
|
||||||
{
|
|
||||||
struct gk20a_platform *platform = gk20a_get_platform(dev);
|
|
||||||
|
|
||||||
/* deinitialise tegra specific scaling quirks */
|
|
||||||
gp10b_tegra_scale_exit(dev);
|
|
||||||
|
|
||||||
#ifdef CONFIG_TEGRA_GK20A_NVHOST
|
|
||||||
nvgpu_free_nvhost_dev(get_gk20a(dev));
|
|
||||||
#endif
|
|
||||||
|
|
||||||
nvgpu_mutex_destroy(&platform->clk_get_freq_lock);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static bool gp10b_tegra_is_railgated(struct device *dev)
|
|
||||||
{
|
|
||||||
struct gk20a *g = get_gk20a(dev);
|
|
||||||
bool ret = false;
|
|
||||||
|
|
||||||
if (pm_runtime_status_suspended(dev)) {
|
|
||||||
ret = true;
|
|
||||||
}
|
|
||||||
|
|
||||||
nvgpu_log(g, gpu_dbg_info, "railgated? %s", ret ? "yes" : "no");
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
void gp10b_tegra_clks_control(struct device *dev, bool enable)
|
void gp10b_tegra_clks_control(struct device *dev, bool enable)
|
||||||
{
|
{
|
||||||
struct gk20a_platform *platform = gk20a_get_platform(dev);
|
struct gk20a_platform *platform = gk20a_get_platform(dev);
|
||||||
@@ -299,51 +201,6 @@ void gp10b_tegra_clks_control(struct device *dev, bool enable)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static int gp10b_tegra_railgate(struct device *dev)
|
|
||||||
{
|
|
||||||
#ifdef CONFIG_TEGRA_BWMGR
|
|
||||||
struct gk20a_platform *platform = gk20a_get_platform(dev);
|
|
||||||
struct gk20a_scale_profile *profile = platform->g->scale_profile;
|
|
||||||
|
|
||||||
/* remove emc frequency floor */
|
|
||||||
if (profile)
|
|
||||||
tegra_bwmgr_set_emc(
|
|
||||||
(struct tegra_bwmgr_client *)profile->private_data,
|
|
||||||
0, TEGRA_BWMGR_SET_EMC_FLOOR);
|
|
||||||
#endif /* CONFIG_TEGRA_BWMGR */
|
|
||||||
|
|
||||||
gp10b_tegra_clks_control(dev, false);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int gp10b_tegra_unrailgate(struct device *dev)
|
|
||||||
{
|
|
||||||
int ret = 0;
|
|
||||||
#ifdef CONFIG_TEGRA_BWMGR
|
|
||||||
struct gk20a_platform *platform = gk20a_get_platform(dev);
|
|
||||||
struct gk20a_scale_profile *profile = platform->g->scale_profile;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
gp10b_tegra_clks_control(dev, true);
|
|
||||||
|
|
||||||
#ifdef CONFIG_TEGRA_BWMGR
|
|
||||||
/* to start with set emc frequency floor to max rate*/
|
|
||||||
if (profile)
|
|
||||||
tegra_bwmgr_set_emc(
|
|
||||||
(struct tegra_bwmgr_client *)profile->private_data,
|
|
||||||
tegra_bwmgr_get_max_emc_rate(),
|
|
||||||
TEGRA_BWMGR_SET_EMC_FLOOR);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int gp10b_tegra_suspend(struct device *dev)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int gp10b_tegra_reset_assert(struct device *dev)
|
int gp10b_tegra_reset_assert(struct device *dev)
|
||||||
{
|
{
|
||||||
struct gk20a_platform *platform = gk20a_get_platform(dev);
|
struct gk20a_platform *platform = gk20a_get_platform(dev);
|
||||||
@@ -512,79 +369,3 @@ int gp10b_clk_get_freqs(struct device *dev,
|
|||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
struct gk20a_platform gp10b_tegra_platform = {
|
|
||||||
#ifdef CONFIG_TEGRA_GK20A_NVHOST
|
|
||||||
.has_syncpoints = true,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* power management configuration */
|
|
||||||
.railgate_delay_init = 500,
|
|
||||||
|
|
||||||
/* ldiv slowdown factor */
|
|
||||||
.ldiv_slowdown_factor_init = SLOWDOWN_FACTOR_FPDIV_BY16,
|
|
||||||
|
|
||||||
/* power management configuration */
|
|
||||||
.can_railgate_init = true,
|
|
||||||
.enable_elpg = true,
|
|
||||||
.enable_elpg_ms = false,
|
|
||||||
.can_elpg_init = true,
|
|
||||||
.enable_blcg = true,
|
|
||||||
.enable_slcg = true,
|
|
||||||
.enable_elcg = true,
|
|
||||||
.can_slcg = true,
|
|
||||||
.can_blcg = true,
|
|
||||||
.can_elcg = true,
|
|
||||||
.enable_aelpg = true,
|
|
||||||
.enable_perfmon = true,
|
|
||||||
|
|
||||||
/* ptimer src frequency in hz*/
|
|
||||||
.ptimer_src_freq = 31250000,
|
|
||||||
|
|
||||||
.ch_wdt_init_limit_ms = 5000,
|
|
||||||
|
|
||||||
.probe = gp10b_tegra_probe,
|
|
||||||
.late_probe = gp10b_tegra_late_probe,
|
|
||||||
.remove = gp10b_tegra_remove,
|
|
||||||
|
|
||||||
/* power management callbacks */
|
|
||||||
.suspend = gp10b_tegra_suspend,
|
|
||||||
.railgate = gp10b_tegra_railgate,
|
|
||||||
.unrailgate = gp10b_tegra_unrailgate,
|
|
||||||
.is_railgated = gp10b_tegra_is_railgated,
|
|
||||||
|
|
||||||
.busy = gk20a_tegra_busy,
|
|
||||||
.idle = gk20a_tegra_idle,
|
|
||||||
|
|
||||||
.dump_platform_dependencies = gk20a_tegra_debug_dump,
|
|
||||||
|
|
||||||
#ifdef CONFIG_NVGPU_SUPPORT_CDE
|
|
||||||
.has_cde = true,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.clk_round_rate = gp10b_round_clk_rate,
|
|
||||||
.get_clk_freqs = gp10b_clk_get_freqs,
|
|
||||||
|
|
||||||
/* frequency scaling configuration */
|
|
||||||
.initscale = gp10b_tegra_scale_init,
|
|
||||||
.prescale = gp10b_tegra_prescale,
|
|
||||||
.postscale = gp10b_tegra_postscale,
|
|
||||||
.devfreq_governor = "nvhost_podgov",
|
|
||||||
|
|
||||||
.qos_notify = gk20a_scale_qos_notify,
|
|
||||||
|
|
||||||
.reset_assert = gp10b_tegra_reset_assert,
|
|
||||||
.reset_deassert = gp10b_tegra_reset_deassert,
|
|
||||||
|
|
||||||
.platform_chip_id = TEGRA_186,
|
|
||||||
.soc_name = "tegra18x",
|
|
||||||
|
|
||||||
.unified_memory = true,
|
|
||||||
.dma_mask = DMA_BIT_MASK(36),
|
|
||||||
|
|
||||||
#ifdef CONFIG_NV_TEGRA_MC
|
|
||||||
.ltc_streamid = TEGRA_SID_GPUB,
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.secure_buffer_size = 401408,
|
|
||||||
};
|
|
||||||
|
|||||||
Reference in New Issue
Block a user