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gpu: nvgpu: volt: Fix MISRA 15.6 violations

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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.

JIRA NVGPU-671

Change-Id: I938f49b2d1d042dc96573e1a579fe82909a679ab
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812421
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Srirangan
2018-09-04 16:46:40 +05:30
committed by mobile promotions
parent 7405cd9a6d
commit 3b413d58fa
4 changed files with 107 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
drivers/gpu/nvgpu/volt/volt_dev.c
View File

@@ -46,8 +46,9 @@ static u32 volt_device_pmu_data_init_super(struct gk20a *g,
struct nv_pmu_volt_volt_device_boardobj_set *pset;
status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata);
if (status)
if (status) {
return status;
}
pdev = (struct voltage_device *)pboard_obj;
pset = (struct nv_pmu_volt_volt_device_boardobj_set *)ppmudata;
@@ -68,8 +69,9 @@ static u32 volt_device_pmu_data_init_pwm(struct gk20a *g,
struct nv_pmu_volt_volt_device_pwm_boardobj_set *pset;
status = volt_device_pmu_data_init_super(g, pboard_obj, ppmudata);
if (status)
if (status) {
return status;
}
pdev = (struct voltage_device_pwm *)pboard_obj;
pset = (struct nv_pmu_volt_volt_device_pwm_boardobj_set *)ppmudata;
@@ -90,8 +92,9 @@ static u32 construct_volt_device(struct gk20a *g,
u32 status = 0;
status = boardobj_construct_super(g, ppboardobj, size, pargs);
if (status)
if (status) {
return status;
}
pvolt_dev = (struct voltage_device *)*ppboardobj;
@@ -121,8 +124,9 @@ static u32 construct_pwm_volt_device(struct gk20a *g,
u32 status = 0;
status = construct_volt_device(g, ppboardobj, size, pargs);
if (status)
if (status) {
return status;
}
pboard_obj = (*ppboardobj);
pdev = (struct voltage_device_pwm *)*ppboardobj;
@@ -148,8 +152,9 @@ static struct voltage_device_entry *volt_dev_construct_dev_entry_pwm(
(struct voltage_device_pwm_entry *)pargs;
pentry = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm_entry));
if (pentry == NULL)
if (pentry == NULL) {
return NULL;
}
memset(pentry, 0, sizeof(struct voltage_device_pwm_entry));
@@ -213,8 +218,9 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g,
struct voltage_device_pwm_entry pwm_entry = { { 0 } };
ptmp_dev = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm));
if (ptmp_dev == NULL)
if (ptmp_dev == NULL) {
return -ENOMEM;
}
frequency_hz = (u32)BIOS_GET_FIELD(p_bios_entry->param0,
NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY);
@@ -247,8 +253,9 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g,
steps = (u8)BIOS_GET_FIELD(p_bios_entry->param3,
NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS);
if (steps == VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID)
if (steps == VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID) {
steps = VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT;
}
ptmp_dev->voltage_offset_scale_uv =
BIOS_GET_FIELD(p_bios_entry->param4,
@@ -265,12 +272,14 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g,
if (ptmp_dev->super.operation_type ==
CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) {
if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC)
if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) {
ptmp_dev->source =
NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0;
if (volt_domain == CTRL_VOLT_DOMAIN_SRAM)
}
if (volt_domain == CTRL_VOLT_DOMAIN_SRAM) {
ptmp_dev->source =
NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1;
}
ptmp_dev->raw_period =
g->ops.clk.get_crystal_clk_hz(g) / frequency_hz;
} else if (ptmp_dev->super.operation_type ==
@@ -319,11 +328,12 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g,
/* Skip creating entry for invalid voltage. */
if ((voltage_uv >= pvolt_dev_pwm->super.voltage_min_uv) &&
(voltage_uv <= pvolt_dev_pwm->super.voltage_max_uv)) {
if (pvolt_dev_pwm->voltage_offset_scale_uv < 0)
if (pvolt_dev_pwm->voltage_offset_scale_uv < 0) {
pwm_entry.duty_cycle =
pvolt_dev_pwm->raw_period - duty_cycle;
else
} else {
pwm_entry.duty_cycle = duty_cycle;
}
/* Check if there is room left in the voltage table. */
if (entry_cnt == VOLTAGE_TABLE_MAX_ENTRIES) {
@@ -349,14 +359,16 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g,
duty_cycle = duty_cycle + (u32)steps;
/* Cap duty cycle to PWM period. */
if (duty_cycle > pvolt_dev_pwm->raw_period)
if (duty_cycle > pvolt_dev_pwm->raw_period) {
duty_cycle = pvolt_dev_pwm->raw_period;
}
} while (duty_cycle < pvolt_dev_pwm->raw_period);
done:
if (pvolt_dev != NULL)
if (pvolt_dev != NULL) {
pvolt_dev->num_entries = entry_cnt;
}
nvgpu_kfree(g, ptmp_dev);
return status;
@@ -390,10 +402,11 @@ static u32 volt_get_volt_devices_table(struct gk20a *g,
memcpy(&entry, entry_offset,
sizeof(struct vbios_voltage_device_table_1x_entry));
if (entry.type == NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV)
if (entry.type == NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV) {
status = volt_get_voltage_device_table_1x_psv(g,
&entry, pvolt_device_metadata,
entry_idx);
}
}
done:
@@ -412,8 +425,9 @@ static u32 _volt_device_devgrp_pmudata_instget(struct gk20a *g,
/*check whether pmuboardobjgrp has a valid boardobj in index*/
if (((u32)BIT(idx) &
pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) {
return -EINVAL;
}
*ppboardobjpmudata = (struct nv_pmu_boardobj *)
&pgrp_set->objects[idx].data.board_obj;
@@ -431,8 +445,9 @@ static u32 _volt_device_devgrp_pmustatus_instget(struct gk20a *g,
/*check whether pmuboardobjgrp has a valid boardobj in index*/
if (((u32)BIT(idx) &
pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0)
pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) {
return -EINVAL;
}
*ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
&pgrp_get_status->objects[idx].data.board_obj;
@@ -459,11 +474,12 @@ static u32 volt_device_state_init(struct gk20a *g,
NULL);
/* Initialize VOLT_DEVICE step size. */
if (pvolt_dev->num_entries <= VOLTAGE_TABLE_MAX_ENTRIES_ONE)
if (pvolt_dev->num_entries <= VOLTAGE_TABLE_MAX_ENTRIES_ONE) {
pvolt_dev->volt_step_uv = NV_PMU_VOLT_VALUE_0V_IN_UV;
else
} else {
pvolt_dev->volt_step_uv = (pvolt_dev->pentry[1]->voltage_uv -
pvolt_dev->pentry[0]->voltage_uv);
}
/* Build VOLT_RAIL SW state from VOLT_DEVICE SW state. */
/* If VOLT_RAIL isn't supported, exit. */
@@ -495,8 +511,9 @@ static u32 volt_device_state_init(struct gk20a *g,
}
done:
if (status)
if (status) {
nvgpu_err(g, "Error in building rail sw state device sw");
}
return status;
}
@@ -510,8 +527,9 @@ u32 volt_dev_pmu_setup(struct gk20a *g)
pboardobjgrp = &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super;
if (!pboardobjgrp->bconstructed)
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
}
status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
@@ -545,8 +563,9 @@ u32 volt_dev_sw_setup(struct gk20a *g)
/* Obtain Voltage Rail Table from VBIOS */
status = volt_get_volt_devices_table(g, &g->perf_pmu.volt.
volt_dev_metadata);
if (status)
if (status) {
goto done;
}
/* Populate data for the VOLT_RAIL PMU interface */
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_DEVICE);

12
drivers/gpu/nvgpu/volt/volt_pmu.c
View File

@@ -54,8 +54,9 @@ static void volt_rpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
return;
}
if (phandlerparams->prpc_call->b_supported)
if (phandlerparams->prpc_call->b_supported) {
phandlerparams->success = 1;
}
}
@@ -124,10 +125,11 @@ u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g)
rpc_call.function = NV_PMU_VOLT_RPC_ID_LOAD;
status = volt_pmu_rpc_execute(g, &rpc_call);
if (status)
if (status) {
nvgpu_err(g,
"Error while executing LOAD RPC: status = 0x%08x.",
status);
}
return status;
}
@@ -241,9 +243,10 @@ static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id,
}
/* Convert the client ID to index. */
if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ)
if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ) {
policy_idx =
pvolt->volt_policy_metadata.perf_core_vf_seq_policy_idx;
}
else {
status = -EINVAL;
goto exit;
@@ -257,9 +260,10 @@ static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id,
/* Execute the voltage change request via PMU RPC. */
status = volt_pmu_rpc_execute(g, &rpc_call);
if (status)
if (status) {
nvgpu_err(g,
"Error while executing VOLT_POLICY_SET_VOLTAGE RPC");
}
exit:
return status;

36
drivers/gpu/nvgpu/volt/volt_policy.c
View File

@@ -43,8 +43,9 @@ static u32 construct_volt_policy(struct gk20a *g,
u32 status = 0;
status = boardobj_construct_super(g, ppboardobj, size, pArgs);
if (status)
if (status) {
return status;
}
pvolt_policy = (struct voltage_policy *)*ppboardobj;
@@ -62,8 +63,9 @@ static u32 construct_volt_policy_split_rail(struct gk20a *g,
u32 status = 0;
status = construct_volt_policy(g, ppboardobj, size, pArgs);
if (status)
if (status) {
return status;
}
pvolt_policy = (struct voltage_policy_split_rail *)*ppboardobj;
@@ -86,8 +88,9 @@ static u32 construct_volt_policy_single_rail(struct gk20a *g,
u32 status = 0;
status = construct_volt_policy(g, ppboardobj, size, pArgs);
if (status)
if (status) {
return status;
}
pvolt_policy = (struct voltage_policy_single_rail *)*ppboardobj;
@@ -104,8 +107,9 @@ static u32 volt_policy_pmu_data_init_single_rail(struct gk20a *g,
struct nv_pmu_volt_volt_policy_sr_boardobj_set *pset;
status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata);
if (status)
if (status) {
goto done;
}
ppolicy = (struct voltage_policy_single_rail *)pboardobj;
pset = (struct nv_pmu_volt_volt_policy_sr_boardobj_set *)
@@ -124,8 +128,9 @@ static u32 volt_policy_pmu_data_init_sr_multi_step(struct gk20a *g,
struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set *pset;
status = volt_policy_pmu_data_init_single_rail(g, pboardobj, ppmudata);
if (status)
if (status) {
goto done;
}
ppolicy = (struct voltage_policy_single_rail_multi_step *)pboardobj;
pset = (struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set *)
@@ -149,8 +154,9 @@ static u32 volt_construct_volt_policy_single_rail_multi_step(struct gk20a *g,
u32 status = 0;
status = construct_volt_policy_single_rail(g, ppboardobj, size, pargs);
if (status)
if (status) {
return status;
}
pboardobj = (*ppboardobj);
p_volt_policy = (struct voltage_policy_single_rail_multi_step *)
@@ -176,8 +182,9 @@ static u32 volt_policy_pmu_data_init_split_rail(struct gk20a *g,
struct nv_pmu_volt_volt_policy_splt_r_boardobj_set *pset;
status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata);
if (status)
if (status) {
goto done;
}
ppolicy = (struct voltage_policy_split_rail *)pboardobj;
pset = (struct nv_pmu_volt_volt_policy_splt_r_boardobj_set *)
@@ -201,8 +208,9 @@ static u32 volt_construct_volt_policy_split_rail_single_step(struct gk20a *g,
u32 status = 0;
status = construct_volt_policy_split_rail(g, ppboardobj, size, pargs);
if (status)
if (status) {
return status;
}
pboardobj = (*ppboardobj);
pboardobj->pmudatainit = volt_policy_pmu_data_init_split_rail;
@@ -374,8 +382,9 @@ static u32 _volt_policy_devgrp_pmudata_instget(struct gk20a *g,
/*check whether pmuboardobjgrp has a valid boardobj in index*/
if (((u32)BIT(idx) &
pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) {
return -EINVAL;
}
*ppboardobjpmudata = (struct nv_pmu_boardobj *)
&pgrp_set->objects[idx].data.board_obj;
@@ -393,8 +402,9 @@ static u32 _volt_policy_devgrp_pmustatus_instget(struct gk20a *g,
/*check whether pmuboardobjgrp has a valid boardobj in index*/
if (((u32)BIT(idx) &
p_get_status->hdr.data.super.obj_mask.super.data[0]) == 0)
p_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) {
return -EINVAL;
}
*ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
&p_get_status->objects[idx].data.board_obj;
@@ -435,8 +445,9 @@ u32 volt_policy_pmu_setup(struct gk20a *g)
pboardobjgrp =
&g->perf_pmu.volt.volt_policy_metadata.volt_policies.super;
if (!pboardobjgrp->bconstructed)
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
}
status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
@@ -470,8 +481,9 @@ u32 volt_policy_sw_setup(struct gk20a *g)
/* Obtain Voltage Rail Table from VBIOS */
status = volt_get_volt_policy_table(g, &g->perf_pmu.volt.
volt_policy_metadata);
if (status)
if (status) {
goto done;
}
/* Populate data for the VOLT_RAIL PMU interface */
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_POLICY);

55
drivers/gpu/nvgpu/volt/volt_rail.c
View File

@@ -89,8 +89,9 @@ u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
volt_dev_idx);
exit:
if (status)
if (status) {
nvgpu_err(g, "Failed to register VOLTAGE_DEVICE");
}
return status;
}
@@ -138,8 +139,9 @@ static u32 volt_rail_init_pmudata_super(struct gk20a *g,
nvgpu_log_info(g, " ");
status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
if (status)
if (status) {
return status;
}
prail = (struct voltage_rail *)board_obj_ptr;
rail_pmu_data = (struct nv_pmu_volt_volt_rail_boardobj_set *)
@@ -166,9 +168,10 @@ static u32 volt_rail_init_pmudata_super(struct gk20a *g,
status = boardobjgrpmask_export(&prail->volt_dev_mask.super,
prail->volt_dev_mask.super.bitcount,
&rail_pmu_data->volt_dev_mask.super);
if (status)
if (status) {
nvgpu_err(g,
"Failed to export BOARDOBJGRPMASK of VOLTAGE_DEVICEs");
}
nvgpu_log_info(g, "Done");
@@ -185,8 +188,9 @@ static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs)
nvgpu_log_info(g, " ");
status = boardobj_construct_super(g, &board_obj_ptr,
sizeof(struct voltage_rail), pargs);
if (status)
if (status) {
return NULL;
}
board_obj_volt_rail_ptr = (struct voltage_rail *)board_obj_ptr;
/* override super class interface */
@@ -221,8 +225,9 @@ u8 volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
{
switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) {
case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
if (vbios_volt_domain == 0)
if (vbios_volt_domain == 0) {
return CTRL_VOLT_DOMAIN_LOGIC;
}
break;
case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL:
switch (vbios_volt_domain) {
@@ -246,8 +251,9 @@ u32 volt_rail_pmu_setup(struct gk20a *g)
pboardobjgrp = &g->perf_pmu.volt.volt_rail_metadata.volt_rails.super;
if (!pboardobjgrp->bconstructed)
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
}
status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
@@ -294,8 +300,9 @@ static u32 volt_get_volt_rail_table(struct gk20a *g,
volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g,
i);
if (volt_domain == CTRL_VOLT_DOMAIN_INVALID)
if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) {
continue;
}
rail_type_data.board_obj.type = volt_domain;
rail_type_data.volt_rail.boot_voltage_uv =
@@ -308,44 +315,49 @@ static u32 volt_get_volt_rail_table(struct gk20a *g,
(u8)entry.ov_limit_vfe_equ_idx;
if (header.table_entry_size >=
NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C)
NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C) {
rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx =
(u8)entry.volt_scale_exp_pwr_equ_idx;
else
} else {
rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx =
CTRL_BOARDOBJ_IDX_INVALID;
}
if (header.table_entry_size >=
NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B)
NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B) {
rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx =
(u8)entry.volt_margin_limit_vfe_equ_idx;
else
} else {
rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx =
CTRL_BOARDOBJ_IDX_INVALID;
}
if (header.table_entry_size >=
NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A)
NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A) {
rail_type_data.volt_rail.vmin_limit_vfe_equ_idx =
(u8)entry.vmin_limit_vfe_equ_idx;
else
} else {
rail_type_data.volt_rail.vmin_limit_vfe_equ_idx =
CTRL_BOARDOBJ_IDX_INVALID;
}
if (header.table_entry_size >=
NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09)
NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09) {
rail_type_data.volt_rail.boot_volt_vfe_equ_idx =
(u8)entry.boot_volt_vfe_equ_idx;
else
} else {
rail_type_data.volt_rail.boot_volt_vfe_equ_idx =
CTRL_BOARDOBJ_IDX_INVALID;
}
if (header.table_entry_size >=
NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08)
NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08) {
rail_type_data.volt_rail.pwr_equ_idx =
(u8)entry.pwr_equ_idx;
else
} else {
rail_type_data.volt_rail.pwr_equ_idx =
CTRL_PMGR_PWR_EQUATION_INDEX_INVALID;
}
prail = construct_volt_rail(g, &rail_type_data);
@@ -370,8 +382,9 @@ static u32 _volt_rail_devgrp_pmudata_instget(struct gk20a *g,
/*check whether pmuboardobjgrp has a valid boardobj in index*/
if (((u32)BIT(idx) &
pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) {
return -EINVAL;
}
*ppboardobjpmudata = (struct nv_pmu_boardobj *)
&pgrp_set->objects[idx].data.board_obj;
@@ -389,8 +402,9 @@ static u32 _volt_rail_devgrp_pmustatus_instget(struct gk20a *g,
/*check whether pmuboardobjgrp has a valid boardobj in index*/
if (((u32)BIT(idx) &
pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0)
pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) {
return -EINVAL;
}
*ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
&pgrp_get_status->objects[idx].data.board_obj;
@@ -426,8 +440,9 @@ u32 volt_rail_sw_setup(struct gk20a *g)
/* Obtain Voltage Rail Table from VBIOS */
status = volt_get_volt_rail_table(g, &g->perf_pmu.volt.
volt_rail_metadata);
if (status)
if (status) {
goto done;
}
/* Populate data for the VOLT_RAIL PMU interface */
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_RAIL);