gpu: nvgpu: volt: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.

JIRA NVGPU-671

Change-Id: I938f49b2d1d042dc96573e1a579fe82909a679ab
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812421
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Srirangan
2018-09-04 16:46:40 +05:30
committed by mobile promotions
parent 7405cd9a6d
commit 3b413d58fa
4 changed files with 107 additions and 57 deletions

View File

@@ -54,8 +54,9 @@ static void volt_rpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
return;
}
if (phandlerparams->prpc_call->b_supported)
if (phandlerparams->prpc_call->b_supported) {
phandlerparams->success = 1;
}
}
@@ -124,10 +125,11 @@ u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g)
rpc_call.function = NV_PMU_VOLT_RPC_ID_LOAD;
status = volt_pmu_rpc_execute(g, &rpc_call);
if (status)
if (status) {
nvgpu_err(g,
"Error while executing LOAD RPC: status = 0x%08x.",
status);
}
return status;
}
@@ -241,9 +243,10 @@ static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id,
}
/* Convert the client ID to index. */
if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ)
if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ) {
policy_idx =
pvolt->volt_policy_metadata.perf_core_vf_seq_policy_idx;
}
else {
status = -EINVAL;
goto exit;
@@ -257,9 +260,10 @@ static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id,
/* Execute the voltage change request via PMU RPC. */
status = volt_pmu_rpc_execute(g, &rpc_call);
if (status)
if (status) {
nvgpu_err(g,
"Error while executing VOLT_POLICY_SET_VOLTAGE RPC");
}
exit:
return status;