From 3b9630a3661fdbb48f48ea53bc1950be3150dcc0 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Wed, 15 Jan 2020 15:16:20 -0800 Subject: [PATCH] gpu: nvgpu: fuse: use hals instead of direct register reads Use fuse hals instead of direct fuse register reads to make code compatible with multiple chip families. JIRA NVGPU-4663 JIRA NVGPU-4835 JIRA NVGPU-4856 Change-Id: I15889aee38baf6393d11becb7ed995e9f0fd5897 Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279629 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Seema Khowala Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/fuse/fuse_gp10b_fusa.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/fuse/fuse_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/fuse/fuse_gp10b_fusa.c index f87b8b54f..7e81bb4c0 100644 --- a/drivers/gpu/nvgpu/hal/fuse/fuse_gp10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fuse/fuse_gp10b_fusa.c @@ -53,7 +53,7 @@ int gp10b_fuse_check_priv_security(struct gk20a *g) return -EINVAL; } - if (nvgpu_readl(g, fuse_opt_priv_sec_en_r()) != 0U) { + if (g->ops.fuse.fuse_opt_priv_sec_en(g) != 0U) { /* * all falcons have to boot in LS mode and this needs * wpr_enabled set to 1 and vpr_auto_fetch_disable @@ -67,7 +67,7 @@ int gp10b_fuse_check_priv_security(struct gk20a *g) is_auto_fetch_disable = (gcplex_config & GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK) != 0U; if (is_wpr_enabled && !is_auto_fetch_disable) { - if (nvgpu_readl(g, fuse_opt_sec_debug_en_r()) != 0U) { + if (g->ops.fuse.fuse_opt_sec_debug_en(g) != 0U) { nvgpu_log(g, gpu_dbg_info, "gcplex_config = 0x%08x, " "secure mode: ACR debug",