From 3c44590b58ff10cd48b6982d2daf097d5eb85cea Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 17 May 2018 11:26:12 -0700 Subject: [PATCH] gpu: nvgpu: dump eng id and status upon timeout Dump eng id and fifo_engine_status if eng fails to idle. This change is helpful for debugging issues where engine is not getting idle or intermittently getting idle due to bad settings of registers in hals set by init_therm_setup_hw and elcg_init_idle_filters Bug 2115080 Change-Id: I4c6d144d3fc575db3f30596de6e536fd07753789 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1722194 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 3f02132b3..1b6284fd1 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -3685,8 +3685,8 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g) { struct nvgpu_timeout timeout; u32 delay = GR_IDLE_CHECK_DEFAULT; - int ret = -ETIMEDOUT; - u32 i, host_num_engines; + int ret = 0; + u32 i, host_num_engines, status; nvgpu_log_fn(g, " "); @@ -3697,8 +3697,9 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g) NVGPU_TIMER_CPU_TIMER); for (i = 0; i < host_num_engines; i++) { + ret = -ETIMEDOUT; do { - u32 status = gk20a_readl(g, fifo_engine_status_r(i)); + status = gk20a_readl(g, fifo_engine_status_r(i)); if (fifo_engine_status_engine_v(status) == fifo_engine_status_engine_idle_v()) { ret = 0; @@ -3711,7 +3712,12 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g) } while (nvgpu_timeout_expired(&timeout) == 0); if (ret != 0) { - nvgpu_log_info(g, "cannot idle engine %u", i); + /* possible causes: + * check register settings programmed in hal set by + * elcg_init_idle_filters and init_therm_setup_hw + */ + nvgpu_err(g, "cannot idle engine: %u " + "engine_status: 0x%08x", i, status); break; } }