gpu: nvgpu: move usermode to hal/fifo

Moved the following HALs from fifo to usermode
- fifo.ring_channel_doorbell -> usermode.ring_doorbell
- fifo.doorbell_token -> usermode.doorbell_token
- fifo.usermode_base -> usermode.base

Created the following HAL
- usermode.setup_hw

Jira NVGPU-2978

Change-Id: I856ea24c126fa22d2f3fe860d4b14087c6d7330b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094813
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -235,6 +235,8 @@ nvgpu-y += \
 	hal/fuse/fuse_gm20b.o \
 	hal/fuse/fuse_gp10b.o \
 	hal/fuse/fuse_gp106.o \
+	hal/fifo/usermode_gv11b.o \
+	hal/fifo/usermode_tu104.o \
 	hal/fifo/engines_gm20b.o \
 	hal/fifo/engines_gp10b.o \
 	hal/fifo/engines_gv11b.o \
@@ -392,8 +394,7 @@ endif
 
 nvgpu-$(CONFIG_GK20A_PCI) += \
 	os/linux/pci.o \
-	os/linux/pci_power.o \
+	os/linux/pci_power.o
-	os/linux/pci_usermode.o
 
 nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += \
 	os/linux/nvhost.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -356,6 +356,8 @@ srcs += common/sim.c \
 	hal/fuse/fuse_gm20b.c \
 	hal/fuse/fuse_gp10b.c \
 	hal/fuse/fuse_gp106.c \
+	hal/fifo/usermode_gv11b.c \
+	hal/fifo/usermode_tu104.c \
 	hal/fifo/engines_gm20b.c \
 	hal/fifo/engines_gp10b.c \
 	hal/fifo/engines_gv11b.c \

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -36,6 +36,7 @@
 #include "hal/fifo/tsg_gv11b.h"
 #include "hal/fifo/userd_gk20a.h"
 #include "hal/fifo/userd_gv11b.h"
+#include "hal/fifo/usermode_gv11b.h"
 #include "hal/fifo/fifo_intr_gv11b.h"
 #include "hal/therm/therm_gm20b.h"
 #include "hal/therm/therm_gp10b.h"
@@ -508,10 +509,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.teardown_ch_tsg = NULL,
 		.setup_sw = vgpu_fifo_setup_sw,
 		.cleanup_sw = vgpu_fifo_cleanup_sw,
-		.ring_channel_doorbell = gv11b_ring_channel_doorbell,
 		.set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask,
-		.usermode_base = gv11b_fifo_usermode_base,
-		.doorbell_token = gv11b_fifo_doorbell_token,
 		.intr_0_enable = NULL,
 		.intr_1_enable = NULL,
 		.intr_0_isr = NULL,
@@ -650,6 +648,13 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.force_reset = vgpu_tsg_force_reset_ch,
 		.post_event_id = nvgpu_tsg_post_event_id,
 	},
+	.usermode = {
+		.setup_hw = NULL,
+		.base = gv11b_usermode_base,
+		.bus_base = gv11b_usermode_bus_base,
+		.ring_doorbell = gv11b_usermode_ring_doorbell,
+		.doorbell_token = gv11b_usermode_doorbell_token,
+	},
 	.netlist = {
 		.get_netlist_name = gv11b_netlist_get_name,
 		.is_fw_defined = gv11b_netlist_is_firmware_defined,
@@ -870,6 +875,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
 	gops->userd = vgpu_gv11b_ops.userd;
 	gops->channel = vgpu_gv11b_ops.channel;
 	gops->tsg = vgpu_gv11b_ops.tsg;
+	gops->usermode = vgpu_gv11b_ops.usermode;
 	gops->sync = vgpu_gv11b_ops.sync;
 	gops->engine_status = vgpu_gv11b_ops.engine_status;
 	gops->pbdma_status = vgpu_gv11b_ops.pbdma_status;

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -74,6 +74,7 @@
 #include "hal/fifo/tsg_gv11b.h"
 #include "hal/fifo/userd_gk20a.h"
 #include "hal/fifo/userd_gv11b.h"
+#include "hal/fifo/usermode_gv11b.h"
 #include "hal/fifo/fifo_intr_gk20a.h"
 #include "hal/fifo/fifo_intr_gv11b.h"
 #include "hal/fifo/ctxsw_timeout_gk20a.h"
@@ -919,10 +920,7 @@ static const struct gpu_ops gv100_ops = {
 		.teardown_unmask_intr = gv100_fifo_teardown_unmask_intr,
 		.setup_sw = nvgpu_fifo_setup_sw,
 		.cleanup_sw = nvgpu_fifo_cleanup_sw,
-		.ring_channel_doorbell = gv11b_ring_channel_doorbell,
 		.set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask,
-		.usermode_base = gv11b_fifo_usermode_base,
-		.doorbell_token = gv11b_fifo_doorbell_token,
 		.runlist_busy_engines = gk20a_fifo_runlist_busy_engines,
 		.intr_0_enable = gk20a_fifo_intr_0_enable,
 		.intr_1_enable = gk20a_fifo_intr_1_enable,
@@ -1075,6 +1073,13 @@ static const struct gpu_ops gv100_ops = {
 		.force_reset = nvgpu_tsg_force_reset_ch,
 		.post_event_id = nvgpu_tsg_post_event_id,
 	},
+	.usermode = {
+		.setup_hw = NULL,
+		.base = gv11b_usermode_base,
+		.bus_base = gv11b_usermode_bus_base,
+		.ring_doorbell = gv11b_usermode_ring_doorbell,
+		.doorbell_token = gv11b_usermode_doorbell_token,
+	},
 	.netlist = {
 		.get_netlist_name = gv100_netlist_get_name,
 		.is_fw_defined = gv100_netlist_is_firmware_defined,
@@ -1448,6 +1453,7 @@ int gv100_init_hal(struct gk20a *g)
 	gops->userd = gv100_ops.userd;
 	gops->channel = gv100_ops.channel;
 	gops->tsg = gv100_ops.tsg;
+	gops->usermode = gv100_ops.usermode;
 	gops->sync = gv100_ops.sync;
 	gops->engine_status = gv100_ops.engine_status;
 	gops->pbdma_status = gv100_ops.pbdma_status;

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -57,38 +57,12 @@
 #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_top_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
 
 #include "fifo_gv11b.h"
 #include "gr_gv11b.h"
 
-u64 gv11b_fifo_usermode_base(struct gk20a *g)
-{
-	return usermode_cfg0_r();
-}
-
-u32 gv11b_fifo_doorbell_token(struct channel_gk20a *c)
-{
-	struct gk20a *g = c->g;
-	struct fifo_gk20a *f = &g->fifo;
-
-	return f->channel_base + c->chid;
-}
-
-void gv11b_ring_channel_doorbell(struct channel_gk20a *c)
-{
-	struct gk20a *g = c->g;
-	struct fifo_gk20a *f = &g->fifo;
-	u32 hw_chid = f->channel_base + c->chid;
-
-	nvgpu_log_info(g, "channel ring door bell %d\n", c->chid);
-
-	nvgpu_usermode_writel(c->g, usermode_notify_channel_pending_r(),
-		usermode_notify_channel_pending_id_f(hw_chid));
-}
-
 u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g)
 {
 	/* using gr_idle_timeout for polling pdma/eng/runlist

drivers/gpu/nvgpu/gv11b/fifo_gv11b.h

@@ -57,7 +57,4 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g);
 
 u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g);
 
-void gv11b_ring_channel_doorbell(struct channel_gk20a *c);
-u64 gv11b_fifo_usermode_base(struct gk20a *g);
-u32 gv11b_fifo_doorbell_token(struct channel_gk20a *c);
 #endif

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -77,6 +77,7 @@
 #include "hal/fifo/tsg_gv11b.h"
 #include "hal/fifo/userd_gk20a.h"
 #include "hal/fifo/userd_gv11b.h"
+#include "hal/fifo/usermode_gv11b.h"
 #include "hal/fifo/fifo_intr_gk20a.h"
 #include "hal/fifo/fifo_intr_gv11b.h"
 #include "hal/fifo/ctxsw_timeout_gv11b.h"
@@ -893,10 +894,7 @@ static const struct gpu_ops gv11b_ops = {
 		.teardown_unmask_intr = gv11b_fifo_teardown_unmask_intr,
 		.setup_sw = nvgpu_fifo_setup_sw,
 		.cleanup_sw = nvgpu_fifo_cleanup_sw,
-		.ring_channel_doorbell = gv11b_ring_channel_doorbell,
 		.set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask,
-		.usermode_base = gv11b_fifo_usermode_base,
-		.doorbell_token = gv11b_fifo_doorbell_token,
 		.runlist_busy_engines = gk20a_fifo_runlist_busy_engines,
 		.intr_0_enable = gv11b_fifo_intr_0_enable,
 		.intr_1_enable = gk20a_fifo_intr_1_enable,
@@ -1051,6 +1049,13 @@ static const struct gpu_ops gv11b_ops = {
 		.force_reset = nvgpu_tsg_force_reset_ch,
 		.post_event_id = nvgpu_tsg_post_event_id,
 	},
+	.usermode = {
+		.setup_hw = NULL,
+		.base = gv11b_usermode_base,
+		.bus_base = gv11b_usermode_bus_base,
+		.ring_doorbell = gv11b_usermode_ring_doorbell,
+		.doorbell_token = gv11b_usermode_doorbell_token,
+	},
 	.netlist = {
 		.get_netlist_name = gv11b_netlist_get_name,
 		.is_fw_defined = gv11b_netlist_is_firmware_defined,
@@ -1348,6 +1353,7 @@ int gv11b_init_hal(struct gk20a *g)
 	gops->userd = gv11b_ops.userd;
 	gops->channel = gv11b_ops.channel;
 	gops->tsg = gv11b_ops.tsg;
+	gops->usermode = gv11b_ops.usermode;
 	gops->sync = gv11b_ops.sync;
 	gops->engine_status = gv11b_ops.engine_status;
 	gops->pbdma_status = gv11b_ops.pbdma_status;

drivers/gpu/nvgpu/hal/fifo/tsg_gv11b.c

@@ -49,7 +49,7 @@ void gv11b_tsg_enable(struct tsg_gk20a *tsg)
 	nvgpu_rwsem_up_read(&tsg->ch_list_lock);
 
 	if (last_ch != NULL) {
-		g->ops.fifo.ring_channel_doorbell(last_ch);
+		g->ops.usermode.ring_doorbell(last_ch);
 	}
 }
 

drivers/gpu/nvgpu/hal/fifo/userd_gv11b.c

@@ -60,5 +60,5 @@ void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *ch)
 	/* Commit everything to GPU. */
 	nvgpu_mb();
 
-	g->ops.fifo.ring_channel_doorbell(ch);
+	g->ops.usermode.ring_doorbell(ch);
 }

drivers/gpu/nvgpu/hal/fifo/usermode_gv11b.c

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/io_usermode.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/fifo.h>
+
+#include "usermode_gv11b.h"
+
+#include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
+
+u64 gv11b_usermode_base(struct gk20a *g)
+{
+	return usermode_cfg0_r();
+}
+
+u64 gv11b_usermode_bus_base(struct gk20a *g)
+{
+	return usermode_cfg0_r();
+}
+
+u32 gv11b_usermode_doorbell_token(struct channel_gk20a *ch)
+{
+	struct gk20a *g = ch->g;
+	struct fifo_gk20a *f = &g->fifo;
+	u32 hw_chid = f->channel_base + ch->chid;
+
+	return usermode_notify_channel_pending_id_f(hw_chid);
+}
+
+void gv11b_usermode_ring_doorbell(struct channel_gk20a *ch)
+{
+	nvgpu_log_info(ch->g, "channel ring door bell %d", ch->chid);
+
+	nvgpu_usermode_writel(ch->g, usermode_notify_channel_pending_r(),
+		gv11b_usermode_doorbell_token(ch));
+}

drivers/gpu/nvgpu/hal/fifo/usermode_gv11b.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_USERMODE_GV11B_H
+#define NVGPU_USERMODE_GV11B_H
+
+#include <nvgpu/types.h>
+
+struct channel_gk20a;
+
+u64 gv11b_usermode_base(struct gk20a *g);
+u64 gv11b_usermode_bus_base(struct gk20a *g);
+u32 gv11b_usermode_doorbell_token(struct channel_gk20a *ch);
+void gv11b_usermode_ring_doorbell(struct channel_gk20a *ch);
+
+#endif /* NVGPU_USERMODE_GV11B_H */

drivers/gpu/nvgpu/hal/fifo/usermode_tu104.c

@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/io.h>
+#include <nvgpu/log.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/channel.h>
+
+#include "usermode_tu104.h"
+
+#include "tu104/func_tu104.h"
+
+#include <nvgpu/hw/tu104/hw_usermode_tu104.h>
+#include <nvgpu/hw/tu104/hw_ctrl_tu104.h>
+#include <nvgpu/hw/tu104/hw_func_tu104.h>
+
+u64 tu104_usermode_base(struct gk20a *g)
+{
+	return usermode_cfg0_r();
+}
+
+u64 tu104_usermode_bus_base(struct gk20a *g)
+{
+	return U64(func_full_phys_offset_v() + func_cfg0_r());
+}
+
+void tu104_usermode_setup_hw(struct gk20a *g)
+{
+	u32 val;
+
+	val = nvgpu_readl(g, ctrl_virtual_channel_cfg_r(0));
+	val |= ctrl_virtual_channel_cfg_pending_enable_true_f();
+	nvgpu_writel(g, ctrl_virtual_channel_cfg_r(0), val);
+}
+
+u32 tu104_usermode_doorbell_token(struct channel_gk20a *ch)
+{
+	struct gk20a *g = ch->g;
+	struct fifo_gk20a *f = &g->fifo;
+	u32 hw_chid = f->channel_base + ch->chid;
+
+	return ctrl_doorbell_vector_f(hw_chid) |
+			ctrl_doorbell_runlist_id_f(ch->runlist_id);
+}
+
+void tu104_usermode_ring_doorbell(struct channel_gk20a *ch)
+{
+	nvgpu_log_info(ch->g, "channel ring door bell %d, runlist %d",
+			ch->chid, ch->runlist_id);
+
+	nvgpu_func_writel(ch->g, func_doorbell_r(),
+			tu104_usermode_doorbell_token(ch));
+}

drivers/gpu/nvgpu/hal/fifo/usermode_tu104.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_USERMODE_TU104_H
+#define NVGPU_USERMODE_TU104_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct channel_gk20a;
+
+u64 tu104_usermode_base(struct gk20a *g);
+u64 tu104_usermode_bus_base(struct gk20a *g);
+void tu104_usermode_setup_hw(struct gk20a *g);
+u32 tu104_usermode_doorbell_token(struct channel_gk20a *ch);
+void tu104_usermode_ring_doorbell(struct channel_gk20a *ch);
+
+#endif /* NVGPU_USERMODE_TU104_H */

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -986,9 +986,6 @@ struct gpu_ops {
 		void (*teardown_mask_intr)(struct gk20a *g);
 		void (*teardown_unmask_intr)(struct gk20a *g);
 		u32 (*get_preempt_timeout)(struct gk20a *g);
-		void (*ring_channel_doorbell)(struct channel_gk20a *c);
-		u64 (*usermode_base)(struct gk20a *g);
-		u32 (*doorbell_token)(struct channel_gk20a *c);
 		int (*init_pdb_cache_war)(struct gk20a *g);
 		void (*deinit_pdb_cache_war)(struct gk20a *g);
 		int (*set_sm_exception_type_mask)(struct channel_gk20a *ch,
@@ -1198,6 +1195,13 @@ struct gpu_ops {
 					u32 err_code, bool verbose);
 		void (*post_event_id)(struct tsg_gk20a *tsg, int event_id);
 	} tsg;
+	struct {
+		void (*setup_hw)(struct gk20a *g);
+		void (*ring_doorbell)(struct channel_gk20a *ch);
+		u32 (*doorbell_token)(struct channel_gk20a *ch);
+		u64 (*base)(struct gk20a *g);
+		u64 (*bus_base)(struct gk20a *g);
+	} usermode;
 	struct {
 		void (*read_engine_status_info) (struct gk20a *g,
 			u32 engine_id, struct nvgpu_engine_status_info *status);

drivers/gpu/nvgpu/os/linux/io_usermode.c

@@ -17,12 +17,10 @@
 
 #include "os_linux.h"
 
-#include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
-
 void nvgpu_usermode_writel(struct gk20a *g, u32 r, u32 v)
 {
 	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
-	void __iomem *reg = l->usermode_regs + (r - usermode_cfg0_r());
+	void __iomem *reg = l->usermode_regs + (r - g->ops.usermode.base(g));
 
 	writel_relaxed(v, reg);
 	nvgpu_log(g, gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v);

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -1985,7 +1985,7 @@ int gk20a_ctrl_dev_mmap(struct file *filp, struct vm_area_struct *vma)
 	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
 	int err;
 
-	if (g->ops.fifo.usermode_base == NULL)
+	if (g->ops.usermode.base == NULL)
 		return -ENOSYS;
 
 	if (priv->usermode_vma.vma != NULL)

drivers/gpu/nvgpu/os/linux/linux-channel.c

@@ -512,7 +512,7 @@ static int nvgpu_channel_alloc_usermode_buffers(struct channel_gk20a *c,
 		goto unmap_free_gpfifo;
 	}
 
-	args->work_submit_token = g->ops.fifo.doorbell_token(c);
+	args->work_submit_token = g->ops.usermode.doorbell_token(c);
 
 	return 0;
 unmap_free_gpfifo:

drivers/gpu/nvgpu/os/linux/module.c

@@ -335,15 +335,7 @@ int gk20a_pm_finalize_poweron(struct device *dev)
 	if (err)
 		goto done;
 
-	if (g->ops.fifo.usermode_base != NULL) {
+	nvgpu_init_usermode_support(g);
-		/*
-		 * Native has regs_bus_addr set but not this one yet. Virtual
-		 * gets usermode_regs_bus_addr directly from chip-specific
-		 * probe, and regs_bus_addr stays unset.
-		 */
-		l->usermode_regs_bus_addr = l->regs_bus_addr +
-			g->ops.fifo.usermode_base(g);
-	}
 
 	err = nvgpu_finalize_poweron_linux(l);
 	if (err)

drivers/gpu/nvgpu/os/linux/module_usermode.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,8 +16,6 @@
 
 #include <nvgpu/types.h>
 
-#include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
-
 #include "os_linux.h"
 
 /*
@@ -57,6 +55,15 @@ void nvgpu_init_usermode_support(struct gk20a *g)
 {
 	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
 
-	l->usermode_regs = l->regs + usermode_cfg0_r();
+	if (g->ops.usermode.base == NULL) {
-	l->usermode_regs_saved = l->usermode_regs;
+		return;
+	}
+
+	if (l->usermode_regs == NULL) {
+		l->usermode_regs = l->regs + g->ops.usermode.base(g);
+		l->usermode_regs_saved = l->usermode_regs;
+	}
+
+	l->usermode_regs_bus_addr = l->regs_bus_addr +
+					g->ops.usermode.bus_base(g);
 }

drivers/gpu/nvgpu/os/linux/pci.c

@@ -39,7 +39,6 @@
 
 #include "pci.h"
 #include "pci_power.h"
-#include "pci_usermode.h"
 
 #include "driver_common.h"
 
@@ -412,8 +411,6 @@ static int nvgpu_pci_init_support(struct pci_dev *pdev)
 	if (err)
 		goto fail_sim;
 
-	nvgpu_pci_init_usermode_support(l);
-
 	return 0;
 
  fail_sim:

drivers/gpu/nvgpu/os/linux/pci_usermode.c

@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-
-#include <nvgpu/types.h>
-
-#include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
-
-#include "os_linux.h"
-
-void nvgpu_pci_init_usermode_support(struct nvgpu_os_linux *l)
-{
-	l->usermode_regs = l->regs + usermode_cfg0_r();
-	l->usermode_regs_saved = l->usermode_regs;
-}

drivers/gpu/nvgpu/os/linux/pci_usermode.h

@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef __NVGPU_PCI_USERMODE_H__
-#define __NVGPU_PCI_USERMODE_H__
-
-struct nvgpu_os_linux;
-
-void nvgpu_pci_init_usermode_support(struct nvgpu_os_linux *l);
-
-#endif

drivers/gpu/nvgpu/tu104/fifo_tu104.c

@@ -39,53 +39,16 @@
 #include <nvgpu/hw/tu104/hw_fifo_tu104.h>
 #include <nvgpu/hw/tu104/hw_pbdma_tu104.h>
 #include <nvgpu/hw/tu104/hw_ram_tu104.h>
-#include <nvgpu/hw/tu104/hw_func_tu104.h>
-#include <nvgpu/hw/tu104/hw_ctrl_tu104.h>
 
 int tu104_init_fifo_setup_hw(struct gk20a *g)
 {
-	u32 val;
-
 	nvgpu_log_fn(g, " ");
 
-	/*
+	g->ops.usermode.setup_hw(g);
-	 * Required settings for tu104_ring_channel_doorbell()
-	 */
-	val = nvgpu_readl(g, ctrl_virtual_channel_cfg_r(0));
-	val |= ctrl_virtual_channel_cfg_pending_enable_true_f();
-	nvgpu_writel(g, ctrl_virtual_channel_cfg_r(0), val);
 
 	return gv11b_init_fifo_setup_hw(g);
 }
 
-void tu104_ring_channel_doorbell(struct channel_gk20a *c)
-{
-	struct fifo_gk20a *f = &c->g->fifo;
-	u32 hw_chid = f->channel_base + c->chid;
-
-	nvgpu_log_info(c->g, "channel ring door bell %d, runlist %d",
-		c->chid, c->runlist_id);
-
-	nvgpu_func_writel(c->g, func_doorbell_r(),
-		ctrl_doorbell_vector_f(hw_chid) |
-		ctrl_doorbell_runlist_id_f(c->runlist_id));
-}
-
-u64 tu104_fifo_usermode_base(struct gk20a *g)
-{
-	return U64(func_full_phys_offset_v()) + func_cfg0_r();
-}
-
-u32 tu104_fifo_doorbell_token(struct channel_gk20a *c)
-{
-	struct gk20a *g = c->g;
-	struct fifo_gk20a *f = &g->fifo;
-	u32 hw_chid = f->channel_base + c->chid;
-
-	return ctrl_doorbell_vector_f(hw_chid) |
-		ctrl_doorbell_runlist_id_f(c->runlist_id);
-}
-
 int tu104_init_pdb_cache_war(struct gk20a *g)
 {
 	u32 size = PAGE_SIZE * 258U;

drivers/gpu/nvgpu/tu104/fifo_tu104.h

@@ -29,9 +29,6 @@ struct gk20a;
 struct channel_gk20a;
 
 int tu104_init_fifo_setup_hw(struct gk20a *g);
-void tu104_ring_channel_doorbell(struct channel_gk20a *ch);
-u64 tu104_fifo_usermode_base(struct gk20a *g);
-u32 tu104_fifo_doorbell_token(struct channel_gk20a *c);
 
 int tu104_init_pdb_cache_war(struct gk20a *g);
 void tu104_deinit_pdb_cache_war(struct gk20a *g);

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -59,6 +59,8 @@
 #include "hal/fuse/fuse_gm20b.h"
 #include "hal/fuse/fuse_gp10b.h"
 #include "hal/fuse/fuse_gp106.h"
+#include "hal/fifo/usermode_gv11b.h"
+#include "hal/fifo/usermode_tu104.h"
 #include "hal/fifo/pbdma_gm20b.h"
 #include "hal/fifo/pbdma_gp10b.h"
 #include "hal/fifo/pbdma_gv11b.h"
@@ -954,9 +956,6 @@ static const struct gpu_ops tu104_ops = {
 		.teardown_unmask_intr = gv11b_fifo_teardown_unmask_intr,
 		.setup_sw = nvgpu_fifo_setup_sw,
 		.cleanup_sw = nvgpu_fifo_cleanup_sw,
-		.ring_channel_doorbell = tu104_ring_channel_doorbell,
-		.usermode_base = tu104_fifo_usermode_base,
-		.doorbell_token = tu104_fifo_doorbell_token,
 		.init_pdb_cache_war = tu104_init_pdb_cache_war,
 		.deinit_pdb_cache_war = tu104_deinit_pdb_cache_war,
 		.set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask,
@@ -1112,6 +1111,13 @@ static const struct gpu_ops tu104_ops = {
 		.force_reset = nvgpu_tsg_force_reset_ch,
 		.post_event_id = nvgpu_tsg_post_event_id,
 	},
+	.usermode = {
+		.setup_hw = tu104_usermode_setup_hw,
+		.base = tu104_usermode_base,
+		.bus_base = tu104_usermode_bus_base,
+		.ring_doorbell = tu104_usermode_ring_doorbell,
+		.doorbell_token = tu104_usermode_doorbell_token,
+	},
 	.netlist = {
 		.get_netlist_name = tu104_netlist_get_name,
 		.is_fw_defined = tu104_netlist_is_firmware_defined,
@@ -1496,6 +1502,7 @@ int tu104_init_hal(struct gk20a *g)
 	gops->userd = tu104_ops.userd;
 	gops->channel = tu104_ops.channel;
 	gops->tsg = tu104_ops.tsg;
+	gops->usermode = tu104_ops.usermode;
 	gops->sync = tu104_ops.sync;
 	gops->engine_status = tu104_ops.engine_status;
 	gops->pbdma_status = tu104_ops.pbdma_status;