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gpu: nvgpu: disable cg in mmu error handler

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With CG enabled sometimes fifo could not be idled
during firmware load.

Bug 200042729

Change-Id: I43d7551c0c7c19314c52ac5f678afed8c6df6415
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/559077
Reviewed-by: Automatic_Commit_Validation_User
This commit is contained in:
Vijayakumar
2014-10-18 19:22:51 +05:30
committed by Dan Willemsen
parent 5febd08ae7
commit 3c6a6376de
2 changed files with 44 additions and 22 deletions
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10
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -973,8 +973,16 @@ static bool gk20a_fifo_handle_mmu_fault(struct gk20a *g)
g->fifo.deferred_reset_pending = false;
/* Disable ELPG */
/* Disable power management */
gk20a_pmu_disable_elpg(g);
g->ops.clock_gating.slcg_gr_load_gating_prod(g,
false);
g->ops.clock_gating.slcg_perf_load_gating_prod(g,
false);
g->ops.clock_gating.slcg_ltc_load_gating_prod(g,
false);
gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_GR_GK20A);
gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_CE2_GK20A);
/* Disable fifo access */
grfifo_ctl = gk20a_readl(g, gr_gpfifo_ctl_r());