nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: vgpu: remove PMU setup in gv11b hal

Browse Source 
vgpu doesn't care about pmu. pmu is managed by RM server.
It also fixed the dump caused by reading fuse register.

Jira EVLR-1934

Change-Id: I779964950783ccf699cd99473fb30e811c5c2ed6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612774
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Richard Zhao
2017-12-06 16:25:21 -08:00
committed by mobile promotions
parent 258ae44712
commit 3cb9cd5267
1 changed files with 0 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -559,8 +559,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
int vgpu_gv11b_init_hal(struct gk20a *g)
{
struct gpu_ops *gops = &g->ops;
u32 val;
bool priv_security;
gops->ltc = vgpu_gv11b_ops.ltc;
gops->ce2 = vgpu_gv11b_ops.ce2;
@@ -589,55 +587,6 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
vgpu_gv11b_ops.chip_init_gpu_characteristics;
gops->get_litter_value = vgpu_gv11b_ops.get_litter_value;
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
if (val) {
priv_security = true;
pr_err("priv security is enabled\n");
} else {
priv_security = false;
pr_err("priv security is disabled\n");
}
__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security);
/* priv security dependent ops */
if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
/* Add in ops from gm20b acr */
gops->pmu.prepare_ucode = gp106_prepare_ucode_blob,
gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn,
gops->pmu.get_wpr = gm20b_wpr_info,
gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
gops->pmu.pmu_populate_loader_cfg =
gp106_pmu_populate_loader_cfg,
gops->pmu.flcn_populate_bl_dmem_desc =
gp106_flcn_populate_bl_dmem_desc,
gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
gops->pmu.falcon_clear_halt_interrupt_status =
clear_halt_interrupt_status,
gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1,
gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap,
gops->pmu.is_priv_load = gv11b_is_priv_load,
gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
} else {
/* Inherit from gk20a */
gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
gops->pmu.load_lsfalcon_ucode = NULL;
gops->pmu.init_wpr_region = NULL;
gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
}
__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
g->name = "gv11b";
return 0;