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gpu: nvgpu: expose physical masks for GPCS/FBPs for MIG

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Following changes are added
1) nvgpu_gr_config->gpc_tpc_mask_physical is now indexed by physical
gpc id instead of logical id.
2) Removed the conversion of logical fbp ids and replace them with
physical ids.
3) nvgpu_gpu_instance->fbp_en_mask now contains the mask of physical fbp ids.
4) gk20a_ctrl_ioctl_gpu_characteristics returns gpu.gpc_mask returns mask
of physical ids.

Bug 200712091

Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I0e066df76e07203ff4a5be5bfff2cef8566b425d
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2648831
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Debarshi Dutta
2022-01-06 15:52:54 +05:30
committed by mobile promotions
parent 2373a87048
commit 3d01b89e68
5 changed files with 25 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/nvgpu/common/gr/gr_config.c
View File

@@ -331,7 +331,6 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g)
u32 cur_gr_instance = nvgpu_gr_get_cur_instance_id(g);
u32 gpc_index;
u32 gpc_phys_id;
u32 gpc_id;
int err;
config = nvgpu_kzalloc(g, sizeof(*config));
@@ -391,19 +390,9 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g)
gpc_phys_id = nvgpu_grmgr_get_gr_gpc_phys_id(g,
cur_gr_instance, gpc_index);
/*
* The gpc_tpc_mask_physical masks are ordered by gpc_id.
* Where gpc_id = gpc_logical_id when MIG=true, else
* gpc_physical_id.
*/
gpc_id = gpc_phys_id;
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
gpc_id = nvgpu_grmgr_get_gr_gpc_logical_id(g,
cur_gr_instance, gpc_index);
}
config->gpc_tpc_mask[gpc_index] =
g->ops.gr.config.get_gpc_tpc_mask(g, config, gpc_phys_id);
config->gpc_tpc_mask_physical[gpc_id] =
config->gpc_tpc_mask_physical[gpc_phys_id] =
g->ops.gr.config.get_gpc_tpc_mask(g, config, gpc_phys_id);
}

7
drivers/gpu/nvgpu/common/gr/gr_config_priv.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -128,13 +128,12 @@ struct nvgpu_gr_config {
/**
* Array to hold mask of TPCs per GPC.
* Array is indexed by GPC logical index.
* Array is indexed by GPC logical index/local IDs when using MIG mode
*/
u32 *gpc_tpc_mask;
/**
* Array to hold mask of TPCs per GPC.
* Array is indexed by GPC physical-id in non-MIG(legacy) mode and by
* logical-id in MIG mode.
* Array is indexed by GPC physical-id.
*/
u32 *gpc_tpc_mask_physical;
/**

27
drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
View File

@@ -295,8 +295,6 @@ static int ga10b_grmgr_get_gpu_instance(struct gk20a *g,
u32 allowed_swizzid_size = g->ops.grmgr.get_allowed_swizzid_size(g);
u32 max_subctx_count = g->ops.gr.init.get_max_subctx_count();
u32 max_fbps_count = g->mig.max_fbps_count;
u32 physical_fbp_en_mask = g->mig.gpu_instance[0].fbp_en_mask;
u32 *physical_fbp_l2_en_mask = g->mig.gpu_instance[0].fbp_l2_en_mask;
if ((mig_gpu_instance_config == NULL) || (num_gpc > NVGPU_MIG_MAX_GPCS)) {
nvgpu_err(g,"mig_gpu_instance_config NULL "
@@ -576,28 +574,11 @@ static int ga10b_grmgr_get_gpu_instance(struct gk20a *g,
}
if (gpu_instance[index].is_memory_partition_supported == false) {
u32 physical_fb_id, logical_fb_id;
u32 *logical_fbp_l2_en_mask =
gpu_instance[index].fbp_l2_en_mask;
gpu_instance[index].num_fbp = g->mig.gpu_instance[0].num_fbp;
gpu_instance[index].fbp_en_mask =
nvgpu_safe_sub_u32(BIT32(gpu_instance[index].num_fbp), 1U);
/* Convert physical to logical FBP mask order */
for (logical_fb_id = 0U, physical_fb_id = 0U;
((logical_fb_id < gpu_instance[index].num_fbp) &&
(physical_fb_id < max_fbps_count));
++physical_fb_id) {
if (physical_fbp_en_mask & BIT32(physical_fb_id)) {
logical_fbp_l2_en_mask[logical_fb_id] =
physical_fbp_l2_en_mask[physical_fb_id];
++logical_fb_id;
}
}
nvgpu_assert(logical_fb_id == gpu_instance[index].num_fbp);
gpu_instance[index].fbp_en_mask = g->mig.gpu_instance[0].fbp_en_mask;
nvgpu_memcpy((u8 *)gpu_instance[index].fbp_l2_en_mask,
(u8 *)g->mig.gpu_instance[0].fbp_l2_en_mask,
nvgpu_safe_mult_u64(max_fbps_count, sizeof(u32)));
} else {
/* SMC Memory partition is not yet supported */
nvgpu_assert(

12
drivers/gpu/nvgpu/include/nvgpu/mig.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -115,14 +115,16 @@ struct nvgpu_gpu_instance {
/**
* Mask of FBPs. A set bit indicates FBP is available, otherwise
* it is not available.
* For Legacy, it is represent physical FBP mask.
* For MIG, it is represent logical FBP mask.
* For Legacy and MIG, it currently represents physical FBP mask.
* [TODO]: When SMC memory partition will be enabled, a mapping should
* be created for local to {logical, physical}.
*/
u32 fbp_en_mask;
/**
* Array to hold physical masks of LTCs per FBP.
* For Legacy, array is indexed by FBP physical index.
* For MIG, array is indexed by FBP logical index.
* For Legacy and MIG, array is currently indexed by FBP physical index.
* [TODO]: When SMC memory partition will be enabled, a mapping should
* be created for local to {logical, physical}.
*/
u32 *fbp_l2_en_mask;
/** Memory area to store h/w CE engine ids. */

12
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2021, NVIDIA Corporation. All rights reserved.
* Copyright (c) 2011-2022, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -364,6 +364,8 @@ static long gk20a_ctrl_ioctl_gpu_characteristics(
long err = 0;
struct nvgpu_gpu_instance *gpu_instance;
u32 gr_instance_id = nvgpu_grmgr_get_gr_instance_id(g, gpu_instance_id);
if (gk20a_busy(g)) {
nvgpu_err(g, "failed to power on gpu");
return -EINVAL;
@@ -377,7 +379,13 @@ static long gk20a_ctrl_ioctl_gpu_characteristics(
gpu.num_gpc = nvgpu_gr_config_get_gpc_count(gr_config);
gpu.max_gpc_count = nvgpu_gr_config_get_max_gpc_count(gr_config);
gpu.gpc_mask = nvgpu_gr_config_get_gpc_mask(gr_config);
/* Convert logical to physical masks */
gpu.gpc_mask = nvgpu_grmgr_get_gr_physical_gpc_mask(g, gr_instance_id);
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg,
"GR Instance ID = %u, physical gpc_mask = 0x%08X, logical gpc_mask = 0x%08X",
gr_instance_id, gpu.gpc_mask, nvgpu_grmgr_get_gr_logical_gpc_mask(g,
gr_instance_id));
gpu.num_tpc_per_gpc = nvgpu_gr_config_get_max_tpc_per_gpc_count(gr_config);