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gpu: nvgpu: move nvgpu_report_gr_exception to common.gr.intr

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Move the nvgpu_report_gr_exception call from gr_gk20a to
gr_intr.c as nvgpu_gr_intr_report_exception

Move local function gk20a_gr_get_channel_from_ctx to gr_intr.c
as nvgpu_gr_intr_get_channel_from_ctx

JIRA NVGPU-1891

Change-Id: I21521ad50989582d8f166a98a21ea3b1dcd3bbff
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098229
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-04-15 17:49:04 -07:00
committed by mobile promotions
parent 3a764030b1
commit 3d2942e412
7 changed files with 142 additions and 148 deletions
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16
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
View File

@@ -172,7 +172,7 @@ bool gm20b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception)
u32 fe = nvgpu_readl(g, gr_fe_hww_esr_r());
u32 info = nvgpu_readl(g, gr_fe_hww_esr_info_r());
nvgpu_report_gr_exception(g, 0,
nvgpu_gr_intr_report_exception(g, 0,
GPU_PGRAPH_FE_EXCEPTION,
fe);
nvgpu_err(g, "fe exception: esr 0x%08x, info 0x%08x",
@@ -185,7 +185,7 @@ bool gm20b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception)
if ((exception & gr_exception_memfmt_m()) != 0U) {
u32 memfmt = nvgpu_readl(g, gr_memfmt_hww_esr_r());
nvgpu_report_gr_exception(g, 0,
nvgpu_gr_intr_report_exception(g, 0,
GPU_PGRAPH_MEMFMT_EXCEPTION,
memfmt);
nvgpu_err(g, "memfmt exception: esr %08x", memfmt);
@@ -197,7 +197,7 @@ bool gm20b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception)
if ((exception & gr_exception_pd_m()) != 0U) {
u32 pd = nvgpu_readl(g, gr_pd_hww_esr_r());
nvgpu_report_gr_exception(g, 0,
nvgpu_gr_intr_report_exception(g, 0,
GPU_PGRAPH_PD_EXCEPTION,
pd);
nvgpu_err(g, "pd exception: esr 0x%08x", pd);
@@ -209,7 +209,7 @@ bool gm20b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception)
if ((exception & gr_exception_scc_m()) != 0U) {
u32 scc = nvgpu_readl(g, gr_scc_hww_esr_r());
nvgpu_report_gr_exception(g, 0,
nvgpu_gr_intr_report_exception(g, 0,
GPU_PGRAPH_SCC_EXCEPTION,
scc);
nvgpu_err(g, "scc exception: esr 0x%08x", scc);
@@ -221,7 +221,7 @@ bool gm20b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception)
if ((exception & gr_exception_ds_m()) != 0U) {
u32 ds = nvgpu_readl(g, gr_ds_hww_esr_r());
nvgpu_report_gr_exception(g, 0,
nvgpu_gr_intr_report_exception(g, 0,
GPU_PGRAPH_DS_EXCEPTION,
ds);
nvgpu_err(g, "ds exception: esr: 0x%08x", ds);
@@ -241,7 +241,7 @@ bool gm20b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception)
} else {
nvgpu_err(g, "unhandled ssync exception");
}
nvgpu_report_gr_exception(g, 0,
nvgpu_gr_intr_report_exception(g, 0,
GPU_PGRAPH_SSYNC_EXCEPTION,
ssync_esr);
}
@@ -250,7 +250,7 @@ bool gm20b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception)
u32 mme = nvgpu_readl(g, gr_mme_hww_esr_r());
u32 info = nvgpu_readl(g, gr_mme_hww_esr_info_r());
nvgpu_report_gr_exception(g, 0,
nvgpu_gr_intr_report_exception(g, 0,
GPU_PGRAPH_MME_EXCEPTION,
mme);
nvgpu_err(g, "mme exception: esr 0x%08x info:0x%08x",
@@ -267,7 +267,7 @@ bool gm20b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception)
if ((exception & gr_exception_sked_m()) != 0U) {
u32 sked = nvgpu_readl(g, gr_sked_hww_esr_r());
nvgpu_report_gr_exception(g, 0,
nvgpu_gr_intr_report_exception(g, 0,
GPU_PGRAPH_SKED_EXCEPTION,
sked);
nvgpu_err(g, "sked exception: esr 0x%08x", sked);

4
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
View File

@@ -22,10 +22,10 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/io.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_intr.h>
#include "gr_intr_gv11b.h"
@@ -355,7 +355,7 @@ void gv11b_gr_intr_handle_tpc_mpc_exception(struct gk20a *g, u32 gpc, u32 tpc)
esr = nvgpu_readl(g, gr_gpc0_tpc0_mpc_hww_esr_r() + offset);
nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, "mpc hww esr 0x%08x", esr);
nvgpu_report_gr_exception(g, ((gpc << 8U) | tpc),
nvgpu_gr_intr_report_exception(g, ((gpc << 8U) | tpc),
GPU_PGRAPH_MPC_EXCEPTION,
esr);