diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 17ae2685b..8d8fed711 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -184,7 +184,9 @@ nvgpu-y += \ hal/cbc/cbc_tu104.o \ hal/fuse/fuse_gm20b.o \ hal/fuse/fuse_gp10b.o \ - hal/fuse/fuse_gp106.o + hal/fuse/fuse_gp106.o \ + hal/fifo/engines_gm20b.o \ + hal/fifo/engines_gv11b.o # Linux specific parts of nvgpu. nvgpu-y += \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 24908e959..fad56a7b2 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -350,7 +350,9 @@ srcs += common/sim.c \ hal/cbc/cbc_tu104.c \ hal/fuse/fuse_gm20b.c \ hal/fuse/fuse_gp10b.c \ - hal/fuse/fuse_gp106.c + hal/fuse/fuse_gp106.c \ + hal/fifo/engines_gm20b.c \ + hal/fifo/engines_gv11b.c ifeq ($(NVGPU_DEBUGGER),1) srcs += common/debugger.c diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 1dca118ab..778bd095b 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -22,6 +22,7 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gm20b.h" +#include "hal/fifo/engines_gm20b.h" #include "common/fb/fb_gm20b.h" #include "common/fb/fb_gp10b.h" @@ -386,7 +387,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .force_reset_ch = vgpu_fifo_force_reset_ch, .init_engine_info = vgpu_fifo_init_engine_info, .get_engines_mask_on_id = NULL, - .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, .dump_pbdma_status = NULL, .dump_eng_status = NULL, .dump_channel_status_ramfc = NULL, @@ -412,6 +412,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { .resetup_ramfc = NULL, .set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask, }, + .engine = { + .is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc, + }, .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gk20a_alloc_syncpt_buf, @@ -687,6 +690,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g) gops->perf = vgpu_gp10b_ops.perf; gops->clock_gating = vgpu_gp10b_ops.clock_gating; gops->fifo = vgpu_gp10b_ops.fifo; + gops->engine = vgpu_gp10b_ops.engine; gops->runlist = vgpu_gp10b_ops.runlist; gops->channel = vgpu_gp10b_ops.channel; gops->sync = vgpu_gp10b_ops.sync; diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index bbad8ed64..edb8d070c 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -22,6 +22,7 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gm20b.h" +#include "hal/fifo/engines_gv11b.h" #include "common/fb/fb_gm20b.h" #include "common/fb/fb_gp10b.h" @@ -456,7 +457,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .force_reset_ch = vgpu_fifo_force_reset_ch, .init_engine_info = vgpu_fifo_init_engine_info, .get_engines_mask_on_id = NULL, - .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, .dump_pbdma_status = NULL, .dump_eng_status = NULL, .dump_channel_status_ramfc = NULL, @@ -490,6 +490,9 @@ static const struct gpu_ops vgpu_gv11b_ops = { .usermode_base = gv11b_fifo_usermode_base, .doorbell_token = gv11b_fifo_doorbell_token, }, + .engine = { + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + }, .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf, @@ -767,6 +770,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g) gops->perf = vgpu_gv11b_ops.perf; gops->clock_gating = vgpu_gv11b_ops.clock_gating; gops->fifo = vgpu_gv11b_ops.fifo; + gops->engine = vgpu_gv11b_ops.engine; gops->runlist = vgpu_gv11b_ops.runlist; gops->channel = vgpu_gv11b_ops.channel; gops->sync = vgpu_gv11b_ops.sync; diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 05b53a018..50e794b75 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -985,11 +985,6 @@ static void gk20a_fifo_handle_dropped_mmu_fault(struct gk20a *g) nvgpu_err(g, "dropped mmu fault (0x%08x)", fault_id); } -bool gk20a_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) -{ - return (engine_subid == fifo_intr_mmu_fault_info_engine_subid_gpc_v()); -} - bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id, u32 engine_subid, bool fake_fault) { @@ -1026,7 +1021,7 @@ bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id, return false; } - return g->ops.fifo.is_fault_engine_subid_gpc(g, engine_subid); + return g->ops.engine.is_fault_engine_subid_gpc(g, engine_subid); } void gk20a_fifo_abort_tsg(struct gk20a *g, struct tsg_gk20a *tsg, bool preempt) diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 9f9e9a53f..8a46938fa 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -308,7 +308,6 @@ u32 gk20a_fifo_userd_gp_get(struct gk20a *g, struct channel_gk20a *c); void gk20a_fifo_userd_gp_put(struct gk20a *g, struct channel_gk20a *c); u64 gk20a_fifo_userd_pb_get(struct gk20a *g, struct channel_gk20a *c); -bool gk20a_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid); #ifdef CONFIG_DEBUG_FS struct fifo_profile_gk20a *gk20a_fifo_profile_acquire(struct gk20a *g); void gk20a_fifo_profile_release(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 55e054778..8972cfa82 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -43,6 +43,7 @@ #include "hal/power_features/cg/gm20b_gating_reglist.h" #include "hal/cbc/cbc_gm20b.h" #include "hal/fuse/fuse_gm20b.h" +#include "hal/fifo/engines_gm20b.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -520,7 +521,6 @@ static const struct gpu_ops gm20b_ops = { .force_reset_ch = gk20a_fifo_force_reset_ch, .init_engine_info = gm20b_fifo_init_engine_info, .get_engines_mask_on_id = gk20a_fifo_engines_on_id, - .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, .dump_pbdma_status = gk20a_dump_pbdma_status, .dump_eng_status = gk20a_dump_eng_status, .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, @@ -552,6 +552,9 @@ static const struct gpu_ops gm20b_ops = { .read_pbdma_data = gk20a_fifo_read_pbdma_data, .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, }, + .engine = { + .is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc, + }, .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gk20a_alloc_syncpt_buf, @@ -838,6 +841,7 @@ int gm20b_init_hal(struct gk20a *g) gops->fb = gm20b_ops.fb; gops->clock_gating = gm20b_ops.clock_gating; gops->fifo = gm20b_ops.fifo; + gops->engine = gm20b_ops.engine; gops->runlist = gm20b_ops.runlist; gops->channel = gm20b_ops.channel; gops->sync = gm20b_ops.sync; diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 1b4ad45aa..7ceb90bdf 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -49,6 +49,7 @@ #include "hal/cbc/cbc_gp10b.h" #include "hal/fuse/fuse_gm20b.h" #include "hal/fuse/fuse_gp10b.h" +#include "hal/fifo/engines_gm20b.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -573,7 +574,6 @@ static const struct gpu_ops gp10b_ops = { .force_reset_ch = gk20a_fifo_force_reset_ch, .init_engine_info = gm20b_fifo_init_engine_info, .get_engines_mask_on_id = gk20a_fifo_engines_on_id, - .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, .dump_pbdma_status = gk20a_dump_pbdma_status, .dump_eng_status = gk20a_dump_eng_status, .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, @@ -606,6 +606,9 @@ static const struct gpu_ops gp10b_ops = { .read_pbdma_data = gk20a_fifo_read_pbdma_data, .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, }, + .engine = { + .is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc, + }, .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gk20a_alloc_syncpt_buf, @@ -923,6 +926,7 @@ int gp10b_init_hal(struct gk20a *g) gops->fb = gp10b_ops.fb; gops->clock_gating = gp10b_ops.clock_gating; gops->fifo = gp10b_ops.fifo; + gops->engine = gp10b_ops.engine; gops->runlist = gp10b_ops.runlist; gops->channel = gp10b_ops.channel; gops->sync = gp10b_ops.sync; diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index d230d317b..22c80c28a 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -33,6 +33,7 @@ #include "hal/fuse/fuse_gm20b.h" #include "hal/fuse/fuse_gp10b.h" #include "hal/fuse/fuse_gp106.h" +#include "hal/fifo/engines_gv11b.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -741,7 +742,6 @@ static const struct gpu_ops gv100_ops = { .force_reset_ch = gk20a_fifo_force_reset_ch, .init_engine_info = gm20b_fifo_init_engine_info, .get_engines_mask_on_id = gk20a_fifo_engines_on_id, - .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, .dump_pbdma_status = gk20a_dump_pbdma_status, .dump_eng_status = gv11b_dump_eng_status, .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, @@ -781,6 +781,9 @@ static const struct gpu_ops gv100_ops = { .read_pbdma_data = gk20a_fifo_read_pbdma_data, .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, }, + .engine = { + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + }, .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gv11b_alloc_syncpt_buf, @@ -1203,6 +1206,7 @@ int gv100_init_hal(struct gk20a *g) gops->nvdec = gv100_ops.nvdec; gops->clock_gating = gv100_ops.clock_gating; gops->fifo = gv100_ops.fifo; + gops->engine = gv100_ops.engine; gops->runlist = gv100_ops.runlist; gops->channel = gv100_ops.channel; gops->sync = gv100_ops.sync; diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index c172e2e44..01c7ba75f 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -216,11 +216,6 @@ void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) g->ops.fifo.ring_channel_doorbell(c); } -bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) -{ - return (engine_subid == gmmu_fault_client_type_gpc_v()); -} - void gv11b_capture_channel_ram_dump(struct gk20a *g, struct channel_gk20a *ch, struct nvgpu_channel_dump_info *info) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 6b6ea911c..abfc1c817 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -66,7 +66,6 @@ int channel_gv11b_setup_ramfc(struct channel_gk20a *c, u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c); u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c); void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c); -bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid); void gv11b_dump_channel_status_ramfc(struct gk20a *g, struct gk20a_debug_output *o, struct nvgpu_channel_dump_info *info); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 25dd73172..4e96d77f2 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -36,6 +36,7 @@ #include "hal/cbc/cbc_gv11b.h" #include "hal/fuse/fuse_gm20b.h" #include "hal/fuse/fuse_gp10b.h" +#include "hal/fifo/engines_gv11b.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -694,7 +695,6 @@ static const struct gpu_ops gv11b_ops = { .force_reset_ch = gk20a_fifo_force_reset_ch, .init_engine_info = gm20b_fifo_init_engine_info, .get_engines_mask_on_id = gk20a_fifo_engines_on_id, - .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, .dump_pbdma_status = gk20a_dump_pbdma_status, .dump_eng_status = gv11b_dump_eng_status, .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, @@ -735,6 +735,9 @@ static const struct gpu_ops gv11b_ops = { .read_pbdma_data = gk20a_fifo_read_pbdma_data, .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, }, + .engine = { + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + }, .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gv11b_alloc_syncpt_buf, @@ -1078,6 +1081,7 @@ int gv11b_init_hal(struct gk20a *g) gops->fb = gv11b_ops.fb; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; + gops->engine = gv11b_ops.engine; gops->runlist = gv11b_ops.runlist; gops->channel = gv11b_ops.channel; gops->sync = gv11b_ops.sync; diff --git a/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c b/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c new file mode 100644 index 000000000..8c13d7483 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "engines_gm20b.h" + +bool gm20b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) +{ + return (engine_subid == fifo_intr_mmu_fault_info_engine_subid_gpc_v()); +} diff --git a/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.h b/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.h new file mode 100644 index 000000000..c6bd95f2e --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_ENGINE_GM20B_H +#define NVGPU_ENGINE_GM20B_H + +#include + +struct gk20a; + +bool gm20b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid); + +#endif /* NVGPU_ENGINE_GM20B_H */ diff --git a/drivers/gpu/nvgpu/hal/fifo/engines_gv11b.c b/drivers/gpu/nvgpu/hal/fifo/engines_gv11b.c new file mode 100644 index 000000000..4730e6bb2 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/engines_gv11b.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "engines_gv11b.h" + +bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) +{ + return (engine_subid == gmmu_fault_client_type_gpc_v()); +} diff --git a/drivers/gpu/nvgpu/hal/fifo/engines_gv11b.h b/drivers/gpu/nvgpu/hal/fifo/engines_gv11b.h new file mode 100644 index 000000000..c88ad9513 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/engines_gv11b.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_ENGINE_GV11B_H +#define NVGPU_ENGINE_GV11B_H + +#include + +struct gk20a; + +bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid); + +#endif /* NVGPU_ENGINE_GV11B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 9b1a73c6b..dede650f0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -805,8 +805,6 @@ struct gpu_ops { void (*userd_gp_put)(struct gk20a *g, struct channel_gk20a *ch); u64 (*userd_pb_get)(struct gk20a *g, struct channel_gk20a *ch); void (*free_channel_ctx_header)(struct channel_gk20a *ch); - bool (*is_fault_engine_subid_gpc)(struct gk20a *g, - u32 engine_subid); void (*dump_pbdma_status)(struct gk20a *g, struct gk20a_debug_output *o); void (*dump_eng_status)(struct gk20a *g, @@ -892,6 +890,11 @@ struct gpu_ops { u32 runlist_state); } runlist; + struct { + bool (*is_fault_engine_subid_gpc)(struct gk20a *g, + u32 engine_subid); + } engine; + struct { #ifdef CONFIG_TEGRA_GK20A_NVHOST int (*alloc_syncpt_buf)(struct channel_gk20a *c, diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index bbbaa2479..870178009 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -35,6 +35,7 @@ #include "hal/fuse/fuse_gm20b.h" #include "hal/fuse/fuse_gp10b.h" #include "hal/fuse/fuse_gp106.h" +#include "hal/fifo/engines_gv11b.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -770,7 +771,6 @@ static const struct gpu_ops tu104_ops = { .force_reset_ch = gk20a_fifo_force_reset_ch, .init_engine_info = gm20b_fifo_init_engine_info, .get_engines_mask_on_id = gk20a_fifo_engines_on_id, - .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, .dump_pbdma_status = gk20a_dump_pbdma_status, .dump_eng_status = gv11b_dump_eng_status, .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, @@ -813,6 +813,9 @@ static const struct gpu_ops tu104_ops = { .read_pbdma_data = tu104_fifo_read_pbdma_data, .reset_pbdma_header = tu104_fifo_reset_pbdma_header, }, + .engine = { + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + }, .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gv11b_alloc_syncpt_buf, @@ -1243,6 +1246,7 @@ int tu104_init_hal(struct gk20a *g) gops->nvdec = tu104_ops.nvdec; gops->clock_gating = tu104_ops.clock_gating; gops->fifo = tu104_ops.fifo; + gops->engine = tu104_ops.engine; gops->runlist = tu104_ops.runlist; gops->channel = tu104_ops.channel; gops->sync = tu104_ops.sync;