nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 17:36:20 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: gk20a: fix misc MISRA 10.3 issues

Browse Source 
MISRA Rule 10.3 prohibits assigning to an object of different essential
or narrower type. This fixes some miscellaneous violations in
gr_gk20a.c.

JIRA NVGPU-1008

Change-Id: I46aa3bcdee23f53ab79615d37c1a797de1b74137
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990390
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-01-08 12:39:05 -05:00
committed by mobile promotions
parent a6f9d1c40e
commit 3d62c3256f
2 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -4100,13 +4100,13 @@ static int gr_gk20a_wait_mem_scrubbing(struct gk20a *g)
CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT, CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT,
NVGPU_TIMER_RETRY_TIMER); NVGPU_TIMER_RETRY_TIMER);
do { do {
fecs_scrubbing = gk20a_readl(g, gr_fecs_dmactl_r()) & fecs_scrubbing = (gk20a_readl(g, gr_fecs_dmactl_r()) &
(gr_fecs_dmactl_imem_scrubbing_m() | (gr_fecs_dmactl_imem_scrubbing_m() |
gr_fecs_dmactl_dmem_scrubbing_m()); gr_fecs_dmactl_dmem_scrubbing_m())) != 0U;
gpccs_scrubbing = gk20a_readl(g, gr_gpccs_dmactl_r()) & gpccs_scrubbing = (gk20a_readl(g, gr_gpccs_dmactl_r()) &
(gr_gpccs_dmactl_imem_scrubbing_m() | (gr_gpccs_dmactl_imem_scrubbing_m() |
gr_gpccs_dmactl_imem_scrubbing_m()); gr_gpccs_dmactl_imem_scrubbing_m())) != 0U;
if (!fecs_scrubbing && !gpccs_scrubbing) { if (!fecs_scrubbing && !gpccs_scrubbing) {
nvgpu_log_fn(g, "done"); nvgpu_log_fn(g, "done");
@@ -5356,7 +5356,7 @@ int gk20a_gr_isr(struct gk20a *g)
gr_engine_id = gk20a_fifo_get_gr_engine_id(g); gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
if (gr_engine_id != FIFO_INVAL_ENGINE_ID) { if (gr_engine_id != FIFO_INVAL_ENGINE_ID) {
gr_engine_id = BIT(gr_engine_id); gr_engine_id = BIT32(gr_engine_id);
} }
grfifo_ctl = gk20a_readl(g, gr_gpfifo_ctl_r()); grfifo_ctl = gk20a_readl(g, gr_gpfifo_ctl_r());
@@ -7368,7 +7368,7 @@ static int gr_gk20a_find_priv_offset_in_pm_buffer(struct gk20a *g,
bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch) bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch)
{ {
int curr_gr_ctx; u32 curr_gr_ctx;
u32 curr_gr_tsgid; u32 curr_gr_tsgid;
struct gk20a *g = ch->g; struct gk20a *g = ch->g;
struct channel_gk20a *curr_ch; struct channel_gk20a *curr_ch;

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -264,7 +264,7 @@ struct gr_gk20a {
struct nvgpu_mutex fecs_mutex; /* protect fecs method */ struct nvgpu_mutex fecs_mutex; /* protect fecs method */
struct nvgpu_cond init_wq; struct nvgpu_cond init_wq;
int initialized; bool initialized;
u32 num_fbps; u32 num_fbps;