From 3d64bc19df4c13a09ce7d285706055241ced6f95 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 6 May 2019 12:53:36 -0700 Subject: [PATCH] gpu: nvgpu: channel MISRA fix for Rule 17.7 Check return value of nvgpu_timeout_init and spit error message. Also return to the calling function upon timeout init error in few cases. JIRA NVGPU-3383 Change-Id: I97fcc7343051842a74d9bf379c372b7094c8de86 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/2113157 Reviewed-by: svc-mobile-coverity Reviewed-by: Thomas Fleury Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/channel.c | 31 ++++++++++++++++++++----- 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index 912912660..6db897f29 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c @@ -224,9 +224,14 @@ int gk20a_wait_channel_idle(struct nvgpu_channel *ch) { bool channel_idle = false; struct nvgpu_timeout timeout; + int ret; - nvgpu_timeout_init(ch->g, &timeout, nvgpu_get_poll_timeout(ch->g), + ret = nvgpu_timeout_init(ch->g, &timeout, nvgpu_get_poll_timeout(ch->g), NVGPU_TIMER_CPU_TIMER); + if (ret != 0) { + nvgpu_err(ch->g, "timeout_init failed: %d", ret); + return ret; + } do { channel_gk20a_joblist_lock(ch); @@ -1463,18 +1468,24 @@ u32 nvgpu_get_gp_free_count(struct nvgpu_channel *c) static void nvgpu_channel_wdt_init(struct nvgpu_channel *ch) { struct gk20a *g = ch->g; + int ret; if (gk20a_channel_check_unserviceable(ch)) { ch->wdt.running = false; return; } + ret = nvgpu_timeout_init(g, &ch->wdt.timer, + ch->wdt.limit_ms, + NVGPU_TIMER_CPU_TIMER); + if (ret != 0) { + nvgpu_err(g, "timeout_init failed: %d", ret); + return; + } + ch->wdt.gp_get = g->ops.userd.gp_get(g, ch); ch->wdt.pb_get = g->ops.userd.pb_get(g, ch); ch->wdt.running = true; - nvgpu_timeout_init(g, &ch->wdt.timer, - ch->wdt.limit_ms, - NVGPU_TIMER_CPU_TIMER); } /** @@ -1705,11 +1716,15 @@ static void nvgpu_channel_worker_poll_init(struct nvgpu_worker *worker) { struct nvgpu_channel_worker *ch_worker = nvgpu_channel_worker_from_worker(worker); + int ret; ch_worker->watchdog_interval = 100U; - nvgpu_timeout_init(worker->g, &ch_worker->timeout, + ret = nvgpu_timeout_init(worker->g, &ch_worker->timeout, ch_worker->watchdog_interval, NVGPU_TIMER_CPU_TIMER); + if (ret != 0) { + nvgpu_err(worker->g, "timeout_init failed: %d", ret); + } } static void nvgpu_channel_worker_poll_wakeup_post_process_item( @@ -1719,12 +1734,16 @@ static void nvgpu_channel_worker_poll_wakeup_post_process_item( struct nvgpu_channel_worker *ch_worker = nvgpu_channel_worker_from_worker(worker); + int ret; if (nvgpu_timeout_peek_expired(&ch_worker->timeout) != 0) { nvgpu_channel_poll_wdt(g); - nvgpu_timeout_init(g, &ch_worker->timeout, + ret = nvgpu_timeout_init(g, &ch_worker->timeout, ch_worker->watchdog_interval, NVGPU_TIMER_CPU_TIMER); + if (ret != 0) { + nvgpu_err(g, "timeout_init failed: %d", ret); + } } } static void nvgpu_channel_worker_poll_wakeup_process_item(