diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs
index 7d3ab28cb..eba8d8770 100644
--- a/drivers/gpu/nvgpu/Makefile.shared.configs
+++ b/drivers/gpu/nvgpu/Makefile.shared.configs
@@ -144,13 +144,13 @@ ifneq ($(profile),safety_release)
 CONFIG_NVGPU_TRACE              := 1
 NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_TRACE
 
-NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_FALCON_DEBUG
-
 #
 # Flags enabled only for regular build profile.
 #
 ifneq ($(profile),safety_debug)
 
+NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_FALCON_DEBUG
+
 CONFIG_NVGPU_SYSFS              := 1
 NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_SYSFS
 
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index d6715f5df..9c6733bd8 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -400,12 +400,14 @@ srcs += common/debugger.c \
 	common/perf/perfbuf.c \
 	hal/regops/regops_gv11b.c \
 	hal/regops/allowlist_gv11b.c \
+	hal/regops/allowlist_ga10b.c \
 	hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c \
 	hal/gr/hwpm_map/hwpm_map_gv100.c \
 	hal/ltc/ltc_gm20b_dbg.c \
 	hal/ptimer/ptimer_gp10b.c \
 	hal/perf/perf_gv11b.c \
 	hal/perf/perf_tu104.c \
+	hal/perf/perf_ga10b.c \
 	hal/gr/gr/gr_gk20a.c \
 	hal/gr/gr/gr_gm20b.c \
 	hal/gr/gr/gr_gp10b.c \
@@ -416,6 +418,7 @@ ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
 srcs += hal/regops/regops_gm20b.c \
 	hal/regops/regops_gp10b.c \
 	hal/regops/regops_tu104.c \
+	hal/regops/regops_ga10b.c \
 	hal/regops/allowlist_tu104.c \
 	hal/perf/perf_gm20b.c
 endif
@@ -536,6 +539,7 @@ srcs += \
 	common/pmu/perfmon/pmu_perfmon.c \
 	common/pmu/perfmon/pmu_perfmon_sw_gm20b.c \
 	common/pmu/perfmon/pmu_perfmon_sw_gv11b.c \
+	common/pmu/perfmon/pmu_perfmon_sw_ga10b.c \
 	common/pmu/pmgr/pmgr.c \
 	common/pmu/pmgr/pmgrpmu.c \
 	common/pmu/pmgr/pwrdev.c \
@@ -564,6 +568,7 @@ srcs += common/pmu/pg/pg_sw_gm20b.c \
 	common/pmu/pg/pg_sw_gp10b.c \
 	common/pmu/pg/pg_sw_gp106.c \
 	common/pmu/pg/pg_sw_gv11b.c \
+	common/pmu/pg/pg_sw_ga10b.c \
 	common/pmu/pg/pmu_pg.c \
 	common/pmu/pg/pmu_aelpg.c
 endif
@@ -669,17 +674,13 @@ srcs += common/sec2/sec2.c \
 	hal/mm/mm_gv100.c \
 	hal/mm/mm_tu104.c \
 	hal/mc/mc_gv100.c  \
-	hal/mc/mc_tu104.c  \
 	hal/bus/bus_gv100.c \
 	hal/bus/bus_tu104.c \
 	hal/ce/ce_tu104.c \
-	hal/class/class_tu104.c \
 	hal/clk/clk_tu104.c \
 	hal/clk/clk_mon_tu104.c \
 	hal/gr/init/gr_init_gv100.c \
-	hal/gr/init/gr_init_tu104.c \
 	hal/gr/intr/gr_intr_tu104.c \
-	hal/gr/falcon/gr_falcon_tu104.c \
 	hal/fbpa/fbpa_tu104.c \
 	hal/init/hal_tu104.c \
 	hal/init/hal_tu104_litter.c \
@@ -692,7 +693,6 @@ srcs += common/sec2/sec2.c \
 	hal/fb/intr/fb_intr_tu104.c \
 	hal/func/func_tu104.c \
 	hal/fifo/fifo_tu104.c \
-	hal/fifo/usermode_tu104.c \
 	hal/fifo/pbdma_tu104.c \
 	hal/fifo/ramfc_tu104.c  \
 	hal/fifo/ramin_tu104.c \
@@ -723,6 +723,12 @@ srcs +=	hal/cbc/cbc_tu104.c
 endif
 endif
 
+srcs += hal/gr/init/gr_init_tu104.c \
+	hal/class/class_tu104.c \
+	hal/mc/mc_tu104.c  \
+	hal/fifo/usermode_tu104.c \
+	hal/gr/falcon/gr_falcon_tu104.c \
+
 ifeq ($(CONFIG_NVGPU_SIM),1)
 srcs += common/sim/sim.c \
 	common/sim/sim_pci.c \
@@ -737,13 +743,9 @@ ifeq ($(CONFIG_NVGPU_STATIC_POWERGATE),1)
 srcs +=	hal/tpc/tpc_gv11b.c
 endif
 
-ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
 srcs += \
 	common/riscv/riscv.c \
 	common/acr/acr_sw_ga10b.c \
-	common/acr/acr_sw_ga100.c \
-	common/pmu/perfmon/pmu_perfmon_sw_ga10b.c \
-	common/pmu/pg/pg_sw_ga10b.c \
 	common/falcon/falcon_sw_ga10b.c \
 
 srcs += hal/init/hal_ga10b.c \
@@ -787,6 +789,7 @@ srcs += hal/init/hal_ga10b.c \
 	hal/gr/intr/gr_intr_ga10b_fusa.c \
 	hal/gr/falcon/gr_falcon_ga10b_fusa.c \
 	hal/gr/falcon/gr_falcon_ga10b.c \
+	hal/gr/falcon/gr_falcon_ga100.c \
 	hal/gr/ecc/ecc_ga10b.c \
 	hal/gr/ecc/ecc_ga10b_fusa.c \
 	hal/netlist/netlist_ga10b_fusa.c \
@@ -804,18 +807,24 @@ srcs += hal/init/hal_ga10b.c \
 	hal/fb/ecc/fb_ecc_ga10b_fusa.c \
 	hal/fb/intr/fb_intr_ga10b_fusa.c \
 	hal/fb/intr/fb_intr_ecc_ga10b_fusa.c \
-	hal/fb/vab/vab_ga10b.c \
 	hal/priv_ring/priv_ring_ga10b_fusa.c \
 	hal/ptimer/ptimer_ga10b_fusa.c \
-	hal/perf/perf_ga10b.c \
-	hal/regops/regops_ga10b.c \
-	hal/regops/allowlist_ga10b.c \
 	hal/power_features/cg/ga10b_gating_reglist.c \
 	hal/therm/therm_ga10b_fusa.c \
 	hal/ce/ce_ga10b_fusa.c \
 	hal/grmgr/grmgr_ga10b.c \
 	hal/sim/sim_ga10b.c \
 
+ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
+srcs += \
+	hal/fb/vab/vab_ga10b.c
+endif
+
+ifeq ($(CONFIG_NVGPU_NON_FUSA),1)
+srcs += \
+	common/acr/acr_sw_ga100.c
+endif
+
 ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
 srcs += \
 	hal/cbc/cbc_ga100.c \
@@ -837,11 +846,9 @@ srcs += \
 	hal/gr/intr/gr_intr_ga100_fusa.c \
 	hal/gr/init/gr_init_ga100_fusa.c \
 	hal/gr/init/gr_init_ga100.c \
-	hal/gr/falcon/gr_falcon_ga100.c \
 	hal/clk/clk_ga100.c \
 	hal/nvdec/nvdec_ga100.c \
 	hal/pmu/pmu_ga100.c \
-	hal/perf/perf_ga100.c \
 	hal/fb/fb_ga100.c \
 	hal/fifo/channel_ga100_fusa.c \
 	hal/fifo/pbdma_ga100_fusa.c \
@@ -850,9 +857,14 @@ srcs += \
 	common/vbios/bios_sw_ga100.c \
 	hal/power_features/cg/ga100_gating_reglist.c \
 	hal/priv_ring/priv_ring_ga100_fusa.c \
+
+ifeq ($(CONFIG_NVGPU_DEBUGGER),1)
+srcs += \
+	hal/perf/perf_ga100.c \
 	hal/regops/regops_ga100.c \
 	hal/regops/allowlist_ga100.c
 endif
+endif
 
 ifeq ($(CONFIG_NVGPU_MIG),1)
 ifeq ($(CONFIG_NVGPU_DGPU),1)
@@ -860,5 +872,3 @@ srcs += \
 	hal/grmgr/grmgr_ga100.c
 endif
 endif
-
-endif
diff --git a/drivers/gpu/nvgpu/common/acr/acr.c b/drivers/gpu/nvgpu/common/acr/acr.c
index 5a91d69e9..0fec2dff8 100644
--- a/drivers/gpu/nvgpu/common/acr/acr.c
+++ b/drivers/gpu/nvgpu/common/acr/acr.c
@@ -32,15 +32,11 @@
 #include "acr_sw_gp10b.h"
 #endif
 #include "acr_sw_gv11b.h"
-#ifdef CONFIG_NVGPU_DGPU
-#include "acr_sw_tu104.h"
-#endif
-#ifdef CONFIG_NVGPU_NON_FUSA
 #include "acr_sw_ga10b.h"
 #ifdef CONFIG_NVGPU_DGPU
+#include "acr_sw_tu104.h"
 #include "acr_sw_ga100.h"
 #endif
-#endif
 
 #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 #include <nvgpu_next_acr.h>
@@ -151,11 +147,9 @@ int nvgpu_acr_init(struct gk20a *g)
 	case NVGPU_GPUID_GV11B:
 		nvgpu_gv11b_acr_sw_init(g, g->acr);
 		break;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	case NVGPU_GPUID_GA10B:
 		nvgpu_ga10b_acr_sw_init(g, g->acr);
 		break;
-#endif /* CONFIG_NVGPU_NON_FUSA */
 #ifdef CONFIG_NVGPU_DGPU
 	case NVGPU_GPUID_TU104:
 		nvgpu_tu104_acr_sw_init(g, g->acr);
diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct.c
index b621f71f4..ffeba1e69 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct.c
+++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct.c
@@ -105,7 +105,7 @@ int nvgpu_acr_lsf_pmu_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 exit:
 	return err;
 }
-#if defined(CONFIG_NVGPU_NON_FUSA)
+
 s32 nvgpu_acr_lsf_pmu_ncore_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 {
 	struct lsf_ucode_desc *lsf_desc = NULL;
@@ -163,7 +163,6 @@ exit:
 	return err;
 }
 #endif
-#endif
 
 int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 {
@@ -171,9 +170,7 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 	u32 ver = nvgpu_safe_add_u32(g->params.gpu_arch,
 					g->params.gpu_impl);
 	struct lsf_ucode_desc *lsf_desc = NULL;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	struct lsf_ucode_desc_wrapper *lsf_desc_wrapper = NULL;
-#endif
 	struct nvgpu_firmware *fecs_sig = NULL;
 	struct flcn_ucode_img *p_img =
 		(struct flcn_ucode_img *)lsf_ucode_img;
@@ -187,7 +184,6 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 			fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG,
 				NVGPU_REQUEST_FIRMWARE_NO_WARN);
 			break;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 		case NVGPU_GPUID_GA10B:
 			if (!nvgpu_is_enabled(g, NVGPU_PKC_LS_SIG_ENABLED)) {
 				fecs_sig = nvgpu_request_firmware(g,
@@ -199,7 +195,6 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 					NVGPU_REQUEST_FIRMWARE_NO_WARN);
 			}
 			break;
-#endif
 #ifdef CONFIG_NVGPU_DGPU
 		case NVGPU_GPUID_TU104:
 			fecs_sig = nvgpu_request_firmware(g, TU104_FECS_UCODE_SIG,
@@ -234,7 +229,6 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 			min_t(size_t, sizeof(*lsf_desc), fecs_sig->size));
 
 		lsf_desc->falcon_id = FALCON_ID_FECS;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	} else {
 		lsf_desc_wrapper =
 			nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_wrapper));
@@ -246,7 +240,6 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 			min_t(size_t, sizeof(*lsf_desc_wrapper), fecs_sig->size));
 
 		lsf_desc_wrapper->lsf_ucode_desc_v2.falcon_id = FALCON_ID_FECS;
-#endif
 	}
 
 	p_img->desc = nvgpu_kzalloc(g, sizeof(struct ls_falcon_ucode_desc));
@@ -286,11 +279,9 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 
 	if (!nvgpu_is_enabled(g, NVGPU_PKC_LS_SIG_ENABLED)) {
 		p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	} else {
 		p_img->lsf_desc_wrapper =
 			(struct lsf_ucode_desc_wrapper *)lsf_desc_wrapper;
-#endif
 	}
 
 	nvgpu_acr_dbg(g, "fecs fw loaded\n");
@@ -301,10 +292,8 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 free_lsf_desc:
 	if (!nvgpu_is_enabled(g, NVGPU_PKC_LS_SIG_ENABLED)) {
 		nvgpu_kfree(g, lsf_desc);
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	} else {
 		nvgpu_kfree(g, lsf_desc_wrapper);
-#endif
 	}
 rel_sig:
 	nvgpu_release_firmware(g, fecs_sig);
@@ -316,9 +305,7 @@ int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 	u32 tmp_size;
 	u32 ver = nvgpu_safe_add_u32(g->params.gpu_arch, g->params.gpu_impl);
 	struct lsf_ucode_desc *lsf_desc = NULL;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	struct lsf_ucode_desc_wrapper *lsf_desc_wrapper = NULL;
-#endif
 	struct nvgpu_firmware *gpccs_sig = NULL;
 	struct flcn_ucode_img *p_img =
 		(struct flcn_ucode_img *)lsf_ucode_img;
@@ -340,7 +327,6 @@ int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 			gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG,
 					NVGPU_REQUEST_FIRMWARE_NO_WARN);
 			break;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 		case NVGPU_GPUID_GA10B:
 			if (!nvgpu_is_enabled(g, NVGPU_PKC_LS_SIG_ENABLED)) {
 				gpccs_sig = nvgpu_request_firmware(g,
@@ -352,7 +338,6 @@ int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 					NVGPU_REQUEST_FIRMWARE_NO_WARN);
 			}
 			break;
-#endif
 #ifdef CONFIG_NVGPU_DGPU
 		case NVGPU_GPUID_TU104:
 			gpccs_sig = nvgpu_request_firmware(g, TU104_GPCCS_UCODE_SIG,
@@ -387,7 +372,6 @@ int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 		nvgpu_memcpy((u8 *)lsf_desc, gpccs_sig->data,
 			min_t(size_t, sizeof(*lsf_desc), gpccs_sig->size));
 		lsf_desc->falcon_id = FALCON_ID_GPCCS;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	} else {
 		lsf_desc_wrapper =
 			nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_wrapper));
@@ -398,7 +382,6 @@ int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 		nvgpu_memcpy((u8 *)lsf_desc_wrapper, gpccs_sig->data,
 			min_t(size_t, sizeof(*lsf_desc_wrapper), gpccs_sig->size));
 		lsf_desc_wrapper->lsf_ucode_desc_v2.falcon_id = FALCON_ID_GPCCS;
-#endif
 	}
 
 	nvgpu_acr_dbg(g, "gpccs fw copied to desc buffer\n");
diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct.h b/drivers/gpu/nvgpu/common/acr/acr_blob_construct.h
index 1a4cec89e..3a4b765c2 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct.h
+++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct.h
@@ -87,10 +87,8 @@ struct flcn_ucode_img {
 	u32 data_size;
 	struct lsf_ucode_desc *lsf_desc;
 	bool is_next_core_img;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	struct lsf_ucode_desc_wrapper *lsf_desc_wrapper;
 	struct falcon_next_core_ucode_desc *ndesc;
-#endif
 };
 
 struct lsfm_managed_ucode_img {
@@ -144,10 +142,8 @@ struct ls_flcn_mgr {
 int nvgpu_acr_prepare_ucode_blob(struct gk20a *g);
 #ifdef CONFIG_NVGPU_LS_PMU
 int nvgpu_acr_lsf_pmu_ucode_details(struct gk20a *g, void *lsf_ucode_img);
-#if defined(CONFIG_NVGPU_NON_FUSA)
 s32 nvgpu_acr_lsf_pmu_ncore_ucode_details(struct gk20a *g, void *lsf_ucode_img);
 #endif
-#endif
 int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img);
 int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img);
 #ifdef CONFIG_NVGPU_DGPU
diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c
index 2ebb763e3..59cf2edf9 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c
+++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c
@@ -31,10 +31,8 @@
 #include <nvgpu/acr.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/soc.h>
-#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
 #include <nvgpu/riscv.h>
 #include <nvgpu/io.h>
-#endif
 
 #include "acr_bootstrap.h"
 #include "acr_priv.h"
@@ -266,7 +264,6 @@ err_free_ucode:
 	return err;
 }
 
-#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
 #define RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS   10000 /*in msec */
 #define RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS       100   /*in msec */
 
@@ -409,4 +406,3 @@ exit:
 
 	return err;
 }
-#endif
diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h
index f63199ecd..0ebd2f0eb 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h
+++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h
@@ -113,11 +113,9 @@ struct hs_acr {
 		struct flcn_acr_desc *acr_dmem_desc;
 	};
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	struct nvgpu_mem acr_falcon2_sysmem_desc;
 	struct flcn2_acr_desc acr_sysmem_desc;
 	struct nvgpu_mem ls_pmu_desc;
-#endif
 
 	/* Falcon used to execute ACR ucode */
 	struct nvgpu_falcon *acr_flcn;
@@ -134,9 +132,6 @@ int nvgpu_acr_wait_for_completion(struct gk20a *g, struct hs_acr *acr_desc,
 int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr,
 	struct hs_acr *acr_desc);
 
-
-#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
 int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr);
-#endif
 
 #endif /* ACR_BOOTSTRAP_H */
diff --git a/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c b/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c
index f0ded89ec..ed4792a87 100644
--- a/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c
+++ b/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c
@@ -195,7 +195,6 @@ void nvgpu_cic_mon_intr_stall_handle(struct gk20a *g)
 	(void)nvgpu_cic_rm_broadcast_last_irq_stall(g);
 }
 
-#ifdef CONFIG_NVGPU_NON_FUSA
 void nvgpu_cic_mon_intr_enable(struct gk20a *g)
 {
 	unsigned long flags = 0;
@@ -272,4 +271,3 @@ bool nvgpu_cic_mon_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
 
 	return true;
 }
-#endif
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c
index 78a0e49d9..466204d9a 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon.c
@@ -29,10 +29,7 @@
 #ifdef CONFIG_NVGPU_DGPU
 #include "falcon_sw_tu104.h"
 #endif
-
-#ifdef CONFIG_NVGPU_NON_FUSA
 #include "falcon_sw_ga10b.h"
-#endif /* CONFIG_NVGPU_NON_FUSA */
 
 #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 #include <nvgpu_next_falcon.h>
@@ -394,7 +391,6 @@ u32 nvgpu_falcon_get_id(struct nvgpu_falcon *flcn)
 	return flcn->flcn_id;
 }
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 bool nvgpu_falcon_is_falcon2_enabled(struct nvgpu_falcon *flcn)
 {
 	return flcn->is_falcon2_enabled ? true : false;
@@ -405,7 +401,6 @@ bool nvgpu_falcon_is_feature_supported(struct nvgpu_falcon *flcn,
 {
 	return nvgpu_test_bit(feature, (void *)&flcn->fuse_settings);
 }
-#endif
 
 struct nvgpu_falcon *nvgpu_falcon_get_instance(struct gk20a *g, u32 flcn_id)
 {
@@ -455,9 +450,6 @@ static int falcon_sw_chip_init(struct gk20a *g, struct nvgpu_falcon *flcn)
 	case NVGPU_GPUID_GP10B:
 		gk20a_falcon_sw_init(flcn);
 		break;
-	case NVGPU_GPUID_GA10B:
-		ga10b_falcon_sw_init(flcn);
-		break;
 #ifdef CONFIG_NVGPU_DGPU
 	case NVGPU_GPUID_TU104:
 	case NVGPU_GPUID_GA100:
@@ -465,6 +457,9 @@ static int falcon_sw_chip_init(struct gk20a *g, struct nvgpu_falcon *flcn)
 		break;
 #endif /* CONFIG_NVGPU_DGPU */
 #endif /* CONFIG_NVGPU_NON_FUSA */
+	case NVGPU_GPUID_GA10B:
+		ga10b_falcon_sw_init(flcn);
+		break;
 	case NVGPU_GPUID_GV11B:
 		gk20a_falcon_sw_init(flcn);
 		break;
@@ -561,6 +556,18 @@ void nvgpu_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable,
 	g->ops.falcon.set_irq(flcn, enable, intr_mask, intr_dest);
 }
 
+int nvgpu_falcon_get_mem_size(struct nvgpu_falcon *flcn,
+			      enum falcon_mem_type type, u32 *size)
+{
+	if (!is_falcon_valid(flcn)) {
+		return -EINVAL;
+	}
+
+	*size = flcn->g->ops.falcon.get_mem_size(flcn, type);
+
+	return 0;
+}
+
 #ifdef CONFIG_NVGPU_DGPU
 int nvgpu_falcon_copy_from_emem(struct nvgpu_falcon *flcn,
 	u32 src, u8 *dst, u32 size, u8 port)
@@ -642,18 +649,6 @@ int nvgpu_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector)
 	return 0;
 }
 
-int nvgpu_falcon_get_mem_size(struct nvgpu_falcon *flcn,
-			      enum falcon_mem_type type, u32 *size)
-{
-	if (!is_falcon_valid(flcn)) {
-		return -EINVAL;
-	}
-
-	*size = flcn->g->ops.falcon.get_mem_size(flcn, type);
-
-	return 0;
-}
-
 int nvgpu_falcon_clear_halt_intr_status(struct nvgpu_falcon *flcn,
 	unsigned int timeout)
 {
diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c
index 877231f5c..09c9bfeec 100644
--- a/drivers/gpu/nvgpu/common/fifo/engines.c
+++ b/drivers/gpu/nvgpu/common/fifo/engines.c
@@ -707,7 +707,6 @@ u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg)
 }
 
 
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 int nvgpu_engine_init_one_dev_extra(struct gk20a *g,
 		const struct nvgpu_device *dev)
 {
@@ -752,7 +751,6 @@ int nvgpu_engine_init_one_dev_extra(struct gk20a *g,
 
 	return 0;
 }
-#endif
 
 static int nvgpu_engine_init_one_dev(struct nvgpu_fifo *f,
 				     const struct nvgpu_device *dev)
@@ -781,7 +779,6 @@ static int nvgpu_engine_init_one_dev(struct nvgpu_fifo *f,
 		}
 	}
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	{
 		/*
 		 * Fill Ampere+ device fields.
@@ -791,7 +788,6 @@ static int nvgpu_engine_init_one_dev(struct nvgpu_fifo *f,
 			return err;
 		}
 	}
-#endif
 
 	f->host_engines[dev->engine_id] = dev;
 	f->active_engines[f->num_engines] = dev;
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist.c b/drivers/gpu/nvgpu/common/fifo/runlist.c
index 50de604ed..36522fb8b 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist.c
+++ b/drivers/gpu/nvgpu/common/fifo/runlist.c
@@ -861,7 +861,6 @@ void nvgpu_runlist_cleanup_sw(struct gk20a *g)
 	f->max_runlists = 0;
 }
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 static void nvgpu_runlist_init_engine_info(struct gk20a *g,
 		struct nvgpu_runlist *runlist,
 		const struct nvgpu_device *dev)
@@ -919,7 +918,6 @@ static u32 nvgpu_runlist_get_pbdma_mask(struct gk20a *g,
 	}
 	return pbdma_mask;
 }
-#endif /* CONFIG_NVGPU_NON_FUSA */
 
 void nvgpu_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f)
 {
@@ -943,13 +941,11 @@ void nvgpu_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f)
 
 			if (dev->runlist_id == runlist->id) {
 				runlist->eng_bitmask |= BIT32(dev->engine_id);
-#ifdef CONFIG_NVGPU_NON_FUSA
 				/*
 				 * Populate additional runlist fields on
 				 * Ampere+ chips.
 				 */
 				nvgpu_runlist_init_engine_info(g, runlist, dev);
-#endif /* CONFIG_NVGPU_NON_FUSA */
 			}
 		}
 
@@ -966,12 +962,10 @@ void nvgpu_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f)
 						runlist->id,
 						&runlist->pbdma_bitmask);
 		}
-#ifdef CONFIG_NVGPU_NON_FUSA
 		else {
 			runlist->pbdma_bitmask =
 				nvgpu_runlist_get_pbdma_mask(g, runlist);
 		}
-#endif /* CONFIG_NVGPU_NON_FUSA */
 		nvgpu_log(g, gpu_dbg_info, "  Active engine bitmask: 0x%x", runlist->eng_bitmask);
 		nvgpu_log(g, gpu_dbg_info, "          PBDMA bitmask: 0x%x", runlist->pbdma_bitmask);
 	}
diff --git a/drivers/gpu/nvgpu/common/gr/fs_state.c b/drivers/gpu/nvgpu/common/gr/fs_state.c
index 847a59957..8dad304d1 100644
--- a/drivers/gpu/nvgpu/common/gr/fs_state.c
+++ b/drivers/gpu/nvgpu/common/gr/fs_state.c
@@ -139,7 +139,6 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
 	return err;
 }
 
-#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config)
 {
 	u32 tpc_index, gpc_index;
@@ -169,5 +168,3 @@ int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *co
 
 	return err;
 }
-#endif
-
diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c
index 025e734a4..d1631a6be 100644
--- a/drivers/gpu/nvgpu/common/gr/gr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr.c
@@ -223,11 +223,9 @@ static int gr_init_setup_hw(struct gk20a *g, struct nvgpu_gr *gr)
 
 	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.gr.init.eng_config != NULL) {
 		g->ops.gr.init.eng_config(g);
 	}
-#endif
 
 	g->ops.gr.init.gpc_mmu(g);
 
@@ -565,10 +563,8 @@ static int gr_init_prepare_hw_impl(struct gk20a *g)
 			sw_non_ctx_load->l[i].value);
 	}
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	nvgpu_gr_init_reset_enable_hw_non_ctx_local(g);
 	nvgpu_gr_init_reset_enable_hw_non_ctx_global(g);
-#endif
 	nvgpu_log_info(g, "end: netlist: sw_non_ctx_load: register writes");
 
 	err = g->ops.gr.falcon.wait_mem_scrubbing(g);
@@ -621,7 +617,6 @@ static int gr_reset_engine(struct gk20a *g)
 		return err;
 	}
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.gr.init.reset_gpcs != NULL) {
 		err = g->ops.gr.init.reset_gpcs(g);
 		if (err != 0) {
@@ -629,7 +624,6 @@ static int gr_reset_engine(struct gk20a *g)
 			return err;
 		}
 	}
-#endif
 
 	err = g->ops.mc.enable_dev(g, dev, true);
 	if (err != 0) {
@@ -797,7 +791,6 @@ int nvgpu_gr_reset(struct gk20a *g)
 }
 #endif
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 static int gr_init_sm_id_config_early(struct gk20a *g, struct nvgpu_gr *gr)
 {
 	int err;
@@ -811,7 +804,6 @@ static int gr_init_sm_id_config_early(struct gk20a *g, struct nvgpu_gr *gr)
 
 	return 0;
 }
-#endif
 
 static int gr_init_ctxsw_falcon_support(struct gk20a *g, struct nvgpu_gr *gr)
 {
@@ -853,7 +845,6 @@ static int gr_init_support_impl(struct gk20a *g)
 		}
 	}
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	/*
 	 * Move sm id programming before loading ctxsw and gpccs firmwares. This
 	 * is the actual sequence expected by ctxsw ucode.
@@ -862,7 +853,6 @@ static int gr_init_support_impl(struct gk20a *g)
 	if (err != 0) {
 		return err;
 	}
-#endif
 
 	err = gr_init_ctxsw_falcon_support(g, gr);
 	if (err != 0) {
@@ -1214,7 +1204,6 @@ u32 nvgpu_gr_get_tpc_num(struct gk20a *g, u32 addr)
 	return 0;
 }
 
-#ifdef CONFIG_NVGPU_NON_FUSA
 void nvgpu_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g)
 {
 	u32 i = 0U;
@@ -1268,4 +1257,3 @@ void nvgpu_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g)
 
 	return;
 }
-#endif
diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
index a3acd6ec5..a0d530b4f 100644
--- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c
+++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
@@ -576,21 +576,17 @@ static int nvgpu_gr_obj_ctx_commit_hw_state(struct gk20a *g,
 	if (err != 0) {
 		goto restore_fe_go_idle;
 	}
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.gr.init.auto_go_idle != NULL) {
 		g->ops.gr.init.auto_go_idle(g, false);
 	}
-#endif
 	err = nvgpu_gr_obj_ctx_alloc_sw_bundle(g);
 	if (err != 0) {
 		goto restore_fe_go_idle;
 	}
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.gr.init.auto_go_idle != NULL) {
 		g->ops.gr.init.auto_go_idle(g, true);
 	}
-#endif
 
 	/* restore fe_go_idle */
 	g->ops.gr.init.fe_go_idle_timeout(g, true);
@@ -617,11 +613,9 @@ static int nvgpu_gr_obj_ctx_commit_hw_state(struct gk20a *g,
 restore_fe_go_idle:
 	/* restore fe_go_idle */
 	g->ops.gr.init.fe_go_idle_timeout(g, true);
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.gr.init.auto_go_idle != NULL) {
 		g->ops.gr.init.auto_go_idle(g, true);
 	}
-#endif
 
 clean_up:
 	return err;
diff --git a/drivers/gpu/nvgpu/common/netlist/netlist.c b/drivers/gpu/nvgpu/common/netlist/netlist.c
index 72fdf061f..697ce0fc5 100644
--- a/drivers/gpu/nvgpu/common/netlist/netlist.c
+++ b/drivers/gpu/nvgpu/common/netlist/netlist.c
@@ -897,6 +897,32 @@ u32 *nvgpu_netlist_get_gpccs_data_list(struct gk20a *g)
 	return g->netlist_vars->ucode.gpccs.data.l;
 }
 
+struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_compute_load_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->sw_non_ctx_local_compute_load;
+}
+
+struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_compute_load_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->sw_non_ctx_global_compute_load;
+}
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_gfx_load_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->sw_non_ctx_local_gfx_load;
+}
+
+struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_gfx_load_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->sw_non_ctx_global_gfx_load;
+}
+#endif /* CONFIG_NVGPU_GRAPHICS */
+
 #ifdef CONFIG_NVGPU_DEBUGGER
 struct netlist_aiv_list *nvgpu_netlist_get_sys_ctxsw_regs(struct gk20a *g)
 {
@@ -1304,31 +1330,4 @@ u32 nvgpu_netlist_get_sys_ctxsw_regs_count(struct gk20a *g)
 	return count;
 }
 #endif /* CONFIG_NVGPU_DEBUGGER */
-
-struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_compute_load_av_list(
-							struct gk20a *g)
-{
-	return &g->netlist_vars->sw_non_ctx_local_compute_load;
-}
-
-struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_compute_load_av_list(
-							struct gk20a *g)
-{
-	return &g->netlist_vars->sw_non_ctx_global_compute_load;
-}
-
-#ifdef CONFIG_NVGPU_GRAPHICS
-struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_gfx_load_av_list(
-							struct gk20a *g)
-{
-	return &g->netlist_vars->sw_non_ctx_local_gfx_load;
-}
-
-struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_gfx_load_av_list(
-							struct gk20a *g)
-{
-	return &g->netlist_vars->sw_non_ctx_global_gfx_load;
-}
-#endif /* CONFIG_NVGPU_GRAPHICS */
-
 #endif
diff --git a/drivers/gpu/nvgpu/common/netlist/netlist_priv.h b/drivers/gpu/nvgpu/common/netlist/netlist_priv.h
index 40f1a88e0..0ad50e210 100644
--- a/drivers/gpu/nvgpu/common/netlist/netlist_priv.h
+++ b/drivers/gpu/nvgpu/common/netlist/netlist_priv.h
@@ -136,14 +136,12 @@ struct nvgpu_netlist_vars {
 	struct netlist_av_list  sw_method_init;
 	struct netlist_aiv_list sw_ctx_load;
 	struct netlist_av_list  sw_non_ctx_load;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	struct netlist_av_list  sw_non_ctx_local_compute_load;
 	struct netlist_av_list  sw_non_ctx_global_compute_load;
 #ifdef CONFIG_NVGPU_GRAPHICS
 	struct netlist_av_list  sw_non_ctx_local_gfx_load;
 	struct netlist_av_list  sw_non_ctx_global_gfx_load;
 #endif  /* CONFIG_NVGPU_GRAPHICS */
-#endif
 	struct netlist_av_list  sw_veid_bundle_init;
 #ifdef CONFIG_NVGPU_DEBUGGER
 	struct {
diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
index 2180289da..6da173b8a 100644
--- a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
+++ b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
@@ -1033,11 +1033,9 @@ int nvgpu_pmu_pg_init(struct gk20a *g, struct nvgpu_pmu *pmu,
 		nvgpu_gv11b_pg_sw_init(g, *pg_p);
 		break;
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	case NVGPU_GPUID_GA10B:
 		nvgpu_ga10b_pg_sw_init(g, *pg_p);
 		break;
-#endif /* CONFIG_NVGPU_NON_FUSA */
 
 	default:
 #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
diff --git a/drivers/gpu/nvgpu/common/power_features/cg/cg.c b/drivers/gpu/nvgpu/common/power_features/cg/cg.c
index 562d2e7cc..0c6769ecd 100644
--- a/drivers/gpu/nvgpu/common/power_features/cg/cg.c
+++ b/drivers/gpu/nvgpu/common/power_features/cg/cg.c
@@ -110,11 +110,9 @@ void nvgpu_cg_blcg_fifo_load_enable(struct gk20a *g)
 	if (g->ops.cg.blcg_fifo_load_gating_prod != NULL) {
 		g->ops.cg.blcg_fifo_load_gating_prod(g, true);
 	}
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.cg.blcg_runlist_load_gating_prod != NULL) {
 		g->ops.cg.blcg_runlist_load_gating_prod(g, true);
 	}
-#endif
 done:
 	nvgpu_mutex_release(&g->cg_pg_lock);
 }
@@ -188,7 +186,6 @@ static void nvgpu_cg_slcg_priring_load_prod(struct gk20a *g, bool enable)
 	if (g->ops.cg.slcg_priring_load_gating_prod != NULL) {
 		g->ops.cg.slcg_priring_load_gating_prod(g, enable);
 	}
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.cg.slcg_rs_ctrl_fbp_load_gating_prod != NULL) {
 		g->ops.cg.slcg_rs_ctrl_fbp_load_gating_prod(g, enable);
 	}
@@ -207,7 +204,6 @@ static void nvgpu_cg_slcg_priring_load_prod(struct gk20a *g, bool enable)
 	if (g->ops.cg.slcg_rs_sys_load_gating_prod != NULL) {
 		g->ops.cg.slcg_rs_sys_load_gating_prod(g, enable);
 	}
-#endif
 
 }
 
@@ -236,11 +232,9 @@ void nvgpu_cg_slcg_fifo_load_enable(struct gk20a *g)
 	if (g->ops.cg.slcg_fifo_load_gating_prod != NULL) {
 		g->ops.cg.slcg_fifo_load_gating_prod(g, true);
 	}
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.cg.slcg_runlist_load_gating_prod != NULL) {
 		g->ops.cg.slcg_runlist_load_gating_prod(g, true);
 	}
-#endif
 done:
 	nvgpu_mutex_release(&g->cg_pg_lock);
 }
@@ -507,11 +501,9 @@ void nvgpu_cg_elcg_set_elcg_enabled(struct gk20a *g, bool enable)
 			nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_RUN);
 		}
 	}
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.cg.elcg_ce_load_gating_prod != NULL) {
 		g->ops.cg.elcg_ce_load_gating_prod(g, g->elcg_enabled);
 	}
-#endif
 	nvgpu_mutex_release(&g->cg_pg_lock);
 }
 
@@ -554,11 +546,9 @@ void nvgpu_cg_blcg_set_blcg_enabled(struct gk20a *g, bool enable)
 	if (g->ops.cg.blcg_gr_load_gating_prod != NULL) {
 		g->ops.cg.blcg_gr_load_gating_prod(g, enable);
 	}
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.cg.blcg_runlist_load_gating_prod != NULL) {
 		g->ops.cg.blcg_runlist_load_gating_prod(g, enable);
 	}
-#endif
 	if (g->ops.cg.blcg_ltc_load_gating_prod != NULL) {
 		g->ops.cg.blcg_ltc_load_gating_prod(g, enable);
 	}
@@ -615,14 +605,12 @@ void nvgpu_cg_slcg_set_slcg_enabled(struct gk20a *g, bool enable)
 	if (g->ops.cg.slcg_fifo_load_gating_prod != NULL) {
 		g->ops.cg.slcg_fifo_load_gating_prod(g, enable);
 	}
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.cg.slcg_runlist_load_gating_prod != NULL) {
 		g->ops.cg.slcg_runlist_load_gating_prod(g, enable);
 	}
 	if (g->ops.cg.slcg_timer_load_gating_prod != NULL) {
 		g->ops.cg.slcg_timer_load_gating_prod(g, enable);
 	}
-#endif
 	if (g->ops.cg.slcg_gr_load_gating_prod != NULL) {
 		g->ops.cg.slcg_gr_load_gating_prod(g, enable);
 	}
@@ -657,11 +645,9 @@ void nvgpu_cg_elcg_ce_load_enable(struct gk20a *g)
 	if (!g->elcg_enabled) {
 		goto done;
 	}
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.cg.elcg_ce_load_gating_prod != NULL) {
 		g->ops.cg.elcg_ce_load_gating_prod(g, true);
 	}
-#endif
 done:
 	nvgpu_mutex_release(&g->cg_pg_lock);
 }
diff --git a/drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c
index 2e53334e8..c02f719ba 100644
--- a/drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c
@@ -242,4 +242,5 @@ void ga10b_ce_request_idle(struct gk20a *g)
 	 */
 
 	num_pce = g->ops.ce.get_num_pce(g);
+	nvgpu_log_info(g, "num_pce=%u", num_pce);
 }
diff --git a/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c
index db63d1377..41f83872f 100644
--- a/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c
@@ -184,6 +184,7 @@ void ga10b_falcon_dump_stats(struct nvgpu_falcon *flcn)
 		gk20a_falcon_dump_stats(flcn);
 	}
 }
+#endif /* CONFIG_NVGPU_FALCON_DEBUG */
 
 bool ga10b_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn)
 {
@@ -217,4 +218,3 @@ bool ga10b_is_falcon_idle(struct nvgpu_falcon *flcn)
 	}
 	return true;
 }
-#endif /* CONFIG_NVGPU_FALCON_DEBUG */
diff --git a/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c
index 074112dc3..d81042b46 100644
--- a/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c
@@ -219,9 +219,11 @@ void ga10b_fifo_ctxsw_timeout_isr(struct gk20a *g,
 			struct nvgpu_runlist *runlist)
 {
 	u32 rleng, reg_val, timeout;
-	u32 active_eng_id;
 	u32 ms = 0U;
+#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
+	u32 active_eng_id;
 	bool recover = false;
+#endif
 	u32 info_status;
 	u32 tsgid = NVGPU_INVALID_TSG_ID;
 	const struct nvgpu_device *dev;
diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/fifo_ga10b_fusa.c
index 8a24adda3..b44e272d9 100644
--- a/drivers/gpu/nvgpu/hal/fifo/fifo_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fifo/fifo_ga10b_fusa.c
@@ -71,9 +71,11 @@ int ga10b_init_fifo_reset_enable_hw(struct gk20a *g)
 		g->ops.pbdma.setup_hw(g);
 	}
 
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	if (g->ops.pbdma.pbdma_force_ce_split != NULL) {
 		g->ops.pbdma.pbdma_force_ce_split(g);
 	}
+#endif
 
 	nvgpu_log_fn(g, "done");
 
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
index e5545c8bd..3656fe7a9 100644
--- a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -64,9 +64,7 @@ u32 ga10b_pbdma_set_clear_intr_offsets(struct gk20a *g,
 
 u32 ga10b_pbdma_get_fc_target(const struct nvgpu_device *dev);
 
-#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 void ga10b_pbdma_dump_status(struct gk20a *g, struct nvgpu_debug_context *o);
-#endif
 
 u32 ga10b_pbdma_get_mmu_fault_id(struct gk20a *g, u32 pbdma_id);
 u32 ga10b_pbdma_get_num_of_pbdmas(void);
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c
index b16e50e62..8bd38528a 100644
--- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -34,6 +34,7 @@ u32 ga10b_ctxsw_prog_hw_get_fecs_header_size(void)
 	return ctxsw_prog_fecs_header_size_in_bytes_v();
 }
 
+#ifdef CONFIG_NVGPU_DEBUGGER
 u32 ga10b_ctxsw_prog_hw_get_main_header_size(void)
 {
 	return ctxsw_prog_ctxsw_header_size_in_bytes_v();
@@ -120,3 +121,4 @@ u32 ga10b_ctxsw_prog_get_gfx_etpcreglist_offset(u32 *gpccs_hdr)
 		gpccs_hdr[ctxsw_prog_local_ext_tpc_reglist_offset_o() >>
 		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
 }
+#endif /* CONFIG_NVGPU_DEBUGGER */
diff --git a/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.c b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.c
index f4f52fe1e..63384cb6d 100644
--- a/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,6 +20,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#ifdef CONFIG_NVGPU_INJECT_HWERR
 #include <nvgpu/io.h>
 #include <nvgpu/gk20a.h>
 
@@ -62,3 +63,4 @@ struct nvgpu_hw_err_inject_info_desc *
 
 	return &mmu_err_desc;
 }
+#endif /* CONFIG_NVGPU_INJECT_HWERR */
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c
index 85c51126d..82c01129d 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c
@@ -357,6 +357,7 @@ void gr_ga100_set_circular_buffer_size(struct gk20a *g, u32 data)
 	}
 }
 
+#ifdef CONFIG_NVGPU_DEBUGGER
 /*
  * The sys, tpc, etpc, ppc and gpc ctxsw_reg bundles are divided into compute
  * and gfx. These registers are stored contigously in a single buffer segment.
@@ -663,3 +664,4 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g,
 	}
 	return -EINVAL;
 }
+#endif
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c
index ce3b37f78..8e15e6572 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c
@@ -1063,6 +1063,7 @@ const u32 *ga10b_gr_get_hwpm_cau_init_data(u32 *count)
 
 #endif /* CONFIG_NVGPU_DEBUGGER */
 
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 void ga10b_gr_vab_init(struct gk20a *g, u32 vab_reg, u32 num_range_checkers,
 	struct nvgpu_vab_range_checker *vab_range_checker)
 {
@@ -1098,3 +1099,4 @@ void ga10b_gr_vab_release(struct gk20a *g, u32 vab_reg)
 {
 	nvgpu_writel(g, gr_gpcs_mmu_vidmem_access_bit_r(), vab_reg);
 }
+#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.h
index 632de9e02..b6c4ffb29 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.h
@@ -40,9 +40,11 @@ int gr_ga10b_dump_gr_status_regs(struct gk20a *g,
 				 struct nvgpu_debug_context *o);
 void gr_ga10b_set_circular_buffer_size(struct gk20a *g, u32 data);
 void ga10b_gr_set_gpcs_rops_crop_debug4(struct gk20a *g, u32 data);
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 void ga10b_gr_vab_init(struct gk20a *g, u32 vab_reg, u32 num_range_checkers,
 	struct nvgpu_vab_range_checker *vab_range_checker);
 void ga10b_gr_vab_release(struct gk20a *g, u32 vab_reg);
+#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
 
 #ifdef CONFIG_NVGPU_DEBUGGER
 int gr_ga10b_create_priv_addr_table(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c
index 0ce789573..fe6ab2dec 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c
@@ -97,11 +97,13 @@ u32 ga10b_gr_intr_enable_mask(struct gk20a *g)
 int ga10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			u32 class_num, u32 offset, u32 data)
 {
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) || (defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS))
 	/*
 	 * Hardware divides sw_method enum value by 2 before passing as "offset".
 	 * Left shift given offset by 2 to obtain sw_method enum value.
 	 */
 	u32 left_shift_by_2 = 2U;
+#endif
 
 	nvgpu_log_fn(g, " ");
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
index 43019500c..cc223760e 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
@@ -584,7 +584,9 @@ static const struct gops_gr_hwpm_map ga100_ops_gr_hwpm_map = {
 static const struct gops_gr_init ga100_ops_gr_init = {
 	.get_no_of_sm = nvgpu_gr_get_no_of_sm,
 	.get_nonpes_aware_tpc = gv11b_gr_init_get_nonpes_aware_tpc,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	.wait_initialized = nvgpu_gr_wait_initialized,
+#endif
 	.ecc_scrub_reg = NULL,
 	.lg_coalesce = NULL,
 	.su_coalesce = NULL,
@@ -1045,7 +1047,9 @@ static const struct gops_pbdma ga100_ops_pbdma = {
 	.set_channel_info_veid = gv11b_pbdma_set_channel_info_veid,
 	.set_channel_info_chid = ga10b_pbdma_set_channel_info_chid,
 	.set_intr_notify = ga10b_pbdma_set_intr_notify,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	.pbdma_force_ce_split = ga100_pbdma_force_ce_split,
+#endif
 	.config_userd_writeback_enable = gv11b_pbdma_config_userd_writeback_enable,
 	.get_mmu_fault_id = ga10b_pbdma_get_mmu_fault_id,
 	.get_num_of_pbdmas = ga100_pbdma_get_num_of_pbdmas,
@@ -1426,7 +1430,9 @@ static const struct gops_mc ga100_ops_mc = {
 	.fb_reset = NULL,
 	.ltc_isr = mc_tu104_ltc_isr,
 	.is_mmu_fault_pending = ga10b_intr_is_mmu_fault_pending,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	.intr_get_unit_info = ga10b_mc_intr_get_unit_info,
+#endif
 };
 #endif
 
@@ -1705,7 +1711,9 @@ static const struct gops_grmgr ga100_ops_grmgr = {
 #else
 	.init_gr_manager = nvgpu_init_gr_manager,
 #endif
+#ifdef CONFIG_NVGPU_NON_FUSA
 	.load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod,
+#endif
 	.discover_gpc_ids = ga10b_grmgr_discover_gpc_ids,
 };
 #endif
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index df2dc689e..3f348479b 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -563,7 +563,9 @@ static const struct gops_gr_hwpm_map ga10b_ops_gr_hwpm_map = {
 static const struct gops_gr_init ga10b_ops_gr_init = {
 	.get_no_of_sm = nvgpu_gr_get_no_of_sm,
 	.get_nonpes_aware_tpc = gv11b_gr_init_get_nonpes_aware_tpc,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	.wait_initialized = nvgpu_gr_wait_initialized,
+#endif
 	/* Since ecc scrubbing is moved to ctxsw ucode, setting HAL to NULL */
 	.ecc_scrub_reg = NULL,
 	.lg_coalesce = NULL,
@@ -761,8 +763,10 @@ static const struct gops_gr_falcon ga10b_ops_gr_falcon = {
 static const struct gops_gr ga10b_ops_gr = {
 	.gr_init_support = nvgpu_gr_init_support,
 	.gr_suspend = nvgpu_gr_suspend,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	.vab_init = ga10b_gr_vab_init,
 	.vab_release = ga10b_gr_vab_release,
+#endif
 #ifdef CONFIG_NVGPU_DEBUGGER
 	.get_gr_status = gr_gm20b_get_gr_status,
 	.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size,
@@ -856,6 +860,7 @@ static const struct gops_fb_intr ga10b_ops_fb_intr = {
 	.handle_ecc_fillunit = ga10b_fb_intr_handle_ecc_fillunit,
 };
 
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 static const struct gops_fb_vab ga10b_ops_fb_vab = {
 	.init = ga10b_fb_vab_init,
 	.reserve = ga10b_fb_vab_reserve,
@@ -863,6 +868,7 @@ static const struct gops_fb_vab ga10b_ops_fb_vab = {
 	.release = ga10b_fb_vab_release,
 	.teardown = ga10b_fb_vab_teardown,
 };
+#endif
 
 static const struct gops_fb ga10b_ops_fb = {
 #ifdef CONFIG_NVGPU_INJECT_HWERR
@@ -1302,8 +1308,6 @@ static const struct gops_pmu ga10b_ops_pmu = {
 	.is_debug_mode_enabled = ga10b_pmu_is_debug_mode_en,
 	/* aperture set up is moved to acr */
 	.setup_apertures = NULL,
-	.secured_pmu_start = gv11b_secured_pmu_start,
-	.write_dmatrfbase = gv11b_write_dmatrfbase,
 	.flcn_setup_boot_config = gv11b_pmu_flcn_setup_boot_config,
 	.pmu_clear_bar0_host_err_status = gv11b_clear_pmu_bar0_host_err_status,
 	.bar0_error_status = gv11b_pmu_bar0_error_status,
@@ -1351,6 +1355,8 @@ static const struct gops_pmu ga10b_ops_pmu = {
 	.pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats,
 	/* PMU ucode */
 	.pmu_ns_bootstrap = ga10b_pmu_ns_bootstrap,
+	.secured_pmu_start = gv11b_secured_pmu_start,
+	.write_dmatrfbase = gv11b_write_dmatrfbase,
 #endif
 };
 
@@ -1435,7 +1441,9 @@ static const struct gops_mc ga10b_ops_mc = {
 	.fb_reset = NULL,
 	.ltc_isr = mc_tu104_ltc_isr,
 	.is_mmu_fault_pending = ga10b_intr_is_mmu_fault_pending,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	.intr_get_unit_info = ga10b_mc_intr_get_unit_info,
+#endif
 };
 
 static const struct gops_debug ga10b_ops_debug = {
@@ -1623,8 +1631,10 @@ static const struct gops_fuse ga10b_ops_fuse = {
 	.read_vin_cal_gain_offset_fuse = NULL,
 	.read_gcplex_config_fuse = ga10b_fuse_read_gcplex_config_fuse,
 	.fuse_status_opt_gpc = ga10b_fuse_status_opt_gpc,
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	.write_feature_override_ecc = ga10b_fuse_write_feature_override_ecc,
 	.write_feature_override_ecc_1 = ga10b_fuse_write_feature_override_ecc_1,
+#endif
 	.read_feature_override_ecc = ga10b_fuse_read_feature_override_ecc,
 	.read_per_device_identifier = ga10b_fuse_read_per_device_identifier,
 	.fetch_falcon_fuse_settings = ga10b_fetch_falcon_fuse_settings,
@@ -1672,7 +1682,9 @@ static const struct gops_grmgr ga10b_ops_grmgr = {
 #else
 	.init_gr_manager = nvgpu_init_gr_manager,
 #endif
+#ifdef CONFIG_NVGPU_NON_FUSA
 	.load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod,
+#endif
 	.discover_gpc_ids = ga10b_grmgr_discover_gpc_ids,
 };
 
@@ -1721,7 +1733,9 @@ int ga10b_init_hal(struct gk20a *g)
 	gops->fb = ga10b_ops_fb;
 	gops->fb.ecc = ga10b_ops_fb_ecc;
 	gops->fb.intr = ga10b_ops_fb_intr;
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	gops->fb.vab = ga10b_ops_fb_vab;
+#endif
 	gops->cg = ga10b_ops_cg;
 	gops->fifo = ga10b_ops_fifo;
 	gops->engine = ga10b_ops_engine;
diff --git a/drivers/gpu/nvgpu/hal/init/hal_init.c b/drivers/gpu/nvgpu/hal/init/hal_init.c
index 00eff52a2..f5c3ca991 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_init.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_init.c
@@ -32,16 +32,11 @@
 #include "hal_gm20b.h"
 #include "hal_gp10b.h"
 #include "hal_gv11b.h"
+#include "hal_ga10b.h"
 #ifdef CONFIG_NVGPU_DGPU
 #include "hal_tu104.h"
-#endif
-
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
-#include "hal_ga10b.h"
-#if defined(CONFIG_NVGPU_DGPU)
 #include "hal_ga100.h"
 #endif
-#endif
 
 #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 #include <nvgpu_next_hal_init.h>
@@ -73,13 +68,12 @@ int nvgpu_init_hal(struct gk20a *g)
 			err = -ENODEV;
 		}
 		break;
+#endif
 	case NVGPU_GPUID_GA10B:
 		if (ga10b_init_hal(g) != 0) {
 			err = -ENODEV;
 		}
 		break;
-#endif
-
 	case NVGPU_GPUID_GV11B:
 		if (gv11b_init_hal(g) != 0) {
 			err = -ENODEV;
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.c
index 602001541..a7b367e63 100644
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.c
@@ -29,6 +29,7 @@
 
 #include <nvgpu/hw/ga10b/hw_ltc_ga10b.h>
 
+#ifdef CONFIG_NVGPU_GRAPHICS
 void ga10b_ltc_set_zbc_stencil_entry(struct gk20a *g, u32 stencil_depth,
 					u32 index)
 {
@@ -65,7 +66,9 @@ void ga10b_ltc_set_zbc_depth_entry(struct gk20a *g, u32 depth_val, u32 index)
 	nvgpu_writel(g,
 		ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), depth_val);
 }
+#endif
 
+#ifdef CONFIG_NVGPU_DEBUGGER
 u32 ga10b_ltc_pri_shared_addr(struct gk20a *g, u32 addr)
 {
 	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
@@ -78,3 +81,4 @@ u32 ga10b_ltc_pri_shared_addr(struct gk20a *g, u32 addr)
 
 	return ltc_shared_base + lts_addr;
 }
+#endif
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h
index df3b38614..e73206824 100644
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h
@@ -29,6 +29,8 @@ struct gk20a;
 
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 u32 ga10b_ltc_zbc_table_size(struct gk20a *g);
+#endif
+#ifdef CONFIG_NVGPU_GRAPHICS
 void ga10b_ltc_set_zbc_stencil_entry(struct gk20a *g, u32 stencil_depth,
 			u32 index);
 void ga10b_ltc_set_zbc_color_entry(struct gk20a *g, u32 *color_l2, u32 index);
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c
index 9d721b30e..fac3bd598 100644
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c
@@ -90,6 +90,7 @@ void ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g)
 	}
 }
 
+#ifdef CONFIG_NVGPU_DEBUGGER
 int ga10b_set_l2_max_ways_evict_last(struct gk20a *g, struct nvgpu_tsg *tsg,
 		u32 num_ways)
 {
@@ -189,6 +190,7 @@ int ga10b_get_l2_max_ways_evict_last(struct gk20a *g, struct nvgpu_tsg *tsg,
 
 	return err;
 }
+#endif /* CONFIG_NVGPU_DEBUGGER */
 
 u64 ga10b_determine_L2_size_bytes(struct gk20a *g)
 {
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c
index 20db19510..c2c57546d 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c
@@ -816,7 +816,9 @@ static void ga10b_intr_isr_stall_host2soc_3(struct gk20a *g)
 		u64 engine_intr_mask;
 		u32 vectorid;
 		const struct nvgpu_device *dev;
+#ifdef CONFIG_NVGPU_POWER_PG
 		int err;
+#endif
 
 		vectorid =
 		   g->mc.intr_unit_info[NVGPU_CIC_INTR_UNIT_CE_STALL].vectorid[0];
@@ -824,6 +826,7 @@ static void ga10b_intr_isr_stall_host2soc_3(struct gk20a *g)
 		handled_subtree_mask |= unit_subtree_mask;
 		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
 
+#ifdef CONFIG_NVGPU_POWER_PG
 		/* disable elpg before accessing CE registers */
 		err = nvgpu_pg_elpg_disable(g);
 		if (err != 0) {
@@ -832,6 +835,7 @@ static void ga10b_intr_isr_stall_host2soc_3(struct gk20a *g)
 			(void) nvgpu_pg_elpg_enable(g);
 			goto exit;
 		}
+#endif
 
 		for (i = 0U; i < g->fifo.num_engines; i++) {
 			dev = g->fifo.active_engines[i];
@@ -852,10 +856,14 @@ static void ga10b_intr_isr_stall_host2soc_3(struct gk20a *g)
 
 		}
 
+#ifdef CONFIG_NVGPU_POWER_PG
 		/* enable elpg again */
 		(void) nvgpu_pg_elpg_enable(g);
+#endif
 	}
+#ifdef CONFIG_NVGPU_POWER_PG
 exit:
+#endif
 	ga10b_intr_subtree_clear_unhandled(g, subtree, intr_leaf0, intr_leaf1,
 				handled_subtree_mask);
 }
diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c
index 8508976f3..b14c02f60 100644
--- a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c
@@ -60,6 +60,7 @@ u32 ga10b_pmu_get_irqmask(struct gk20a *g)
 	return mask;
 }
 
+#ifdef CONFIG_NVGPU_LS_PMU
 static int ga10b_pmu_ns_falcon_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
 			u32 args_offset)
 {
@@ -211,6 +212,7 @@ int ga10b_pmu_ns_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
 
 	return err;
 }
+#endif /* CONFIG_NVGPU_LS_PMU */
 
 void ga10b_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu)
 {
@@ -347,18 +349,18 @@ bool ga10b_pmu_is_debug_mode_en(struct gk20a *g)
 
 void ga10b_pmu_handle_swgen1_irq(struct gk20a *g, u32 intr)
 {
+#ifdef CONFIG_NVGPU_FALCON_DEBUG
 	struct nvgpu_pmu *pmu = g->pmu;
 	int err = 0;
 
 	if ((intr & pwr_falcon_irqstat_swgen1_true_f()) != 0U) {
-#ifdef CONFIG_NVGPU_FALCON_DEBUG
 		err = nvgpu_falcon_dbg_buf_display(pmu->flcn);
 		if (err != 0) {
 			nvgpu_err(g, "nvgpu_falcon_dbg_buf_display failed err=%d",
 				err);
 		}
-#endif
 	}
+#endif
 }
 
 /*
diff --git a/drivers/gpu/nvgpu/include/nvgpu/cic_mon.h b/drivers/gpu/nvgpu/include/nvgpu/cic_mon.h
index c2dc02985..e6ebd0d0b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/cic_mon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/cic_mon.h
@@ -27,8 +27,6 @@
 #include <nvgpu/static_analysis.h>
 #include <nvgpu/log.h>
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
-
 #define U32_BITS		32U
 #define DIV_BY_U32_BITS(x)	((x) / U32_BITS)
 #define MOD_BY_U32_BITS(x)	((x) % U32_BITS)
@@ -91,8 +89,6 @@ bool nvgpu_cic_mon_intr_is_unit_info_valid(struct gk20a *g, u32 unit);
 bool nvgpu_cic_mon_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
 		u64 *subtree_mask);
 
-#endif
-
 struct nvgpu_err_desc;
 /**
  * @file
@@ -641,8 +637,6 @@ void nvgpu_cic_mon_intr_nonstall_pause(struct gk20a *g);
  */
 void nvgpu_cic_mon_intr_nonstall_resume(struct gk20a *g);
 
-#ifdef CONFIG_NVGPU_NON_FUSA
 void nvgpu_cic_mon_intr_enable(struct gk20a *g);
-#endif
 
 #endif /* NVGPU_CIC_MON_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/class.h b/drivers/gpu/nvgpu/include/nvgpu/class.h
index e389179d7..429acecf9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/class.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/class.h
@@ -96,7 +96,6 @@
 #define	TURING_A			0xC597U
 #endif
 
-#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_DGPU)
 /* FIXME: below defines are used in dGPU safety build. */
 #define	MAXWELL_COMPUTE_B		0xB1C0U
 #define	PASCAL_COMPUTE_A		0xC0C0U
@@ -113,6 +112,5 @@
 #define	AMPERE_COMPUTE_B		0xC7C0U
 #define AMPERE_CHANNEL_GPFIFO_A		0xC56FU
 #define AMPERE_CHANNEL_GPFIFO_B		0xC76FU
-#endif
 
 #endif /* NVGPU_CLASS_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/device.h b/drivers/gpu/nvgpu/include/nvgpu/device.h
index 89b41e949..36d0dad10 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/device.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/device.h
@@ -150,7 +150,6 @@ struct nvgpu_device {
 	u32 pbdma_id;
 
 	/** @cond DOXYGEN_SHOULD_SKIP_THIS */
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	/* Ampere+ device info additions */
 
 	/**
@@ -179,7 +178,6 @@ struct nvgpu_device {
 	 * it may make sense to not have this link.
 	 */
 	struct nvgpu_pbdma_info pbdma_info;
-#endif
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/ecc.h b/drivers/gpu/nvgpu/include/nvgpu/ecc.h
index e4ab2fbdd..a531c5032 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/ecc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/ecc.h
@@ -173,12 +173,10 @@ struct nvgpu_ecc {
 		struct nvgpu_ecc_stat **sm_icache_ecc_corrected_err_count;
 		/** SM icache uncorrected error count. */
 		struct nvgpu_ecc_stat **sm_icache_ecc_uncorrected_err_count;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 		/** SM RAMS corrected error count. */
 		struct nvgpu_ecc_stat **sm_rams_ecc_corrected_err_count;
 		/** SM RAMS uncorrected error count. */
 		struct nvgpu_ecc_stat **sm_rams_ecc_uncorrected_err_count;
-#endif
 
 		/** GCC l1.5-cache corrected error count. */
 		struct nvgpu_ecc_stat *gcc_l15_ecc_corrected_err_count;
@@ -229,7 +227,6 @@ struct nvgpu_ecc {
 		struct nvgpu_ecc_stat *mmu_fillunit_ecc_corrected_err_count;
 		/** hubmmu fillunit uncorrected error count. */
 		struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_err_count;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 		/* Leave extra tab to fit into nvgpu_ecc.fb structure */
 		struct nvgpu_ecc_stat *mmu_l2tlb_ecc_corrected_unique_err_count;
 		/** hubmmu l2tlb uncorrected unique error count. */
@@ -242,7 +239,6 @@ struct nvgpu_ecc {
 		struct nvgpu_ecc_stat *mmu_fillunit_ecc_corrected_unique_err_count;
 		/** hubmmu fillunit uncorrected unique error count. */
 		struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_unique_err_count;
-#endif
 	} fb;
 
 	/**
diff --git a/drivers/gpu/nvgpu/include/nvgpu/engine_status.h b/drivers/gpu/nvgpu/include/nvgpu/engine_status.h
index 5c82069e8..589f8b98b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/engine_status.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/engine_status.h
@@ -95,14 +95,12 @@ enum nvgpu_engine_status_ctx_status {
 struct nvgpu_engine_status_info {
 	/** Engine status h/w register's read value. */
 	u32 reg_data;
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	/** @cond DOXYGEN_SHOULD_SKIP_THIS */
 	/* Ampere+ engine status additions */
 
 	/** Engine status_1 h/w register's read value. */
 	u32 reg1_data;
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
-#endif
 	/** Channel or tsg id that is currently assigned to the engine. */
 	u32 ctx_id;
 	/** Ctx_status field of engine_status h/w register. */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h
index 3b76c5472..b634da312 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/engines.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h
@@ -34,12 +34,10 @@ struct gk20a;
 struct nvgpu_device;
 
 /** @cond DOXYGEN_SHOULD_SKIP_THIS */
-#if defined(CONFIG_NVGPU_NON_FUSA)
 #define ENGINE_PBDMA_INSTANCE0 0U
 
 int nvgpu_engine_init_one_dev_extra(struct gk20a *g,
 		const struct nvgpu_device *dev);
-#endif
 /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 
 /**
diff --git a/drivers/gpu/nvgpu/include/nvgpu/errata.h b/drivers/gpu/nvgpu/include/nvgpu/errata.h
index e1c41bf9d..0401f0969 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/errata.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/errata.h
@@ -34,18 +34,7 @@ struct gk20a;
  */
 
 /** @cond DOXYGEN_SHOULD_SKIP_THIS */
-#if defined(CONFIG_NVGPU_NON_FUSA)
 #define ERRATA_FLAGS_NEXT						\
-	/* GA100 */							\
-	DEFINE_ERRATA(NVGPU_ERRATA_200601972, "GA100", "LTC TSTG"),	\
-	/* GA10B */							\
-	DEFINE_ERRATA(NVGPU_ERRATA_2969956, "GA10B", "FMODEL FB LTCS"),	\
-	DEFINE_ERRATA(NVGPU_ERRATA_200677649, "GA10B", "UCODE"),	\
-	DEFINE_ERRATA(NVGPU_ERRATA_3154076, "GA10B", "PROD VAL"),	\
-	DEFINE_ERRATA(NVGPU_ERRATA_3288192, "GA10B", "L4 SCF NOT SUPPORTED"),
-#else
-#define ERRATA_FLAGS_NEXT
-#endif
 /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 
 /*
@@ -69,6 +58,13 @@ struct gk20a;
 	DEFINE_ERRATA(NVGPU_ERRATA_INIT_PDB_CACHE, "TU104", "MM PDB"),	\
 	DEFINE_ERRATA(NVGPU_ERRATA_FB_PDB_CACHE, "TU104", "FB PDB"),	\
 	DEFINE_ERRATA(NVGPU_ERRATA_VBIOS_NVLINK_MASK, "TU104", "Nvlink VBIOS"),\
+	/* GA100 */							\
+	DEFINE_ERRATA(NVGPU_ERRATA_200601972, "GA100", "LTC TSTG"),     \
+	/* GA10B */							\
+	DEFINE_ERRATA(NVGPU_ERRATA_2969956, "GA10B", "FMODEL FB LTCS"),	\
+	DEFINE_ERRATA(NVGPU_ERRATA_200677649, "GA10B", "UCODE"),	\
+	DEFINE_ERRATA(NVGPU_ERRATA_3154076, "GA10B", "PROD VAL"),	\
+	DEFINE_ERRATA(NVGPU_ERRATA_3288192, "GA10B", "L4 SCF NOT SUPPORTED"), \
 	/* NvGPU Driver */						\
 	DEFINE_ERRATA(NVGPU_ERRATA_SYNCPT_INVALID_ID_0, "SW", "Syncpt ID"),\
 	DEFINE_ERRATA(NVGPU_MAX_ERRATA_BITS, "NA", "Marks max number of flags"),
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
index c0c9536fc..eddd585cd 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
@@ -178,7 +178,6 @@
 /**
  * Falcon/Falcon2 fuse settings bit
  */
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 #define FCD            (0U)
 #define FENEN          (1U)
 #define NVRISCV_BRE_EN (2U)
@@ -192,7 +191,6 @@
 #define SECURE_DBGD    (10U)
 #define AES_ALGO_DIS   (11U)
 #define PKC_ALGO_DIS   (12U)
-#endif
 
 struct gk20a;
 struct nvgpu_falcon;
@@ -275,20 +273,16 @@ struct nvgpu_falcon {
 	bool is_falcon2_enabled;
 	/** Indicates if the falcon interrupts are enabled. */
 	bool is_interrupt_enabled;
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	/** Fuse settings */
 	unsigned long fuse_settings;
-#endif
 	/** Lock to access the falcon's IMEM. */
 	struct nvgpu_mutex imem_lock;
 	/** Lock to access the falcon's DMEM. */
 	struct nvgpu_mutex dmem_lock;
-#ifdef CONFIG_NVGPU_DGPU
 	/** Indicates if the falcon supports EMEM. */
 	bool emem_supported;
 	/** Lock to access the falcon's EMEM. */
 	struct nvgpu_mutex emem_lock;
-#endif
 	/** Functions for engine specific reset and memory access. */
 	struct nvgpu_falcon_engine_dependency_ops flcn_engine_dep_ops;
 #ifdef CONFIG_NVGPU_FALCON_DEBUG
@@ -691,11 +685,31 @@ void nvgpu_falcon_sw_free(struct gk20a *g, u32 flcn_id);
 void nvgpu_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable,
 	u32 intr_mask, u32 intr_dest);
 
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
+/**
+ * @brief Get the size of falcon's memory.
+ *
+ * @param flcn [in] The falcon.
+ * @param type [in] Falcon memory type (IMEM, DMEM).
+ *		    - Supported types: MEM_DMEM (0), MEM_IMEM (1)
+ * @param size [out] Size of the falcon memory type.
+ *
+ * This function is called to get the size of falcon's memory for validation
+ * while copying to IMEM/DMEM.
+ *
+ * Steps:
+ * - Validate that the passed in falcon struct is not NULL and is for supported
+ *   falcon. If not valid, return -EINVAL.
+ * - Read the size of the falcon memory of \a type in bytes from the HW config
+ *   register in output parameter \a size.
+ *
+ * @return 0 in case of success, < 0 in case of failure.
+ */
+int nvgpu_falcon_get_mem_size(struct nvgpu_falcon *flcn,
+			      enum falcon_mem_type type, u32 *size);
+
 bool nvgpu_falcon_is_falcon2_enabled(struct nvgpu_falcon *flcn);
 bool nvgpu_falcon_is_feature_supported(struct nvgpu_falcon *flcn,
 		u32 feature);
-#endif
 
 #ifdef CONFIG_NVGPU_DGPU
 int nvgpu_falcon_copy_from_emem(struct nvgpu_falcon *flcn,
@@ -728,28 +742,6 @@ void nvgpu_falcon_dump_stats(struct nvgpu_falcon *flcn);
  */
 int nvgpu_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector);
 
-/**
- * @brief Get the size of falcon's memory.
- *
- * @param flcn [in] The falcon.
- * @param type [in] Falcon memory type (IMEM, DMEM).
- *		    - Supported types: MEM_DMEM (0), MEM_IMEM (1)
- * @param size [out] Size of the falcon memory type.
- *
- * This function is called to get the size of falcon's memory for validation
- * while copying to IMEM/DMEM.
- *
- * Steps:
- * - Validate that the passed in falcon struct is not NULL and is for supported
- *   falcon. If not valid, return -EINVAL.
- * - Read the size of the falcon memory of \a type in bytes from the HW config
- *   register in output parameter \a size.
- *
- * @return 0 in case of success, < 0 in case of failure.
- */
-int nvgpu_falcon_get_mem_size(struct nvgpu_falcon *flcn,
-			      enum falcon_mem_type type, u32 *size);
-
 int nvgpu_falcon_clear_halt_intr_status(struct nvgpu_falcon *flcn,
 		unsigned int timeout);
 int nvgpu_falcon_copy_from_dmem(struct nvgpu_falcon *flcn,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
index 9f6a338e3..f4d52a55b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/fuse.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
@@ -32,7 +32,6 @@ struct gk20a;
 #include <nvgpu/types.h>
 #include <nvgpu/errno.h>
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 struct nvgpu_fuse_feature_override_ecc {
 	/** overide_ecc register feature */
 	/** sm_lrf enable */
@@ -70,7 +69,6 @@ struct nvgpu_fuse_feature_override_ecc {
 	/** sm_l1_icache overide */
 	bool sm_l1_icache_override;
 };
-#endif
 
 #define GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK	BIT32(0)
 #define GCPLEX_CONFIG_VPR_ENABLED_MASK			BIT32(1)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h
index f7568ffc2..ed4e50e6b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h
@@ -141,16 +141,13 @@ struct gops_ce {
 	 */
 	void (*intr_enable)(struct gk20a *g, bool enable);
 
+	void (*intr_retrigger)(struct gk20a *g, u32 inst_id);
+
 #ifdef CONFIG_NVGPU_DGPU
 	int (*ce_app_init_support)(struct gk20a *g);
 	void (*ce_app_suspend)(struct gk20a *g);
 	void (*ce_app_destroy)(struct gk20a *g);
 #endif
-
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
-	void (*intr_retrigger)(struct gk20a *g, u32 inst_id);
-#endif
-
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/cg.h b/drivers/gpu/nvgpu/include/nvgpu/gops/cg.h
index dfc99d504..1b9d857ce 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/cg.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/cg.h
@@ -61,7 +61,6 @@ struct gops_cg {
 	void (*blcg_pmu_load_gating_prod)(struct gk20a *g, bool prod);
 	void (*blcg_xbar_load_gating_prod)(struct gk20a *g, bool prod);
 	void (*blcg_hshub_load_gating_prod)(struct gk20a *g, bool prod);
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	void (*slcg_runlist_load_gating_prod)(struct gk20a *g, bool prod);
 	void (*blcg_runlist_load_gating_prod)(struct gk20a *g, bool prod);
 
@@ -76,7 +75,6 @@ struct gops_cg {
 	void (*slcg_timer_load_gating_prod)(struct gk20a *g, bool prod);
 
 	void (*elcg_ce_load_gating_prod)(struct gk20a *g, bool prod);
-#endif
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/gops/falcon.h
index dba9cc4f5..1e9104c46 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/falcon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/falcon.h
@@ -53,9 +53,7 @@ struct gops_falcon {
 	void (*set_bcr)(struct nvgpu_falcon *flcn);
 	void (*dump_brom_stats)(struct nvgpu_falcon *flcn);
 	u32  (*get_brom_retcode)(struct nvgpu_falcon *flcn);
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	bool (*is_priv_lockdown)(struct nvgpu_falcon *flcn);
-#endif
 	u32 (*dmemc_blk_mask)(void);
 	bool (*check_brom_passed)(u32 retcode);
 	bool (*check_brom_failed)(u32 retcode);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/fb.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fb.h
index 1f738d878..1a24cb78c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/fb.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/fb.h
@@ -438,6 +438,9 @@ struct gops_fb {
 
 	struct nvgpu_hw_err_inject_info_desc * (*get_hubmmu_err_desc)
 							(struct gk20a *g);
+
+	u32 (*get_num_active_ltcs)(struct gk20a *g);
+
 #ifdef CONFIG_NVGPU_COMPRESSION
 	void (*cbc_configure)(struct gk20a *g, struct nvgpu_cbc *cbc);
 	/**
@@ -492,8 +495,6 @@ struct gops_fb {
 #endif
 
 #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
-	u32 (*get_num_active_ltcs)(struct gk20a *g);
-
 #ifdef CONFIG_NVGPU_MIG
 	int (*config_veid_smc_map)(struct gk20a *g, bool enable);
 	int (*set_smc_eng_config)(struct gk20a *g, bool enable);
@@ -530,8 +531,8 @@ struct gops_fb {
 	size_t (*get_vidmem_size)(struct gk20a *g);
 	int (*apply_pdb_cache_errata)(struct gk20a *g);
 	int (*init_fbpa)(struct gk20a *g);
-	void (*handle_fbpa_intr)(struct gk20a *g, u32 fbpa_id);
 #endif
+	void (*handle_fbpa_intr)(struct gk20a *g, u32 fbpa_id);
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h
index acbf1705c..60187f42c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h
@@ -237,6 +237,7 @@ struct gops_fifo {
 	void (*bar1_snooping_disable)(struct gk20a *g);
 	bool (*find_pbdma_for_runlist)(struct gk20a *g,
 				       u32 runlist_id, u32 *pbdma_id);
+	void (*runlist_intr_retrigger)(struct gk20a *g, u32 intr_tree);
 
 #ifdef CONFIG_NVGPU_RECOVERY
 	void (*recover)(struct gk20a *g, u32 act_eng_bitmask,
@@ -248,11 +249,6 @@ struct gops_fifo {
 	int (*set_sm_exception_type_mask)(struct nvgpu_channel *ch,
 			u32 exception_mask);
 #endif
-
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
-	void (*runlist_intr_retrigger)(struct gk20a *g, u32 intr_tree);
-#endif
-
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 
 };
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h
index c884e681b..4adb5e6cc 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h
@@ -32,9 +32,7 @@
  */
 struct gk20a;
 
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 struct nvgpu_fuse_feature_override_ecc;
-#endif
 
 /**
  * Fuse HAL operations.
@@ -241,18 +239,16 @@ struct gops_fuse {
 	int (*read_ucode_version)(struct gk20a *g, u32 falcon_id,
 			u32 *ucode_version);
 
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	int (*fetch_falcon_fuse_settings)(struct gk20a *g, u32 falcon_id,
 			unsigned long *fuse_settings);
-#endif
-
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
-	void (*write_feature_override_ecc)(struct gk20a *g, u32 val);
-	void (*write_feature_override_ecc_1)(struct gk20a *g, u32 val);
 	void (*read_feature_override_ecc)(struct gk20a *g,
 			struct nvgpu_fuse_feature_override_ecc *ecc_feature);
 	u32 (*fuse_opt_sm_ttu_en)(struct gk20a *g);
 	u32 (*opt_sec_source_isolation_en)(struct gk20a *g);
+
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
+	void (*write_feature_override_ecc)(struct gk20a *g, u32 val);
+	void (*write_feature_override_ecc_1)(struct gk20a *g, u32 val);
 #endif
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
index 401f722a8..328067055 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
@@ -498,10 +498,8 @@ struct gops_gr_intr {
 				     struct nvgpu_channel *fault_ch);
 
 	/** @cond DOXYGEN_SHOULD_SKIP_THIS */
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	int (*retrigger)(struct gk20a *g);
 	u32 (*enable_mask)(struct gk20a *g);
-#endif
 	int (*handle_fecs_error)(struct gk20a *g,
 				 struct nvgpu_channel *ch,
 				 struct nvgpu_gr_isr_data *isr_data);
@@ -836,10 +834,8 @@ struct gops_gr_init {
 				   u64 addr, u32 size, bool patch);
 	u32 (*get_patch_slots)(struct gk20a *g,
 			       struct nvgpu_gr_config *config);
-#ifdef CONFIG_NVGPU_DGPU
 	int (*load_sw_bundle64)(struct gk20a *g,
 			struct netlist_av64_list *sw_bundle64_init);
-#endif
 #ifdef CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION
 	void (*restore_stats_counter_bundle_data)(struct gk20a *g,
 			struct netlist_av_list *sw_bundle_init);
@@ -899,13 +895,11 @@ struct gops_gr_init {
 	bool (*is_allowed_sw_bundle)(struct gk20a *g,
 			u32 bundle_addr, u32 bundle_value, int *context);
 	bool (*is_allowed_reg)(struct gk20a *g, u32 addr);
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	void (*auto_go_idle)(struct gk20a *g, bool enable);
 	void (*eng_config)(struct gk20a *g);
 	int (*reset_gpcs)(struct gk20a *g);
 	int (*sm_id_config_early)(struct gk20a *g,
 			struct nvgpu_gr_config *config);
-#endif
 	/** @endcond */
 };
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
index 431703d59..c75650b36 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
@@ -52,10 +52,8 @@ struct gops_ltc_intr {
 	/** @cond DOXYGEN_SHOULD_SKIP_THIS */
 	void (*configure)(struct gk20a *g);
 	void (*en_illegal_compstat)(struct gk20a *g, bool enable);
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	void (*isr_extra)(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value);
 	void (*ltc_intr3_configure_extra)(struct gk20a *g, u32 *reg);
-#endif
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };
 
@@ -163,9 +161,7 @@ struct gops_ltc {
 	u32 (*pri_is_lts_tstg_addr)(struct gk20a *g, u32 addr);
 	int (*set_l2_sector_promotion)(struct gk20a *g, struct nvgpu_tsg *tsg,
 			u32 policy);
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	u32 (*pri_shared_addr)(struct gk20a *g, u32 addr);
-#endif
 #endif
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h
index 11a7cfffb..ecbe9d58a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h
@@ -212,9 +212,7 @@ struct gops_mc {
 
 	void (*intr_mask)(struct gk20a *g);
 
-#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	void (*intr_enable)(struct gk20a *g);
-#endif
 
 	void (*intr_stall_unit_config)(struct gk20a *g, u32 unit,
 				bool enable);
@@ -237,6 +235,8 @@ struct gops_mc {
 
 	int (*enable_devtype)(struct gk20a *g, u32 devtype, bool enable);
 
+	void (*fbpa_isr)(struct gk20a *g);
+
 #ifdef CONFIG_NVGPU_LS_PMU
 	bool (*is_enabled)(struct gk20a *g, u32 unit);
 #endif
@@ -255,10 +255,8 @@ struct gops_mc {
 
 #ifdef CONFIG_NVGPU_DGPU
 	bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr);
-	void (*fbpa_isr)(struct gk20a *g);
 #endif
 
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	/**
 	 * @brief Reset HW engines.
 	 *
@@ -289,7 +287,6 @@ struct gops_mc {
 	int (*reset_engines_all)(struct gk20a *g, u32 devtype);
 	void (*elpg_enable)(struct gk20a *g);
 	bool (*intr_get_unit_info)(struct gk20a *g, u32 unit);
-#endif
 
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h
index 0ca368be3..d903afc5c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h
@@ -82,6 +82,10 @@ struct gops_pbdma {
 	u32 (*allowed_syncpoints_0_index_f)(u32 syncpt);
 	u32 (*allowed_syncpoints_0_valid_f)(void);
 	u32 (*allowed_syncpoints_0_index_v)(u32 offset);
+	u32 (*set_channel_info_chid)(u32 chid);
+	u32 (*set_intr_notify)(u32 eng_intr_vector);
+	u32 (*get_mmu_fault_id)(struct gk20a *g, u32 pbdma_id);
+	u32 (*get_num_of_pbdmas)(void);
 
 	/** NON FUSA */
 	void (*syncpt_debug_dump)(struct gk20a *g,
@@ -90,11 +94,7 @@ struct gops_pbdma {
 	void (*dump_status)(struct gk20a *g,
 			struct nvgpu_debug_context *o);
 #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
-	u32 (*set_channel_info_chid)(u32 chid);
-	u32 (*set_intr_notify)(u32 eng_intr_vector);
-	u32 (*get_mmu_fault_id)(struct gk20a *g, u32 pbdma_id);
 	void (*pbdma_force_ce_split)(struct gk20a *g);
-	u32 (*get_num_of_pbdmas)(void);
 #endif
 };
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h b/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h
index 9a8309720..9ad4e9b86 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h
@@ -101,7 +101,6 @@ struct gops_runlist {
 			bool wait_preempt);
 	void (*init_enginfo)(struct gk20a *g, struct nvgpu_fifo *f);
 	u32 (*get_tsg_max_timeslice)(void);
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	u32 (*get_runlist_id)(struct gk20a *g, u32 runlist_pri_base);
 	u32 (*get_engine_id_from_rleng_id)(struct gk20a *g,
 				u32 rleng_id, u32 runlist_pri_base);
@@ -111,7 +110,6 @@ struct gops_runlist {
 	u32 (*get_engine_intr_id)(struct gk20a *g, u32 runlist_pri_base,
 			u32 rleng_id);
 	u32 (*get_esched_fb_thread_id)(struct gk20a *g, u32 runlist_pri_base);
-#endif
 
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h b/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h
index 591af661f..98aaa5916 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h
@@ -52,9 +52,7 @@ struct nvgpu_gr_config;
  */
 int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config);
 /** @cond DOXYGEN_SHOULD_SKIP_THIS */
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config);
-#endif
 /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 
 #endif /* NVGPU_GR_FS_STATE_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
index a24c499be..1333db43c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
@@ -353,10 +353,8 @@ int nvgpu_gr_reset(struct gk20a *g);
 #endif
 
 /** @cond DOXYGEN_SHOULD_SKIP_THIS */
-#if defined(CONFIG_NVGPU_NON_FUSA)
 void nvgpu_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g);
 void nvgpu_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g);
-#endif
 /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 
 #endif /* NVGPU_GR_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mc.h b/drivers/gpu/nvgpu/include/nvgpu/mc.h
index 5bde51341..e7a723555 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/mc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/mc.h
@@ -157,7 +157,6 @@ struct nvgpu_device;
 /** Bit offset of the Architecture field in the HW version register */
 #define NVGPU_GPU_ARCHITECTURE_SHIFT 4U
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 struct nvgpu_intr_unit_info {
 	/**
 	 * top bit 0 -> subtree 0 -> leaf0, leaf1 -> leaf 0, 1
@@ -181,7 +180,6 @@ struct nvgpu_intr_unit_info {
 	 */
 	bool valid;
 };
-#endif
 
 /**
  * This struct holds the variables needed to manage the configuration and
@@ -204,7 +202,6 @@ struct nvgpu_mc {
 
 	/** @cond DOXYGEN_SHOULD_SKIP_THIS */
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	/**
 	 * intr info array indexed by s/w defined intr unit name
 	 */
@@ -214,7 +211,6 @@ struct nvgpu_mc {
 	 * Each subtree corresponds to a bit in intr_top register.
 	 */
 	u64 subtree_mask_restore[HOST2SOC_NUM_SUBTREE];
-#endif
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/netlist.h b/drivers/gpu/nvgpu/include/nvgpu/netlist.h
index 8b7792df0..621b75c85 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/netlist.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/netlist.h
@@ -348,6 +348,18 @@ u32 *nvgpu_netlist_get_gpccs_inst_list(struct gk20a *g);
  */
 u32 *nvgpu_netlist_get_gpccs_data_list(struct gk20a *g);
 
+struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_compute_load_av_list(
+							struct gk20a *g);
+struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_compute_load_av_list(
+							struct gk20a *g);
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_gfx_load_av_list(
+							struct gk20a *g);
+struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_gfx_load_av_list(
+							struct gk20a *g);
+#endif /* CONFIG_NVGPU_GRAPHICS */
+
 #ifdef CONFIG_NVGPU_DEBUGGER
 struct netlist_aiv_list *nvgpu_netlist_get_sys_ctxsw_regs(struct gk20a *g);
 struct netlist_aiv_list *nvgpu_netlist_get_gpc_ctxsw_regs(struct gk20a *g);
@@ -408,18 +420,6 @@ void nvgpu_netlist_vars_set_dynamic(struct gk20a *g, bool set);
 void nvgpu_netlist_vars_set_buffer_size(struct gk20a *g, u32 size);
 void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index);
 
-
-struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_compute_load_av_list(
-							struct gk20a *g);
-struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_compute_load_av_list(
-							struct gk20a *g);
-#ifdef CONFIG_NVGPU_GRAPHICS
-struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_gfx_load_av_list(
-							struct gk20a *g);
-struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_gfx_load_av_list(
-							struct gk20a *g);
-#endif /* CONFIG_NVGPU_GRAPHICS */
-
 #ifdef CONFIG_NVGPU_DEBUGGER
 struct netlist_aiv_list *nvgpu_netlist_get_sys_compute_ctxsw_regs(
 							struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h
index c6e38dc2c..0ab22c64c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h
@@ -101,10 +101,8 @@ struct mmu_fault_info;
 #define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED	(17U)
 #define GPU_SM_MACHINE_CHECK_ERROR			(18U)
 #define GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED	(20U)
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 #define GPU_SM_RAMS_ECC_CORRECTED			(21U)
 #define GPU_SM_RAMS_ECC_UNCORRECTED			(22U)
-#endif
 
 /**
  * @}
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/pbdma.h
index 25a3ec97c..090191b24 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pbdma.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pbdma.h
@@ -37,7 +37,6 @@
 struct gk20a;
 
 /** @cond DOXYGEN_SHOULD_SKIP_THIS */
-#if defined(CONFIG_NVGPU_NON_FUSA)
 #define PBDMA_PER_RUNLIST_SIZE		2U
 #define NVGPU_INVALID_PBDMA_PRI_BASE	U32_MAX
 #define NVGPU_INVALID_PBDMA_ID		U32_MAX
@@ -48,7 +47,6 @@ struct nvgpu_pbdma_info {
 	/** The ID of the i'th PBDMA that runs channels on this runlist */
 	u32 pbdma_id[PBDMA_PER_RUNLIST_SIZE];
 };
-#endif
 /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 
 /**
diff --git a/drivers/gpu/nvgpu/include/nvgpu/runlist.h b/drivers/gpu/nvgpu/include/nvgpu/runlist.h
index d8a274f60..0015e3ce5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/runlist.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/runlist.h
@@ -40,11 +40,9 @@ struct nvgpu_channel;
 struct nvgpu_device;
 
 /** @cond DOXYGEN_SHOULD_SKIP_THIS */
-#if defined(CONFIG_NVGPU_NON_FUSA)
 struct nvgpu_pbdma_info;
 
 #define RLENG_PER_RUNLIST_SIZE			3
-#endif
 
 /**
  * Low interleave level for runlist entry. TSGs with this interleave level
@@ -168,7 +166,6 @@ struct nvgpu_runlist {
 	struct nvgpu_mutex runlist_lock;
 
 	/** @cond DOXYGEN_SHOULD_SKIP_THIS */
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	/* Ampere+ runlist info additions */
 
 	/** Runlist pri base - offset into device's runlist space */
@@ -179,7 +176,6 @@ struct nvgpu_runlist {
 	const struct nvgpu_pbdma_info *pbdma_info;
 	/** Pointer to engine info for per runlist engine id */
 	const struct nvgpu_device *rl_dev_list[RLENG_PER_RUNLIST_SIZE];
-#endif
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };