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gpu: nvgpu: Add support to pass platform data to ACR
This patch passes an extra byte(23:16) value to 'mode' variable of ACR interface, value depends on func 'nvgpu_platform_is_simulation'. This will let ACR ucode to identify whether a platform is simulation(VDK) or not(VSP & Silicon). Change-Id: I78efe9cd748c023dd17e80f498c3b8b34edd18e5 Signed-off-by: mpoojary <mpoojary@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2673063 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
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@@ -26,6 +26,7 @@
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#include <nvgpu/dma.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/pmu.h>
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#include <nvgpu/pmu.h>
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#include <nvgpu/grmgr.h>
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#include <nvgpu/grmgr.h>
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#include <nvgpu/soc.h>
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#ifdef CONFIG_NVGPU_LS_PMU
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#ifdef CONFIG_NVGPU_LS_PMU
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#include <nvgpu/pmu/fw.h>
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#include <nvgpu/pmu/fw.h>
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#endif
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#endif
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@@ -167,6 +168,12 @@ static int ga10b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
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} else {
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} else {
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acr_sysmem_desc->gpu_mode &= (u32)(~MIG_MODE);
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acr_sysmem_desc->gpu_mode &= (u32)(~MIG_MODE);
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}
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}
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if (nvgpu_platform_is_simulation(g)) {
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acr_sysmem_desc->gpu_mode |= ACR_SIMULATION_MODE;
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} else {
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acr_sysmem_desc->gpu_mode &= (u32)(~ACR_SIMULATION_MODE);
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}
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}
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}
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load:
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load:
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -746,6 +746,9 @@ struct flcn_acr_desc {
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/* MIG mode selection*/
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/* MIG mode selection*/
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#define MIG_MODE BIT(8U)
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#define MIG_MODE BIT(8U)
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/* Let ACR know when in simulation*/
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#define ACR_SIMULATION_MODE BIT(16U)
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struct flcn2_acr_desc {
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struct flcn2_acr_desc {
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/**
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/**
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* WPR Region ID holding the WPR header and its details
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* WPR Region ID holding the WPR header and its details
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@@ -781,8 +784,9 @@ struct flcn2_acr_desc {
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/**
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/**
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* stores flag value to enable:
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* stores flag value to enable:
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* emulate_mode 7:0 bit
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* emulate_mode 7:0 bit
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* MIG mode 15:8 bit
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* MIG mode 15:8 bit
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* Simulation mode 23:16 bit
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*/
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*/
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u32 gpu_mode;
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u32 gpu_mode;
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};
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};
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