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gpu: nvgpu: Add support to pass platform data to ACR

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This patch passes an extra byte(23:16) value to 'mode' variable of ACR interface,
value depends on func 'nvgpu_platform_is_simulation'.
This will let ACR ucode to identify whether a platform is simulation(VDK)
or not(VSP & Silicon).

Change-Id: I78efe9cd748c023dd17e80f498c3b8b34edd18e5
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2673063
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
mpoojary
2022-02-21 08:37:26 +00:00
committed by mobile promotions
parent 5ec241a1d8
commit 3da5e1515f
2 changed files with 14 additions and 3 deletions
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7
drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c
View File

@@ -26,6 +26,7 @@
#include <nvgpu/dma.h>
#include <nvgpu/pmu.h>
#include <nvgpu/grmgr.h>
#include <nvgpu/soc.h>
#ifdef CONFIG_NVGPU_LS_PMU
#include <nvgpu/pmu/fw.h>
#endif
@@ -167,6 +168,12 @@ static int ga10b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
} else {
acr_sysmem_desc->gpu_mode &= (u32)(~MIG_MODE);
}
if (nvgpu_platform_is_simulation(g)) {
acr_sysmem_desc->gpu_mode |= ACR_SIMULATION_MODE;
} else {
acr_sysmem_desc->gpu_mode &= (u32)(~ACR_SIMULATION_MODE);
}
}
load:

10
drivers/gpu/nvgpu/common/acr/nvgpu_acr_interface.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -746,6 +746,9 @@ struct flcn_acr_desc {
/* MIG mode selection*/
#define MIG_MODE BIT(8U)
/* Let ACR know when in simulation*/
#define ACR_SIMULATION_MODE BIT(16U)
struct flcn2_acr_desc {
/**
* WPR Region ID holding the WPR header and its details
@@ -781,8 +784,9 @@ struct flcn2_acr_desc {
/**
* stores flag value to enable:
* emulate_mode 7:0 bit
* MIG mode 15:8 bit
* emulate_mode 7:0 bit
* MIG mode 15:8 bit
* Simulation mode 23:16 bit
*/
u32 gpu_mode;
};