From 3e2eff564fad5b1960278ad9f36e65f06a0b3e0e Mon Sep 17 00:00:00 2001 From: Rajesh Devaraj Date: Thu, 5 Jan 2023 12:37:05 +0000 Subject: [PATCH] gpu: nvgpu: update pbdma intr enable set/clear masks as hals To reduce the entire duplication of pbdma_intr_enable for future chips, make set and clear masks as HALs. JIRA NVGPU-9325 Change-Id: Id8434fc15ca4bf542680a8452dc294f2c4068084 Signed-off-by: Rajesh Devaraj Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2838036 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Ramalingam C Reviewed-by: Ankur Kishore GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h | 6 +++++- drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c | 18 +++++++++--------- drivers/gpu/nvgpu/hal/init/hal_ga100.c | 6 +++++- drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 4 ++++ drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h | 6 +++++- 5 files changed, 28 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h index fa240c2c1..b0a098208 100644 --- a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h +++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -69,4 +69,8 @@ void ga10b_pbdma_dump_status(struct gk20a *g, struct nvgpu_debug_context *o); u32 ga10b_pbdma_get_mmu_fault_id(struct gk20a *g, u32 pbdma_id); u32 ga10b_pbdma_get_num_of_pbdmas(void); +u32 ga10b_pbdma_intr_0_en_set_tree_mask(void); +u32 ga10b_pbdma_intr_0_en_clear_tree_mask(void); +u32 ga10b_pbdma_intr_1_en_set_tree_mask(void); +u32 ga10b_pbdma_intr_1_en_clear_tree_mask(void); #endif /* NVGPU_PBDMA_GA10B_H */ diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c index e7cf37c2f..e2f52dbbf 100644 --- a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -40,7 +40,7 @@ #include -static u32 pbdma_intr_0_en_set_tree_mask(void) +u32 ga10b_pbdma_intr_0_en_set_tree_mask(void) { u32 mask = pbdma_intr_0_en_set_tree_gpfifo_enabled_f() | pbdma_intr_0_en_set_tree_gpptr_enabled_f() | @@ -61,7 +61,7 @@ static u32 pbdma_intr_0_en_set_tree_mask(void) return mask; } -static u32 pbdma_intr_0_en_clear_tree_mask(void) +u32 ga10b_pbdma_intr_0_en_clear_tree_mask(void) { u32 mask = pbdma_intr_0_en_clear_tree_gpfifo_enabled_f() | pbdma_intr_0_en_clear_tree_gpptr_enabled_f() | @@ -82,7 +82,7 @@ static u32 pbdma_intr_0_en_clear_tree_mask(void) return mask; } -static u32 pbdma_intr_1_en_set_tree_mask(void) +u32 ga10b_pbdma_intr_1_en_set_tree_mask(void) { u32 mask = pbdma_intr_1_en_set_tree_hce_re_illegal_op_enabled_f() | pbdma_intr_1_en_set_tree_hce_re_alignb_enabled_f() | pbdma_intr_1_en_set_tree_hce_priv_enabled_f() | @@ -93,7 +93,7 @@ static u32 pbdma_intr_1_en_set_tree_mask(void) return mask; } -static u32 pbdma_intr_1_en_clear_tree_mask(void) +u32 ga10b_pbdma_intr_1_en_clear_tree_mask(void) { u32 mask = pbdma_intr_1_en_clear_tree_hce_re_illegal_op_enabled_f() | pbdma_intr_1_en_clear_tree_hce_re_alignb_enabled_f() | @@ -204,9 +204,9 @@ static void ga10b_pbdma_disable_all_intr(struct gk20a *g) for (tree = 0U; tree < pbdma_intr_0_en_clear_tree__size_2_v(); tree++) { nvgpu_writel(g, pbdma_intr_0_en_clear_tree_r(pbdma_id, - tree), pbdma_intr_0_en_clear_tree_mask()); + tree), g->ops.pbdma.intr_0_en_clear_tree_mask()); nvgpu_writel(g, pbdma_intr_1_en_clear_tree_r(pbdma_id, - tree), pbdma_intr_1_en_clear_tree_mask()); + tree), g->ops.pbdma.intr_1_en_clear_tree_mask()); } } } @@ -352,9 +352,9 @@ void ga10b_pbdma_intr_enable(struct gk20a *g, bool enable) /* enable pbdma interrupts and route to tree_0 */ nvgpu_writel(g, pbdma_intr_0_en_set_tree_r(pbdma_id, - tree), pbdma_intr_0_en_set_tree_mask()); + tree), g->ops.pbdma.intr_0_en_set_tree_mask()); nvgpu_writel(g, pbdma_intr_1_en_set_tree_r(pbdma_id, - tree), pbdma_intr_1_en_set_tree_mask()); + tree), g->ops.pbdma.intr_1_en_set_tree_mask()); } } diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index e68c4bc33..121418cc9 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -1,7 +1,7 @@ /* * GA100 Tegra HAL interface * - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1043,6 +1043,10 @@ static const struct gops_pbdma ga100_ops_pbdma = { .cleanup_sw = nvgpu_pbdma_cleanup_sw, .setup_hw = NULL, .intr_enable = ga10b_pbdma_intr_enable, + .intr_0_en_set_tree_mask = ga10b_pbdma_intr_0_en_set_tree_mask, + .intr_0_en_clear_tree_mask = ga10b_pbdma_intr_0_en_clear_tree_mask, + .intr_1_en_set_tree_mask = ga10b_pbdma_intr_1_en_set_tree_mask, + .intr_1_en_clear_tree_mask = ga10b_pbdma_intr_1_en_clear_tree_mask, .acquire_val = gm20b_pbdma_acquire_val, .get_signature = gp10b_pbdma_get_signature, #ifdef CONFIG_NVGPU_HAL_NON_FUSA diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 84e8b291a..689230f40 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1061,6 +1061,10 @@ static const struct gops_pbdma ga10b_ops_pbdma = { .cleanup_sw = nvgpu_pbdma_cleanup_sw, .setup_hw = NULL, .intr_enable = ga10b_pbdma_intr_enable, + .intr_0_en_set_tree_mask = ga10b_pbdma_intr_0_en_set_tree_mask, + .intr_0_en_clear_tree_mask = ga10b_pbdma_intr_0_en_clear_tree_mask, + .intr_1_en_set_tree_mask = ga10b_pbdma_intr_1_en_set_tree_mask, + .intr_1_en_clear_tree_mask = ga10b_pbdma_intr_1_en_clear_tree_mask, .acquire_val = gm20b_pbdma_acquire_val, .get_signature = gp10b_pbdma_get_signature, #ifdef CONFIG_NVGPU_HAL_NON_FUSA diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h index 722d4b508..eddda70d3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -45,6 +45,10 @@ struct gops_pbdma { void (*cleanup_sw)(struct gk20a *g); void (*setup_hw)(struct gk20a *g); void (*intr_enable)(struct gk20a *g, bool enable); + u32 (*intr_0_en_set_tree_mask)(void); + u32 (*intr_0_en_clear_tree_mask)(void); + u32 (*intr_1_en_set_tree_mask)(void); + u32 (*intr_1_en_clear_tree_mask)(void); bool (*handle_intr_0)(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0, u32 *error_notifier);