diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index d5b261a4e..f175c6a03 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -235,6 +235,7 @@ nvgpu-y += \ hal/fifo/ramfc_gv11b.o \ hal/fifo/ramfc_tu104.o \ hal/fifo/ramin_gk20a.o \ + hal/fifo/ramin_gm20b.o \ hal/fifo/ramin_gv11b.o \ hal/fifo/tsg_gk20a.o \ hal/fifo/tsg_gv11b.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 7e9e00dda..627e04117 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -367,6 +367,7 @@ srcs += common/sim.c \ hal/fifo/ramfc_gv11b.c \ hal/fifo/ramfc_tu104.c \ hal/fifo/ramin_gk20a.c \ + hal/fifo/ramin_gm20b.c \ hal/fifo/ramin_gv11b.c \ hal/fifo/tsg_gk20a.c \ hal/fifo/tsg_gv11b.c \ diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index fb247b3a2..481b27844 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -25,6 +25,7 @@ #include "hal/fifo/engines_gm20b.h" #include "hal/fifo/pbdma_gm20b.h" #include "hal/fifo/pbdma_gp10b.h" +#include "hal/fifo/ramin_gm20b.h" #include "hal/fifo/userd_gk20a.h" #include "hal/therm/therm_gm20b.h" #include "hal/therm/therm_gp10b.h" @@ -502,6 +503,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { }, .ramin = { .set_gr_ptr = NULL, + .set_big_page_size = gm20b_ramin_set_big_page_size, }, .runlist = { .reschedule = NULL, @@ -551,7 +553,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .l2_invalidate = vgpu_mm_l2_invalidate, .l2_flush = vgpu_mm_l2_flush, .cbc_clean = NULL, - .set_big_page_size = gm20b_mm_set_big_page_size, .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gp10b_mm_get_default_big_page_size, .gpu_phys_addr = gm20b_gpu_phys_addr, diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index 8bb32b991..d4665b027 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -26,6 +26,7 @@ #include "hal/fifo/pbdma_gm20b.h" #include "hal/fifo/pbdma_gp10b.h" #include "hal/fifo/pbdma_gv11b.h" +#include "hal/fifo/ramin_gm20b.h" #include "hal/fifo/tsg_gv11b.h" #include "hal/fifo/userd_gk20a.h" #include "hal/fifo/userd_gv11b.h" @@ -591,6 +592,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { }, .ramin = { .set_gr_ptr = NULL, + .set_big_page_size = gm20b_ramin_set_big_page_size, }, .runlist = { .reschedule = NULL, @@ -640,7 +642,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .l2_invalidate = vgpu_mm_l2_invalidate, .l2_flush = vgpu_mm_l2_flush, .cbc_clean = NULL, - .set_big_page_size = gm20b_mm_set_big_page_size, .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gp10b_mm_get_default_big_page_size, .gpu_phys_addr = gm20b_gpu_phys_addr, diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 440053826..879fd545c 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c @@ -410,8 +410,8 @@ void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_hi_w(), ram_in_adr_limit_hi_f(u64_hi32(vm->va_limit - 1U))); - if ((big_page_size != 0U) && (g->ops.mm.set_big_page_size != NULL)) { - g->ops.mm.set_big_page_size(g, inst_block, big_page_size); + if ((big_page_size != 0U) && (g->ops.ramin.set_big_page_size != NULL)) { + g->ops.ramin.set_big_page_size(g, inst_block, big_page_size); } } diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 18ad160af..1426c91de 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -59,6 +59,7 @@ #include "hal/fifo/pbdma_status_gm20b.h" #include "hal/fifo/ramfc_gk20a.h" #include "hal/fifo/ramin_gk20a.h" +#include "hal/fifo/ramin_gm20b.h" #include "hal/fifo/tsg_gk20a.h" #include "hal/fifo/userd_gk20a.h" #include "hal/fifo/fifo_intr_gk20a.h" @@ -697,6 +698,7 @@ static const struct gpu_ops gm20b_ops = { }, .ramin = { .set_gr_ptr = gk20a_ramin_set_gr_ptr, + .set_big_page_size = gm20b_ramin_set_big_page_size, }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, @@ -748,7 +750,6 @@ static const struct gpu_ops gm20b_ops = { .l2_invalidate = gk20a_mm_l2_invalidate, .l2_flush = gk20a_mm_l2_flush, .cbc_clean = gk20a_mm_cbc_clean, - .set_big_page_size = gm20b_mm_set_big_page_size, .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gm20b_mm_get_default_big_page_size, .gpu_phys_addr = gm20b_gpu_phys_addr, diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c index 41ded94e2..5e68f1df6 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c @@ -28,28 +28,6 @@ #include "mm_gm20b.h" #include -#include - -void gm20b_mm_set_big_page_size(struct gk20a *g, - struct nvgpu_mem *mem, u32 size) -{ - u32 val; - - nvgpu_log_fn(g, " "); - - nvgpu_log_info(g, "big page size %u\n", size); - val = nvgpu_mem_rd32(g, mem, ram_in_big_page_size_w()); - val &= ~ram_in_big_page_size_m(); - - if (size == SZ_64K) { - val |= ram_in_big_page_size_64kb_f(); - } else { - val |= ram_in_big_page_size_128kb_f(); - } - - nvgpu_mem_wr32(g, mem, ram_in_big_page_size_w(), val); - nvgpu_log_fn(g, "done"); -} u32 gm20b_mm_get_big_page_sizes(void) { diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h index bb7783a0f..84ea8c0ec 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,8 +27,6 @@ struct gk20a; #define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1)) #define PDE_ADDR_END(x, y) ((x) | ((0x1UL << (y)) - 1)) -void gm20b_mm_set_big_page_size(struct gk20a *g, - struct nvgpu_mem *mem, u32 size); u32 gm20b_mm_get_big_page_sizes(void); u32 gm20b_mm_get_default_big_page_size(void); bool gm20b_mm_support_sparse(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 1a52c3235..8ff1966d8 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -70,6 +70,7 @@ #include "hal/fifo/ramfc_gk20a.h" #include "hal/fifo/ramfc_gp10b.h" #include "hal/fifo/ramin_gk20a.h" +#include "hal/fifo/ramin_gm20b.h" #include "hal/fifo/tsg_gk20a.h" #include "hal/fifo/userd_gk20a.h" #include "hal/fifo/fifo_intr_gk20a.h" @@ -784,6 +785,7 @@ static const struct gpu_ops gp10b_ops = { }, .ramin = { .set_gr_ptr = gk20a_ramin_set_gr_ptr, + .set_big_page_size = gm20b_ramin_set_big_page_size, }, .runlist = { .reschedule = gk20a_runlist_reschedule, @@ -838,7 +840,6 @@ static const struct gpu_ops gp10b_ops = { .l2_invalidate = gk20a_mm_l2_invalidate, .l2_flush = gk20a_mm_l2_flush, .cbc_clean = gk20a_mm_cbc_clean, - .set_big_page_size = gm20b_mm_set_big_page_size, .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gp10b_mm_get_default_big_page_size, .gpu_phys_addr = gm20b_gpu_phys_addr, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index a45cec0a1..cee41dbe1 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -58,6 +58,7 @@ #include "hal/fifo/pbdma_status_gm20b.h" #include "hal/fifo/ramfc_gp10b.h" #include "hal/fifo/ramfc_gv11b.h" +#include "hal/fifo/ramin_gm20b.h" #include "hal/fifo/ramin_gv11b.h" #include "hal/fifo/tsg_gv11b.h" #include "hal/fifo/userd_gk20a.h" @@ -969,6 +970,7 @@ static const struct gpu_ops gv100_ops = { }, .ramin = { .set_gr_ptr = gv11b_ramin_set_gr_ptr, + .set_big_page_size = gm20b_ramin_set_big_page_size, }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, @@ -1021,7 +1023,6 @@ static const struct gpu_ops gv100_ops = { .l2_invalidate = gk20a_mm_l2_invalidate, .l2_flush = gv11b_mm_l2_flush, .cbc_clean = gk20a_mm_cbc_clean, - .set_big_page_size = gm20b_mm_set_big_page_size, .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gp10b_mm_get_default_big_page_size, .gpu_phys_addr = gv11b_gpu_phys_addr, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 6ad9f5f76..171ac31a8 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -59,6 +59,7 @@ #include "hal/fifo/engines_gv11b.h" #include "hal/fifo/ramfc_gp10b.h" #include "hal/fifo/ramfc_gv11b.h" +#include "hal/fifo/ramin_gm20b.h" #include "hal/fifo/ramin_gv11b.h" #include "hal/fifo/tsg_gv11b.h" #include "hal/fifo/userd_gk20a.h" @@ -924,6 +925,7 @@ static const struct gpu_ops gv11b_ops = { }, .ramin = { .set_gr_ptr = gv11b_ramin_set_gr_ptr, + .set_big_page_size = gm20b_ramin_set_big_page_size, }, .runlist = { .reschedule = gv11b_runlist_reschedule, @@ -978,7 +980,6 @@ static const struct gpu_ops gv11b_ops = { .l2_invalidate = gk20a_mm_l2_invalidate, .l2_flush = gv11b_mm_l2_flush, .cbc_clean = gk20a_mm_cbc_clean, - .set_big_page_size = gm20b_mm_set_big_page_size, .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gp10b_mm_get_default_big_page_size, .gpu_phys_addr = gv11b_gpu_phys_addr, diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 363c78451..395f2ed91 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -55,8 +55,8 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block, g->ops.mm.init_pdb(g, inst_block, vm); - if ((big_page_size != 0U) && (g->ops.mm.set_big_page_size != NULL)) { - g->ops.mm.set_big_page_size(g, inst_block, big_page_size); + if ((big_page_size != 0U) && (g->ops.ramin.set_big_page_size != NULL)) { + g->ops.ramin.set_big_page_size(g, inst_block, big_page_size); } gv11b_init_subcontext_pdb(vm, inst_block, false); diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_gm20b.c b/drivers/gpu/nvgpu/hal/fifo/ramin_gm20b.c new file mode 100644 index 000000000..9e7254f4f --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_gm20b.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "hal/fifo/ramin_gm20b.h" + +#include + +void gm20b_ramin_set_big_page_size(struct gk20a *g, + struct nvgpu_mem *mem, u32 size) +{ + u32 val; + + nvgpu_log_fn(g, " "); + + nvgpu_log_info(g, "big page size %u", size); + val = nvgpu_mem_rd32(g, mem, ram_in_big_page_size_w()); + val &= ~ram_in_big_page_size_m(); + + if (size == SZ_64K) { + val |= ram_in_big_page_size_64kb_f(); + } else { + val |= ram_in_big_page_size_128kb_f(); + } + + nvgpu_mem_wr32(g, mem, ram_in_big_page_size_w(), val); + nvgpu_log_fn(g, "done"); +} diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_gm20b.h b/drivers/gpu/nvgpu/hal/fifo/ramin_gm20b.h new file mode 100644 index 000000000..506a8f07f --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_gm20b.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef RAMIN_GM20B_H +#define RAMIN_GM20B_H + +struct gk20a; + +void gm20b_ramin_set_big_page_size(struct gk20a *g, + struct nvgpu_mem *mem, u32 size); + +#endif /* RAMIN_GM20B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 505d937fd..2c6dd0b30 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1020,6 +1020,8 @@ struct gpu_ops { struct { void (*set_gr_ptr)(struct gk20a *g, struct nvgpu_mem *inst_block, u64 gpu_va); + void (*set_big_page_size)(struct gk20a *g, + struct nvgpu_mem *mem, u32 size); } ramin; struct { int (*reschedule)(struct channel_gk20a *ch, bool preempt_next); @@ -1289,8 +1291,6 @@ struct gpu_ops { void (*l2_invalidate)(struct gk20a *g); int (*l2_flush)(struct gk20a *g, bool invalidate); void (*cbc_clean)(struct gk20a *g); - void (*set_big_page_size)(struct gk20a *g, - struct nvgpu_mem *mem, u32 size); u32 (*get_big_page_sizes)(void); u32 (*get_default_big_page_size)(void); u32 (*get_iommu_bit)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/libnvgpu-drv.export b/drivers/gpu/nvgpu/libnvgpu-drv.export index 3d61a5f65..aa4496728 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv.export @@ -32,7 +32,7 @@ gk20a_locked_gmmu_map gk20a_locked_gmmu_unmap gm20b_fb_tlb_invalidate gm20b_fuse_status_opt_gpc -gm20b_mm_set_big_page_size +gm20b_ramin_set_big_page_size gp10b_fb_compression_page_size gp10b_init_bar2_vm gp10b_mm_get_default_big_page_size diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 433880657..5d2e8ba74 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -63,6 +63,7 @@ #include "hal/fifo/ramfc_gp10b.h" #include "hal/fifo/ramfc_gv11b.h" #include "hal/fifo/ramfc_tu104.h" +#include "hal/fifo/ramin_gm20b.h" #include "hal/fifo/ramin_gv11b.h" #include "hal/fifo/tsg_gv11b.h" #include "hal/fifo/userd_gk20a.h" @@ -1007,6 +1008,7 @@ static const struct gpu_ops tu104_ops = { }, .ramin = { .set_gr_ptr = gv11b_ramin_set_gr_ptr, + .set_big_page_size = gm20b_ramin_set_big_page_size, }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, @@ -1059,7 +1061,6 @@ static const struct gpu_ops tu104_ops = { .l2_invalidate = gk20a_mm_l2_invalidate, .l2_flush = gv11b_mm_l2_flush, .cbc_clean = gk20a_mm_cbc_clean, - .set_big_page_size = gm20b_mm_set_big_page_size, .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gp10b_mm_get_default_big_page_size, .gpu_phys_addr = gv11b_gpu_phys_addr, diff --git a/userspace/units/mm/page_table_faults/page_table_faults.c b/userspace/units/mm/page_table_faults/page_table_faults.c index 687027b15..c3cbaf810 100644 --- a/userspace/units/mm/page_table_faults/page_table_faults.c +++ b/userspace/units/mm/page_table_faults/page_table_faults.c @@ -46,6 +46,7 @@ #include "hal/fb/fb_gp10b.h" #include "hal/fb/fb_gm20b.h" #include "hal/fb/fb_gv11b.h" +#include "hal/fifo/ramin_gm20b.h" #define TEST_PA_ADDRESS 0xEFAD80000000 #define TEST_COMP_TAG 0xEF @@ -127,7 +128,6 @@ static int init_mm(struct unit_module *m, struct gk20a *g) g->ops.mm.fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy; g->ops.mm.mmu_fault_disable_hw = gv11b_mm_mmu_fault_disable_hw; g->ops.mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; - g->ops.mm.set_big_page_size = gm20b_mm_set_big_page_size; g->ops.mm.l2_flush = gv11b_mm_l2_flush; g->ops.fb.init_hw = gv11b_fb_init_hw; g->ops.fb.enable_hub_intr = gv11b_fb_enable_hub_intr; @@ -142,6 +142,7 @@ static int init_mm(struct unit_module *m, struct gk20a *g) g->ops.fb.mmu_fault_pending = gv11b_fb_mmu_fault_pending; g->ops.fb.is_fault_buf_enabled = gv11b_fb_is_fault_buf_enabled; g->ops.fb.fault_buf_set_state_hw = gv11b_fb_fault_buf_set_state_hw; + g->ops.ramin.set_big_page_size = gm20b_ramin_set_big_page_size; g->ops.channel.count = gv11b_channel_count; /* @@ -318,7 +319,7 @@ static int test_page_faults_inst_block(struct unit_module *m, struct gk20a *g, } else if (scenario == 2) { /* Handle branch case in gv11b_init_inst_block() */ big_page_size = g->ops.mm.get_default_big_page_size(); - g->ops.mm.set_big_page_size = NULL; + g->ops.ramin.set_big_page_size = NULL; } if (g->ops.mm.alloc_inst_block(g, &inst_blk_desc) != 0) {