From 3e43f92f211b2fd9c039321ce292351f12b65876 Mon Sep 17 00:00:00 2001
From: Sagar Kadamati <skadamati@nvidia.com>
Date: Tue, 4 May 2021 16:09:51 +0530
Subject: [PATCH] gpu: nvgpu: add ga10b & ga100 sources

Mass copy ga10b & ga100 sources from nvgpu-next repo.
TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1

Jira NVGPU-4771

Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
---
 arch/nvgpu-next-common.yaml                   |  180 +
 arch/nvgpu-next-gpu_hw.yaml                   |   98 +
 arch/nvgpu-next-hal-vgpu.yaml                 |   30 +
 arch/nvgpu-next-hal.yaml                      |  427 +
 arch/nvgpu-next-linux.yaml                    |   41 +
 drivers/gpu/nvgpu/Makefile                    |  154 +
 drivers/gpu/nvgpu/Makefile.sources            |  139 +
 drivers/gpu/nvgpu/common/acr/acr_sw_ga100.c   |   59 +
 drivers/gpu/nvgpu/common/acr/acr_sw_ga100.h   |   31 +
 drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c   |  343 +
 drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.h   |   31 +
 .../common/acr/nvgpu_next_acr_bootstrap.c     |  167 +
 .../common/acr/nvgpu_next_acr_bootstrap.h     |   32 +
 drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c |   92 +
 .../gpu/nvgpu/common/falcon/falcon_sw_ga10b.c |  158 +
 .../gpu/nvgpu/common/falcon/falcon_sw_ga10b.h |   28 +
 drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c   |   44 +
 .../nvgpu/common/fifo/nvgpu_next_engines.c    |   79 +
 .../nvgpu/common/fifo/nvgpu_next_runlist.c    |  113 +
 .../gpu/nvgpu/common/gr/nvgpu_next_fs_state.c |   57 +
 drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c   |   81 +
 drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c   |   92 +
 .../nvgpu/common/netlist/nvgpu_next_netlist.c |  383 +
 .../common/netlist/nvgpu_next_netlist_priv.h  |   92 +
 .../common/pmu/perfmon/pmu_perfmon_sw_ga10b.c |   38 +
 .../common/pmu/perfmon/pmu_perfmon_sw_ga10b.h |   29 +
 drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c |  379 +
 drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h |  298 +
 .../common/profiler/nvgpu_next_profiler.c     |   38 +
 .../common/profiler/nvgpu_next_profiler.h     |   28 +
 drivers/gpu/nvgpu/common/riscv/riscv.c        |  121 +
 drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c |   61 +
 .../nvgpu/common/sim/nvgpu_next_sim_netlist.c |  445 +
 .../gpu/nvgpu/common/vbios/bios_sw_ga100.c    |   98 +
 .../gpu/nvgpu/common/vbios/bios_sw_ga100.h    |   30 +
 drivers/gpu/nvgpu/hal/bus/bus_ga100.c         |   40 +
 drivers/gpu/nvgpu/hal/bus/bus_ga100.h         |   33 +
 drivers/gpu/nvgpu/hal/bus/bus_ga10b.c         |  156 +
 drivers/gpu/nvgpu/hal/bus/bus_ga10b.h         |   32 +
 drivers/gpu/nvgpu/hal/cbc/cbc_ga100.c         |  158 +
 drivers/gpu/nvgpu/hal/cbc/cbc_ga100.h         |   36 +
 drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c         |  152 +
 drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.h         |   37 +
 drivers/gpu/nvgpu/hal/ce/ce_ga10b.h           |   34 +
 drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c      |  239 +
 drivers/gpu/nvgpu/hal/class/class_ga100.c     |   86 +
 drivers/gpu/nvgpu/hal/class/class_ga100.h     |   35 +
 drivers/gpu/nvgpu/hal/class/class_ga10b.c     |   88 +
 drivers/gpu/nvgpu/hal/class/class_ga10b.h     |   35 +
 drivers/gpu/nvgpu/hal/clk/clk_ga100.c         |   38 +
 drivers/gpu/nvgpu/hal/clk/clk_ga100.h         |   28 +
 drivers/gpu/nvgpu/hal/falcon/falcon_ga10b.h   |   44 +
 .../gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c  |  215 +
 drivers/gpu/nvgpu/hal/fb/ecc/fb_ecc_ga10b.h   |   35 +
 .../gpu/nvgpu/hal/fb/ecc/fb_ecc_ga10b_fusa.c  |  119 +
 drivers/gpu/nvgpu/hal/fb/fb_ga100.c           |   80 +
 drivers/gpu/nvgpu/hal/fb/fb_ga100.h           |   37 +
 drivers/gpu/nvgpu/hal/fb/fb_ga10b.c           |  378 +
 drivers/gpu/nvgpu/hal/fb/fb_ga10b.h           |   63 +
 drivers/gpu/nvgpu/hal/fb/fb_ga10b_fusa.c      |  313 +
 drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_ga10b.h |   33 +
 .../nvgpu/hal/fb/fb_mmu_fault_ga10b_fusa.c    |   98 +
 .../gpu/nvgpu/hal/fb/intr/fb_intr_ecc_ga10b.h |   34 +
 .../hal/fb/intr/fb_intr_ecc_ga10b_fusa.c      |  194 +
 drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ga10b.h |   35 +
 .../nvgpu/hal/fb/intr/fb_intr_ga10b_fusa.c    |  133 +
 drivers/gpu/nvgpu/hal/fb/vab/vab_ga10b.c      |  372 +
 drivers/gpu/nvgpu/hal/fb/vab/vab_ga10b.h      |   37 +
 drivers/gpu/nvgpu/hal/fifo/channel_ga100.h    |   32 +
 .../gpu/nvgpu/hal/fifo/channel_ga100_fusa.c   |   40 +
 drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h    |   43 +
 .../gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c   |  255 +
 .../gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b.h  |   36 +
 .../nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c |  300 +
 .../gpu/nvgpu/hal/fifo/engine_status_ga10b.h  |   34 +
 .../nvgpu/hal/fifo/engine_status_ga10b_fusa.c |  153 +
 drivers/gpu/nvgpu/hal/fifo/fifo_ga10b.h       |   36 +
 drivers/gpu/nvgpu/hal/fifo/fifo_ga10b_fusa.c  |  154 +
 drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b.h  |   42 +
 .../gpu/nvgpu/hal/fifo/fifo_intr_ga10b_fusa.c |  485 +
 drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b.h |   38 +
 .../nvgpu/hal/fifo/fifo_utils_ga10b_fusa.c    |   77 +
 drivers/gpu/nvgpu/hal/fifo/pbdma_ga100.h      |   38 +
 drivers/gpu/nvgpu/hal/fifo/pbdma_ga100_fusa.c |  106 +
 drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.c      |   85 +
 drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h      |   74 +
 drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c |  615 ++
 .../gpu/nvgpu/hal/fifo/pbdma_status_ga10b.h   |   34 +
 .../nvgpu/hal/fifo/pbdma_status_ga10b_fusa.c  |  120 +
 drivers/gpu/nvgpu/hal/fifo/preempt_ga10b.h    |   31 +
 .../gpu/nvgpu/hal/fifo/preempt_ga10b_fusa.c   |   55 +
 drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b.h      |   35 +
 drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b_fusa.c |  168 +
 drivers/gpu/nvgpu/hal/fifo/ramin_ga10b.h      |   34 +
 drivers/gpu/nvgpu/hal/fifo/ramin_ga10b_fusa.c |   52 +
 .../gpu/nvgpu/hal/fifo/runlist_fifo_ga100.h   |   35 +
 .../nvgpu/hal/fifo/runlist_fifo_ga100_fusa.c  |   71 +
 .../gpu/nvgpu/hal/fifo/runlist_fifo_ga10b.c   |  128 +
 .../gpu/nvgpu/hal/fifo/runlist_fifo_ga10b.h   |   44 +
 .../nvgpu/hal/fifo/runlist_fifo_ga10b_fusa.c  |  135 +
 drivers/gpu/nvgpu/hal/fifo/runlist_ga10b.h    |   41 +
 .../gpu/nvgpu/hal/fifo/runlist_ga10b_fusa.c   |  114 +
 drivers/gpu/nvgpu/hal/fifo/tsg_ga10b.c        |   39 +
 drivers/gpu/nvgpu/hal/fifo/tsg_ga10b.h        |   32 +
 drivers/gpu/nvgpu/hal/fifo/userd_ga10b.c      |   51 +
 drivers/gpu/nvgpu/hal/fifo/userd_ga10b.h      |   33 +
 drivers/gpu/nvgpu/hal/fifo/usermode_ga10b.h   |   32 +
 .../gpu/nvgpu/hal/fifo/usermode_ga10b_fusa.c  |  100 +
 drivers/gpu/nvgpu/hal/func/func_ga10b.c       |   33 +
 drivers/gpu/nvgpu/hal/func/func_ga10b.h       |   32 +
 drivers/gpu/nvgpu/hal/fuse/fuse_ga100.c       |   67 +
 drivers/gpu/nvgpu/hal/fuse/fuse_ga100.h       |   35 +
 drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.c       |  438 +
 drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.h       |   55 +
 .../hal/gr/ctxsw_prog/ctxsw_prog_ga100.c      |   84 +
 .../hal/gr/ctxsw_prog/ctxsw_prog_ga100.h      |   43 +
 .../hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.c  |   76 +
 .../hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c |   33 +
 .../hal/gr/ctxsw_prog/ctxsw_prog_ga10b.c      |   94 +
 .../hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h      |   58 +
 .../hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.c  |   92 +
 .../hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c |  122 +
 drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.c      |   64 +
 drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.h      |   40 +
 drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b_fusa.c |  168 +
 .../gpu/nvgpu/hal/gr/falcon/gr_falcon_ga100.c |   69 +
 .../gpu/nvgpu/hal/gr/falcon/gr_falcon_ga100.h |   33 +
 .../gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b.c |   58 +
 .../gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b.h |   46 +
 .../hal/gr/falcon/gr_falcon_ga10b_fusa.c      |  119 +
 drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c        |  665 ++
 drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.h        |   42 +
 drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c        | 1075 ++
 drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.h        |   67 +
 drivers/gpu/nvgpu/hal/gr/gr/gr_pri_ga10b.h    |   64 +
 drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.c |   56 +
 drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.h |   47 +
 .../nvgpu/hal/gr/init/gr_init_ga100_fusa.c    |  152 +
 drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c |  107 +
 drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h |   73 +
 .../nvgpu/hal/gr/init/gr_init_ga10b_fusa.c    |  518 +
 drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100.h |   56 +
 .../nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c    |  244 +
 drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h |   77 +
 .../nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c    | 1088 ++
 drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.c      |   86 +
 drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.h      |   35 +
 drivers/gpu/nvgpu/hal/grmgr/grmgr_ga100.c     | 1209 +++
 drivers/gpu/nvgpu/hal/grmgr/grmgr_ga100.h     |   37 +
 drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c     | 1008 ++
 drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h     |   49 +
 drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c         |   42 +
 drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h         |   29 +
 drivers/gpu/nvgpu/hal/init/hal_ga100.c        | 1958 ++++
 drivers/gpu/nvgpu/hal/init/hal_ga100.h        |   32 +
 drivers/gpu/nvgpu/hal/init/hal_ga100_litter.c |  201 +
 drivers/gpu/nvgpu/hal/init/hal_ga100_litter.h |   28 +
 drivers/gpu/nvgpu/hal/init/hal_ga10b.c        | 1880 ++++
 drivers/gpu/nvgpu/hal/init/hal_ga10b.h        |   32 +
 drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.c |  209 +
 drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.h |   28 +
 .../gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h   |   37 +
 .../nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c  |  896 ++
 drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.c         |   80 +
 drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h         |   49 +
 drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c    |  190 +
 drivers/gpu/nvgpu/hal/mc/mc_ga10b.h           |   41 +
 drivers/gpu/nvgpu/hal/mc/mc_ga10b_fusa.c      |  282 +
 drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b.h      |   50 +
 drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c | 1036 ++
 drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b.h    |   37 +
 .../gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b_fusa.c   |  391 +
 .../nvgpu/hal/mm/mmu_fault/mmu_fault_ga10b.h  |   30 +
 .../hal/mm/mmu_fault/mmu_fault_ga10b_fusa.c   |  169 +
 drivers/gpu/nvgpu/hal/netlist/netlist_ga100.c |   55 +
 drivers/gpu/nvgpu/hal/netlist/netlist_ga100.h |   35 +
 drivers/gpu/nvgpu/hal/netlist/netlist_ga10b.h |   36 +
 .../nvgpu/hal/netlist/netlist_ga10b_fusa.c    |   76 +
 drivers/gpu/nvgpu/hal/nvdec/nvdec_ga100.c     |   30 +
 drivers/gpu/nvgpu/hal/nvdec/nvdec_ga100.h     |   30 +
 drivers/gpu/nvgpu/hal/perf/perf_ga100.c       |  357 +
 drivers/gpu/nvgpu/hal/perf/perf_ga100.h       |   43 +
 drivers/gpu/nvgpu/hal/perf/perf_ga10b.c       |  743 ++
 drivers/gpu/nvgpu/hal/perf/perf_ga10b.h       |   68 +
 drivers/gpu/nvgpu/hal/pmu/pmu_ga100.c         |   43 +
 drivers/gpu/nvgpu/hal/pmu/pmu_ga100.h         |   30 +
 drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c         |  344 +
 drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.h         |   56 +
 .../power_features/cg/ga100_gating_reglist.c  |  958 ++
 .../power_features/cg/ga100_gating_reglist.h  |  153 +
 .../power_features/cg/ga10b_gating_reglist.c  | 1148 ++
 .../power_features/cg/ga10b_gating_reglist.h  |  183 +
 .../gpu/nvgpu/hal/priv_ring/priv_ring_ga100.h |   31 +
 .../hal/priv_ring/priv_ring_ga100_fusa.c      |  110 +
 .../gpu/nvgpu/hal/priv_ring/priv_ring_ga10b.h |  109 +
 .../hal/priv_ring/priv_ring_ga10b_fusa.c      |  712 ++
 drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b.h   |   31 +
 .../gpu/nvgpu/hal/ptimer/ptimer_ga10b_fusa.c  |   74 +
 .../gpu/nvgpu/hal/regops/allowlist_ga100.c    | 1722 +++
 .../gpu/nvgpu/hal/regops/allowlist_ga100.h    |   61 +
 .../gpu/nvgpu/hal/regops/allowlist_ga10b.c    |  826 ++
 .../gpu/nvgpu/hal/regops/allowlist_ga10b.h    |   61 +
 drivers/gpu/nvgpu/hal/regops/regops_ga100.c   | 9395 +++++++++++++++++
 drivers/gpu/nvgpu/hal/regops/regops_ga100.h   |   37 +
 drivers/gpu/nvgpu/hal/regops/regops_ga10b.c   | 1760 +++
 drivers/gpu/nvgpu/hal/regops/regops_ga10b.h   |   37 +
 drivers/gpu/nvgpu/hal/therm/therm_ga10b.h     |   30 +
 .../gpu/nvgpu/hal/therm/therm_ga10b_fusa.c    |   86 +
 drivers/gpu/nvgpu/hal/top/top_ga10b.h         |   36 +
 drivers/gpu/nvgpu/hal/top/top_ga10b_fusa.c    |  178 +
 .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c  | 1206 +++
 .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.h  |   30 +
 .../include/nvgpu/gr/nvgpu_next_fs_state.h    |   31 +
 .../nvgpu/include/nvgpu/gr/nvgpu_next_gr.h    |   37 +
 .../include/nvgpu/gr/nvgpu_next_gr_ecc.h      |   30 +
 .../include/nvgpu/hw/ga100/hw_bus_ga100.h     |  116 +
 .../include/nvgpu/hw/ga100/hw_ce_ga100.h      |   78 +
 .../include/nvgpu/hw/ga100/hw_ctrl_ga100.h    |   72 +
 .../nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h      |  154 +
 .../include/nvgpu/hw/ga100/hw_falcon_ga100.h  |  129 +
 .../include/nvgpu/hw/ga100/hw_fb_ga100.h      |  359 +
 .../include/nvgpu/hw/ga100/hw_fbpa_ga100.h    |   80 +
 .../include/nvgpu/hw/ga100/hw_flush_ga100.h   |   86 +
 .../include/nvgpu/hw/ga100/hw_func_ga100.h    |  107 +
 .../include/nvgpu/hw/ga100/hw_fuse_ga100.h    |  115 +
 .../include/nvgpu/hw/ga100/hw_gc6_ga100.h     |   64 +
 .../include/nvgpu/hw/ga100/hw_gmmu_ga100.h    |  137 +
 .../include/nvgpu/hw/ga100/hw_gr_ga100.h      | 1256 +++
 .../include/nvgpu/hw/ga100/hw_ltc_ga100.h     |  358 +
 .../include/nvgpu/hw/ga100/hw_mc_ga100.h      |   76 +
 .../include/nvgpu/hw/ga100/hw_pbdma_ga100.h   |  257 +
 .../include/nvgpu/hw/ga100/hw_perf_ga100.h    |  118 +
 .../include/nvgpu/hw/ga100/hw_pgsp_ga100.h    |   88 +
 .../include/nvgpu/hw/ga100/hw_pnvdec_ga100.h  |   64 +
 .../include/nvgpu/hw/ga100/hw_pram_ga100.h    |   64 +
 .../include/nvgpu/hw/ga100/hw_pri_fbp_ga100.h |   70 +
 .../include/nvgpu/hw/ga100/hw_pri_gpc_ga100.h |   70 +
 .../nvgpu/hw/ga100/hw_pri_ringmaster_ga100.h  |  100 +
 .../hw/ga100/hw_pri_ringstation_sys_ga100.h   |   74 +
 .../include/nvgpu/hw/ga100/hw_pri_sys_ga100.h |   87 +
 .../include/nvgpu/hw/ga100/hw_proj_ga100.h    |  101 +
 .../include/nvgpu/hw/ga100/hw_psec_ga100.h    |  150 +
 .../include/nvgpu/hw/ga100/hw_pwr_ga100.h     |  235 +
 .../include/nvgpu/hw/ga100/hw_ram_ga100.h     |  175 +
 .../include/nvgpu/hw/ga100/hw_runlist_ga100.h |  228 +
 .../include/nvgpu/hw/ga100/hw_smcarb_ga100.h  |   90 +
 .../include/nvgpu/hw/ga100/hw_therm_ga100.h   |  114 +
 .../include/nvgpu/hw/ga100/hw_timer_ga100.h   |   74 +
 .../include/nvgpu/hw/ga100/hw_top_ga100.h     |   98 +
 .../include/nvgpu/hw/ga100/hw_trim_ga100.h    |  185 +
 .../include/nvgpu/hw/ga100/hw_xp_ga100.h      |   87 +
 .../include/nvgpu/hw/ga100/hw_xve_ga100.h     |  102 +
 .../include/nvgpu/hw/ga10b/hw_bus_ga10b.h     |  113 +
 .../include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h    |   62 +
 .../include/nvgpu/hw/ga10b/hw_ce_ga10b.h      |  111 +
 .../include/nvgpu/hw/ga10b/hw_ctrl_ga10b.h    |   72 +
 .../nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h      |  185 +
 .../include/nvgpu/hw/ga10b/hw_falcon_ga10b.h  |  125 +
 .../include/nvgpu/hw/ga10b/hw_fb_ga10b.h      |  379 +
 .../include/nvgpu/hw/ga10b/hw_flush_ga10b.h   |   86 +
 .../include/nvgpu/hw/ga10b/hw_func_ga10b.h    |   87 +
 .../include/nvgpu/hw/ga10b/hw_fuse_ga10b.h    |  148 +
 .../include/nvgpu/hw/ga10b/hw_gmmu_ga10b.h    |  137 +
 .../include/nvgpu/hw/ga10b/hw_gr_ga10b.h      | 1206 +++
 .../include/nvgpu/hw/ga10b/hw_ltc_ga10b.h     |  373 +
 .../include/nvgpu/hw/ga10b/hw_mc_ga10b.h      |   76 +
 .../include/nvgpu/hw/ga10b/hw_pbdma_ga10b.h   |  245 +
 .../include/nvgpu/hw/ga10b/hw_perf_ga10b.h    |  162 +
 .../include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h    |   64 +
 .../include/nvgpu/hw/ga10b/hw_pram_ga10b.h    |   62 +
 .../include/nvgpu/hw/ga10b/hw_pri_fbp_ga10b.h |   71 +
 .../include/nvgpu/hw/ga10b/hw_pri_gpc_ga10b.h |   71 +
 .../nvgpu/hw/ga10b/hw_pri_ringmaster_ga10b.h  |  100 +
 .../hw/ga10b/hw_pri_ringstation_sys_ga10b.h   |   74 +
 .../include/nvgpu/hw/ga10b/hw_pri_sys_ga10b.h |   89 +
 .../include/nvgpu/hw/ga10b/hw_priscv_ga10b.h  |   81 +
 .../include/nvgpu/hw/ga10b/hw_proj_ga10b.h    |  102 +
 .../include/nvgpu/hw/ga10b/hw_pwr_ga10b.h     |  262 +
 .../include/nvgpu/hw/ga10b/hw_ram_ga10b.h     |  172 +
 .../include/nvgpu/hw/ga10b/hw_runlist_ga10b.h |  225 +
 .../include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h  |   90 +
 .../include/nvgpu/hw/ga10b/hw_therm_ga10b.h   |  132 +
 .../include/nvgpu/hw/ga10b/hw_timer_ga10b.h   |   73 +
 .../include/nvgpu/hw/ga10b/hw_top_ga10b.h     |   96 +
 .../gpu/nvgpu/include/nvgpu/nvgpu_next_cic.h  |   95 +
 .../nvgpu/include/nvgpu/nvgpu_next_class.h    |   36 +
 .../nvgpu/include/nvgpu/nvgpu_next_device.h   |   58 +
 .../gpu/nvgpu/include/nvgpu/nvgpu_next_ecc.h  |   38 +
 .../include/nvgpu/nvgpu_next_engine_status.h  |   37 +
 .../nvgpu/include/nvgpu/nvgpu_next_engines.h  |   41 +
 .../gpu/nvgpu/include/nvgpu/nvgpu_next_err.h  |   32 +
 .../nvgpu/include/nvgpu/nvgpu_next_errata.h   |   35 +
 .../gpu/nvgpu/include/nvgpu/nvgpu_next_fb.h   |   65 +
 .../gpu/nvgpu/include/nvgpu/nvgpu_next_fuse.h |   71 +
 .../nvgpu/include/nvgpu/nvgpu_next_gops_ce.h  |   29 +
 .../nvgpu/include/nvgpu/nvgpu_next_gops_cg.h  |   42 +
 .../nvgpu/include/nvgpu/nvgpu_next_gops_fb.h  |   36 +
 .../include/nvgpu/nvgpu_next_gops_fb_vab.h    |   61 +
 .../include/nvgpu/nvgpu_next_gops_fifo.h      |   29 +
 .../include/nvgpu/nvgpu_next_gops_fuse.h      |   34 +
 .../nvgpu/include/nvgpu/nvgpu_next_gops_gr.h  |   29 +
 .../nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h     |   41 +
 .../include/nvgpu/nvgpu_next_gops_gr_init.h   |   33 +
 .../include/nvgpu/nvgpu_next_gops_gr_intr.h   |   29 +
 .../include/nvgpu/nvgpu_next_gops_grmgr.h     |   37 +
 .../nvgpu/include/nvgpu/nvgpu_next_gops_ltc.h |   28 +
 .../include/nvgpu/nvgpu_next_gops_ltc_intr.h  |   29 +
 .../nvgpu/include/nvgpu/nvgpu_next_gops_mc.h  |   60 +
 .../include/nvgpu/nvgpu_next_gops_pbdma.h     |   33 +
 .../include/nvgpu/nvgpu_next_gops_perf.h      |   30 +
 .../include/nvgpu/nvgpu_next_gops_priv_ring.h |   32 +
 .../include/nvgpu/nvgpu_next_gops_runlist.h   |   37 +
 .../nvgpu/include/nvgpu/nvgpu_next_litter.h   |   36 +
 .../gpu/nvgpu/include/nvgpu/nvgpu_next_mc.h   |   69 +
 .../gpu/nvgpu/include/nvgpu/nvgpu_next_mm.h   |   29 +
 .../nvgpu/include/nvgpu/nvgpu_next_netlist.h  |   90 +
 .../nvgpu/include/nvgpu/nvgpu_next_pbdma.h    |   44 +
 .../nvgpu/include/nvgpu/nvgpu_next_runlist.h  |   52 +
 .../gpu/nvgpu/include/nvgpu/nvgpu_next_sim.h  |   42 +
 drivers/gpu/nvgpu/include/nvgpu/riscv.h       |  101 +
 drivers/gpu/nvgpu/nvgpu_next_gpuid.h          |   70 +
 .../nvgpu/os/linux/nvgpu_next_ioctl_prof.c    |  137 +
 .../nvgpu/os/linux/nvgpu_next_ioctl_prof.h    |   24 +
 .../os/linux/nvlink/hal/ga10b_mssnvlink.c     |   93 +
 .../gpu/nvgpu/os/linux/platform_ga10b_tegra.c |  325 +
 .../vgpu/ga10b/platform_ga10b_vgpu_tegra.c    |   69 +
 326 files changed, 62836 insertions(+)
 create mode 100644 arch/nvgpu-next-common.yaml
 create mode 100644 arch/nvgpu-next-gpu_hw.yaml
 create mode 100644 arch/nvgpu-next-hal-vgpu.yaml
 create mode 100644 arch/nvgpu-next-hal.yaml
 create mode 100644 arch/nvgpu-next-linux.yaml
 create mode 100644 drivers/gpu/nvgpu/common/acr/acr_sw_ga100.c
 create mode 100644 drivers/gpu/nvgpu/common/acr/acr_sw_ga100.h
 create mode 100644 drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.c
 create mode 100644 drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.h
 create mode 100644 drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c
 create mode 100644 drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c
 create mode 100644 drivers/gpu/nvgpu/common/fifo/nvgpu_next_engines.c
 create mode 100644 drivers/gpu/nvgpu/common/fifo/nvgpu_next_runlist.c
 create mode 100644 drivers/gpu/nvgpu/common/gr/nvgpu_next_fs_state.c
 create mode 100644 drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c
 create mode 100644 drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c
 create mode 100644 drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist.c
 create mode 100644 drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist_priv.h
 create mode 100644 drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.c
 create mode 100644 drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.h
 create mode 100644 drivers/gpu/nvgpu/common/riscv/riscv.c
 create mode 100644 drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c
 create mode 100644 drivers/gpu/nvgpu/common/sim/nvgpu_next_sim_netlist.c
 create mode 100644 drivers/gpu/nvgpu/common/vbios/bios_sw_ga100.c
 create mode 100644 drivers/gpu/nvgpu/common/vbios/bios_sw_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/bus/bus_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/bus/bus_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/bus/bus_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/bus/bus_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/cbc/cbc_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/cbc/cbc_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/ce/ce_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/class/class_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/class/class_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/class/class_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/class/class_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/clk/clk_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/clk/clk_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/falcon/falcon_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fb/ecc/fb_ecc_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fb/ecc/fb_ecc_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fb/fb_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/fb/fb_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/fb/fb_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/fb/fb_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fb/fb_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fb/vab/vab_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/fb/vab/vab_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/channel_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/channel_ga100_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/fifo_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/fifo_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/pbdma_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/pbdma_ga100_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/pbdma_status_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/pbdma_status_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/preempt_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/preempt_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/ramin_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/ramin_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga100_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/runlist_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/runlist_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/tsg_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/tsg_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/userd_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/userd_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/usermode_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fifo/usermode_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/func/func_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/func/func_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/fuse/fuse_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/fuse/fuse_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/gr/gr_pri_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/grmgr/grmgr_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/grmgr/grmgr_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/init/hal_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/init/hal_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/init/hal_ga100_litter.c
 create mode 100644 drivers/gpu/nvgpu/hal/init/hal_ga100_litter.h
 create mode 100644 drivers/gpu/nvgpu/hal/init/hal_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/init/hal_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.c
 create mode 100644 drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.h
 create mode 100644 drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/mc/mc_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/mc/mc_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/netlist/netlist_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/netlist/netlist_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/netlist/netlist_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/netlist/netlist_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/nvdec/nvdec_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/nvdec/nvdec_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/perf/perf_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/perf/perf_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/perf/perf_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/perf/perf_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/pmu/pmu_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/pmu/pmu_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c
 create mode 100644 drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.h
 create mode 100644 drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c
 create mode 100644 drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.h
 create mode 100644 drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga100_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/regops/allowlist_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/regops/allowlist_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/regops/regops_ga100.c
 create mode 100644 drivers/gpu/nvgpu/hal/regops/regops_ga100.h
 create mode 100644 drivers/gpu/nvgpu/hal/regops/regops_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/regops/regops_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/therm/therm_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/therm/therm_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/top/top_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/hal/top/top_ga10b_fusa.c
 create mode 100644 drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
 create mode 100644 drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_fs_state.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr_ecc.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_bus_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ce_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ctrl_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_falcon_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fb_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fbpa_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_flush_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_func_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fuse_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gc6_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gmmu_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ltc_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_mc_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pbdma_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_perf_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pgsp_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pnvdec_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pram_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_fbp_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_gpc_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_ringmaster_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_ringstation_sys_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_sys_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_proj_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_psec_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pwr_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ram_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_runlist_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_smcarb_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_therm_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_timer_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_top_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_trim_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xp_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xve_ga100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_bus_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ce_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ctrl_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_falcon_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fb_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_flush_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_func_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gmmu_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ltc_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_mc_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pbdma_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pram_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_fbp_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_gpc_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_ringmaster_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_ringstation_sys_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_sys_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_priscv_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_proj_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pwr_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ram_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_runlist_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_therm_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_timer_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_top_ga10b.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_cic.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_class.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_device.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_ecc.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engine_status.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engines.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_err.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_errata.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fb.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fuse.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ce.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_cg.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb_vab.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fifo.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fuse.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_init.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_intr.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_grmgr.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc_intr.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_mc.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_pbdma.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_perf.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_priv_ring.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_runlist.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_litter.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mc.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mm.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_netlist.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_pbdma.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_runlist.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_sim.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/riscv.h
 create mode 100644 drivers/gpu/nvgpu/nvgpu_next_gpuid.h
 create mode 100644 drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.c
 create mode 100644 drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.h
 create mode 100644 drivers/gpu/nvgpu/os/linux/nvlink/hal/ga10b_mssnvlink.c
 create mode 100644 drivers/gpu/nvgpu/os/linux/platform_ga10b_tegra.c
 create mode 100644 drivers/gpu/nvgpu/os/linux/vgpu/ga10b/platform_ga10b_vgpu_tegra.c

diff --git a/arch/nvgpu-next-common.yaml b/arch/nvgpu-next-common.yaml
new file mode 100644
index 000000000..f02600c80
--- /dev/null
+++ b/arch/nvgpu-next-common.yaml
@@ -0,0 +1,180 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All Rights Reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+
+# Common elements and units in nvgpu.
+#
+
+##
+## Common elements.
+##
+
+nvgpu_next_fifo:
+  safe: no
+  owner: Seshendra G
+  children:
+    engines:
+      safe: no
+      sources: [ include/nvgpu/nvgpu_next_engines.h,
+                 common/fifo/nvgpu_next_engines.c ]
+
+    runlist:
+      safe: no
+      sources: [ include/nvgpu/nvgpu_next_runlist.h,
+                 common/fifo/nvgpu_next_runlist.c ]
+
+    pbdma:
+      safe: no
+      sources: [ include/nvgpu/nvgpu_next_pbdma.h ]
+
+    fifo:
+      safe: no
+      sources: [ include/nvgpu/nvgpu_next_gops_fifo.h ]
+
+nvgpu_next_sim:
+  safe: no
+  owner: Vedashree V
+  sources: [ include/nvgpu/nvgpu_next_sim.h,
+             common/sim/nvgpu_next_sim_netlist.c,
+             common/sim/nvgpu_next_sim.c ]
+
+nvgpu_next_netlist:
+  safe: no
+  owner: Vedashree V
+  sources: [ include/nvgpu/nvgpu_next_gops_fifo.h,
+             include/nvgpu/nvgpu_next_netlist.h,
+             common/netlist/nvgpu_next_netlist_priv.h,
+             common/netlist/nvgpu_next_netlist.c ]
+
+nvgpu_next_gr:
+  safe: no
+  owner: Vedashree V
+  sources: [ include/nvgpu/nvgpu_next_gops_gr.h,
+             include/nvgpu/gr/nvgpu_next_gr.h,
+             include/nvgpu/gr/nvgpu_next_fs_state.h,
+             include/nvgpu/gr/nvgpu_next_gr_ecc.h,
+             include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h,
+             common/gr/nvgpu_next_fs_state.c,
+             common/gr/nvgpu_next_gr.c ]
+
+nvgpu_next_bios:
+  safe: no
+  owner: Thomas F
+  sources: [ common/vbios/bios_sw_ga100.c,
+             common/vbios/bios_sw_ga100.h ]
+
+nvgpu_next_device:
+  safe: yes
+  owner: Alex W
+  sources: [ include/nvgpu/nvgpu_next_device.h ]
+
+nvgpu_next_ltc:
+  safe: no
+  owner: Antony
+  sources: [ include/nvgpu/nvgpu_next_gops_ltc.h,
+             include/nvgpu/nvgpu_next_gops_ltc_intr.h ]
+
+nvgpu_next_ce:
+  safe: no
+  owner: Antony
+  sources: [ include/nvgpu/nvgpu_next_gops_ce.h ]
+
+nvgpu_next_grmgr:
+  safe: no
+  owner: Lakshmanan M
+  sources: [ include/nvgpu/nvgpu_next_gops_grmgr.h ]
+
+nvgpu_next_priv_ring:
+  safe: no
+  owner: Lakshmanan M
+  sources: [ include/nvgpu/nvgpu_next_gops_priv_ring.h ]
+
+nvgpu_next_pmu_perfmon:
+  safe: no
+  owner: Ramesh M
+  sources: [ common/pmu/perfmon/pmu_perfmon_sw_ga10b.c,
+             common/pmu/perfmon/pmu_perfmon_sw_ga10b.h ]
+
+nvgpu_next_mc:
+  safe: yes
+  owner: Antony Clince Alex
+  sources: [ common/mc/nvgpu_next_mc.c,
+             include/nvgpu/nvgpu_next_mc.h ]
+
+nvgpu_next_cic:
+  safe: yes
+  owner: Tejal Kudav
+  sources: [ include/nvgpu/nvgpu_next_cic.h,
+             common/cic/nvgpu_next_cic.c ]
+
+nvgpu_next_pmu_pg:
+  safe: no
+  owner: Ramesh M
+  sources: [ common/pmu/pg/pg_sw_ga10b.c,
+             common/pmu/pg/pg_sw_ga10b.h ]
+
+nvgpu_next_err:
+  safe: yes
+  owner: Antony Clince Alex
+  sources: [ include/nvgpu/nvgpu_next_err.h ]
+
+nvgpu_next_acr_fusa:
+  safe: no
+  owner: Deepak G
+  sources: [ common/acr/nvgpu_next_acr_bootstrap.c,
+             common/acr/nvgpu_next_acr_bootstrap.h,
+             include/nvgpu/riscv.h,
+             common/riscv/riscv.c ]
+
+nvgpu_next_acr:
+  safe: no
+  owner: Deepak G
+  sources: [ common/acr/acr_sw_ga10b.c,
+             common/acr/acr_sw_ga10b.h,
+             common/acr/acr_sw_ga100.c,
+             common/acr/acr_sw_ga100.h  ]
+
+nvgpu_next_falcon:
+  safe: no
+  owner: Deepak G
+  sources: [ common/falcon/falcon_sw_ga10b.c,
+             common/falcon/falcon_sw_ga10b.h ]
+
+nvgpu_next_litter:
+  safe: no
+  owner: Antony
+  sources: [ include/nvgpu/nvgpu_next_litter.h ]
+
+nvgpu_next_profiler:
+  safe: no
+  owner: Antony
+  sources: [ common/profiler/nvgpu_next_profiler.h,
+             common/profiler/nvgpu_next_profiler.c ]
+
+nvgpu_next_fb:
+  safe: no
+  owner: Vedashree V
+  sources: [ common/fb/nvgpu_next_fb.c ]
+
+nvgpu_next_utils:
+  safe: no
+  owner: Vedashree V
+  sources: [ include/nvgpu/nvgpu_next_errata.h ]
diff --git a/arch/nvgpu-next-gpu_hw.yaml b/arch/nvgpu-next-gpu_hw.yaml
new file mode 100644
index 000000000..efd9ab3be
--- /dev/null
+++ b/arch/nvgpu-next-gpu_hw.yaml
@@ -0,0 +1,98 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All Rights Reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+
+# Define meta elements and units for describing GPU HW interactions in
+# nvgpu.
+#
+
+nvgpu_next_headers:
+  safe: no
+  owner: Seshendra G
+  sources: [ include/nvgpu/hw/ga100/hw_bus_ga100.h,
+             include/nvgpu/hw/ga100/hw_ce_ga100.h,
+             include/nvgpu/hw/ga100/hw_ctrl_ga100.h,
+             include/nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h,
+             include/nvgpu/hw/ga100/hw_falcon_ga100.h,
+             include/nvgpu/hw/ga100/hw_fb_ga100.h,
+             include/nvgpu/hw/ga100/hw_flush_ga100.h,
+             include/nvgpu/hw/ga100/hw_func_ga100.h,
+             include/nvgpu/hw/ga100/hw_fuse_ga100.h,
+             include/nvgpu/hw/ga100/hw_gc6_ga100.h,
+             include/nvgpu/hw/ga100/hw_gmmu_ga100.h,
+             include/nvgpu/hw/ga100/hw_gr_ga100.h,
+             include/nvgpu/hw/ga100/hw_ltc_ga100.h,
+             include/nvgpu/hw/ga100/hw_mc_ga100.h,
+             include/nvgpu/hw/ga100/hw_pbdma_ga100.h,
+             include/nvgpu/hw/ga100/hw_perf_ga100.h,
+             include/nvgpu/hw/ga100/hw_pgsp_ga100.h,
+             include/nvgpu/hw/ga100/hw_pram_ga100.h,
+             include/nvgpu/hw/ga100/hw_pri_fbp_ga100.h,
+             include/nvgpu/hw/ga100/hw_pri_gpc_ga100.h,
+             include/nvgpu/hw/ga100/hw_pri_ringmaster_ga100.h,
+             include/nvgpu/hw/ga100/hw_pri_ringstation_sys_ga100.h,
+             include/nvgpu/hw/ga100/hw_pri_sys_ga100.h,
+             include/nvgpu/hw/ga100/hw_proj_ga100.h,
+             include/nvgpu/hw/ga100/hw_psec_ga100.h,
+             include/nvgpu/hw/ga100/hw_pwr_ga100.h,
+             include/nvgpu/hw/ga100/hw_ram_ga100.h,
+             include/nvgpu/hw/ga100/hw_runlist_ga100.h,
+             include/nvgpu/hw/ga100/hw_smcarb_ga100.h,
+             include/nvgpu/hw/ga100/hw_timer_ga100.h,
+             include/nvgpu/hw/ga100/hw_top_ga100.h,
+             include/nvgpu/hw/ga100/hw_pnvdec_ga100.h,
+             include/nvgpu/hw/ga100/hw_therm_ga100.h,
+             include/nvgpu/hw/ga100/hw_trim_ga100.h,
+             include/nvgpu/hw/ga100/hw_xp_ga100.h,
+             include/nvgpu/hw/ga100/hw_xve_ga100.h,
+             include/nvgpu/hw/ga100/hw_fbpa_ga100.h,
+             include/nvgpu/hw/ga10b/hw_bus_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_ce_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_ctrl_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_falcon_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_fb_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_flush_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_func_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_fuse_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_gmmu_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_gr_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_ltc_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_mc_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_pbdma_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_perf_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_pram_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_pri_fbp_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_pri_gpc_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_pri_ringmaster_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_pri_ringstation_sys_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_pri_sys_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_proj_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_priscv_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_pwr_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_ram_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_runlist_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_therm_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_timer_ga10b.h,
+             include/nvgpu/hw/ga10b/hw_top_ga10b.h ]
diff --git a/arch/nvgpu-next-hal-vgpu.yaml b/arch/nvgpu-next-hal-vgpu.yaml
new file mode 100644
index 000000000..58e3eb327
--- /dev/null
+++ b/arch/nvgpu-next-hal-vgpu.yaml
@@ -0,0 +1,30 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All Rights Reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+
+# VGPU HAL units.
+#
+
+vgpu-next-init:
+  safe: no
+  owner: Aparna D
+  sources: [ hal/vgpu/init/vgpu_hal_ga10b.c,
+             hal/vgpu/init/vgpu_hal_ga10b.h ]
diff --git a/arch/nvgpu-next-hal.yaml b/arch/nvgpu-next-hal.yaml
new file mode 100644
index 000000000..20e8076f1
--- /dev/null
+++ b/arch/nvgpu-next-hal.yaml
@@ -0,0 +1,427 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All Rights Reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+
+# HAL units. These are the units that have access to HW.
+#
+
+nvgpu_next_init:
+  safe: no
+  owner: Seshendra G
+  sources: [ hal/init/hal_ga100.c,
+             hal/init/hal_ga100.h,
+             hal/init/hal_ga10b.c,
+             hal/init/hal_ga10b.h,
+             hal/init/hal_ga100_litter.c,
+             hal/init/hal_ga100_litter.h,
+             hal/init/hal_ga10b_litter.c,
+             hal/init/hal_ga10b_litter.h ]
+
+nvgpu_next_class:
+  safe: no
+  owner: Seshendra G
+  sources: [ hal/class/class_ga10b.h,
+             hal/class/class_ga10b.c,
+             hal/class/class_ga100.h,
+             hal/class/class_ga100.c,
+             include/nvgpu/nvgpu_next_class.h ]
+
+nvgpu_next_top:
+  safe: no
+  owner: Seshendra G
+  sources: [ hal/top/top_ga10b.h,
+             hal/top/top_ga10b_fusa.c ]
+
+nvgpu_next_fuse:
+  safe: no
+  owner: Seshendra G
+  sources: [ include/nvgpu/nvgpu_next_gops_fuse.h,
+             include/nvgpu/nvgpu_next_fuse.h,
+             hal/fuse/fuse_ga10b.h,
+             hal/fuse/fuse_ga100.h,
+             hal/fuse/fuse_ga10b.c,
+             hal/fuse/fuse_ga100.c ]
+
+nvgpu_next_clk:
+  safe: no
+  sources: [ hal/clk/clk_ga100.c,
+             hal/clk/clk_ga100.h ]
+
+nvgpu_next_fifo:
+  safe: no
+  owner: Seshendra G
+  children:
+    runlist:
+      safe: no
+      sources: [ include/nvgpu/nvgpu_next_gops_runlist.h,
+             hal/fifo/runlist_ga10b.h,
+             hal/fifo/runlist_ga10b_fusa.c ]
+
+    runlist_fusa:
+      safe: no
+      sources: [ hal/fifo/runlist_fifo_ga10b.h,
+                 hal/fifo/runlist_fifo_ga10b.c,
+                 hal/fifo/runlist_fifo_ga10b_fusa.c,
+                 hal/fifo/runlist_fifo_ga100.h,
+                 hal/fifo/runlist_fifo_ga100_fusa.c ]
+
+    fifo_fusa:
+     safe: no
+     sources: [ hal/fifo/fifo_ga10b_fusa.c,
+                hal/fifo/fifo_intr_ga10b_fusa.c,
+                hal/fifo/ctxsw_timeout_ga10b_fusa.c,
+                hal/fifo/ctxsw_timeout_ga10b.h,
+                hal/fifo/fifo_intr_ga10b.h,
+                hal/fifo/fifo_ga10b.h ]
+
+    channel_fusa:
+      safe: no
+      sources: [ hal/fifo/channel_ga10b_fusa.c,
+                 hal/fifo/channel_ga10b.h,
+                 hal/fifo/channel_ga100_fusa.c,
+                 hal/fifo/channel_ga100.h ]
+
+    tsg:
+      safe: no
+      sources: [ hal/fifo/tsg_ga10b.h,
+                 hal/fifo/tsg_ga10b.c ]
+
+    engine_status_fusa:
+      safe: no
+      sources: [ include/nvgpu/nvgpu_next_engine_status.h,
+                 hal/fifo/engine_status_ga10b_fusa.c,
+                 hal/fifo/engine_status_ga10b.h ]
+
+    ramfc_fusa:
+      safe: no
+      sources: [ hal/fifo/ramfc_ga10b_fusa.c,
+                 hal/fifo/ramfc_ga10b.h ]
+
+    pbdma_status_fusa:
+      safe: no
+      sources: [ hal/fifo/pbdma_status_ga10b_fusa.c,
+                 hal/fifo/pbdma_status_ga10b.h ]
+
+    pbdma_fusa:
+      safe: no
+      sources: [ hal/fifo/pbdma_ga10b_fusa.c,
+                 hal/fifo/pbdma_ga10b.h,
+                 hal/fifo/pbdma_ga100_fusa.c,
+                 hal/fifo/pbdma_ga100.h,
+                 include/nvgpu/nvgpu_next_gops_pbdma.h ]
+
+    preempt_fusa:
+      safe: no
+      sources: [ hal/fifo/preempt_ga10b_fusa.c,
+                 hal/fifo/preempt_ga10b.h ]
+    pbdma:
+      safe: no
+      sources: [ hal/fifo/pbdma_ga10b.c ]
+
+    ramin_fusa:
+      safe: no
+      sources: [ hal/fifo/ramin_ga10b_fusa.c,
+                 hal/fifo/ramin_ga10b.h ]
+
+    usermode_fusa:
+      safe: no
+      sources: [ hal/fifo/usermode_ga10b_fusa.c,
+                 hal/fifo/usermode_ga10b.h ]
+
+    userd:
+      safe: no
+      sources: [ hal/fifo/userd_ga10b.c,
+                 hal/fifo/userd_ga10b.h ]
+
+    utils_fusa:
+      safe: no
+      sources: [ hal/fifo/fifo_utils_ga10b_fusa.c,
+                 hal/fifo/fifo_utils_ga10b.h ]
+nvgpu_next_mm:
+  safe: no
+  owner: Seema K
+  children:
+    mm:
+      safe: no
+      sources: [ include/nvgpu/nvgpu_next_mm.h ]
+    mmu_fault:
+      safe: no
+      sources: [ hal/mm/mmu_fault/mmu_fault_ga10b_fusa.c,
+                 hal/mm/mmu_fault/mmu_fault_ga10b.h ]
+
+    gmmu_fusa:
+      safe: no
+      sources: [ hal/mm/gmmu/gmmu_ga10b_fusa.c,
+                 hal/mm/gmmu/gmmu_ga10b.h ]
+
+nvgpu_next_gr:
+  safe: no
+  owner: Seema K
+  children:
+    ctxsw_prog_fusa:
+      safe: no
+      sources: [ hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c,
+                 hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h,
+                 hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c,
+                 hal/gr/ctxsw_prog/ctxsw_prog_ga100.h]
+    ctxsw_prog:
+      safe: no
+      sources: [ hal/gr/ctxsw_prog/ctxsw_prog_ga10b.c,
+                 hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.c,
+                 hal/gr/ctxsw_prog/ctxsw_prog_ga100.c,
+                 hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.c ]
+
+    init_fusa:
+      safe: no
+      sources: [ include/nvgpu/nvgpu_next_gops_gr_init.h,
+                 hal/gr/init/gr_init_ga10b_fusa.c,
+                 hal/gr/init/gr_init_ga100_fusa.c,
+                 hal/gr/init/gr_init_ga100.h,
+                 hal/gr/init/gr_init_ga10b.h ]
+
+    init:
+      safe: no
+      sources: [ hal/gr/init/gr_init_ga10b.c,
+                 hal/gr/init/gr_init_ga10b.h,
+                 hal/gr/init/gr_init_ga100.c,
+                 hal/gr/init/gr_init_ga100.h ]
+
+    intr_fusa:
+      safe: no
+      sources: [ include/nvgpu/nvgpu_next_gops_gr_intr.h,
+                 hal/gr/intr/gr_intr_ga10b_fusa.c,
+                 hal/gr/intr/gr_intr_ga10b.h,
+                 hal/gr/intr/gr_intr_ga100_fusa.c,
+                 hal/gr/intr/gr_intr_ga100.h ]
+
+    gr:
+      safe: no
+      sources: [ hal/gr/gr/gr_ga10b.c,
+                 hal/gr/gr/gr_ga10b.h,
+                 hal/gr/gr/gr_ga100.c,
+                 hal/gr/gr/gr_ga100.h,
+                 hal/gr/gr/gr_pri_ga10b.h ]
+
+    falcon_fusa:
+      safe: no
+      sources: [ hal/gr/falcon/gr_falcon_ga10b_fusa.c,
+                 hal/gr/falcon/gr_falcon_ga10b.h ]
+    falcon:
+      safe: no
+      sources: [ hal/gr/falcon/gr_falcon_ga10b.c,
+                 hal/gr/falcon/gr_falcon_ga100.c,
+                 hal/gr/falcon/gr_falcon_ga100.h ]
+
+    zbc:
+      safe: no
+      sources: [ hal/gr/zbc/zbc_ga10b.c,
+                 hal/gr/zbc/zbc_ga10b.h ]
+
+    ecc_fusa:
+      safe: no
+      sources: [ hal/gr/ecc/ecc_ga10b_fusa.c,
+                 hal/gr/ecc/ecc_ga10b.h ]
+
+    ecc:
+      safe: no
+      sources: [ hal/gr/ecc/ecc_ga10b.c ,
+                 hal/gr/ecc/ecc_ga10b.h ]
+
+nvgpu_next_ltc:
+  safe: no
+  owner: Vedashree V
+  children:
+    ltc:
+      safe: no
+      sources: [ hal/ltc/ltc_ga10b.c ]
+
+    ltc_fusa:
+      safe: no
+      sources: [ hal/ltc/ltc_ga10b.h,
+                 hal/ltc/ltc_ga10b_fusa.c ]
+
+    ltc_intr:
+      safe: no
+      sources: [ hal/ltc/intr/ltc_intr_ga10b.h,
+                 hal/ltc/intr/ltc_intr_ga10b_fusa.c ]
+
+nvgpu_next_mc_fusa:
+  safe: no
+  owner: Seema K
+  sources: [ hal/mc/mc_intr_ga10b_fusa.c,
+             include/nvgpu/nvgpu_next_mc.h,
+             hal/mc/mc_intr_ga10b.h,
+             include/nvgpu/nvgpu_next_gops_mc.h,
+             hal/mc/mc_ga10b_fusa.c,
+             hal/mc/mc_ga10b.h ]
+
+nvgpu_next_cbc:
+  safe: no
+  owner: Vedashree V
+  sources: [ hal/cbc/cbc_ga10b.c,
+             hal/cbc/cbc_ga10b.h,
+             hal/cbc/cbc_ga100.c,
+             hal/cbc/cbc_ga100.h ]
+
+nvgpu_next_fb:
+  safe: no
+  owner: Vedashree V
+  sources: [ hal/fb/fb_ga10b.c,
+             hal/fb/fb_ga100.h,
+             hal/fb/fb_ga100.c,
+             hal/fb/vab/vab_ga10b.c,
+             hal/fb/vab/vab_ga10b.h,
+             include/nvgpu/nvgpu_next_fb.h,
+             include/nvgpu/nvgpu_next_gops_fb_vab.h ]
+
+nvgpu_next_fb_fusa:
+  safe: no
+  owner: Seshendra G
+  sources: [ include/nvgpu/nvgpu_next_ecc.h,
+             hal/fb/fb_ga10b.h,
+             hal/fb/fb_ga10b_fusa.c,
+             include/nvgpu/nvgpu_next_gops_fb.h,
+             hal/fb/ecc/fb_ecc_ga10b.h,
+             hal/fb/ecc/fb_ecc_ga10b_fusa.c,
+             hal/fb/intr/fb_intr_ga10b.h,
+             hal/fb/intr/fb_intr_ga10b_fusa.c,
+             hal/fb/fb_mmu_fault_ga10b.h,
+             hal/fb/fb_mmu_fault_ga10b_fusa.c,
+             hal/fb/intr/fb_intr_ecc_ga10b.h,
+             hal/fb/intr/fb_intr_ecc_ga10b_fusa.c ]
+
+nvgpu_next_netlist:
+  safe: no
+  owner: Seshendra G
+  sources: [ hal/netlist/netlist_ga10b_fusa.c,
+             hal/netlist/netlist_ga10b.h,
+             hal/netlist/netlist_ga100.c,
+             hal/netlist/netlist_ga100.h ]
+
+nvgpu_next_bus:
+  safe: no
+  owner: Seshendra G
+  sources: [ hal/bus/bus_ga10b.c,
+             hal/bus/bus_ga10b.h,
+             hal/bus/bus_ga100.c,
+             hal/bus/bus_ga100.h ]
+
+nvgpu_next_regops:
+  safe: no
+  owner: Seshendra G
+  sources: [ hal/regops/regops_ga10b.c,
+             hal/regops/regops_ga100.c,
+             hal/regops/regops_ga10b.h,
+             hal/regops/regops_ga100.h,
+             hal/regops/allowlist_ga10b.c,
+             hal/regops/allowlist_ga10b.h,
+             hal/regops/allowlist_ga100.c,
+             hal/regops/allowlist_ga100.h ]
+
+nvgpu_next_falcon_fusa:
+  safe: no
+  owner: Divya S
+  sources: [ hal/falcon/falcon_ga10b_fusa.c,
+             hal/falcon/falcon_ga10b.h  ]
+
+nvgpu_next_pmu:
+  safe: no
+  owner: Mahantesh K
+  sources: [ hal/pmu/pmu_ga10b.h,
+             hal/pmu/pmu_ga10b.c,
+             hal/pmu/pmu_ga100.h,
+             hal/pmu/pmu_ga100.c  ]
+
+nvgpu_next_gsp:
+  safe: no
+  owner: Deepak G
+  sources: [ hal/gsp/gsp_ga10b.h,
+             hal/gsp/gsp_ga10b.c  ]
+
+nvgpu_next_priv_ring_fusa:
+  safe: no
+  owner: Seema K
+  sources: [ hal/priv_ring/priv_ring_ga10b_fusa.c,
+             hal/priv_ring/priv_ring_ga10b.h,
+             hal/priv_ring/priv_ring_ga100_fusa.c,
+             hal/priv_ring/priv_ring_ga100.h ]
+
+nvgpu_next_ptimer_fusa:
+  safe: no
+  owner: Seema K
+  sources: [ hal/ptimer/ptimer_ga10b_fusa.c,
+             hal/ptimer/ptimer_ga10b.h ]
+
+nvgpu_next_perf:
+  safe: no
+  owner: Seshendra G
+  sources: [ hal/perf/perf_ga10b.c,
+             hal/perf/perf_ga10b.h,
+             hal/perf/perf_ga100.c,
+             hal/perf/perf_ga100.h,
+             include/nvgpu/nvgpu_next_gops_perf.h ]
+
+nvgpu_next_cg:
+  safe: no
+  owner: Antony
+  sources: [ include/nvgpu/nvgpu_next_gops_cg.h,
+             hal/power_features/cg/ga10b_gating_reglist.c,
+             hal/power_features/cg/ga10b_gating_reglist.h,
+             hal/power_features/cg/ga100_gating_reglist.c,
+             hal/power_features/cg/ga100_gating_reglist.h ]
+
+nvgpu_next_therm_fusa:
+  safe: no
+  owner: Antony
+  sources: [ hal/therm/therm_ga10b_fusa.c,
+             hal/therm/therm_ga10b.h ]
+
+nvgpu_next_ce_fusa:
+  safe: no
+  owner: Antony
+  sources: [ hal/ce/ce_ga10b_fusa.c,
+             hal/ce/ce_ga10b.h ]
+
+nvgpu_next_misc:
+  safe: no
+  owner: Vedashree V
+  sources: [ nvgpu_next_gpuid.h ]
+
+nvgpu_next_nvdec:
+  safe: no
+  owner: Mahantesh K
+  sources: [ hal/nvdec/nvdec_ga100.c,
+             hal/nvdec/nvdec_ga100.h ]
+
+nvgpu_next_grmgr:
+  safe: no
+  owner: Lakshmanan M
+  sources: [ hal/grmgr/grmgr_ga10b.c,
+             hal/grmgr/grmgr_ga10b.h,
+             hal/grmgr/grmgr_ga100.c,
+             hal/grmgr/grmgr_ga100.h,]
+
+nvgpu_next_func:
+  safe: no
+  owner: Vedashree V
+  sources: [ hal/func/func_ga10b.c,
+             hal/func/func_ga10b.h ]
+
diff --git a/arch/nvgpu-next-linux.yaml b/arch/nvgpu-next-linux.yaml
new file mode 100644
index 000000000..4d2229883
--- /dev/null
+++ b/arch/nvgpu-next-linux.yaml
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All Rights Reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+
+# Linux elements and units in nvgpu.
+#
+# The safe: tag is ommited through out since all Linux units are by definition
+# not safe.
+#
+# I also have not put a huge amount of thought into this since none of this
+# code is "safe" code. Nor are we planning on spending a lot of effort to
+# clean this up. At least not yet.
+
+nvgpu_next_platform:
+  sources: [ os/linux/platform_ga10b_tegra.c,
+             os/linux/nvlink/hal/ga10b_mssnvlink.c ]
+
+vgpu-next:
+  sources: [ os/linux/vgpu/ga10b/platform_ga10b_vgpu_tegra.c ]
+
+nvgpu_next_ioctl:
+  sources: [ os/linux/nvgpu_next_ioctl_prof.c,
+             os/linux/nvgpu_next_ioctl_prof.h ]
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 56522b1a5..2c9676b44 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -786,3 +786,157 @@ ifeq ($(CONFIG_NVGPU_GR_VIRTUALIZATION),y)
 nvgpu-$(CONFIG_NVGPU_HAL_NON_FUSA) += \
 	hal/vgpu/init/vgpu_hal_gv11b.o
 endif
+
+
+ifeq ($(CONFIG_ARCH_TEGRA_23x_SOC),y)
+CONFIG_NVGPU_NEXT := y
+ccflags-y += -DCONFIG_NVGPU_NEXT
+# Multi Instance GPU support
+CONFIG_NVGPU_MIG := y
+endif
+
+ifeq ($(CONFIG_NVGPU_NEXT),y)
+ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),y)
+nvgpu-y += \
+	common/fifo/nvgpu_next_engines.o \
+	common/fifo/nvgpu_next_runlist.o \
+	common/acr/nvgpu_next_acr_bootstrap.o \
+	common/falcon/falcon_sw_ga10b.o \
+	common/fb/nvgpu_next_fb.o \
+	common/riscv/riscv.o \
+	common/acr/acr_sw_ga10b.o \
+	common/acr/acr_sw_ga100.o \
+	common/sim/nvgpu_next_sim.o \
+	common/gr/nvgpu_next_gr.o \
+	common/gr/nvgpu_next_fs_state.o \
+	common/netlist/nvgpu_next_netlist.o \
+	common/sim/nvgpu_next_sim_netlist.o \
+	common/pmu/perfmon/pmu_perfmon_sw_ga10b.o \
+	common/cic/nvgpu_next_cic.o \
+	common/pmu/pg/pg_sw_ga10b.o \
+	common/profiler/nvgpu_next_profiler.o
+
+nvgpu-y += \
+	hal/init/hal_ga10b.o \
+	hal/init/hal_ga10b_litter.o \
+	hal/gr/zbc/zbc_ga10b.o \
+	hal/class/class_ga10b.o \
+	hal/class/class_ga100.o \
+	hal/mc/mc_ga10b_fusa.o \
+	hal/mc/mc_intr_ga10b_fusa.o \
+	hal/mm/mmu_fault/mmu_fault_ga10b_fusa.o \
+	hal/mm/gmmu/gmmu_ga10b_fusa.o \
+	hal/func/func_ga10b.o \
+	hal/fuse/fuse_ga10b.o \
+	hal/falcon/falcon_ga10b_fusa.o \
+	hal/fifo/usermode_ga10b_fusa.o \
+	hal/fifo/fifo_intr_ga10b_fusa.o \
+	hal/fifo/ctxsw_timeout_ga10b_fusa.o \
+	hal/fifo/fifo_ga10b_fusa.o \
+	hal/fifo/pbdma_ga10b_fusa.o \
+	hal/fifo/pbdma_ga10b.o \
+	hal/fifo/usermode_ga10b_fusa.o \
+	hal/fifo/fifo_utils_ga10b_fusa.o \
+	hal/fifo/engine_status_ga10b_fusa.o \
+	hal/fifo/pbdma_status_ga10b_fusa.o \
+	hal/fifo/preempt_ga10b_fusa.o \
+	hal/fifo/runlist_fifo_ga10b_fusa.o \
+	hal/fifo/runlist_fifo_ga10b.o \
+	hal/fifo/tsg_ga10b.o \
+	hal/fifo/userd_ga10b.o \
+	hal/fifo/ramin_ga10b_fusa.o \
+	hal/fifo/ramfc_ga10b_fusa.o \
+	hal/fifo/runlist_ga10b_fusa.o \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga10b.o \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.o \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.o \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga100.o \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.o \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.o \
+	hal/gr/gr/gr_ga10b.o \
+	hal/gr/init/gr_init_ga10b.o \
+	hal/gr/init/gr_init_ga10b_fusa.o \
+	hal/gr/intr/gr_intr_ga10b_fusa.o \
+	hal/gr/falcon/gr_falcon_ga10b_fusa.o \
+	hal/gr/falcon/gr_falcon_ga10b.o \
+	hal/gr/ecc/ecc_ga10b.o \
+	hal/gr/ecc/ecc_ga10b_fusa.o \
+	hal/netlist/netlist_ga10b_fusa.o \
+	hal/fifo/channel_ga10b_fusa.o \
+	hal/ltc/ltc_ga10b_fusa.o \
+	hal/ltc/ltc_ga10b.o \
+	hal/ltc/intr/ltc_intr_ga10b_fusa.o \
+	hal/top/top_ga10b_fusa.o \
+	hal/bus/bus_ga10b.o \
+	hal/pmu/pmu_ga10b.o \
+	hal/gsp/gsp_ga10b.o \
+	hal/fb/fb_ga100.o \
+	hal/fb/fb_ga10b.o \
+	hal/fb/fb_ga10b_fusa.o \
+	hal/fb/fb_mmu_fault_ga10b_fusa.o \
+	hal/fb/ecc/fb_ecc_ga10b_fusa.o \
+	hal/fb/intr/fb_intr_ga10b_fusa.o \
+	hal/fb/intr/fb_intr_ecc_ga10b_fusa.o \
+	hal/fb/vab/vab_ga10b.o \
+	hal/priv_ring/priv_ring_ga10b_fusa.o \
+	hal/ptimer/ptimer_ga10b_fusa.o \
+	hal/perf/perf_ga10b.o \
+	hal/regops/regops_ga10b.o \
+	hal/regops/allowlist_ga10b.o \
+	hal/power_features/cg/ga10b_gating_reglist.o \
+	hal/therm/therm_ga10b_fusa.o \
+	hal/ce/ce_ga10b_fusa.o \
+	hal/grmgr/grmgr_ga10b.o
+
+ifeq ($(CONFIG_NVGPU_COMPRESSION),y)
+nvgpu-y += \
+	hal/cbc/cbc_ga100.o \
+	hal/cbc/cbc_ga10b.o
+endif
+
+nvgpu-$(CONFIG_NVGPU_GR_VIRTUALIZATION) += \
+	hal/vgpu/init/vgpu_hal_ga10b.o \
+	os/linux/vgpu/ga10b/platform_ga10b_vgpu_tegra.o
+
+endif
+
+ifeq ($(CONFIG_NVGPU_DGPU),y)
+nvgpu-y += \
+	hal/init/hal_ga100.o \
+	hal/init/hal_ga100_litter.o \
+	hal/gr/gr/gr_ga100.o \
+	hal/bus/bus_ga100.o \
+	hal/fuse/fuse_ga100.o \
+	hal/gr/intr/gr_intr_ga100_fusa.o \
+	hal/gr/init/gr_init_ga100_fusa.o \
+	hal/gr/init/gr_init_ga100.o \
+	hal/gr/falcon/gr_falcon_ga100.o \
+	hal/clk/clk_ga100.o \
+	hal/nvdec/nvdec_ga100.o \
+	hal/pmu/pmu_ga100.o \
+	hal/perf/perf_ga100.o \
+	hal/fb/fb_ga100.o \
+	hal/fifo/channel_ga100_fusa.o \
+	hal/fifo/pbdma_ga100_fusa.o \
+	hal/fifo/runlist_fifo_ga100_fusa.o \
+	hal/netlist/netlist_ga100.o \
+	common/vbios/bios_sw_ga100.o \
+	hal/power_features/cg/ga100_gating_reglist.o \
+	hal/priv_ring/priv_ring_ga100_fusa.o \
+	hal/regops/regops_ga100.o \
+	hal/regops/allowlist_ga100.o
+endif
+
+ifeq ($(CONFIG_NVGPU_MIG),y)
+ccflags-y += -DCONFIG_NVGPU_MIG
+ifeq ($(CONFIG_NVGPU_DGPU),y)
+nvgpu-y += \
+	hal/grmgr/grmgr_ga100.o
+endif
+endif
+
+nvgpu-y += \
+	os/linux/platform_ga10b_tegra.o \
+	os/linux/nvgpu_next_ioctl_prof.o \
+	os/linux/nvlink/hal/ga10b_mssnvlink.o
+endif
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index c9d4a3df3..4b49bb7bd 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -709,3 +709,142 @@ endif
 ifeq ($(CONFIG_NVGPU_TPC_POWERGATE),1)
 srcs +=	hal/tpc/tpc_gv11b.c
 endif
+
+ifeq ($(CONFIG_NVGPU_NEXT),1)
+ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
+srcs += \
+	common/fifo/nvgpu_next_engines.c \
+	common/acr/nvgpu_next_acr_bootstrap.c \
+	common/riscv/riscv.c \
+	common/acr/acr_sw_ga10b.c \
+	common/acr/acr_sw_ga100.c \
+	common/fb/nvgpu_next_fb.c \
+	common/fifo/nvgpu_next_runlist.c \
+	common/gr/nvgpu_next_gr.c \
+	common/gr/nvgpu_next_fs_state.c \
+	common/netlist/nvgpu_next_netlist.c \
+	common/sim/nvgpu_next_sim.c \
+	common/sim/nvgpu_next_sim_netlist.c \
+	common/pmu/perfmon/pmu_perfmon_sw_ga10b.c \
+	common/cic/nvgpu_next_cic.c \
+	common/pmu/pg/pg_sw_ga10b.c \
+	common/falcon/falcon_sw_ga10b.c \
+	common/profiler/nvgpu_next_profiler.c
+
+srcs += hal/init/hal_ga10b.c \
+	hal/init/hal_ga10b_litter.c \
+	hal/gr/zbc/zbc_ga10b.c \
+	hal/class/class_ga10b.c \
+	hal/class/class_ga100.c \
+	hal/mc/mc_ga10b_fusa.c \
+	hal/mc/mc_intr_ga10b_fusa.c \
+	hal/mm/mmu_fault/mmu_fault_ga10b_fusa.c \
+	hal/mm/gmmu/gmmu_ga10b_fusa.c \
+	hal/func/func_ga10b.c \
+	hal/fuse/fuse_ga10b.c \
+	hal/falcon/falcon_ga10b_fusa.c \
+	hal/fifo/usermode_ga10b_fusa.c \
+	hal/fifo/fifo_intr_ga10b_fusa.c \
+	hal/fifo/ctxsw_timeout_ga10b_fusa.c \
+	hal/fifo/fifo_utils_ga10b_fusa.c \
+	hal/fifo/fifo_ga10b_fusa.c \
+	hal/fifo/pbdma_ga10b_fusa.c \
+	hal/fifo/pbdma_ga10b.c \
+	hal/fifo/engine_status_ga10b_fusa.c \
+	hal/fifo/pbdma_status_ga10b_fusa.c \
+	hal/fifo/preempt_ga10b_fusa.c \
+	hal/fifo/runlist_fifo_ga10b_fusa.c \
+	hal/fifo/runlist_fifo_ga10b.c \
+	hal/fifo/runlist_ga10b_fusa.c \
+	hal/fifo/tsg_ga10b.c \
+	hal/fifo/userd_ga10b.c \
+	hal/fifo/ramin_ga10b_fusa.c \
+	hal/fifo/ramfc_ga10b_fusa.c \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga10b.c \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.c \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga100.c \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.c \
+	hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c \
+	hal/gr/gr/gr_ga10b.c \
+	hal/gr/init/gr_init_ga10b.c \
+	hal/gr/init/gr_init_ga10b_fusa.c \
+	hal/gr/intr/gr_intr_ga10b_fusa.c \
+	hal/gr/falcon/gr_falcon_ga10b_fusa.c \
+	hal/gr/falcon/gr_falcon_ga10b.c \
+	hal/gr/ecc/ecc_ga10b.c \
+	hal/gr/ecc/ecc_ga10b_fusa.c \
+	hal/netlist/netlist_ga10b_fusa.c \
+	hal/fifo/channel_ga10b_fusa.c \
+	hal/ltc/ltc_ga10b_fusa.c \
+	hal/ltc/ltc_ga10b.c \
+	hal/ltc/intr/ltc_intr_ga10b_fusa.c \
+	hal/top/top_ga10b_fusa.c \
+	hal/bus/bus_ga10b.c \
+	hal/pmu/pmu_ga10b.c \
+	hal/gsp/gsp_ga10b.c \
+	hal/fb/fb_ga10b.c \
+	hal/fb/fb_mmu_fault_ga10b_fusa.c \
+	hal/fb/fb_ga10b_fusa.c \
+	hal/fb/ecc/fb_ecc_ga10b_fusa.c \
+	hal/fb/intr/fb_intr_ga10b_fusa.c \
+	hal/fb/intr/fb_intr_ecc_ga10b_fusa.c \
+	hal/fb/vab/vab_ga10b.c \
+	hal/priv_ring/priv_ring_ga10b_fusa.c \
+	hal/ptimer/ptimer_ga10b_fusa.c \
+	hal/perf/perf_ga10b.c \
+	hal/regops/regops_ga10b.c \
+	hal/regops/allowlist_ga10b.c \
+	hal/power_features/cg/ga10b_gating_reglist.c \
+	hal/therm/therm_ga10b_fusa.c \
+	hal/ce/ce_ga10b_fusa.c \
+	hal/grmgr/grmgr_ga10b.c
+
+ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
+srcs += \
+	hal/cbc/cbc_ga100.c \
+	hal/cbc/cbc_ga10b.c
+endif
+
+endif
+
+ifeq ($(CONFIG_NVGPU_IGPU_VIRT),1)
+srcs += \
+	hal/vgpu/init/vgpu_hal_ga10b.c
+endif
+
+ifeq ($(CONFIG_NVGPU_DGPU),1)
+srcs += \
+	hal/init/hal_ga100.c \
+	hal/init/hal_ga100_litter.c \
+	hal/gr/gr/gr_ga100.c \
+	hal/bus/bus_ga100.c \
+	hal/fuse/fuse_ga100.c \
+	hal/gr/intr/gr_intr_ga100_fusa.c \
+	hal/gr/init/gr_init_ga100_fusa.c \
+	hal/gr/init/gr_init_ga100.c \
+	hal/gr/falcon/gr_falcon_ga100.c \
+	hal/clk/clk_ga100.c \
+	hal/nvdec/nvdec_ga100.c \
+	hal/pmu/pmu_ga100.c \
+	hal/perf/perf_ga100.c \
+	hal/fb/fb_ga100.c \
+	hal/fifo/channel_ga100_fusa.c \
+	hal/fifo/pbdma_ga100_fusa.c \
+	hal/fifo/runlist_fifo_ga100_fusa.c \
+	hal/netlist/netlist_ga100.c \
+	common/vbios/bios_sw_ga100.c \
+	hal/power_features/cg/ga100_gating_reglist.c \
+	hal/priv_ring/priv_ring_ga100_fusa.c \
+	hal/regops/regops_ga100.c \
+	hal/regops/allowlist_ga100.c
+endif
+
+ifeq ($(CONFIG_NVGPU_MIG),1)
+ifeq ($(CONFIG_NVGPU_DGPU),1)
+srcs += \
+	hal/grmgr/grmgr_ga100.c
+endif
+endif
+
+endif
diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.c b/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.c
new file mode 100644
index 000000000..c760988da
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/falcon.h>
+
+#include "common/acr/acr_priv.h"
+#include "common/acr/acr_sw_tu104.h"
+#include "acr_sw_ga100.h"
+
+static u32* ga100_get_versioned_sig(struct gk20a *g, struct nvgpu_acr *acr,
+	u32 *sig, u32 *sig_size)
+{
+	u32 ucode_version = 0U;
+	u32 sig_size_words = 0U;
+	u32 sig_idx = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	g->ops.fuse.read_ucode_version(g, FALCON_ID_SEC2, &ucode_version);
+
+	*sig_size = *sig_size/acr->num_of_sig;
+
+	sig_idx = (!ucode_version) ? 1U : 0U;
+
+	sig_size_words = *sig_size/4U;
+
+	sig = sig + nvgpu_safe_mult_u32(sig_idx, sig_size_words);
+
+	return sig;
+}
+
+void nvgpu_next_dgpu_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
+{
+	nvgpu_log_fn(g, " ");
+
+	acr->num_of_sig = 2U;
+	nvgpu_tu104_acr_sw_init(g, acr);
+	acr->get_versioned_sig = ga100_get_versioned_sig;
+}
diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.h b/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.h
new file mode 100644
index 000000000..04ea2da94
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef ACR_SW_GA100_H
+#define ACR_SW_GA100_H
+
+struct gk20a;
+struct nvgpu_acr;
+
+void nvgpu_next_dgpu_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
+
+#endif /*ACR_SW_GA100_H*/
diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c b/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c
new file mode 100644
index 000000000..97aa17d98
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c
@@ -0,0 +1,343 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <nvgpu/types.h>
+#include <nvgpu/firmware.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/dma.h>
+#include <nvgpu/pmu.h>
+#ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/fw.h>
+#endif
+
+#include "common/acr/acr_wpr.h"
+#include "common/acr/acr_priv.h"
+#include "common/acr/acr_blob_alloc.h"
+#include "common/acr/acr_blob_construct.h"
+#include "common/acr/acr_bootstrap.h"
+#include "common/acr/acr_sw_gv11b.h"
+#include "acr_sw_ga10b.h"
+
+#define RECOVERY_UCODE_BLOB_SIZE      (0U)
+#define WPR_OFFSET                    (0U)
+
+#define GSPDBG_RISCV_ACR_FW_MANIFEST  "acr-gsp.manifest.encrypt.bin.out.bin"
+#define GSPDBG_RISCV_ACR_FW_CODE      "acr-gsp.text.encrypt.bin"
+#define GSPDBG_RISCV_ACR_FW_DATA      "acr-gsp.data.encrypt.bin"
+
+#define GSPPROD_RISCV_ACR_FW_MANIFEST "acr-gsp.manifest.encrypt.bin.out.bin.prod"
+#define GSPPROD_RISCV_ACR_FW_CODE     "acr-gsp.text.encrypt.bin.prod"
+#define GSPPROD_RISCV_ACR_FW_DATA     "acr-gsp.data.encrypt.bin.prod"
+
+static int ga10b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr)
+{
+	int err = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	err = nvgpu_acr_bootstrap_hs_ucode_riscv(g, g->acr);
+	if (err != 0) {
+		nvgpu_err(g, "ACR bootstrap failed");
+	}
+
+	return err;
+}
+
+static int ga10b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
+	struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery)
+{
+	int err = 0;
+#ifdef CONFIG_NVGPU_LS_PMU
+	struct nvgpu_mem *ls_pmu_desc = &acr_desc->ls_pmu_desc;
+	struct nvgpu_firmware *fw_desc;
+#endif
+	struct nvgpu_mem *acr_falcon2_sysmem_desc =
+					&acr_desc->acr_falcon2_sysmem_desc;
+	struct flcn2_acr_desc *acr_sysmem_desc = &acr_desc->acr_sysmem_desc;
+
+	nvgpu_log_fn(g, " ");
+
+#ifdef CONFIG_NVGPU_NON_FUSA
+	if (is_recovery) {
+		/*
+		 * In case of recovery ucode blob size is 0 as it has already
+		 * been authenticated during cold boot.
+		 */
+		if (!nvgpu_mem_is_valid(&acr_desc->acr_falcon2_sysmem_desc)) {
+			nvgpu_err(g, "invalid mem acr_falcon2_sysmem_desc");
+			return -EINVAL;
+                }
+		acr_sysmem_desc->nonwpr_ucode_blob_size =
+						RECOVERY_UCODE_BLOB_SIZE;
+	} else
+#endif
+        {
+		/*
+		 * Alloc space for  sys mem space to which interface struct is
+		 * copied.
+		 */
+		if (nvgpu_mem_is_valid(acr_falcon2_sysmem_desc)) {
+			acr_sysmem_desc->nonwpr_ucode_blob_size =
+						RECOVERY_UCODE_BLOB_SIZE;
+			goto load;
+                }
+		err = nvgpu_dma_alloc_flags_sys(g,
+				NVGPU_DMA_PHYSICALLY_ADDRESSED,
+				sizeof(struct flcn2_acr_desc),
+				acr_falcon2_sysmem_desc);
+		if (err != 0) {
+			goto end;
+        	}
+
+#ifdef CONFIG_NVGPU_LS_PMU
+		if(g->support_ls_pmu &&
+			nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
+			err = nvgpu_dma_alloc_flags_sys(g,
+					NVGPU_DMA_PHYSICALLY_ADDRESSED,
+					sizeof(struct falcon_next_core_ucode_desc),
+					ls_pmu_desc);
+			if (err != 0) {
+				goto end;
+			}
+
+			fw_desc = nvgpu_pmu_fw_desc_desc(g, g->pmu);
+
+			nvgpu_mem_wr_n(g, ls_pmu_desc, 0U, fw_desc->data,
+					sizeof(struct falcon_next_core_ucode_desc));
+
+			acr_sysmem_desc->ls_pmu_desc =
+					nvgpu_mem_get_addr(g, ls_pmu_desc);
+		}
+#endif
+		/*
+		 * Start address of non wpr sysmem region holding ucode blob.
+		 */
+		acr_sysmem_desc->nonwpr_ucode_blob_start =
+			nvgpu_mem_get_addr(g, &g->acr->ucode_blob);
+		/*
+		 * LS ucode blob size.
+		 */
+		nvgpu_assert(g->acr->ucode_blob.size <= U32_MAX);
+		acr_sysmem_desc->nonwpr_ucode_blob_size =
+			(u32)g->acr->ucode_blob.size;
+		/*
+		 * Max regions to be used by acr. Cannot be 0U.
+		 */
+		acr_sysmem_desc->regions.no_regions = 1U;
+		/*
+		 * Offset from the WPR region holding the wpr header
+		 */
+		acr_sysmem_desc->wpr_offset = WPR_OFFSET;
+        }
+load:
+	/*
+	 * Push the acr descriptor data to sysmem.
+	 */
+	nvgpu_mem_wr_n(g, acr_falcon2_sysmem_desc, 0U,
+				acr_sysmem_desc,
+					sizeof(struct flcn2_acr_desc));
+
+end:
+	return err;
+}
+
+/* LSF static config functions */
+#ifdef CONFIG_NVGPU_LS_PMU
+static u32 ga10b_acr_lsf_pmu(struct gk20a *g,
+		struct acr_lsf_config *lsf)
+{
+	if (!g->support_ls_pmu) {
+		/* skip adding LS PMU ucode to ACR blob */
+		return 0;
+	}
+
+	/* PMU LS falcon info */
+	lsf->falcon_id = FALCON_ID_PMU;
+	lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
+	lsf->is_lazy_bootstrap = false;
+	lsf->is_priv_load = false;
+	lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details;
+	lsf->get_cmd_line_args_offset = nvgpu_pmu_fw_get_cmd_line_args_offset;
+
+	return BIT32(lsf->falcon_id);
+}
+
+static u32 ga10b_acr_lsf_pmu_next_core(struct gk20a *g,
+		struct acr_lsf_config *lsf)
+{
+	nvgpu_log_fn(g, " ");
+
+	if (!g->support_ls_pmu) {
+		/* skip adding LS PMU ucode to ACR blob */
+		return 0;
+	}
+
+	/* PMU LS falcon info */
+	lsf->falcon_id = FALCON_ID_PMU_NEXT_CORE;
+	lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
+	lsf->is_lazy_bootstrap = false;
+	lsf->is_priv_load = false;
+	lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ncore_ucode_details;
+	lsf->get_cmd_line_args_offset = NULL;
+
+	return BIT32(lsf->falcon_id);
+}
+#endif
+
+/* LSF init */
+static u32 ga10b_acr_lsf_fecs(struct gk20a *g,
+		struct acr_lsf_config *lsf)
+{
+	/* FECS LS falcon info */
+	lsf->falcon_id = FALCON_ID_FECS;
+	lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
+
+	/*
+	 * Lazy bootstrap is a secure iGPU feature where LS falcons(FECS and
+	 * GPCCS) are bootstrapped by LSPMU in both cold boot and recovery boot.
+	 * As there is no ACR running after boot, we need LSPMU to bootstrap LS
+	 * falcons to support recovery.
+	 * In absence of LSPMU, ACR will bootstrap LS falcons but recovery is
+	 * not supported.
+	 */
+	lsf->is_lazy_bootstrap = g->support_ls_pmu ? true : false;
+
+	lsf->is_priv_load = false;
+	lsf->get_lsf_ucode_details = nvgpu_acr_lsf_fecs_ucode_details;
+	lsf->get_cmd_line_args_offset = NULL;
+
+	return BIT32(lsf->falcon_id);
+}
+
+static u32 ga10b_acr_lsf_gpccs(struct gk20a *g,
+		struct acr_lsf_config *lsf)
+{
+	/* GPCCS LS falcon info */
+	lsf->falcon_id = FALCON_ID_GPCCS;
+
+	/*
+	 * Lazy bootstrap is a secure iGPU feature where LS falcons(FECS and
+	 * GPCCS) are bootstrapped by LSPMU in both cold boot and recovery boot.
+	 * As there is no ACR running after boot, we need LSPMU to bootstrap LS
+	 * falcons to support recovery.
+	 * In absence of LSPMU, ACR will bootstrap LS falcons but recovery is
+	 * not supported.
+	 */
+	lsf->is_lazy_bootstrap = g->support_ls_pmu ? true : false;
+
+	lsf->is_priv_load = true;
+	lsf->get_lsf_ucode_details = nvgpu_acr_lsf_gpccs_ucode_details;
+	lsf->get_cmd_line_args_offset = NULL;
+
+	return BIT32(lsf->falcon_id);
+}
+
+static u32 ga10b_acr_lsf_config(struct gk20a *g,
+	struct nvgpu_acr *acr)
+{
+	u32 lsf_enable_mask = 0U;
+#ifdef CONFIG_NVGPU_LS_PMU
+	if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
+		lsf_enable_mask |= ga10b_acr_lsf_pmu_next_core(g,
+				&acr->lsf[FALCON_ID_PMU_NEXT_CORE]);
+	} else {
+		lsf_enable_mask |= ga10b_acr_lsf_pmu(g, &acr->lsf[FALCON_ID_PMU]);
+	}
+#endif
+	lsf_enable_mask |= ga10b_acr_lsf_fecs(g, &acr->lsf[FALCON_ID_FECS]);
+	lsf_enable_mask |= ga10b_acr_lsf_gpccs(g, &acr->lsf[FALCON_ID_GPCCS]);
+
+	return lsf_enable_mask;
+}
+
+static void ga10b_acr_default_sw_init(struct gk20a *g, struct hs_acr *riscv_hs)
+{
+	nvgpu_log_fn(g, " ");
+
+	riscv_hs->acr_type = ACR_DEFAULT;
+
+	if (g->ops.pmu.is_debug_mode_enabled(g)) {
+		riscv_hs->acr_code_name = GSPDBG_RISCV_ACR_FW_CODE;
+		riscv_hs->acr_data_name = GSPDBG_RISCV_ACR_FW_DATA;
+		riscv_hs->acr_manifest_name = GSPDBG_RISCV_ACR_FW_MANIFEST;
+	} else {
+		riscv_hs->acr_code_name = GSPPROD_RISCV_ACR_FW_CODE;
+		riscv_hs->acr_data_name = GSPPROD_RISCV_ACR_FW_DATA;
+		riscv_hs->acr_manifest_name = GSPPROD_RISCV_ACR_FW_MANIFEST;
+	}
+
+	riscv_hs->acr_flcn = &g->gsp_flcn;
+	riscv_hs->report_acr_engine_bus_err_status =
+		nvgpu_pmu_report_bar0_pri_err_status;
+	riscv_hs->acr_engine_bus_err_status =
+		g->ops.pmu.bar0_error_status;
+	riscv_hs->acr_validate_mem_integrity = g->ops.pmu.validate_mem_integrity;
+}
+
+static void ga10b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
+{
+	nvgpu_log_fn(g, " ");
+
+	acr->g = g;
+
+	acr->bootstrap_owner = FALCON_ID_GSPLITE;
+
+	acr->lsf_enable_mask = ga10b_acr_lsf_config(g, acr);
+
+	ga10b_acr_default_sw_init(g, &acr->acr_asc);
+
+	acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob;
+	acr->get_wpr_info = nvgpu_acr_wpr_info_sys;
+	acr->alloc_blob_space = nvgpu_acr_alloc_blob_space_sys;
+	acr->bootstrap_hs_acr = ga10b_bootstrap_hs_acr;
+	acr->patch_wpr_info_to_ucode = ga10b_acr_patch_wpr_info_to_ucode;
+}
+
+extern void nvgpu_next_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
+{
+	nvgpu_log_fn(g, " ");
+	acr->g = g;
+
+#ifdef CONFIG_NVGPU_NON_FUSA
+	if (nvgpu_falcon_is_falcon2_enabled(&g->gsp_flcn)) {
+		nvgpu_set_enabled(g, NVGPU_ACR_NEXT_CORE_ENABLED, true);
+	}
+#else
+	if (nvgpu_falcon_is_falcon2_enabled(&g->pmu_flcn)) {
+		/*
+		 * ACR will be booting on PMU engine so need changes
+		 * in ACR unit
+		 */
+		nvgpu_set_enabled(g, NVGPU_ACR_NEXT_CORE_ENABLED, true);
+	}
+#endif
+
+	/* TODO: Make it generic for PMU/GSP */
+	if (nvgpu_is_enabled(g, NVGPU_ACR_NEXT_CORE_ENABLED)) {
+		nvgpu_info(g, "Booting RISCV core in Peregrine");
+		ga10b_acr_sw_init(g, acr);
+	} else {
+		nvgpu_info(g, "Booting Falcon core in Peregrine");
+		nvgpu_gv11b_acr_sw_init(g, g->acr);
+		acr->lsf_enable_mask = ga10b_acr_lsf_config(g, acr);
+	}
+}
diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.h b/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.h
new file mode 100644
index 000000000..84f4e16e0
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef ACR_SW_GA10B_H
+#define ACR_SW_GA10B_H
+
+struct gk20a;
+struct nvgpu_acr;
+
+void nvgpu_next_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
+
+#endif /*ACR_SW_GA10B_H*/
diff --git a/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.c b/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.c
new file mode 100644
index 000000000..11268015c
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/dma.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/firmware.h>
+#include <nvgpu/riscv.h>
+#include <nvgpu/pmu.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/acr.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/io.h>
+
+#include "common/acr/acr_bootstrap.h"
+#include "common/acr/acr_priv.h"
+
+#define RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS   10000 /*in msec */
+#define RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS       100   /*in msec */
+
+static void ga10b_riscv_release_firmware(struct gk20a *g, struct nvgpu_acr *acr)
+{
+        nvgpu_release_firmware(g, acr->acr_asc.manifest_fw);
+        nvgpu_release_firmware(g, acr->acr_asc.code_fw);
+        nvgpu_release_firmware(g, acr->acr_asc.data_fw);
+}
+
+static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr)
+{
+	int err = 0;
+
+	acr->manifest_fw = nvgpu_request_firmware(g,
+					acr->acr_manifest_name,
+					NVGPU_REQUEST_FIRMWARE_NO_WARN);
+	if (acr->manifest_fw == NULL) {
+		nvgpu_err(g, "%s ucode get fail for %s",
+			acr->acr_manifest_name, g->name);
+		return -ENOENT;
+	}
+
+	acr->code_fw = nvgpu_request_firmware(g,
+					acr->acr_code_name,
+					NVGPU_REQUEST_FIRMWARE_NO_WARN);
+	if (acr->code_fw == NULL) {
+		nvgpu_err(g, "%s ucode get fail for %s",
+			acr->acr_code_name, g->name);
+		nvgpu_release_firmware(g, acr->manifest_fw);
+		return -ENOENT;
+	}
+
+	acr->data_fw = nvgpu_request_firmware(g,
+					acr->acr_data_name,
+					NVGPU_REQUEST_FIRMWARE_NO_WARN);
+	if (acr->data_fw == NULL) {
+		nvgpu_err(g, "%s ucode get fail for %s",
+			acr->acr_data_name, g->name);
+		nvgpu_release_firmware(g, acr->manifest_fw);
+		nvgpu_release_firmware(g, acr->code_fw);
+		return -ENOENT;
+	}
+
+	return err;
+}
+
+static bool nvgpu_acr_wait_for_riscv_brom_completion(struct nvgpu_falcon *flcn,
+						signed int timeoutms)
+{
+	u32 reg = 0;
+
+	do {
+		reg = flcn->g->ops.falcon.get_brom_retcode(flcn);
+		if (flcn->g->ops.falcon.check_brom_passed(reg)) {
+			break;
+		}
+
+		if (timeoutms <= 0) {
+			return false;
+		}
+
+		nvgpu_msleep(10);
+                timeoutms -= 10;
+
+	} while (true);
+
+    return true;
+}
+
+int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr)
+{
+	int err = 0;
+	bool brom_complete = false;
+	u32 timeout = 0;
+	u64 acr_sysmem_desc_addr = 0LL;
+
+	err = ga10b_load_riscv_acr_ucodes(g, &acr->acr_asc);
+	if (err !=0) {
+		nvgpu_err(g, "RISCV ucode loading failed");
+		return -EINVAL;
+	}
+
+	err = acr->patch_wpr_info_to_ucode(g, acr, &acr->acr_asc, false);
+	if (err != 0) {
+		nvgpu_err(g, "RISCV ucode patch wpr info failed");
+		return err;
+	}
+
+	acr_sysmem_desc_addr = nvgpu_mem_get_addr(g,
+				&acr->acr_asc.acr_falcon2_sysmem_desc);
+
+	nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn);
+
+	nvgpu_riscv_hs_ucode_load_bootstrap(acr->acr_asc.acr_flcn,
+						acr->acr_asc.manifest_fw,
+						acr->acr_asc.code_fw,
+						acr->acr_asc.data_fw,
+						acr_sysmem_desc_addr);
+
+	if (nvgpu_platform_is_silicon(g)) {
+		timeout = RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS;
+	} else {
+		timeout = RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS;
+	}
+	brom_complete = nvgpu_acr_wait_for_riscv_brom_completion(
+			acr->acr_asc.acr_flcn, timeout);
+
+	nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn);
+
+	if (brom_complete == false) {
+		nvgpu_err(g, "RISCV BROM timed out, limit: %d ms", timeout);
+		err = -ETIMEDOUT;
+	} else {
+		nvgpu_info(g, "RISCV BROM passed");
+	}
+
+	/* wait for complete & halt */
+	if (nvgpu_platform_is_silicon(g)) {
+		timeout = ACR_COMPLETION_TIMEOUT_SILICON_MS;
+	} else {
+		timeout = ACR_COMPLETION_TIMEOUT_NON_SILICON_MS;
+	}
+	err = nvgpu_acr_wait_for_completion(g, &acr->acr_asc, timeout);
+
+	ga10b_riscv_release_firmware(g, acr);
+
+	return err;
+}
diff --git a/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.h b/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.h
new file mode 100644
index 000000000..747773194
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_ACR_BOOTSTRAP_H
+#define NVGPU_NEXT_ACR_BOOTSTRAP_H
+
+struct gk20a;
+struct nvgpu_acr;
+struct hs_acr;
+
+int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr);
+
+#endif /* NVGPU_NEXT_ACR_BOOTSTRAP_H */
diff --git a/drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c b/drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c
new file mode 100644
index 000000000..9dfeec9be
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c
@@ -0,0 +1,92 @@
+/*
+ *
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/lock.h>
+#include <nvgpu/cic.h>
+
+void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
+		u32 num_entries)
+{
+	unsigned long flags = 0;
+	u32 i = 0U;
+	struct nvgpu_intr_unit_info *intr_unit_info;
+
+	nvgpu_assert(num_entries <= NVGPU_CIC_INTR_VECTORID_SIZE_MAX);
+
+	nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries);
+
+	intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
+
+	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
+
+	if (intr_unit_info[unit].valid == false) {
+		for (i = 0U; i < num_entries; i++) {
+			nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i,
+					*(vectorid + i));
+			intr_unit_info[unit].vectorid[i] = *(vectorid + i);
+		}
+		intr_unit_info[unit].vectorid_size = num_entries;
+	}
+	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+}
+
+bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
+{
+	struct nvgpu_intr_unit_info *intr_unit_info;
+	bool info_valid = false;
+
+	if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
+		nvgpu_err(g, "invalid unit(%d)", unit);
+		return false;
+	}
+
+	intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
+
+	if (intr_unit_info[unit].valid == true) {
+		info_valid = true;
+	}
+
+	return info_valid;
+}
+
+bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
+		u64 *subtree_mask)
+{
+	if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
+		nvgpu_err(g, "invalid unit(%d)", unit);
+		return false;
+	}
+	if (nvgpu_cic_intr_is_unit_info_valid(g, unit) != true) {
+		if (g->ops.mc.intr_get_unit_info(g, unit) != true) {
+			nvgpu_err(g, "failed to fetch info for unit(%d)", unit);
+			return false;
+		}
+	}
+	*subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree;
+	*subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask;
+	nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)",
+			*subtree, *subtree_mask);
+
+	return true;
+}
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c b/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c
new file mode 100644
index 000000000..98c22efee
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <nvgpu/gk20a.h>
+#include <nvgpu/falcon.h>
+
+#include "common/falcon/falcon_sw_gk20a.h"
+#include "common/falcon/falcon_sw_ga10b.h"
+
+static void check_and_enable_falcon2(struct nvgpu_falcon *flcn,
+		unsigned long *fuse_settings)
+{
+	struct gk20a *g = flcn->g;
+	bool is_falcon_enabled = false;
+	bool is_falcon2_enabled = false;
+	int err = 0;
+
+	nvgpu_info(g, "Fetch FUSE settings for FALCON - %d *", flcn->flcn_id);
+
+	err = g->ops.fuse.fetch_falcon_fuse_settings(g, flcn->flcn_id,
+			fuse_settings);
+	if (err != 0) {
+		nvgpu_err(g, "Failed to fetch fuse settings for Falcon %d",
+				flcn->flcn_id);
+		/*  setting default to FALCON until bring-up */
+		nvgpu_err(g, " setting default to Falcon");
+		flcn->is_falcon2_enabled = false;
+		return;
+	}
+
+	nvgpu_info(g, "fuse_settings -  %lx", *fuse_settings);
+
+	is_falcon_enabled =
+		(!(nvgpu_falcon_is_feature_supported(flcn, FCD)) &&
+		!nvgpu_falcon_is_feature_supported(flcn, DCS));
+
+	is_falcon2_enabled = !is_falcon_enabled &&
+		nvgpu_falcon_is_feature_supported(flcn, DCS);
+
+	/* select the FALCON/RISCV core based on fuse */
+	if (!is_falcon_enabled && !is_falcon2_enabled) {
+		nvgpu_err(g, "Invalid fuse combination, both core disabled");
+		nvgpu_err(g, "Further execution will try on FALCON core");
+		flcn->is_falcon2_enabled = false;
+	} else if (is_falcon_enabled && !is_falcon2_enabled) {
+		nvgpu_info(g, "FALCON is enabled");
+		/* FALCON is enabled*/
+		flcn->is_falcon2_enabled = false;
+	} else {
+		nvgpu_info(g, "FALCON/RISCV can be enabled, default RISCV is enabled");
+		flcn->is_falcon2_enabled = true;
+	}
+
+	if (flcn->is_falcon2_enabled) {
+		if (nvgpu_falcon_is_feature_supported(flcn,
+				NVRISCV_BRE_EN)) {
+			nvgpu_info(g, "BRE info enabled");
+		} else {
+			nvgpu_info(g, "BRE info not enabled");
+		}
+
+		if (nvgpu_falcon_is_feature_supported(flcn, NVRISCV_DEVD)) {
+			nvgpu_info(g, "DevD");
+		} else {
+			nvgpu_info(g, "DevE");
+		}
+
+		if (nvgpu_falcon_is_feature_supported(flcn,
+			NVRISCV_PLD)) {
+			nvgpu_info(g, "PL request disabled");
+		} else {
+			nvgpu_info(g, "PL request enabled");
+		}
+
+		if (nvgpu_falcon_is_feature_supported(flcn, NVRISCV_SEN)) {
+			nvgpu_info(g, "S enabled");
+
+			if (nvgpu_falcon_is_feature_supported(flcn,
+				NVRISCV_SA)) {
+				nvgpu_info(g, "assert enabled");
+			} else {
+				nvgpu_info(g, "assert disabled");
+			}
+
+			if (nvgpu_falcon_is_feature_supported(flcn,
+				NVRISCV_SH)) {
+				nvgpu_info(g, "HALT enabled");
+			} else {
+				nvgpu_info(g, "HALT disabled");
+			}
+
+			if (nvgpu_falcon_is_feature_supported(flcn,
+				NVRISCV_SI)) {
+				nvgpu_info(g, "interrupt enabled");
+			} else {
+				nvgpu_info(g, "interrupt disabled");
+			}
+		} else {
+			nvgpu_info(g, "S not enabled");
+		}
+	}
+}
+
+extern void nvgpu_next_falcon_sw_init(struct nvgpu_falcon *flcn)
+{
+	struct gk20a *g = flcn->g;
+
+	switch (flcn->flcn_id) {
+	case FALCON_ID_PMU:
+		flcn->flcn_base = g->ops.pmu.falcon_base_addr();
+		flcn->flcn2_base = g->ops.pmu.falcon2_base_addr();
+		flcn->is_falcon_supported = true;
+		flcn->is_interrupt_enabled = true;
+
+		check_and_enable_falcon2(flcn, &flcn->fuse_settings);
+		break;
+	case FALCON_ID_GSPLITE:
+		flcn->flcn_base = g->ops.gsp.falcon_base_addr();
+		flcn->flcn2_base = g->ops.gsp.falcon2_base_addr();
+		flcn->is_falcon_supported = true;
+		flcn->is_interrupt_enabled = false;
+
+		check_and_enable_falcon2(flcn, &flcn->fuse_settings);
+		break;
+	default:
+		/*
+		 * set false to inherit falcon support
+		 * from previous chips HAL
+		 */
+		flcn->is_falcon_supported = false;
+		break;
+	}
+
+	if (flcn->is_falcon_supported) {
+		gk20a_falcon_engine_dependency_ops(flcn);
+	} else {
+		gk20a_falcon_sw_init(flcn);
+	}
+
+}
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.h b/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.h
new file mode 100644
index 000000000..cafb9713a
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.h
@@ -0,0 +1,28 @@
+
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_FALCON_SW_GA10B_H
+#define NVGPU_FALCON_SW_GA10B_H
+
+void nvgpu_next_falcon_sw_init(struct nvgpu_falcon *flcn);
+
+#endif /* NVGPU_FALCON_SW_GA10B_H */
diff --git a/drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c b/drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c
new file mode 100644
index 000000000..7e9b76c17
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/fb.h>
+
+int nvgpu_fb_vab_init_hal(struct gk20a *g)
+{
+	int err = 0;
+
+	if (g->ops.fb.vab.init != NULL) {
+		err = g->ops.fb.vab.init(g);
+	}
+	return err;
+}
+
+int nvgpu_fb_vab_teardown_hal(struct gk20a *g)
+{
+	int err = 0;
+
+	if (g->ops.fb.vab.teardown != NULL)  {
+		err = g->ops.fb.vab.teardown(g);
+	}
+	return err;
+}
\ No newline at end of file
diff --git a/drivers/gpu/nvgpu/common/fifo/nvgpu_next_engines.c b/drivers/gpu/nvgpu/common/fifo/nvgpu_next_engines.c
new file mode 100644
index 000000000..a7141c027
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/fifo/nvgpu_next_engines.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/device.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/fifo.h>
+
+int nvgpu_next_engine_init_one_dev(struct gk20a *g,
+				   const struct nvgpu_device *dev)
+{
+	struct nvgpu_device *dev_rw = (struct nvgpu_device *)dev;
+
+	/*
+	 * Currently due to the nature of the nvgpu_next repo, this will still
+	 * be called even on non-ga10b systems. Eventually this code will fold into
+	 * the nvgpu-linux repo, at which point this logic will be present in
+	 * nvgpu_engine_init_one_dev().
+	 *
+	 * In any event, the purpose of this is to make sure we _don't_ execute
+	 * this code pre-ga10b. We can check for HALs that only exist on ga10x to
+	 * short circuit.
+	 */
+	if (g->ops.runlist.get_engine_id_from_rleng_id == NULL) {
+		return 0;
+	}
+
+	/*
+	 * Init PBDMA info for this device; needs FIFO to be alive to do this.
+	 * SW expects at least pbdma instance0 to be valid.
+	 *
+	 * See JIRA NVGPU-4980 for multiple pbdma support.
+	 */
+	g->ops.runlist.get_pbdma_info(g,
+				      dev->next.rl_pri_base,
+				      &dev_rw->next.pbdma_info);
+	if (dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0] ==
+	    NVGPU_INVALID_PBDMA_ID) {
+		nvgpu_err(g, "busted pbdma info: no pbdma for engine id:%d",
+			  dev->engine_id);
+		return -EINVAL;
+	}
+
+	dev_rw->pbdma_id = dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0];
+
+	nvgpu_log(g, gpu_dbg_device, "Parsed engine: ID: %u", dev->engine_id);
+	nvgpu_log(g, gpu_dbg_device, "  inst_id %u,  runlist_id: %u,  fault id %u",
+                  dev->inst_id, dev->runlist_id, dev->fault_id);
+	nvgpu_log(g, gpu_dbg_device, "  intr_id %u,  reset_id %u",
+                  dev->intr_id, dev->reset_id);
+	nvgpu_log(g, gpu_dbg_device, "  engine_type %u",
+                  dev->type);
+	nvgpu_log(g, gpu_dbg_device, "  reset_id 0x%08x, rleng_id 0x%x",
+                  dev->reset_id, dev->next.rleng_id);
+	nvgpu_log(g, gpu_dbg_device, "  runlist_pri_base 0x%x",
+		  dev->next.rl_pri_base);
+
+	return 0;
+}
diff --git a/drivers/gpu/nvgpu/common/fifo/nvgpu_next_runlist.c b/drivers/gpu/nvgpu/common/fifo/nvgpu_next_runlist.c
new file mode 100644
index 000000000..6ec71fdba
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/fifo/nvgpu_next_runlist.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/engines.h>
+#include <nvgpu/device.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/pbdma.h>
+#include <nvgpu/gk20a.h>
+
+static void nvgpu_runlist_init_engine_info(struct gk20a *g,
+		struct nvgpu_runlist *runlist,
+		const struct nvgpu_device *dev)
+{
+	u32 i = 0U;
+
+	/*
+	 * runlist_pri_base, chram_bar0_offset and pbdma_info
+	 * will get over-written with same info, if multiple engines
+	 * are present on same runlist. Required optimization will be
+	 * done as part of JIRA NVGPU-4980
+	 */
+	runlist->nvgpu_next.runlist_pri_base =
+			dev->next.rl_pri_base;
+	runlist->nvgpu_next.chram_bar0_offset =
+		g->ops.runlist.get_chram_bar0_offset(g, dev->next.rl_pri_base);
+
+	nvgpu_log(g, gpu_dbg_info, "runlist[%d]: runlist_pri_base 0x%x",
+		runlist->id, runlist->nvgpu_next.runlist_pri_base);
+	nvgpu_log(g, gpu_dbg_info, "runlist[%d]: chram_bar0_offset 0x%x",
+		runlist->id, runlist->nvgpu_next.chram_bar0_offset);
+
+	runlist->nvgpu_next.pbdma_info = &dev->next.pbdma_info;
+	for  (i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) {
+		nvgpu_log(g, gpu_dbg_info,
+			"runlist[%d]: pbdma_id[%d] %d pbdma_pri_base[%d] 0x%x",
+			runlist->id, i,
+			runlist->nvgpu_next.pbdma_info->pbdma_id[i], i,
+			runlist->nvgpu_next.pbdma_info->pbdma_pri_base[i]);
+	}
+
+	runlist->nvgpu_next.rl_dev_list[dev->next.rleng_id] = dev;
+}
+
+static u32 nvgpu_runlist_get_pbdma_mask(struct gk20a *g,
+					struct nvgpu_runlist *runlist)
+{
+	u32 pbdma_mask = 0U;
+	u32 i;
+	u32 pbdma_id;
+
+	nvgpu_assert(runlist != NULL);
+
+	for ( i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) {
+		pbdma_id = runlist->nvgpu_next.pbdma_info->pbdma_id[i];
+		if (pbdma_id != NVGPU_INVALID_PBDMA_ID)
+			pbdma_mask |= BIT32(pbdma_id);
+	}
+	return pbdma_mask;
+}
+
+void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f)
+{
+	struct nvgpu_runlist *runlist;
+	const struct nvgpu_device *dev;
+	u32 i, j;
+
+	nvgpu_log_fn(g, " ");
+
+	if (g->is_virtual) {
+		return;
+	}
+
+	for (i = 0U; i < f->num_runlists; i++) {
+		runlist = &f->active_runlists[i];
+
+		nvgpu_log(g, gpu_dbg_info, "Configuring runlist %u (%u)", runlist->id, i);
+
+		for (j = 0U; j < f->num_engines; j++) {
+			dev = f->active_engines[j];
+
+			if (dev->runlist_id == runlist->id) {
+				runlist->eng_bitmask |= BIT32(dev->engine_id);
+				nvgpu_runlist_init_engine_info(g, runlist, dev);
+			}
+		}
+
+		runlist->pbdma_bitmask = nvgpu_runlist_get_pbdma_mask(g, runlist);
+
+		nvgpu_log(g, gpu_dbg_info, "  Active engine bitmask: 0x%x", runlist->eng_bitmask);
+		nvgpu_log(g, gpu_dbg_info, "          PBDMA bitmask: 0x%x", runlist->pbdma_bitmask);
+	}
+
+	nvgpu_log_fn(g, "done");
+}
diff --git a/drivers/gpu/nvgpu/common/gr/nvgpu_next_fs_state.c b/drivers/gpu/nvgpu/common/gr/nvgpu_next_fs_state.c
new file mode 100644
index 000000000..d756f3ee6
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/gr/nvgpu_next_fs_state.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/static_analysis.h>
+
+#include <nvgpu/gr/config.h>
+#include <nvgpu/gr/nvgpu_next_fs_state.h>
+
+int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config)
+{
+	u32 tpc_index, gpc_index;
+	u32 sm_id = 0;
+	u32 num_sm;
+	int err = 0;
+
+	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
+
+	err = g->ops.gr.config.init_sm_id_table(g, config);
+	if (err != 0) {
+		return err;
+	}
+
+	num_sm = nvgpu_gr_config_get_no_of_sm(config);
+	nvgpu_assert(num_sm > 0U);
+
+	for (sm_id = 0; sm_id < num_sm; sm_id++) {
+		struct nvgpu_sm_info *sm_info =
+			nvgpu_gr_config_get_sm_info(config, sm_id);
+		tpc_index = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
+		gpc_index = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
+
+		g->ops.gr.init.sm_id_numbering(g, gpc_index, tpc_index, sm_id,
+					       config, NULL, false);
+	}
+
+	return err;
+}
diff --git a/drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c b/drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c
new file mode 100644
index 000000000..7595176d9
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/netlist.h>
+#include <nvgpu/io.h>
+
+#include <nvgpu/gr/nvgpu_next_gr.h>
+
+void nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g)
+{
+	u32 i = 0U;
+	struct netlist_av_list *sw_non_ctx_local_compute_load =
+		nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
+#ifdef CONFIG_NVGPU_GRAPHICS
+	struct netlist_av_list *sw_non_ctx_local_gfx_load =
+		nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
+#endif
+
+	for (i = 0U; i < sw_non_ctx_local_compute_load->count; i++) {
+		nvgpu_writel(g, sw_non_ctx_local_compute_load->l[i].addr,
+			sw_non_ctx_local_compute_load->l[i].value);
+	}
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		for (i = 0U; i < sw_non_ctx_local_gfx_load->count; i++) {
+			nvgpu_writel(g, sw_non_ctx_local_gfx_load->l[i].addr,
+				sw_non_ctx_local_gfx_load->l[i].value);
+		}
+	}
+#endif
+
+	return;
+}
+
+void nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g)
+{
+	u32 i = 0U;
+	struct netlist_av_list *sw_non_ctx_global_compute_load =
+		nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
+#ifdef CONFIG_NVGPU_GRAPHICS
+	struct netlist_av_list *sw_non_ctx_global_gfx_load =
+		nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
+#endif
+
+	for (i = 0U; i < sw_non_ctx_global_compute_load->count; i++) {
+		nvgpu_writel(g, sw_non_ctx_global_compute_load->l[i].addr,
+			sw_non_ctx_global_compute_load->l[i].value);
+	}
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		for (i = 0U; i < sw_non_ctx_global_gfx_load->count; i++) {
+			nvgpu_writel(g, sw_non_ctx_global_gfx_load->l[i].addr,
+				sw_non_ctx_global_gfx_load->l[i].value);
+		}
+	}
+#endif
+
+	return;
+}
diff --git a/drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c b/drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c
new file mode 100644
index 000000000..01a242bd5
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c
@@ -0,0 +1,92 @@
+/*
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/lock.h>
+#include <nvgpu/mc.h>
+
+void nvgpu_mc_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
+		u32 num_entries)
+{
+	unsigned long flags = 0;
+	u32 i = 0U;
+	struct nvgpu_intr_unit_info *intr_unit_info;
+
+	nvgpu_assert(num_entries <= MC_INTR_VECTORID_SIZE_MAX);
+
+	nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries);
+
+	intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
+
+	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
+
+	if (intr_unit_info[unit].valid == false) {
+		for (i = 0U; i < num_entries; i++) {
+			nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i,
+					*(vectorid + i));
+			intr_unit_info[unit].vectorid[i] = *(vectorid + i);
+		}
+		intr_unit_info[unit].vectorid_size = num_entries;
+	}
+	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+}
+
+bool nvgpu_mc_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
+{
+	struct nvgpu_intr_unit_info *intr_unit_info;
+	bool info_valid = false;
+
+	if (unit >= MC_INTR_UNIT_MAX) {
+		nvgpu_err(g, "invalid unit(%d)", unit);
+		return false;
+	}
+
+	intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
+
+	if (intr_unit_info[unit].valid == true) {
+		info_valid = true;
+	}
+
+	return info_valid;
+}
+
+bool nvgpu_mc_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
+		u64 *subtree_mask)
+{
+	if (unit >= MC_INTR_UNIT_MAX) {
+		nvgpu_err(g, "invalid unit(%d)", unit);
+		return false;
+	}
+	if (nvgpu_mc_intr_is_unit_info_valid(g, unit) != true) {
+		if (g->ops.mc.intr_get_unit_info(g, unit) != true) {
+			nvgpu_err(g, "failed to fetch info for unit(%d)", unit);
+			return false;
+		}
+	}
+	*subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree;
+	*subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask;
+	nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)",
+			*subtree, *subtree_mask);
+
+	return true;
+}
diff --git a/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist.c b/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist.c
new file mode 100644
index 000000000..534aabb21
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist.c
@@ -0,0 +1,383 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/string.h>
+#include <nvgpu/netlist.h>
+
+#include "common/netlist/netlist_priv.h"
+
+/* Copied from common/netlist/netlist.c */
+static int nvgpu_netlist_alloc_load_av_list(struct gk20a *g, u8 *src, u32 len,
+			struct netlist_av_list *av_list)
+{
+	av_list->count = len / U32(sizeof(struct netlist_av));
+	if (nvgpu_netlist_alloc_av_list(g, av_list) == NULL) {
+		return -ENOMEM;
+	}
+
+	nvgpu_memcpy((u8 *)av_list->l, src, len);
+
+	return 0;
+}
+
+/* Copied from common/netlist/netlist.c */
+static int nvgpu_netlist_alloc_load_aiv_list(struct gk20a *g, u8 *src, u32 len,
+			struct netlist_aiv_list *aiv_list)
+{
+	aiv_list->count = len / U32(sizeof(struct netlist_aiv));
+	if (nvgpu_netlist_alloc_aiv_list(g, aiv_list) == NULL) {
+		return -ENOMEM;
+	}
+
+	nvgpu_memcpy((u8 *)aiv_list->l, src, len);
+
+	return 0;
+}
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g,
+			u32 region_id, u8 *src, u32 size,
+			struct nvgpu_netlist_vars *netlist_vars, int *err_code)
+{
+	int err = 0;
+	bool handled = true;
+
+	switch (region_id) {
+	case NETLIST_REGIONID_CTXREG_SYS_COMPUTE:
+		nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_COMPUTE");
+		err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+			&netlist_vars->ctxsw_regs.nvgpu_next.sys_compute);
+		break;
+	case NETLIST_REGIONID_CTXREG_GPC_COMPUTE:
+		nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_COMPUTE");
+		err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+			&netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute);
+		break;
+	case NETLIST_REGIONID_CTXREG_TPC_COMPUTE:
+		nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_COMPUTE");
+		err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+			&netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute);
+		break;
+	case NETLIST_REGIONID_CTXREG_PPC_COMPUTE:
+		nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_COMPUTE");
+		err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+			&netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute);
+		break;
+	case NETLIST_REGIONID_CTXREG_ETPC_COMPUTE:
+		nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_COMPUTE");
+		err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+			&netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute);
+		break;
+	case NETLIST_REGIONID_CTXREG_LTS_BC:
+		nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_BC");
+		err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+			&netlist_vars->ctxsw_regs.nvgpu_next.lts_bc);
+		break;
+	case NETLIST_REGIONID_CTXREG_LTS_UC:
+		nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_UC");
+		err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+			&netlist_vars->ctxsw_regs.nvgpu_next.lts_uc);
+		break;
+	default:
+		handled = false;
+		break;
+	}
+
+	if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) {
+		handled = true;
+		switch (region_id) {
+#ifdef CONFIG_NVGPU_GRAPHICS
+		case NETLIST_REGIONID_CTXREG_SYS_GFX:
+			nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_GFX");
+			err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+				&netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx);
+			break;
+		case NETLIST_REGIONID_CTXREG_GPC_GFX:
+			nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_GFX");
+			err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+				&netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx);
+			break;
+		case NETLIST_REGIONID_CTXREG_TPC_GFX:
+			nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_GFX");
+			err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+				&netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx);
+			break;
+		case NETLIST_REGIONID_CTXREG_PPC_GFX:
+			nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_GFX");
+			err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+				&netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx);
+			break;
+		case NETLIST_REGIONID_CTXREG_ETPC_GFX:
+			nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_GFX");
+			err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
+				&netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx);
+			break;
+#endif
+		default:
+			handled = false;
+			break;
+		}
+	}
+	*err_code = err;
+
+	return handled;
+}
+
+void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g)
+{
+	struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars;
+
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_compute.l);
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute.l);
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute.l);
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute.l);
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute.l);
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_bc.l);
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_uc.l);
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx.l);
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx.l);
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx.l);
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx.l);
+	nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx.l);
+}
+#endif /* CONFIG_NVGPU_DEBUGGER */
+
+bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g,
+			u32 region_id, u8 *src, u32 size,
+			struct nvgpu_netlist_vars *netlist_vars, int *err_code)
+{
+	int err = 0;
+	bool handled = true;
+
+	switch(region_id) {
+	case NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD:
+		nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD");
+		err = nvgpu_netlist_alloc_load_av_list(g, src, size,
+			&netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load);
+		break;
+	case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD:
+		nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD");
+		err = nvgpu_netlist_alloc_load_av_list(g, src, size,
+			&netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load);
+		break;
+	default:
+		handled = false;
+		break;
+	}
+
+	if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) {
+		handled = true;
+		switch (region_id) {
+#ifdef CONFIG_NVGPU_GRAPHICS
+		case NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD:
+			nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD");
+			err = nvgpu_netlist_alloc_load_av_list(g, src, size,
+				&netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load);
+			break;
+		case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD:
+			nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD");
+			err = nvgpu_netlist_alloc_load_av_list(g, src, size,
+				&netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load);
+			break;
+#endif
+		default:
+			handled = false;
+			break;
+		}
+	}
+	*err_code = err;
+
+	return handled;
+}
+
+void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g)
+{
+	struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars;
+
+	nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load.l);
+	nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load.l);
+#ifdef CONFIG_NVGPU_GRAPHICS
+	nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load.l);
+	nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load.l);
+#endif
+}
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_compute;
+}
+
+struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute;
+}
+
+struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute;
+}
+
+struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute;
+}
+
+struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute;
+}
+
+struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.nvgpu_next.lts_bc;
+}
+
+struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx;
+}
+
+struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx;
+}
+
+struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx;
+}
+
+struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx;
+}
+
+struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx;
+}
+
+u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g)
+{
+	u32 count = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count;
+
+	count = nvgpu_safe_add_u32(count,
+		nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count);
+	return count;
+}
+
+u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g)
+{
+	u32 count = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count;
+
+	count = nvgpu_safe_add_u32(count,
+		nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count);
+	return count;
+}
+
+u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g)
+{
+	u32 count = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count;
+
+	count = nvgpu_safe_add_u32(count,
+		nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count);
+	return count;
+}
+
+u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g)
+{
+	u32 count = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count;
+
+	count = nvgpu_safe_add_u32(count,
+		nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count);
+	return count;
+}
+
+u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g)
+{
+	u32 count = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count;
+
+	count = nvgpu_safe_add_u32(count,
+		nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count);
+	return count;
+}
+
+void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g)
+{
+	nvgpu_log_info(g, "GRCTX_REG_LIST_SYS_(COMPUTE/GRAPICS)_COUNT   :%d %d",
+		nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count,
+		nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count);
+	nvgpu_log_info(g, "GRCTX_REG_LIST_GPC_(COMPUTE/GRAPHICS)_COUNT  :%d %d",
+		nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count,
+		nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count);
+	nvgpu_log_info(g, "GRCTX_REG_LIST_TPC_(COMPUTE/GRAPHICS)_COUNT  :%d %d",
+		nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count,
+		nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count);
+	nvgpu_log_info(g, "GRCTX_REG_LIST_PPC_(COMPUTE/GRAHPICS)_COUNT  :%d %d",
+		nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count,
+		nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count);
+	nvgpu_log_info(g, "GRCTX_REG_LIST_ETPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
+		nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count,
+		nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count);
+	nvgpu_log_info(g, "GRCTX_REG_LIST_LTS_BC_COUNT                  :%d",
+		nvgpu_next_netlist_get_lts_ctxsw_regs(g)->count);
+}
+#endif /* CONFIG_NVGPU_DEBUGGER */
+
+struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load;
+}
+
+struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load;
+}
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load;
+}
+
+struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(
+							struct gk20a *g)
+{
+	return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load;
+}
+#endif /* CONFIG_NVGPU_GRAPHICS */
diff --git a/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist_priv.h b/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist_priv.h
new file mode 100644
index 000000000..cee5ae83f
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist_priv.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_NETLIST_PRIV_H
+#define NVGPU_NEXT_NETLIST_PRIV_H
+
+/**
+ * @file
+ *
+ * Declare netlist_vars specific struct and defines.
+ */
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct netlist_av_list;
+struct netlist_aiv_list;
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+#define NETLIST_REGIONID_CTXREG_SYS_COMPUTE		36
+#define NETLIST_REGIONID_CTXREG_GPC_COMPUTE		38
+#define NETLIST_REGIONID_CTXREG_TPC_COMPUTE		40
+#define NETLIST_REGIONID_CTXREG_PPC_COMPUTE		42
+#define NETLIST_REGIONID_CTXREG_ETPC_COMPUTE		44
+#ifdef CONFIG_NVGPU_GRAPHICS
+#define NETLIST_REGIONID_CTXREG_SYS_GFX			37
+#define NETLIST_REGIONID_CTXREG_GPC_GFX			39
+#define NETLIST_REGIONID_CTXREG_TPC_GFX			41
+#define NETLIST_REGIONID_CTXREG_PPC_GFX			43
+#define NETLIST_REGIONID_CTXREG_ETPC_GFX		45
+#endif  /* CONFIG_NVGPU_GRAPHICS */
+#endif /* CONFIG_NVGPU_DEBUGGER */
+
+#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD	48
+#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD	50
+#ifdef CONFIG_NVGPU_GRAPHICS
+#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD	49
+#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD	51
+#endif  /* CONFIG_NVGPU_GRAPHICS */
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+#define NETLIST_REGIONID_CTXREG_LTS_BC			57
+#define NETLIST_REGIONID_CTXREG_LTS_UC			58
+#endif /* CONFIG_DEBUGGER */
+
+struct nvgpu_next_netlist_vars {
+	struct netlist_av_list  sw_non_ctx_local_compute_load;
+	struct netlist_av_list  sw_non_ctx_global_compute_load;
+#ifdef CONFIG_NVGPU_GRAPHICS
+	struct netlist_av_list  sw_non_ctx_local_gfx_load;
+	struct netlist_av_list  sw_non_ctx_global_gfx_load;
+#endif  /* CONFIG_NVGPU_GRAPHICS */
+};
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+struct nvgpu_next_ctxsw_regs {
+	struct netlist_aiv_list sys_compute;
+	struct netlist_aiv_list gpc_compute;
+	struct netlist_aiv_list tpc_compute;
+	struct netlist_aiv_list ppc_compute;
+	struct netlist_aiv_list etpc_compute;
+	struct netlist_aiv_list lts_bc;
+	struct netlist_aiv_list lts_uc;
+#ifdef CONFIG_NVGPU_GRAPHICS
+	struct netlist_aiv_list sys_gfx;
+	struct netlist_aiv_list gpc_gfx;
+	struct netlist_aiv_list tpc_gfx;
+	struct netlist_aiv_list ppc_gfx;
+	struct netlist_aiv_list etpc_gfx;
+#endif /* CONFIG_NVGPU_GRAPHICS */
+};
+#endif /* CONFIG_NVGPU_DEBUGGER */
+
+#endif /* NVGPU_NEXT_NETLIST_PRIV_H */
diff --git a/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.c b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.c
new file mode 100644
index 000000000..e5c234801
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/pmu/pmu_perfmon.h>
+#include <nvgpu/log.h>
+
+#include "pmu_perfmon_sw_ga10b.h"
+
+void nvgpu_next_perfmon_sw_init(struct gk20a *g,
+		struct nvgpu_pmu_perfmon *perfmon)
+{
+	nvgpu_log_fn(g, " ");
+
+	perfmon->init_perfmon = nvgpu_pmu_init_perfmon_rpc;
+	perfmon->start_sampling = nvgpu_pmu_perfmon_start_sampling_rpc;
+	perfmon->stop_sampling = nvgpu_pmu_perfmon_stop_sampling_rpc;
+	perfmon->get_samples_rpc = nvgpu_pmu_perfmon_get_samples_rpc;
+	perfmon->perfmon_event_handler = nvgpu_pmu_handle_perfmon_event_rpc;
+}
diff --git a/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.h b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.h
new file mode 100644
index 000000000..238a256fc
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_PERFMON_SW_GA10B_H
+#define NVGPU_PMU_PERFMON_SW_GA10B_H
+
+void nvgpu_next_perfmon_sw_init(struct gk20a *g,
+		struct nvgpu_pmu_perfmon *perfmon);
+
+#endif /* NVGPU_PMU_PERFMON_SW_GA10B_H */
diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c
new file mode 100644
index 000000000..b3db96c1b
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/pmu.h>
+#include <nvgpu/pmu/pmu_pg.h>
+#include <nvgpu/pmu/pmuif/pg.h>
+#include <nvgpu/pmu/cmd.h>
+
+#include "common/pmu/pg/pmu_pg.h"
+#include "common/pmu/pg/pg_sw_gp106.h"
+#include "common/pmu/pg/pg_sw_gm20b.h"
+#include "common/pmu/pg/pg_sw_gv11b.h"
+#include "pg_sw_ga10b.h"
+
+u32 ga10b_pmu_pg_engines_list(struct gk20a *g)
+{
+	return nvgpu_is_enabled(g, NVGPU_ELPG_MS_ENABLED) ?
+		(BIT32(PMU_PG_ELPG_ENGINE_ID_GRAPHICS) |
+			BIT32(PMU_PG_ELPG_ENGINE_ID_MS_LTC)) :
+		(BIT32(PMU_PG_ELPG_ENGINE_ID_GRAPHICS));
+}
+
+static int ga10b_pmu_pg_pre_init(struct gk20a *g, struct nvgpu_pmu *pmu)
+{
+	struct pmu_rpc_struct_lpwr_loading_pre_init rpc;
+	int status;
+	u32 idx;
+
+	nvgpu_log_fn(g, " ");
+
+	(void) memset(&rpc, 0,
+		sizeof(struct pmu_rpc_struct_lpwr_loading_pre_init));
+
+	rpc.arch_sf_support_mask = NV_PMU_ARCH_FEATURE_SUPPORT_MASK;
+	rpc.base_period_ms = NV_PMU_BASE_SAMPLING_PERIOD_MS;
+	rpc.b_no_pstate_vbios = true;
+
+	/* Initialize LPWR GR and MS grp data for GRAPHICS and MS_LTC engine */
+	for (idx = 0; idx < NV_PMU_LPWR_GRP_CTRL_ID__COUNT; idx++)
+	{
+		if (idx == NV_PMU_LPWR_GRP_CTRL_ID_GR) {
+			rpc.grp_ctrl_mask[idx] =
+				BIT(PMU_PG_ELPG_ENGINE_ID_GRAPHICS);
+		}
+
+		if (nvgpu_is_enabled(g, NVGPU_ELPG_MS_ENABLED)) {
+			if (idx == NV_PMU_LPWR_GRP_CTRL_ID_MS) {
+				rpc.grp_ctrl_mask[idx] =
+					BIT(PMU_PG_ELPG_ENGINE_ID_MS_LTC);
+			}
+		}
+	}
+
+	PMU_RPC_EXECUTE_CPB(status, pmu, PG_LOADING, PRE_INIT, &rpc, 0);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute RPC status=0x%x", status);
+	}
+
+	return status;
+}
+
+static int ga10b_pmu_pg_init(struct gk20a *g, struct nvgpu_pmu *pmu,
+		u8 pg_engine_id)
+{
+	struct pmu_rpc_struct_lpwr_loading_pg_ctrl_init rpc;
+	int status;
+
+	nvgpu_log_fn(g, " ");
+
+	/* init ELPG */
+	(void) memset(&rpc, 0,
+			sizeof(struct pmu_rpc_struct_lpwr_loading_pg_ctrl_init));
+	rpc.ctrl_id = (u32)pg_engine_id;
+	rpc.support_mask = NV_PMU_SUB_FEATURE_SUPPORT_MASK;
+
+	PMU_RPC_EXECUTE_CPB(status, pmu, PG_LOADING, INIT, &rpc, 0);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute RPC status=0x%x",
+			status);
+	}
+
+	/* Update Stats Dmem offset for reading statistics info */
+	pmu->pg->stat_dmem_offset[pg_engine_id] = rpc.stats_dmem_offset;
+
+	return status;
+}
+
+static int ga10b_pmu_pg_allow(struct gk20a *g, struct nvgpu_pmu *pmu,
+		u8 pg_engine_id)
+{
+	struct pmu_rpc_struct_lpwr_pg_ctrl_allow rpc;
+	int status;
+
+	nvgpu_log_fn(g, " ");
+
+	(void) memset(&rpc, 0,
+		sizeof(struct pmu_rpc_struct_lpwr_pg_ctrl_allow));
+	rpc.ctrl_id = (u32)pg_engine_id;
+
+	PMU_RPC_EXECUTE_CPB(status, pmu, PG, ALLOW, &rpc, 0);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute RPC status=0x%x",
+			status);
+		return status;
+	}
+
+	return status;
+}
+
+static int ga10b_pmu_pg_disallow(struct gk20a *g, struct nvgpu_pmu *pmu,
+		u8 pg_engine_id)
+{
+	struct pmu_rpc_struct_lpwr_pg_ctrl_disallow rpc;
+	int status;
+
+	nvgpu_log_fn(g, " ");
+
+	(void) memset(&rpc, 0,
+		sizeof(struct pmu_rpc_struct_lpwr_pg_ctrl_disallow));
+	rpc.ctrl_id = (u32)pg_engine_id;
+
+	PMU_RPC_EXECUTE_CPB(status, pmu, PG, DISALLOW, &rpc, 0);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute RPC status=0x%x",
+			status);
+	}
+
+	return status;
+}
+
+static int ga10b_pmu_pg_threshold_update(struct gk20a *g,
+		struct nvgpu_pmu *pmu, u8 pg_engine_id)
+{
+	struct pmu_rpc_struct_lpwr_pg_ctrl_threshold_update rpc;
+	int status;
+
+	nvgpu_log_fn(g, " ");
+
+	(void) memset(&rpc, 0,
+		sizeof(struct pmu_rpc_struct_lpwr_pg_ctrl_threshold_update));
+	rpc.ctrl_id = (u32)pg_engine_id;
+
+#ifdef CONFIG_NVGPU_SIM
+	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
+		rpc.threshold_cycles.idle = PMU_PG_IDLE_THRESHOLD_SIM;
+		rpc.threshold_cycles.ppu = PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM;
+	} else
+#endif
+	{
+		rpc.threshold_cycles.idle = PMU_PG_IDLE_THRESHOLD;
+		rpc.threshold_cycles.ppu = PMU_PG_POST_POWERUP_IDLE_THRESHOLD;
+	}
+
+	PMU_RPC_EXECUTE_CPB(status, pmu, PG, THRESHOLD_UPDATE, &rpc, 0);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute RPC status=0x%x",
+			status);
+	}
+
+	return status;
+}
+
+static int ga10b_pmu_pg_sfm_update(struct gk20a *g,
+		struct nvgpu_pmu *pmu, u8 pg_engine_id)
+{
+	struct pmu_rpc_struct_lpwr_pg_ctrl_sfm_update rpc;
+	int status;
+
+	nvgpu_log_fn(g, " ");
+
+	(void) memset(&rpc, 0,
+		sizeof(struct pmu_rpc_struct_lpwr_pg_ctrl_sfm_update));
+	rpc.ctrl_id = (u32)pg_engine_id;
+	rpc.enabled_mask = NV_PMU_SUB_FEATURE_SUPPORT_MASK;
+
+	PMU_RPC_EXECUTE_CPB(status, pmu, PG, SFM_UPDATE, &rpc, 0);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute RPC status=0x%x",
+			status);
+	}
+
+	return status;
+}
+
+static int ga10b_pmu_pg_post_init(struct gk20a *g,struct nvgpu_pmu *pmu)
+{
+	struct pmu_rpc_struct_lpwr_loading_post_init rpc;
+	int status;
+
+	nvgpu_log_fn(g, " ");
+
+	(void) memset(&rpc, 0,
+			sizeof(struct pmu_rpc_struct_lpwr_loading_post_init));
+
+	PMU_RPC_EXECUTE_CPB(status, pmu, PG_LOADING, POST_INIT, &rpc, 0);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute RPC status=0x%x", status);
+	}
+
+	return status;
+}
+
+static int ga10b_pmu_pg_init_send(struct gk20a *g,
+		struct nvgpu_pmu *pmu, u8 pg_engine_id)
+{
+	int status;
+
+	nvgpu_log_fn(g, " ");
+
+	status = ga10b_pmu_pg_pre_init(g, pmu);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute PG_PRE_INIT RPC");
+		return status;
+	}
+
+	status = ga10b_pmu_pg_init(g, pmu, pg_engine_id);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute PG_INIT RPC");
+		return status;
+	}
+
+	status = ga10b_pmu_pg_threshold_update(g, pmu, pg_engine_id);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute PG_THRESHOLD_UPDATE RPC");
+		return status;
+	}
+
+	status = ga10b_pmu_pg_sfm_update(g, pmu, pg_engine_id);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute PG_SFM_UPDATE RPC");
+		return status;
+	}
+
+	status = ga10b_pmu_pg_post_init(g, pmu);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute PG_POST_INIT RPC");
+		return status;
+	}
+
+	return status;
+}
+
+static int ga10b_pmu_pg_load_buff(struct gk20a *g, struct nvgpu_pmu *pmu)
+{
+	struct pmu_rpc_struct_lpwr_loading_pg_ctrl_buf_load rpc;
+	u32 gr_engine_id;
+	int status;
+
+	nvgpu_log_fn(g, " ");
+
+	gr_engine_id = nvgpu_engine_get_gr_id(g);
+
+	(void) memset(&rpc, 0,
+		sizeof(struct pmu_rpc_struct_lpwr_loading_pg_ctrl_buf_load));
+	rpc.ctrl_id = nvgpu_safe_cast_u32_to_u8(gr_engine_id);
+	rpc.buf_idx = PMU_PGENG_GR_BUFFER_IDX_FECS;
+	rpc.dma_desc.params = (pmu->pg->pg_buf.size & 0xFFFFFFU);
+	rpc.dma_desc.params |= (U32(PMU_DMAIDX_VIRT) << U32(24));
+	rpc.dma_desc.address.lo = u64_lo32(pmu->pg->pg_buf.gpu_va);
+	rpc.dma_desc.address.hi = u64_hi32(pmu->pg->pg_buf.gpu_va);
+
+	pmu->pg->buf_loaded = false;
+
+	PMU_RPC_EXECUTE_CPB(status, pmu, PG_LOADING, BUF_LOAD, &rpc, 0);
+	if (status != 0) {
+		nvgpu_err(g, "Failed to execute RPC status=0x%x",
+			status);
+		return status;
+	}
+
+	return status;
+}
+
+static void ga10b_pg_rpc_handler(struct gk20a *g, struct nvgpu_pmu *pmu,
+		struct nv_pmu_rpc_header *rpc)
+{
+	nvgpu_log_fn(g, " ");
+
+	switch (rpc->function) {
+	case NV_PMU_RPC_ID_PG_LOADING_PRE_INIT:
+		nvgpu_pmu_dbg(g, "Reply to PG_PRE_INIT");
+		break;
+	case NV_PMU_RPC_ID_PG_LOADING_POST_INIT:
+		nvgpu_pmu_dbg(g, "Reply to PG_POST_INIT");
+		break;
+	case NV_PMU_RPC_ID_PG_LOADING_INIT:
+		nvgpu_pmu_dbg(g, "Reply to PG_INIT");
+		break;
+	case NV_PMU_RPC_ID_PG_THRESHOLD_UPDATE:
+		nvgpu_pmu_dbg(g, "Reply to PG_THRESHOLD_UPDATE");
+		break;
+	case NV_PMU_RPC_ID_PG_SFM_UPDATE:
+		nvgpu_pmu_dbg(g, "Reply to PG_SFM_UPDATE");
+		nvgpu_pmu_fw_state_change(g, pmu, PMU_FW_STATE_ELPG_BOOTED, true);
+		break;
+	case NV_PMU_RPC_ID_PG_LOADING_BUF_LOAD:
+		nvgpu_pmu_dbg(g, "Reply to PG_LOADING_BUF_LOAD");
+		pmu->pg->buf_loaded = true;
+		nvgpu_pmu_fw_state_change(g, pmu, PMU_FW_STATE_LOADING_ZBC, true);
+		break;
+	case NV_PMU_RPC_ID_PG_ALLOW:
+		nvgpu_pmu_dbg(g, "Reply to PG_ALLOW");
+			pmu->pg->elpg_stat = PMU_ELPG_STAT_ON;
+		break;
+	case NV_PMU_RPC_ID_PG_DISALLOW:
+		nvgpu_pmu_dbg(g, "Reply to PG_DISALLOW");
+			pmu->pg->elpg_stat = PMU_ELPG_STAT_OFF;
+		break;
+	default:
+		nvgpu_err(g,
+			"unsupported PG rpc function : 0x%x", rpc->function);
+		break;
+	}
+}
+
+static int ga10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
+		struct pmu_pg_stats_data *pg_stat_data)
+{
+	struct nvgpu_pmu *pmu = g->pmu;
+	struct pmu_pg_stats_v3 stats;
+	int err;
+
+	err = nvgpu_falcon_copy_from_dmem(pmu->flcn,
+		pmu->pg->stat_dmem_offset[pg_engine_id],
+			(u8 *)&stats, (u32)sizeof(struct pmu_pg_stats_v3), 0);
+	if (err != 0) {
+		nvgpu_err(g, "PMU falcon DMEM copy failed");
+		return err;
+	}
+
+	pg_stat_data->ingating_time = stats.total_sleep_time_us;
+	pg_stat_data->ungating_time = stats.total_non_sleep_time_us;
+	pg_stat_data->gating_cnt = stats.entry_count;
+	pg_stat_data->avg_entry_latency_us = stats.entry_latency_avg_us;
+	pg_stat_data->avg_exit_latency_us = stats.exit_latency_avg_us;
+
+	return err;
+}
+
+void nvgpu_next_pg_sw_init(struct gk20a *g,
+		struct nvgpu_pmu_pg *pg)
+{
+	nvgpu_log_fn(g, " ");
+
+	pg->elpg_statistics = ga10b_pmu_elpg_statistics;
+	pg->init_param = NULL;
+	pg->supported_engines_list = ga10b_pmu_pg_engines_list;
+	pg->engines_feature_list = NULL;
+	pg->set_sub_feature_mask = NULL;
+	pg->save_zbc = gm20b_pmu_save_zbc;
+	pg->allow = ga10b_pmu_pg_allow;
+	pg->disallow = ga10b_pmu_pg_disallow;
+	pg->init = ga10b_pmu_pg_init;
+	pg->alloc_dmem = NULL;
+	pg->load_buff = ga10b_pmu_pg_load_buff;
+	pg->hw_load_zbc = NULL;
+	pg->rpc_handler = ga10b_pg_rpc_handler;
+	pg->init_send = ga10b_pmu_pg_init_send;
+}
diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h
new file mode 100644
index 000000000..2958760b9
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_PMU_PG_SW_GA10B_H
+#define NVGPU_PMU_PG_SW_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+#define NV_PMU_SUB_FEATURE_SUPPORT_MASK		0xf84
+#define NV_PMU_ARCH_FEATURE_SUPPORT_MASK	0x1B3
+#define NV_PMU_BASE_SAMPLING_PERIOD_MS		0xFFFF
+
+/*
+* Brief Identifier for each Lpwr Group Ctrl ids
+*/
+enum
+{
+	NV_PMU_LPWR_GRP_CTRL_ID_GR = 0,
+	NV_PMU_LPWR_GRP_CTRL_ID_MS,
+	NV_PMU_LPWR_GRP_CTRL_ID__COUNT,
+};
+
+/*
+* Defines the structure that holds data used to execute PRE_INIT RPC.
+*/
+struct pmu_rpc_struct_lpwr_loading_pre_init
+{
+	/*
+	 * [IN/OUT] Must be first field in RPC structure.
+	 */
+	struct nv_pmu_rpc_header hdr;
+	/*
+	 * [IN] Lpwr group data
+	 */
+	u32 grp_ctrl_mask[NV_PMU_LPWR_GRP_CTRL_ID__COUNT];
+	/*
+	 * [IN] Mask of NV_PMU_SUBFEATURE_ID_ARCH_xyz
+	 */
+	u32 arch_sf_support_mask;
+	/*
+	 * [IN] Base sampling period for centralised LPWR callback
+	 */
+	u16 base_period_ms;
+	/*
+	 * [IN] Indicates if it is a no pstate vbios
+	 */
+	bool b_no_pstate_vbios;
+	/*
+	 * [NONE] Must be last field in RPC structure.
+	 */
+	u32 scratch[1];
+};
+
+/*
+* Defines the structure that holds data used to execute POST_INIT RPC.
+*/
+struct pmu_rpc_struct_lpwr_loading_post_init
+{
+	/* [IN/OUT] Must be first field in RPC structure */
+	struct nv_pmu_rpc_header hdr;
+	/* Must be last field in RPC structure.*/
+	u32 scratch[5];
+};
+
+struct pmu_rpc_struct_lpwr_loading_pg_ctrl_init
+{
+	/*[IN/OUT] Must be first field in RPC structure */
+	struct nv_pmu_rpc_header hdr;
+	/*
+	* [OUT] stats dmem offset
+	*/
+	u32 stats_dmem_offset;
+	/*
+	* [OUT] Engines hold off Mask
+	*/
+	u32 eng_hold_off_Mask;
+	/*
+	* [OUT] HW FSM index
+	*/
+	u8 hw_eng_idx;
+	/*
+	* [OUT] Indicates if wakeup reason type is cumulative or normal
+	*/
+	bool b_cumulative_wakeup_mask;
+	/*
+	* [IN/OUT] Sub-feature support mask
+	*/
+	u32 support_mask;
+	/*
+	* [IN] Controller ID - NV_PMU_PG_ELPG_ENGINE_ID_xyz
+	*/
+	u32 ctrl_id;
+	/*
+	* [IN] Dummy array to match with pmu struct
+	*/
+	u8 dummy[8];
+	/*
+	* [NONE] Must be last field in RPC structure.
+	*/
+	u32 scratch[1];
+};
+
+/*
+* Defines the structure that holds data used to execute PG_CTRL_ALLOW RPC.
+*/
+struct pmu_rpc_struct_lpwr_pg_ctrl_allow
+{
+	/*
+	 * [IN/OUT] Must be first field in RPC structure.
+	 */
+	struct nv_pmu_rpc_header hdr;
+	/*
+	 * [IN] Controller ID - NV_PMU_PG_ELPG_ENGINE_ID_xyz
+	 */
+	u32 ctrl_id;
+	/*
+	 * [NONE] Must be last field in RPC structure.
+	 */
+	u32 scratch[1];
+};
+
+/*
+* Defines the structure that holds data used to execute PG_CTRL_DISALLOW RPC.
+*/
+struct pmu_rpc_struct_lpwr_pg_ctrl_disallow
+{
+	/*
+	 * [IN/OUT] Must be first field in RPC structure.
+	 */
+	struct nv_pmu_rpc_header hdr;
+	/*
+	 * [IN] Controller ID - NV_PMU_PG_ELPG_ENGINE_ID_xyz
+	 */
+	u32 ctrl_id;
+	/*
+	 * [NONE] Must be last field in RPC structure.
+	 */
+	u32 scratch[1];
+};
+
+/*
+* Brief Structure defining PG Ctrl thresholds
+*/
+struct pg_ctrl_threshold
+{
+	/*
+	 *Idle threshold. HW FSM raises entry interrupt after expiration
+	 *of idle threshold.
+	 */
+	u32 idle;
+	/*
+	 * Post power up threshold. This helps to avoid immediate entry
+	 * after exit. PPU threshold is used for HOST based wake-up.
+	 */
+	u32 ppu;
+	/* Minimum value of Idle threshold supported */
+	u32 min_idle;
+	/* Maximum value of Idle threshold supported */
+	u32 max_idle;
+};
+
+/*
+* Defines the structure that holds data used to execute PG_CTRL_THRESHOLD_UPDATE RPC.
+*/
+struct pmu_rpc_struct_lpwr_pg_ctrl_threshold_update
+{
+	/*
+	 * [IN/OUT] Must be first field in RPC structure.
+	 */
+	struct nv_pmu_rpc_header hdr;
+	/*
+	 * [IN] Controller ID - NV_PMU_PG_ELPG_ENGINE_ID_xyz
+	 */
+	u32 ctrl_id;
+	/*
+	 * [IN] PgCtrl thresholds
+	 */
+	struct pg_ctrl_threshold threshold_cycles;
+	/*
+	 * [NONE] Must be last field in RPC structure.
+	 */
+	u32 scratch[1];
+};
+
+/*
+* Defines the structure that holds data used to execute PG_CTRL_SFM_UPDATE RPC.
+*/
+struct pmu_rpc_struct_lpwr_pg_ctrl_sfm_update
+{
+	/*
+	 * [IN/OUT] Must be first field in RPC structure.
+	 */
+	struct nv_pmu_rpc_header hdr;
+	/*
+	 * [IN] Updated enabled mask - NV_PMU_PG_ELPG_ENGINE_ID_xyz
+	*/
+	u32 enabled_mask;
+	/*
+	 * [IN] Controller ID - NV_PMU_PG_ELPG_ENGINE_ID_xyz
+	 */
+	u32 ctrl_id;
+	/*
+	 * [NONE] Must be last field in RPC structure.
+	 */
+	u32 scratch[1];
+};
+
+/*
+* Defines the structure that holds data used to execute PG_CTRL_BUF_LOAD RPC.
+*/
+struct pmu_rpc_struct_lpwr_loading_pg_ctrl_buf_load
+{
+	/*
+	 * [IN/OUT] Must be first field in RPC structure.
+	 */
+	struct nv_pmu_rpc_header hdr;
+	/*
+	 * [IN] DMA buffer descriptor
+	 */
+	struct flcn_mem_desc_v0 dma_desc;
+	/*
+	 * [IN] PgCtrl ID
+	 */
+	u8 ctrl_id;
+	/*
+	 * [IN] Engine Buffer Index
+	 */
+	u8 buf_idx;
+	/*
+	 * [NONE] Must be last field in RPC structure.
+	 */
+	u32 scratch[1];
+};
+
+/*
+* Brief Statistics structure for PG features
+*/
+struct pmu_pg_stats_v3
+{
+	/* Number of time PMU successfully engaged sleep state */
+	u32 entry_count;
+	/* Number of time PMU exit sleep state */
+	u32 exit_count;
+	/* Number of time PMU aborted in entry sequence */
+	u32 abort_count;
+	/* Number of time task thrashing/starvation detected by Task MGMT feature */
+	u32 detection_count;
+	/*
+	* Time for which GPU was neither in Sleep state not
+	* executing sleep sequence.
+	*/
+	u32 powered_up_time_us;
+	/* Entry and exit latency of current sleep cycle */
+	u32 entry_latency_us;
+	u32 exit_latency_us;
+	/* Resident time for current sleep cycle. */
+	u32 resident_time_us;
+	/* Rolling average entry and exit latencies */
+	u32 entry_latency_avg_us;
+	u32 exit_latency_avg_us;
+	/* Max entry and exit latencies */
+	u32 entry_latency_max_us;
+	u32 exit_latency_max_us;
+	/* Total time spent in sleep and non-sleep state */
+	u32 total_sleep_time_us;
+	u32 total_non_sleep_time_us;
+	/* Wakeup Type - Saves events that caused a power-up. */
+	u32 wake_up_events;
+	/* Abort Reason - Saves reason that caused an abort */
+	u32 abort_reason;
+	u32 sw_disallow_reason_mask;
+	u32 hw_disallow_reason_mask;
+};
+
+void nvgpu_next_pg_sw_init(struct gk20a *g, struct nvgpu_pmu_pg *pg);
+u32 ga10b_pmu_pg_engines_list(struct gk20a *g);
+
+#endif /* NVGPU_PMU_PG_SW_GA10B_H */
diff --git a/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.c b/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.c
new file mode 100644
index 000000000..5b64ef4c0
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+
+#include "nvgpu_next_profiler.h"
+
+void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g)
+{
+	if (g->ops.perf.reset_hs_streaming_credits != NULL) {
+		/* Reset high speed streaming credits to 0. */
+		g->ops.perf.reset_hs_streaming_credits(g);
+	}
+
+	if (g->ops.perf.enable_hs_streaming != NULL) {
+		/* Disable high speed streaming */
+		g->ops.perf.enable_hs_streaming(g, false);
+	}
+}
diff --git a/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.h b/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.h
new file mode 100644
index 000000000..68e2ae33d
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_PROFILER_H
+#define NVGPU_NEXT_PROFILER_H
+
+void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g);
+
+#endif /* NVGPU_NEXT_PROFILER_H */
diff --git a/drivers/gpu/nvgpu/common/riscv/riscv.c b/drivers/gpu/nvgpu/common/riscv/riscv.c
new file mode 100644
index 000000000..10820c096
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/riscv/riscv.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/falcon.h>
+#include <nvgpu/riscv.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/firmware.h>
+
+static bool is_falcon_valid(struct nvgpu_falcon *flcn)
+{
+	if (flcn == NULL) {
+		return false;
+	}
+
+	if (!flcn->is_falcon_supported) {
+		nvgpu_err(flcn->g, "Core-id %d not supported", flcn->flcn_id);
+		return false;
+	}
+
+	return true;
+}
+
+u32 nvgpu_riscv_readl(struct nvgpu_falcon *flcn, u32 offset)
+{
+	return nvgpu_readl(flcn->g,
+			   nvgpu_safe_add_u32(flcn->flcn2_base, offset));
+}
+
+void nvgpu_riscv_writel(struct nvgpu_falcon *flcn,
+				       u32 offset, u32 val)
+{
+	nvgpu_writel(flcn->g, nvgpu_safe_add_u32(flcn->flcn2_base, offset), val);
+}
+
+int nvgpu_riscv_hs_ucode_load_bootstrap(struct nvgpu_falcon *flcn,
+						struct nvgpu_firmware *manifest_fw,
+						struct nvgpu_firmware *code_fw,
+						struct nvgpu_firmware *data_fw,
+						u64 ucode_sysmem_desc_addr)
+{
+	struct gk20a *g;
+	u32 dmem_size = 0U;
+	int err = 0;
+
+	if (!is_falcon_valid(flcn)) {
+		return -EINVAL;
+	}
+
+	g = flcn->g;
+
+	/* core reset */
+	err = nvgpu_falcon_reset(flcn);
+	if (err != 0) {
+		nvgpu_err(g, "core reset failed err=%d", err);
+		return err;
+	}
+
+	/* Copy dmem desc address to mailbox */
+	nvgpu_falcon_mailbox_write(flcn, FALCON_MAILBOX_0,
+					u64_lo32(ucode_sysmem_desc_addr));
+	nvgpu_falcon_mailbox_write(flcn, FALCON_MAILBOX_1,
+					u64_hi32(ucode_sysmem_desc_addr));
+
+	g->ops.falcon.set_bcr(flcn);
+	err = nvgpu_falcon_get_mem_size(flcn, MEM_DMEM, &dmem_size);
+	err = nvgpu_falcon_copy_to_imem(flcn, 0x0, code_fw->data,
+					code_fw->size, 0, true, 0x0);
+
+	if (err != 0) {
+		nvgpu_err(g, "RISCV code copy to IMEM failed");
+		goto exit;
+	}
+
+	err = nvgpu_falcon_copy_to_dmem(flcn, 0x0, data_fw->data,
+					data_fw->size, 0x0);
+	if (err != 0) {
+		nvgpu_err(g, "RISCV data copy to DMEM failed");
+		goto exit;
+	}
+
+	err = nvgpu_falcon_copy_to_dmem(flcn, dmem_size - manifest_fw->size,
+				manifest_fw->data, manifest_fw->size, 0x0);
+	if (err != 0) {
+		nvgpu_err(g, "RISCV manifest copy to DMEM failed");
+		goto exit;
+	}
+
+	g->ops.falcon.bootstrap(flcn, 0x0);
+exit:
+	return err;
+}
+
+void nvgpu_riscv_dump_brom_stats(struct nvgpu_falcon *flcn)
+{
+	if (!is_falcon_valid(flcn)) {
+		return;
+	}
+
+	flcn->g->ops.falcon.dump_brom_stats(flcn);
+}
+
diff --git a/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c b/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c
new file mode 100644
index 000000000..ef07a70d1
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/utils.h>
+#include <nvgpu/hw_sim.h>
+#include <nvgpu/sim.h>
+#include <nvgpu/string.h>
+
+static void nvgpu_next_sim_esc_readl(struct gk20a *g,
+		const char *path, u32 index, u32 *data)
+{
+	int err;
+	u32 data_offset;
+
+	sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
+		      sim_escape_read_hdr_size());
+	*sim_msg_param(g, 0) = index;
+	*sim_msg_param(g, 4) = sizeof(u32);
+	data_offset = round_up(
+		nvgpu_safe_add_u64(strlen(path), 1ULL), sizeof(u32));
+	*sim_msg_param(g, 8) = data_offset;
+	strcpy((char *)sim_msg_param(g, sim_escape_read_hdr_size()), path);
+
+	err = issue_rpc_and_wait(g);
+
+	if (err == 0) {
+		nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g,
+			nvgpu_safe_add_u32(data_offset,
+				sim_escape_read_hdr_size())),
+			sizeof(u32));
+	} else {
+		*data = 0xffffffff;
+		WARN(1, "issue_rpc_and_wait failed err=%d", err);
+	}
+}
+
+void nvgpu_next_init_sim_support(struct gk20a *g)
+{
+	if (g->sim) {
+		g->sim->esc_readl = nvgpu_next_sim_esc_readl;
+	}
+}
diff --git a/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim_netlist.c b/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim_netlist.c
new file mode 100644
index 000000000..185d47f3f
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim_netlist.c
@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/sim.h>
+#include <nvgpu/netlist.h>
+#include "nvgpu/nvgpu_next_sim.h"
+
+int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g)
+{
+	u32 i;
+	struct netlist_av_list *sw_non_ctx_local_compute_load;
+	struct netlist_av_list *sw_non_ctx_local_gfx_load;
+	struct netlist_av_list *sw_non_ctx_global_compute_load;
+	struct netlist_av_list *sw_non_ctx_global_gfx_load;
+
+	sw_non_ctx_local_compute_load =
+		nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG_SIZE", 0,
+			    &sw_non_ctx_local_compute_load->count);
+
+	if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_compute_load) ==
+									NULL) {
+		nvgpu_info(g, "sw_non_ctx_local_compute_load failed");
+	}
+
+	for (i = 0; i < sw_non_ctx_local_compute_load->count; i++) {
+		struct netlist_av *l = sw_non_ctx_local_compute_load->l;
+		g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:REG",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:VALUE",
+				    i, &l[i].value);
+	}
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+	sw_non_ctx_local_gfx_load =
+		nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG_SIZE", 0,
+			    &sw_non_ctx_local_gfx_load->count);
+
+	if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_gfx_load) ==
+									NULL) {
+		nvgpu_info(g, "sw_non_ctx_local_gfx_load failed");
+	}
+
+	for (i = 0; i < sw_non_ctx_local_gfx_load->count; i++) {
+		struct netlist_av *l = sw_non_ctx_local_gfx_load->l;
+		g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:REG",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:VALUE",
+				    i, &l[i].value);
+	}
+#endif
+
+
+	sw_non_ctx_global_compute_load =
+		nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG_SIZE", 0,
+			    &sw_non_ctx_global_compute_load->count);
+
+	if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_compute_load) ==
+									NULL) {
+		nvgpu_info(g, "sw_non_ctx_global_compute_load failed");
+	}
+
+	for (i = 0; i < sw_non_ctx_global_compute_load->count; i++) {
+		struct netlist_av *l = sw_non_ctx_global_compute_load->l;
+		g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:REG",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:VALUE",
+				    i, &l[i].value);
+	}
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+	sw_non_ctx_global_gfx_load =
+		nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG_SIZE", 0,
+			    &sw_non_ctx_global_gfx_load->count);
+
+	if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_gfx_load) ==
+									NULL) {
+		nvgpu_info(g, "sw_non_ctx_global_gfx_load failed");
+	}
+
+	for (i = 0; i < sw_non_ctx_global_gfx_load->count; i++) {
+		struct netlist_av *l = sw_non_ctx_global_gfx_load->l;
+		g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:REG",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:VALUE",
+				    i, &l[i].value);
+	}
+#endif
+	return 0;
+}
+
+void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g)
+{
+	struct netlist_av_list *sw_non_ctx_local_compute_load;
+	struct netlist_av_list *sw_non_ctx_local_gfx_load;
+	struct netlist_av_list *sw_non_ctx_global_compute_load;
+	struct netlist_av_list *sw_non_ctx_global_gfx_load;
+
+	sw_non_ctx_local_compute_load =
+		nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
+	sw_non_ctx_global_compute_load =
+		nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
+
+
+	nvgpu_kfree(g, sw_non_ctx_local_compute_load->l);
+	nvgpu_kfree(g, sw_non_ctx_global_compute_load->l);
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+	sw_non_ctx_local_gfx_load =
+		nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
+	sw_non_ctx_global_gfx_load =
+		nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
+
+	nvgpu_kfree(g, sw_non_ctx_local_gfx_load->l);
+	nvgpu_kfree(g, sw_non_ctx_global_gfx_load->l);
+#endif
+}
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g)
+{
+	u32 i;
+	struct netlist_aiv_list *sys_compute_ctxsw_regs;
+	struct netlist_aiv_list *gpc_compute_ctxsw_regs;
+	struct netlist_aiv_list *tpc_compute_ctxsw_regs;
+	struct netlist_aiv_list *ppc_compute_ctxsw_regs;
+	struct netlist_aiv_list *etpc_compute_ctxsw_regs;
+	struct netlist_aiv_list *lts_ctxsw_regs;
+	struct netlist_aiv_list *sys_gfx_ctxsw_regs;
+	struct netlist_aiv_list *gpc_gfx_ctxsw_regs;
+	struct netlist_aiv_list *tpc_gfx_ctxsw_regs;
+	struct netlist_aiv_list *ppc_gfx_ctxsw_regs;
+	struct netlist_aiv_list *etpc_gfx_ctxsw_regs;
+
+	sys_compute_ctxsw_regs =
+			nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE_COUNT", 0,
+			    &sys_compute_ctxsw_regs->count);
+
+	if (nvgpu_netlist_alloc_aiv_list(g, sys_compute_ctxsw_regs) == NULL) {
+		nvgpu_info(g, "sys_compute_ctxsw_regs failed");
+	}
+
+	for (i = 0; i < sys_compute_ctxsw_regs->count; i++) {
+		struct netlist_aiv *l = sys_compute_ctxsw_regs->l;
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:ADDR",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:INDEX",
+				    i, &l[i].index);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:VALUE",
+				    i, &l[i].value);
+	}
+
+	gpc_compute_ctxsw_regs =
+			nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE_COUNT", 0,
+			    &gpc_compute_ctxsw_regs->count);
+
+	if (nvgpu_netlist_alloc_aiv_list(g, gpc_compute_ctxsw_regs) == NULL) {
+		nvgpu_info(g, "gpc_compute_ctxsw_regs failed");
+	}
+
+	for (i = 0; i < gpc_compute_ctxsw_regs->count; i++) {
+		struct netlist_aiv *l = gpc_compute_ctxsw_regs->l;
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:ADDR",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:INDEX",
+				    i, &l[i].index);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:VALUE",
+				    i, &l[i].value);
+	}
+
+	tpc_compute_ctxsw_regs =
+			nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE_COUNT", 0,
+			    &tpc_compute_ctxsw_regs->count);
+
+	if (nvgpu_netlist_alloc_aiv_list(g, tpc_compute_ctxsw_regs) == NULL) {
+		nvgpu_info(g, "tpc_compute_ctxsw_regs failed");
+	}
+
+	for (i = 0; i < tpc_compute_ctxsw_regs->count; i++) {
+		struct netlist_aiv *l = tpc_compute_ctxsw_regs->l;
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:ADDR",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:INDEX",
+				    i, &l[i].index);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:VALUE",
+				    i, &l[i].value);
+	}
+
+	ppc_compute_ctxsw_regs =
+			nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE_COUNT", 0,
+			    &ppc_compute_ctxsw_regs->count);
+
+	if (nvgpu_netlist_alloc_aiv_list(g, ppc_compute_ctxsw_regs) == NULL) {
+		nvgpu_info(g, "ppc_compute_ctxsw_regs failed");
+	}
+
+	for (i = 0; i < ppc_compute_ctxsw_regs->count; i++) {
+		struct netlist_aiv *l = ppc_compute_ctxsw_regs->l;
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:ADDR",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:INDEX",
+				    i, &l[i].index);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:VALUE",
+				    i, &l[i].value);
+	}
+
+	etpc_compute_ctxsw_regs =
+			nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE_COUNT", 0,
+			    &etpc_compute_ctxsw_regs->count);
+
+	if (nvgpu_netlist_alloc_aiv_list(g, etpc_compute_ctxsw_regs) == NULL) {
+		nvgpu_info(g, "etpc_compute_ctxsw_regs failed");
+	}
+
+	for (i = 0; i < etpc_compute_ctxsw_regs->count; i++) {
+		struct netlist_aiv *l = etpc_compute_ctxsw_regs->l;
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:ADDR",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:INDEX",
+				    i, &l[i].index);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:VALUE",
+				    i, &l[i].value);
+	}
+
+	/*
+	 * TODO: https://jirasw.nvidia.com/browse/NVGPU-5761
+	 */
+	lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC_COUNT", 0,
+				&lts_ctxsw_regs->count);
+	nvgpu_log_info(g, "total: %d lts registers", lts_ctxsw_regs->count);
+
+	if (nvgpu_netlist_alloc_aiv_list(g, lts_ctxsw_regs) == NULL) {
+		nvgpu_info(g, "lts_ctxsw_regs failed");
+	}
+
+	for (i = 0U; i < lts_ctxsw_regs->count; i++) {
+		struct netlist_aiv *l = lts_ctxsw_regs->l;
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:ADDR",
+					i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:INDEX",
+					i, &l[i].index);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:VALUE",
+					i, &l[i].value);
+		nvgpu_log_info(g, "entry(%d) a(0x%x) i(%d) v(0x%x)", i, l[i].addr,
+				l[i].index, l[i].value);
+	}
+
+	sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS_COUNT", 0,
+			    &sys_gfx_ctxsw_regs->count);
+
+	if (nvgpu_netlist_alloc_aiv_list(g, sys_gfx_ctxsw_regs) == NULL) {
+		nvgpu_info(g, "sys_gfx_ctxsw_regs failed");
+	}
+
+	for (i = 0; i < sys_gfx_ctxsw_regs->count; i++) {
+		struct netlist_aiv *l = sys_gfx_ctxsw_regs->l;
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:ADDR",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:INDEX",
+				    i, &l[i].index);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:VALUE",
+				    i, &l[i].value);
+	}
+
+	gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS_COUNT", 0,
+			    &gpc_gfx_ctxsw_regs->count);
+
+	if (nvgpu_netlist_alloc_aiv_list(g, gpc_gfx_ctxsw_regs) == NULL) {
+		nvgpu_info(g, "gpc_gfx_ctxsw_regs failed");
+	}
+
+	for (i = 0; i < gpc_gfx_ctxsw_regs->count; i++) {
+		struct netlist_aiv *l = gpc_gfx_ctxsw_regs->l;
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:ADDR",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:INDEX",
+				    i, &l[i].index);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:VALUE",
+				    i, &l[i].value);
+	}
+
+	tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS_COUNT", 0,
+			    &tpc_gfx_ctxsw_regs->count);
+
+	if (nvgpu_netlist_alloc_aiv_list(g, tpc_gfx_ctxsw_regs) == NULL) {
+		nvgpu_info(g, "tpc_gfx_ctxsw_regs failed");
+	}
+
+	for (i = 0; i < tpc_gfx_ctxsw_regs->count; i++) {
+		struct netlist_aiv *l = tpc_gfx_ctxsw_regs->l;
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:ADDR",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:INDEX",
+				    i, &l[i].index);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:VALUE",
+				    i, &l[i].value);
+	}
+
+	ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS_COUNT", 0,
+			    &ppc_gfx_ctxsw_regs->count);
+
+	if (nvgpu_netlist_alloc_aiv_list(g, ppc_gfx_ctxsw_regs) == NULL) {
+		nvgpu_info(g, "ppc_gfx_ctxsw_regs failed");
+	}
+
+	for (i = 0; i < ppc_gfx_ctxsw_regs->count; i++) {
+		struct netlist_aiv *l = ppc_gfx_ctxsw_regs->l;
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:ADDR",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:INDEX",
+				    i, &l[i].index);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:VALUE",
+				    i, &l[i].value);
+	}
+
+	etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
+
+	/* query sizes and counts */
+	g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS_COUNT", 0,
+			    &etpc_gfx_ctxsw_regs->count);
+
+	if (nvgpu_netlist_alloc_aiv_list(g, etpc_gfx_ctxsw_regs) == NULL) {
+		nvgpu_info(g, "etpc_gfx_ctxsw_regs failed");
+	}
+
+	for (i = 0; i < etpc_gfx_ctxsw_regs->count; i++) {
+		struct netlist_aiv *l = etpc_gfx_ctxsw_regs->l;
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:ADDR",
+				    i, &l[i].addr);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:INDEX",
+				    i, &l[i].index);
+		g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:VALUE",
+				    i, &l[i].value);
+	}
+
+	return 0;
+}
+
+void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g)
+{
+	struct netlist_aiv_list *sys_compute_ctxsw_regs;
+	struct netlist_aiv_list *gpc_compute_ctxsw_regs;
+	struct netlist_aiv_list *tpc_compute_ctxsw_regs;
+	struct netlist_aiv_list *ppc_compute_ctxsw_regs;
+	struct netlist_aiv_list *etpc_compute_ctxsw_regs;
+	struct netlist_aiv_list *lts_ctxsw_regs;
+	struct netlist_aiv_list *sys_gfx_ctxsw_regs;
+	struct netlist_aiv_list *gpc_gfx_ctxsw_regs;
+	struct netlist_aiv_list *tpc_gfx_ctxsw_regs;
+	struct netlist_aiv_list *ppc_gfx_ctxsw_regs;
+	struct netlist_aiv_list *etpc_gfx_ctxsw_regs;
+
+	sys_compute_ctxsw_regs =
+			nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
+	gpc_compute_ctxsw_regs =
+			nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
+	tpc_compute_ctxsw_regs =
+			nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
+	ppc_compute_ctxsw_regs =
+			nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
+	etpc_compute_ctxsw_regs =
+			nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
+	lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
+
+	nvgpu_kfree(g, sys_compute_ctxsw_regs->l);
+	nvgpu_kfree(g, gpc_compute_ctxsw_regs->l);
+	nvgpu_kfree(g, tpc_compute_ctxsw_regs->l);
+	nvgpu_kfree(g, ppc_compute_ctxsw_regs->l);
+	nvgpu_kfree(g, etpc_compute_ctxsw_regs->l);
+	nvgpu_kfree(g, lts_ctxsw_regs->l);
+
+	sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
+	gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
+	tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
+	ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
+	etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
+
+	nvgpu_kfree(g, sys_gfx_ctxsw_regs->l);
+	nvgpu_kfree(g, gpc_gfx_ctxsw_regs->l);
+	nvgpu_kfree(g, tpc_gfx_ctxsw_regs->l);
+	nvgpu_kfree(g, ppc_gfx_ctxsw_regs->l);
+	nvgpu_kfree(g, etpc_gfx_ctxsw_regs->l);
+}
+#endif /* CONFIG_NVGPU_DEBUGGER */
diff --git a/drivers/gpu/nvgpu/common/vbios/bios_sw_ga100.c b/drivers/gpu/nvgpu/common/vbios/bios_sw_ga100.c
new file mode 100644
index 000000000..6b99f29a2
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/vbios/bios_sw_ga100.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+
+#include "common/vbios/bios_sw_tu104.h"
+#include "common/vbios/bios_sw_ga100.h"
+
+#define NVGPU_PG209_MIN_VBIOS		0
+
+struct nvgpu_vbios_board {
+	u16 board_id;
+	u32 vbios_version;
+};
+
+#define NVGPU_GA100_NUM_BOARDS		1
+
+static struct nvgpu_vbios_board vbios_boards[NVGPU_GA100_NUM_BOARDS] = {
+	/* PG209 SKU 200 */
+	[0] = {
+		.board_id = 0x0209,
+		.vbios_version = 0,	/* any VBIOS for now */
+	},
+};
+
+static int ga100_bios_verify_version(struct gk20a *g)
+{
+	struct nvgpu_vbios_board *board = NULL;
+	u32 i;
+
+	nvgpu_info(g, "VBIOS board id %04x", g->bios->vbios_board_id);
+
+	nvgpu_info(g, "VBIOS version %08x:%02x\n",
+		g->bios->vbios_version,
+		g->bios->vbios_oem_version);
+
+#if NVGPU_PG209_MIN_VBIOS
+	if (g->bios->vbios_version < NVGPU_PG209_MIN_VBIOS) {
+		nvgpu_err(g, "unsupported VBIOS version %08x",
+			g->bios->vbios_version);
+		return -EINVAL;
+	}
+#endif
+
+	for (i = 0; i < NVGPU_GA100_NUM_BOARDS; i++) {
+		if (g->bios->vbios_board_id == vbios_boards[i].board_id) {
+			board = &vbios_boards[i];
+		}
+	}
+
+	if (board == NULL) {
+		nvgpu_warn(g, "unknown board id %04x",
+			g->bios->vbios_board_id);
+		return 0;
+	}
+
+	if ((board->vbios_version != 0U) &&
+		(g->bios->vbios_version < board->vbios_version)) {
+		nvgpu_warn(g, "VBIOS version should be at least %08x",
+			board->vbios_version);
+	}
+
+	return 0;
+}
+
+void nvgpu_ga100_bios_sw_init(struct gk20a *g, struct nvgpu_bios *bios)
+{
+	bios->init = tu104_bios_init;
+	bios->verify_version = ga100_bios_verify_version;
+	bios->preos_wait_for_halt = NULL;
+	bios->preos_reload_check = NULL;
+	bios->preos_bios = NULL;
+	bios->devinit_bios = NULL;
+	bios->verify_devinit = tu104_bios_verify_devinit;
+}
+
diff --git a/drivers/gpu/nvgpu/common/vbios/bios_sw_ga100.h b/drivers/gpu/nvgpu/common/vbios/bios_sw_ga100.h
new file mode 100644
index 000000000..c79ddb17d
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/vbios/bios_sw_ga100.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_BIOS_SW_GA100_H
+#define NVGPU_BIOS_SW_GA100_H
+
+struct gk20a;
+
+void nvgpu_ga100_bios_sw_init(struct gk20a *g, struct nvgpu_bios *bios);
+
+#endif /* NVGPU_BIOS_SW_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/bus/bus_ga100.c b/drivers/gpu/nvgpu/hal/bus/bus_ga100.c
new file mode 100644
index 000000000..415dd9141
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/bus/bus_ga100.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/timers.h>
+#include <nvgpu/mm.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+
+#include "bus_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_bus_ga100.h>
+
+u32 ga100_bus_read_sw_scratch(struct gk20a *g, u32 index)
+{
+	return gk20a_readl(g, bus_sw_scratch_r(index));
+}
+
+void ga100_bus_write_sw_scratch(struct gk20a *g, u32 index, u32 val)
+{
+	gk20a_writel(g, bus_sw_scratch_r(index), val);
+}
diff --git a/drivers/gpu/nvgpu/hal/bus/bus_ga100.h b/drivers/gpu/nvgpu/hal/bus/bus_ga100.h
new file mode 100644
index 000000000..6715898a6
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/bus/bus_ga100.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GA100_BUS
+#define NVGPU_GA100_BUS
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+u32 ga100_bus_read_sw_scratch(struct gk20a *g, u32 index);
+void ga100_bus_write_sw_scratch(struct gk20a *g, u32 index, u32 val);
+
+#endif
diff --git a/drivers/gpu/nvgpu/hal/bus/bus_ga10b.c b/drivers/gpu/nvgpu/hal/bus/bus_ga10b.c
new file mode 100644
index 000000000..2dcf6aa12
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/bus/bus_ga10b.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/io.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/nvgpu_err.h>
+
+#include "bus_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_bus_ga10b.h>
+
+#define BUS_INTR_0_PRI_MASK \
+	(\
+	bus_intr_0_pri_fecserr_m() | \
+	bus_intr_0_pri_timeout_m() \
+	)
+
+#define BUS_INTR_0_FB_MASK \
+	( \
+	bus_intr_0_fb_req_timeout_m() | \
+	bus_intr_0_fb_ack_timeout_m() | \
+	bus_intr_0_fb_ack_extra_m() | \
+	bus_intr_0_fb_rdata_timeout_m() | \
+	bus_intr_0_fb_rdata_extra_m() \
+	)
+
+int ga10b_bus_init_hw(struct gk20a *g)
+{
+	u32 intr_en_mask = 0;
+
+	/*
+	 * pbus: pri related interrupts which are generated when fecs could
+	 * communicate error back to host. This is the case of non-posted
+	 * transactions (generally reads)
+	 * pri_fecserr: This bit is set when a pri request returns from fecs
+	 * with error status.
+	 * pri_timeout: This bit is set when a pri request to anywhere is
+	 * discarded due to timeout.
+	 * priv_ring: pri error in pri hub that could not be reported to host
+	 * (error on a posted transaction generally writes).
+	 */
+	intr_en_mask =  bus_intr_en_0_pri_fecserr_m() |
+			bus_intr_en_0_pri_timeout_m() |
+			bus_intr_en_0_fb_req_timeout_m() |
+			bus_intr_en_0_fb_ack_timeout_m() |
+			bus_intr_en_0_fb_ack_extra_m() |
+			bus_intr_en_0_fb_rdata_timeout_m() |
+			bus_intr_en_0_fb_rdata_extra_m() |
+			bus_intr_en_0_sw_m() |
+			bus_intr_en_0_posted_deadlock_timeout_m() |
+			bus_intr_en_0_mpmu_m() |
+			bus_intr_en_0_access_timeout_m();
+
+	nvgpu_log_info(g, "bus fb_timeout=0x%x",
+		bus_fb_timeout_period_v(nvgpu_readl(g,  bus_fb_timeout_r())));
+
+	nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE);
+
+	nvgpu_writel(g, bus_intr_en_0_r(), intr_en_mask);
+	return 0;
+}
+
+void ga10b_bus_isr(struct gk20a *g)
+{
+	u32 bus_intr_0 = 0U;
+	u32 err_type = GPU_HOST_PBUS_TIMEOUT_ERROR;
+	u32 bus_intr_0_handled = 0U;
+
+	bus_intr_0 = nvgpu_readl(g, bus_intr_0_r());
+
+	/*
+	 * These bits signal that a PRI transaction has failed or timed out
+	 * pri_fecserr_m(): fecs initiated PRI transaction failed.
+	 * pri_timeout_m(): PRI transaction timed out.
+	 */
+	if ((bus_intr_0 & BUS_INTR_0_PRI_MASK) != 0U) {
+		if ((bus_intr_0 & bus_intr_0_pri_fecserr_m()) != 0U) {
+			err_type = GPU_HOST_PBUS_FECS_ERROR;
+		}
+		g->ops.ptimer.isr(g);
+
+		bus_intr_0_handled |= (bus_intr_0 & BUS_INTR_0_PRI_MASK);
+	}
+
+	/*
+	 * These bits indicate fatal errors in the CPU-to-Frame buffer memory.
+	 */
+	if ((bus_intr_0 & BUS_INTR_0_FB_MASK) != 0U) {
+		nvgpu_err(g, "errors detected on FB access path, status: 0x%08x",
+				bus_intr_0 & BUS_INTR_0_FB_MASK);
+		bus_intr_0_handled |= (bus_intr_0 & BUS_INTR_0_FB_MASK);
+	}
+
+	/*
+	 * Indicates a software interrupt, generated by writing 1 to
+	 * NV_PBUS_SW_INTR_0.
+	 */
+	if ((bus_intr_0 & bus_intr_0_sw_m()) != 0U) {
+		nvgpu_err(g, "software interrupt");
+		bus_intr_0_handled |= bus_intr_0_sw_m();
+	}
+
+	/*
+	 * This bit is set when a deadlock on the posted path is detected.
+	 */
+	if ((bus_intr_0 & bus_intr_0_posted_deadlock_timeout_m()) != 0U) {
+		nvgpu_err(g, "deadlock on posted transaction");
+		bus_intr_0_handled |= bus_intr_0_posted_deadlock_timeout_m();
+	}
+
+	/*
+	 * Indicates an interrupt from mpmu
+	 */
+	if ((bus_intr_0 & bus_intr_0_mpmu_m()) != 0U) {
+		nvgpu_err(g, "interrupt from MPMU");
+		bus_intr_0_handled |= bus_intr_0_mpmu_m();
+	}
+
+	/*
+	 * Indicates that a request from a sideband requester has timed out.
+	 */
+	if ((bus_intr_0 & bus_intr_0_access_timeout_m()) != 0U) {
+		nvgpu_err(g, "access timeout detected on sideband requester");
+		bus_intr_0_handled |= bus_intr_0_access_timeout_m();
+	}
+
+	if (bus_intr_0 != bus_intr_0_handled) {
+		nvgpu_err(g, "unhandled interrupts, status: 0x%x",
+				bus_intr_0 & ~bus_intr_0_handled);
+	}
+
+	nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST, 0, err_type, bus_intr_0);
+	nvgpu_writel(g, bus_intr_0_r(), bus_intr_0);
+}
diff --git a/drivers/gpu/nvgpu/hal/bus/bus_ga10b.h b/drivers/gpu/nvgpu/hal/bus/bus_ga10b.h
new file mode 100644
index 000000000..69f6ca444
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/bus/bus_ga10b.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_BUS_GA10B_H
+#define NVGPU_BUS_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+int ga10b_bus_init_hw(struct gk20a *g);
+void ga10b_bus_isr(struct gk20a *g);
+
+#endif /* NVGPU_BUS_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/cbc/cbc_ga100.c b/drivers/gpu/nvgpu/hal/cbc/cbc_ga100.c
new file mode 100644
index 000000000..072e27507
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/cbc/cbc_ga100.c
@@ -0,0 +1,158 @@
+/*
+ * GA100 CBC
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/sizes.h>
+#include <nvgpu/ltc.h>
+#include <nvgpu/cbc.h>
+#include <nvgpu/comptags.h>
+
+#include "cbc_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_ltc_ga100.h>
+
+#define SIZE_2K	(SZ_1K << 1U)
+#define AMAP_DIVIDE_ROUNDING_BASE_VALUE		U32(SIZE_2K)
+#define AMAP_SWIZZLE_ROUNDING_BASE_VALUE	U32(SZ_64K)
+
+int ga100_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc)
+{
+	/*
+	 * - Compbit backing store is a memory buffer to store compressed data
+	 * corresponding to total compressible memory.
+	 * - In GA10B, 1 ROP tile = 256B data is compressed to 1B compression
+	 * bits. i.e. 1 GOB = 512B data is compressed to 2B compbits.
+	 * - A comptagline is a collection of compbits corresponding to a
+	 * compressible page size. In GA10B, compressible page size is 256KB.
+	 *
+	 * - GA10B has 2 LTCs with 4 slices each. A 256KB page is distributed
+	 *   into 8 slices having 32KB (64 GOBs) data each.
+	 * - Thus, each comptagline per slice contains compression status bits
+	 * corresponding to 64 GOBs.
+	 */
+	u32 compbit_backing_size;
+
+	/* max memory size (MB) to cover */
+	u32 max_size = g->max_comptag_mem;
+
+	u32 max_comptag_lines;
+
+	u32 hw_max_comptag_lines =
+		ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v();
+
+	u32 gobs_per_comptagline_per_slice =
+		ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(
+				nvgpu_readl(g, ltc_ltcs_ltss_cbc_param2_r()));
+
+	u32 compstatus_per_gob = 2U;
+
+	u32 cbc_param = nvgpu_readl(g, ltc_ltcs_ltss_cbc_param_r());
+
+	u32 comptags_size =
+		ltc_ltcs_ltss_cbc_param_bytes_per_comptagline_per_slice_v(
+			cbc_param);
+
+	u32 amap_divide_rounding = AMAP_DIVIDE_ROUNDING_BASE_VALUE <<
+		ltc_ltcs_ltss_cbc_param_amap_divide_rounding_v(cbc_param);
+
+	u32 amap_swizzle_rounding = AMAP_SWIZZLE_ROUNDING_BASE_VALUE <<
+		ltc_ltcs_ltss_cbc_param_amap_swizzle_rounding_v(cbc_param);
+
+	int err;
+
+	nvgpu_log_fn(g, " ");
+
+	/* Already initialized */
+	if (cbc->max_comptag_lines != 0U) {
+		return 0;
+	}
+
+	if (g->ops.fb.is_comptagline_mode_enabled(g)) {
+		/*
+		 * one tag line covers 256KB
+		 * So, number of comptag lines = (max_size * SZ_1M) / SZ_256K
+		 */
+		max_comptag_lines = max_size << 2U;
+
+		if (max_comptag_lines == 0U) {
+			return 0;
+		}
+
+		if (max_comptag_lines > hw_max_comptag_lines) {
+			max_comptag_lines = hw_max_comptag_lines;
+		}
+	} else {
+		max_comptag_lines = hw_max_comptag_lines;
+	}
+
+	/* Memory required for comptag lines in all slices of all ltcs */
+	compbit_backing_size =  nvgpu_safe_mult_u32(
+		nvgpu_safe_mult_u32(max_comptag_lines,
+			nvgpu_ltc_get_slices_per_ltc(g)),
+		nvgpu_ltc_get_ltc_count(g));
+
+	/* Total memory required for compstatus */
+	compbit_backing_size =  nvgpu_safe_mult_u32(
+		nvgpu_safe_mult_u32(compbit_backing_size,
+			gobs_per_comptagline_per_slice), compstatus_per_gob);
+
+	compbit_backing_size += nvgpu_ltc_get_ltc_count(g) *
+					amap_divide_rounding;
+	compbit_backing_size += amap_swizzle_rounding;
+
+	/* aligned to 2KB * ltc_count */
+	compbit_backing_size +=
+		nvgpu_ltc_get_ltc_count(g) <<
+			ltc_ltcs_ltss_cbc_base_alignment_shift_v();
+
+	/* must be a multiple of 64KB */
+	compbit_backing_size = round_up(compbit_backing_size, SZ_64K);
+
+	err = nvgpu_cbc_alloc(g, compbit_backing_size, true);
+	if (err != 0) {
+		return err;
+	}
+
+	err = gk20a_comptag_allocator_init(g, &cbc->comp_tags,
+						max_comptag_lines);
+	if (err != 0) {
+		return err;
+	}
+
+	cbc->max_comptag_lines = max_comptag_lines;
+	cbc->comptags_per_cacheline =
+		nvgpu_ltc_get_cacheline_size(g) / comptags_size;
+	cbc->gobs_per_comptagline_per_slice = gobs_per_comptagline_per_slice;
+	cbc->compbit_backing_size = compbit_backing_size;
+
+	nvgpu_log(g, gpu_dbg_pte, "compbit backing store size : 0x%x",
+		compbit_backing_size);
+	nvgpu_log(g, gpu_dbg_pte, "max comptag lines: %d",
+		max_comptag_lines);
+	nvgpu_log(g, gpu_dbg_pte, "gobs_per_comptagline_per_slice: %d",
+		cbc->gobs_per_comptagline_per_slice);
+
+	return 0;
+}
diff --git a/drivers/gpu/nvgpu/hal/cbc/cbc_ga100.h b/drivers/gpu/nvgpu/hal/cbc/cbc_ga100.h
new file mode 100644
index 000000000..5c9ca2755
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/cbc/cbc_ga100.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef CBC_GA100_H
+#define CBC_GA100_H
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_cbc;
+
+int ga100_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc);
+
+#endif
+#endif /* CBC_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c b/drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c
new file mode 100644
index 000000000..a79e09e72
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c
@@ -0,0 +1,152 @@
+/*
+ * GA10B CBC
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/sizes.h>
+#include <nvgpu/ltc.h>
+#include <nvgpu/cbc.h>
+#include <nvgpu/comptags.h>
+
+#include "cbc_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_ltc_ga10b.h>
+
+int ga10b_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc)
+{
+	/*
+	 * - Compbit backing store is a memory buffer to store compressed data
+	 * corresponding to total compressible memory.
+	 * - In GA10B, 1 ROP tile = 256B data is compressed to 1B compression
+	 * bits. i.e. 1 GOB = 512B data is compressed to 2B compbits.
+	 * - A comptagline is a collection of compbits corresponding to a
+	 * compressible page size. In GA10B, compressible page size is 64KB.
+	 *
+	 * - GA10B has 2 LTCs with 4 slices each. A 64KB page is distributed
+	 *   into 8 slices having 8KB (16 GOBs) data each.
+	 * - Thus, each comptagline per slice contains compression status bits
+	 * corresponding to 16 GOBs.
+	 */
+	u32 compbit_backing_size;
+
+	/* max memory size (MB) to cover */
+	u32 max_size = g->max_comptag_mem;
+
+	/*
+	 * one tag line covers 64KB
+	 * So, number of comptag lines = (max_size * SZ_1M) / SZ_64K
+	 */
+	u32 max_comptag_lines = max_size << 4U;
+
+	u32 hw_max_comptag_lines =
+		ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v();
+
+	u32 gobs_per_comptagline_per_slice =
+		ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(
+				nvgpu_readl(g, ltc_ltcs_ltss_cbc_param2_r()));
+
+	u32 compstatus_per_gob = 2U;
+
+	u32 comptags_size =
+		ltc_ltcs_ltss_cbc_param_bytes_per_comptagline_per_slice_v(
+			nvgpu_readl(g, ltc_ltcs_ltss_cbc_param_r()));
+
+	/*
+	 * For Tegra, the addressing works differently. Unlike DGPU, all
+	 * partitions talk to the same memory.
+	 */
+	u32 ltc_count = 1U;
+
+	/* check if vidmem is present */
+	bool alloc_vidmem = g->ops.fb.get_vidmem_size != NULL ? true : false;
+	int err;
+
+	nvgpu_log_fn(g, " ");
+
+	if (max_comptag_lines == 0U) {
+		return 0;
+	}
+
+	/* Already initialized */
+	if (cbc->max_comptag_lines != 0U) {
+		return 0;
+	}
+
+	if (max_comptag_lines > hw_max_comptag_lines) {
+		max_comptag_lines = hw_max_comptag_lines;
+	}
+
+	/* Memory required for comptag lines in all slices of all ltcs */
+	compbit_backing_size =  nvgpu_safe_mult_u32(
+		nvgpu_safe_mult_u32(max_comptag_lines,
+			nvgpu_ltc_get_slices_per_ltc(g)), ltc_count);
+
+	/* Total memory required for compstatus */
+	compbit_backing_size =  nvgpu_safe_mult_u32(
+		nvgpu_safe_mult_u32(compbit_backing_size,
+			gobs_per_comptagline_per_slice), compstatus_per_gob);
+
+	/* aligned to 2KB * ltc_count */
+	compbit_backing_size +=
+		ltc_count << ltc_ltcs_ltss_cbc_base_alignment_shift_v();
+
+	/* must be a multiple of 64KB */
+	compbit_backing_size = round_up(compbit_backing_size, SZ_64K);
+
+	err = nvgpu_cbc_alloc(g, compbit_backing_size, alloc_vidmem);
+	if (err != 0) {
+		return err;
+	}
+
+	err = gk20a_comptag_allocator_init(g, &cbc->comp_tags,
+						max_comptag_lines);
+	if (err != 0) {
+		return err;
+	}
+
+	cbc->max_comptag_lines = max_comptag_lines;
+	cbc->comptags_per_cacheline =
+		nvgpu_ltc_get_cacheline_size(g) / comptags_size;
+	cbc->gobs_per_comptagline_per_slice = gobs_per_comptagline_per_slice;
+	cbc->compbit_backing_size = compbit_backing_size;
+
+	nvgpu_log(g, gpu_dbg_pte, "supported LTCs: 0x%x",
+		nvgpu_ltc_get_ltc_count(g));
+	nvgpu_log(g, gpu_dbg_pte, "ltc_count used for calculations: 0x%x",
+		ltc_count);
+	nvgpu_log(g, gpu_dbg_pte, "compbit backing store size : 0x%x",
+		compbit_backing_size);
+	nvgpu_log(g, gpu_dbg_pte, "max comptag lines: %d",
+		max_comptag_lines);
+	nvgpu_log(g, gpu_dbg_pte, "gobs_per_comptagline_per_slice: %d",
+		cbc->gobs_per_comptagline_per_slice);
+
+	return 0;
+}
+
+void ga10b_cbc_init(struct gk20a *g, struct nvgpu_cbc *cbc)
+{
+	g->ops.fb.cbc_configure(g, cbc);
+	g->ops.cbc.ctrl(g, nvgpu_cbc_op_clear, 0U, cbc->max_comptag_lines - 1U);
+}
diff --git a/drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.h b/drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.h
new file mode 100644
index 000000000..47ab25740
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef CBC_GA10B_H
+#define CBC_GA10B_H
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_cbc;
+
+int ga10b_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc);
+void ga10b_cbc_init(struct gk20a *g, struct nvgpu_cbc *cbc);
+
+#endif
+#endif /* CBC_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/ce/ce_ga10b.h b/drivers/gpu/nvgpu/hal/ce/ce_ga10b.h
new file mode 100644
index 000000000..1eca679b2
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/ce/ce_ga10b.h
@@ -0,0 +1,34 @@
+/*
+ * Ampere GPU series copy engine
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_CE_GA10B_H
+#define NVGPU_CE_GA10B_H
+
+struct gk20a;
+
+void ga10b_ce_init_hw(struct  gk20a *g);
+void ga10b_ce_intr_enable(struct gk20a *g, bool enable);
+void ga10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
+void ga10b_ce_intr_retrigger(struct gk20a *g, u32 inst_id);
+
+#endif /* NVGPU_CE_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c
new file mode 100644
index 000000000..777606fbc
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c
@@ -0,0 +1,239 @@
+/*
+ * Ampere GPU series Copy Engine.
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/log.h>
+#include <nvgpu/device.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/mc.h>
+
+#include "hal/ce/ce_gv11b.h"
+#include "hal/ce/ce_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_ce_ga10b.h>
+
+#define CE_LCE_STALL_INTR_MASK \
+	(\
+	ce_lce_intr_en_blockpipe_m() |\
+	ce_lce_intr_en_launcherr_m() |\
+	ce_lce_intr_en_invalid_config_m() |\
+	ce_lce_intr_en_mthd_buffer_fault_m() |\
+	ce_lce_intr_en_fbuf_crc_fail_m() |\
+	ce_lce_intr_en_fbuf_magic_chk_fail_m() |\
+	ce_lce_intr_en_poison_error_m() |\
+	ce_lce_intr_en_stalling_debug_m() \
+	)
+
+#define CE_LCE_NONSTALL_INTR_MASK \
+	( \
+	ce_lce_intr_en_nonblockpipe_m() \
+	)
+
+static void ga10b_ce_intr_stall_nonstall_enable(struct gk20a *g,
+		const struct nvgpu_device *dev, bool enable)
+{
+	u32 intr_en_mask = 0U;
+	u32 intr_ctrl = 0U;
+	u32 intr_notify_ctrl = 0U;
+	u32 intr_ctrl_msk = 0U;
+	u32 intr_notify_ctrl_msk = 0U;
+	u32 inst_id = dev->inst_id;
+
+	intr_ctrl = nvgpu_readl(g, ce_lce_intr_ctrl_r(inst_id));
+	intr_notify_ctrl =
+		nvgpu_readl(g, ce_lce_intr_notify_ctrl_r(inst_id));
+
+	/*
+	 * The copy engine interrupts are enabled using a single enable
+	 * register: ce_lce_intr_en_r. The interrupts generated by the
+	 * CE engine are grouped into two:
+	 * Stall:
+	 * - Represented by: CE_LCE_STALL_INTR_MASK.
+	 * Non-Stall:
+	 * - Represented by: CE_LCE_NONSTALL_INTR_MASK.
+	 * Stalling interrupts are routed either to the cpu/gsp using
+	 * the POR value of vector_id in register: ce_lce_intr_ctrl_r.
+	 * This vector aligns with the intr_id field in device info.
+	 * Similarly non-stalling interrupts are routed to cpu/gsp using
+	 * the POR value of vector_id in register:
+	 * ce_lce_intr_notify_ctrl_r. However unlike the former, the
+	 * non-stalling interrupt vectors for GRCE0,1 share the vector
+	 * id of GR engine. Hence there is a mis-alignment between the
+	 * POR value of vector_id in ce_lce_intr_notify_ctrl_r register
+	 * of GRCE0,1 with the intr_id field in the device info.
+	 */
+	if (enable) {
+		/*
+		 * Enable all stall, non-stall interrupts. Configure
+		 * intr_(notify_,)_ctrl_r, so that all engine interrupts
+		 * are reported to CPU on the POR values of vector_ids.
+		 * In addition, disable reporting to GSP.
+		 */
+		intr_en_mask = CE_LCE_STALL_INTR_MASK |
+			CE_LCE_NONSTALL_INTR_MASK;
+		intr_ctrl_msk = ce_lce_intr_ctrl_cpu_enable_f() |
+			ce_lce_intr_ctrl_gsp_disable_f();
+		intr_notify_ctrl_msk =
+			ce_lce_intr_notify_ctrl_cpu_enable_f() |
+			ce_lce_intr_notify_ctrl_gsp_disable_f();
+
+	} else {
+		/*
+		 * Mask all interrupts from the engine and disable
+		 * reporting to both CPU, GSP.
+		 */
+		intr_en_mask = 0U;
+		intr_ctrl_msk = ce_lce_intr_ctrl_cpu_disable_f() |
+			ce_lce_intr_ctrl_gsp_disable_f();
+		intr_notify_ctrl_msk =
+			ce_lce_intr_notify_ctrl_cpu_disable_f() |
+			ce_lce_intr_notify_ctrl_gsp_disable_f();
+	}
+
+	intr_ctrl = set_field(intr_ctrl, ce_lce_intr_ctrl_cpu_m() |
+			ce_lce_intr_ctrl_gsp_m(),
+			intr_ctrl_msk);
+	intr_notify_ctrl = set_field(intr_notify_ctrl,
+			ce_lce_intr_notify_ctrl_cpu_m() |
+			ce_lce_intr_notify_ctrl_gsp_m(),
+			intr_notify_ctrl_msk);
+
+	nvgpu_log(g, gpu_dbg_intr, "ce(%d) intr_ctrl(0x%x) "\
+			"intr_notify_ctrl(0x%x) intr_en_mask(0x%x)",
+			inst_id, intr_ctrl, intr_notify_ctrl,
+			intr_en_mask);
+
+	nvgpu_writel(g, ce_lce_intr_ctrl_r(inst_id), intr_ctrl);
+	nvgpu_writel(g, ce_lce_intr_notify_ctrl_r(inst_id),
+			intr_notify_ctrl);
+	nvgpu_writel(g, ce_lce_intr_en_r(inst_id), intr_en_mask);
+}
+
+void ga10b_ce_init_hw(struct gk20a *g)
+{
+	u32 i = 0U;
+	u32 nonstall_vectorid_tree[NVGPU_CIC_INTR_VECTORID_SIZE_MAX];
+	u32 num_nonstall_vectors = 0;
+
+	for (i = 0U; i < nvgpu_device_count(g, NVGPU_DEVTYPE_LCE); i++) {
+		const struct nvgpu_device *dev =
+			nvgpu_device_get(g, NVGPU_DEVTYPE_LCE, i);
+		nvgpu_assert(dev != NULL);
+
+		/*
+		 * The intr_id in dev info is broken for non-stall interrupts
+		 * from grce0,1. Therefore, instead read the vectors from the
+		 * POR values of intr_notify_ctrl_r.
+		 */
+		nonstall_vectorid_tree[num_nonstall_vectors] =
+			ce_lce_intr_notify_ctrl_vector_v(
+			nvgpu_readl(g, ce_lce_intr_notify_ctrl_r(dev->inst_id)));
+		nvgpu_log(g, gpu_dbg_intr, "ce(%d) non-stall vector(%d)",
+			  dev->inst_id,
+			  nonstall_vectorid_tree[num_nonstall_vectors]);
+		num_nonstall_vectors++;
+	}
+
+	/*
+	 * Initalize struct nvgpu_mc with POR values of non-stall vectors ids.
+	 */
+	nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_CE,
+			nonstall_vectorid_tree, num_nonstall_vectors);
+}
+
+void ga10b_ce_intr_enable(struct gk20a *g, bool enable)
+{
+	u32 i = 0U;
+
+	for (i = 0U; i < nvgpu_device_count(g, NVGPU_DEVTYPE_LCE); i++) {
+		const struct nvgpu_device *dev =
+			nvgpu_device_get(g, NVGPU_DEVTYPE_LCE, i);
+		nvgpu_assert(dev != NULL);
+
+		ga10b_ce_intr_stall_nonstall_enable(g, dev, enable);
+	}
+}
+
+void ga10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
+{
+	u32 ce_intr = nvgpu_readl(g, ce_intr_status_r(inst_id));
+	u32 clear_intr = 0U;
+
+	nvgpu_log(g, gpu_dbg_intr, "ce(%u) isr 0x%08x 0x%08x", inst_id,
+			ce_intr, inst_id);
+
+	/*
+	 * Mismatch between the CRC entry in fault buffer and the
+	 * CRC computed from the methods in the buffer.
+	 */
+	if ((ce_intr & ce_intr_status_fbuf_crc_fail_pending_f()) != 0U) {
+		nvgpu_err(g, "ce: inst %d, fault buffer crc mismatch", inst_id);
+		clear_intr |= ce_intr_status_fbuf_crc_fail_reset_f();
+	}
+
+	/*
+	 * The MAGIC_NUM entry in fault buffer does not match with the expected
+	 * value: NV_CE_MTHD_BUFFER_GLOBAL_HDR_MAGIC_NUM_VAL. This error
+	 * indicates a memory corruption.
+	 */
+	if ((ce_intr & ce_intr_status_fbuf_magic_chk_fail_pending_f()) != 0U) {
+		nvgpu_err(g, "ce: inst %d, fault buffer magic check fail",
+				inst_id);
+		clear_intr |= ce_intr_status_fbuf_magic_chk_fail_reset_f();
+	}
+
+	/*
+	 * The poison error indicates that the data returned from the memory
+	 * subsytem is corrupted due to an uncorrectable ecc error.
+	 */
+	if ((ce_intr & ce_intr_status_poison_error_pending_f()) != 0U) {
+		nvgpu_err(g, "ce: inst %d: poison error, uncorrected ecc error",
+				inst_id);
+		clear_intr |= ce_intr_status_poison_error_reset_f();
+	}
+
+	/*
+	 * The stalling_debug error interrupt is triggered when SW writes TRUE
+	 * to NV_CE_LCE_OPT_EXT_DEBUG_TRIGGER_STALLING.
+	 */
+	if ((ce_intr & ce_intr_status_stalling_debug_pending_f()) != 0U) {
+		nvgpu_err(g, "ce: inst %d: stalling debug interrupt", inst_id);
+		clear_intr |= ce_intr_status_stalling_debug_pending_f();
+	}
+
+	nvgpu_writel(g, ce_intr_status_r(inst_id), clear_intr);
+
+	/*
+	 * The remaining legacy interrupts are handled by legacy interrupt
+	 * handler.
+	 */
+	gv11b_ce_stall_isr(g, inst_id, pri_base);
+}
+
+void ga10b_ce_intr_retrigger(struct gk20a *g, u32 inst_id)
+{
+	nvgpu_writel(g, ce_intr_retrigger_r(inst_id),
+			ce_intr_retrigger_trigger_true_f());
+}
diff --git a/drivers/gpu/nvgpu/hal/class/class_ga100.c b/drivers/gpu/nvgpu/hal/class/class_ga100.c
new file mode 100644
index 000000000..0eb9dac7a
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/class/class_ga100.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/class.h>
+#include <nvgpu/nvgpu_next_class.h>
+#include <nvgpu/barrier.h>
+
+#include "hal/class/class_ga10b.h"
+
+#include "class_ga100.h"
+
+bool ga100_class_is_valid(u32 class_num)
+{
+	bool valid;
+
+	nvgpu_speculation_barrier();
+
+	switch (class_num) {
+	case AMPERE_COMPUTE_A:
+	case AMPERE_DMA_COPY_A:
+#ifdef CONFIG_NVGPU_GRAPHICS
+	case AMPERE_A:
+#endif
+		valid = true;
+		break;
+	default:
+		valid = ga10b_class_is_valid(class_num);
+		break;
+	}
+	return valid;
+};
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+bool ga100_class_is_valid_gfx(u32 class_num)
+{
+	bool valid;
+
+	nvgpu_speculation_barrier();
+
+	switch (class_num) {
+	case AMPERE_A:
+		valid = true;
+		break;
+	default:
+		valid = false;
+		break;
+	}
+	return valid;
+}
+#endif
+
+bool ga100_class_is_valid_compute(u32 class_num)
+{
+	bool valid;
+
+	nvgpu_speculation_barrier();
+
+	switch (class_num) {
+	case AMPERE_COMPUTE_A:
+		valid = true;
+		break;
+	default:
+		valid = ga10b_class_is_valid_compute(class_num);
+		break;
+	}
+	return valid;
+}
diff --git a/drivers/gpu/nvgpu/hal/class/class_ga100.h b/drivers/gpu/nvgpu/hal/class/class_ga100.h
new file mode 100644
index 000000000..4968584e3
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/class/class_ga100.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_CLASS_GA100
+#define NVGPU_CLASS_GA100
+
+#include <nvgpu/types.h>
+
+bool ga100_class_is_valid(u32 class_num);
+bool ga100_class_is_valid_compute(u32 class_num);
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+bool ga100_class_is_valid_gfx(u32 class_num);
+#endif
+
+#endif /* NVGPU_CLASS_GA100 */
diff --git a/drivers/gpu/nvgpu/hal/class/class_ga10b.c b/drivers/gpu/nvgpu/hal/class/class_ga10b.c
new file mode 100644
index 000000000..ccfc12bd3
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/class/class_ga10b.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/class.h>
+#include <nvgpu/nvgpu_next_class.h>
+#include <nvgpu/barrier.h>
+
+#include "hal/class/class_tu104.h"
+
+#include "class_ga10b.h"
+
+bool ga10b_class_is_valid(u32 class_num)
+{
+	bool valid;
+
+	nvgpu_speculation_barrier();
+
+	switch (class_num) {
+	case AMPERE_SMC_PARTITION_REF:
+	case AMPERE_COMPUTE_B:
+	case AMPERE_DMA_COPY_B:
+	case AMPERE_CHANNEL_GPFIFO_B:
+#ifdef CONFIG_NVGPU_GRAPHICS
+	case AMPERE_B:
+#endif
+		valid = true;
+		break;
+	default:
+		valid = tu104_class_is_valid(class_num);
+		break;
+	}
+	return valid;
+};
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+bool ga10b_class_is_valid_gfx(u32 class_num)
+{
+	bool valid;
+
+	nvgpu_speculation_barrier();
+
+	switch (class_num) {
+	case AMPERE_B:
+		valid = true;
+		break;
+	default:
+		valid = tu104_class_is_valid_gfx(class_num);
+		break;
+	}
+	return valid;
+}
+#endif
+
+bool ga10b_class_is_valid_compute(u32 class_num)
+{
+	bool valid;
+
+	nvgpu_speculation_barrier();
+
+	switch (class_num) {
+	case AMPERE_COMPUTE_B:
+		valid = true;
+		break;
+	default:
+		valid = tu104_class_is_valid_compute(class_num);
+		break;
+	}
+	return valid;
+}
diff --git a/drivers/gpu/nvgpu/hal/class/class_ga10b.h b/drivers/gpu/nvgpu/hal/class/class_ga10b.h
new file mode 100644
index 000000000..0e44e4d5d
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/class/class_ga10b.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_CLASS_GA10B
+#define NVGPU_CLASS_GA10B
+
+#include <nvgpu/types.h>
+
+bool ga10b_class_is_valid(u32 class_num);
+bool ga10b_class_is_valid_compute(u32 class_num);
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+bool ga10b_class_is_valid_gfx(u32 class_num);
+#endif
+
+#endif /* NVGPU_CLASS_GA10B */
diff --git a/drivers/gpu/nvgpu/hal/clk/clk_ga100.c b/drivers/gpu/nvgpu/hal/clk/clk_ga100.c
new file mode 100644
index 000000000..73de5946e
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/clk/clk_ga100.c
@@ -0,0 +1,38 @@
+/*
+ * GA100 Clocks
+ *
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/hw/ga100/hw_trim_ga100.h>
+
+#include "clk_ga100.h"
+
+u32 ga100_clk_get_cntr_sysclk_source(struct gk20a *g)
+{
+	return trim_sys_fr_clk_cntr_sysclk_cfg_source_sys_noeg_f();
+}
+
+u32 ga100_clk_get_cntr_xbarclk_source(struct gk20a *g)
+{
+	return trim_sys_fll_fr_clk_cntr_xbarclk_cfg_source_xbar_nobg_duplicate_f();
+}
diff --git a/drivers/gpu/nvgpu/hal/clk/clk_ga100.h b/drivers/gpu/nvgpu/hal/clk/clk_ga100.h
new file mode 100644
index 000000000..183a2f759
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/clk/clk_ga100.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef CLK_GA100_H
+#define CLK_GA100_H
+
+u32 ga100_clk_get_cntr_xbarclk_source(struct gk20a *g);
+u32 ga100_clk_get_cntr_sysclk_source(struct gk20a *g);
+
+#endif /* CLK_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b.h b/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b.h
new file mode 100644
index 000000000..d148f59be
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_FALCON_GA10B_H
+#define NVGPU_FALCON_GA10B_H
+
+#include <nvgpu/falcon.h>
+
+#define FALCON_DMEM_BLKSIZE2	8U
+u32 ga10b_falcon_dmemc_blk_mask(void);
+u32 ga10b_falcon_imemc_blk_field(u32 blk);
+u32 ga10b_falcon_get_mem_size(struct nvgpu_falcon *flcn,
+		enum falcon_mem_type mem_type);
+bool ga10b_falcon_is_cpu_halted(struct nvgpu_falcon *flcn);
+void ga10b_falcon_set_bcr(struct nvgpu_falcon *flcn);
+void ga10b_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector);
+void ga10b_falcon_dump_brom_stats(struct nvgpu_falcon *flcn);
+u32  ga10b_falcon_get_brom_retcode(struct nvgpu_falcon *flcn);
+bool ga10b_falcon_is_priv_lockdown(struct nvgpu_falcon *flcn);
+bool ga10b_falcon_check_brom_passed(u32 retcode);
+void ga10b_falcon_brom_config(struct nvgpu_falcon *flcn, u64 fmc_code_addr,
+		u64 fmc_data_addr, u64 manifest_addr);
+void ga10b_falcon_dump_stats(struct nvgpu_falcon *flcn);
+bool ga10b_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn);
+bool ga10b_is_falcon_idle(struct nvgpu_falcon *flcn);
+#endif /* NVGPU_FALCON_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c
new file mode 100644
index 000000000..f208284e5
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <nvgpu/falcon.h>
+#include <nvgpu/log.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/riscv.h>
+#include <nvgpu/hw/ga10b/hw_falcon_ga10b.h>
+#include <nvgpu/hw/ga10b/hw_priscv_ga10b.h>
+
+#include "hal/falcon/falcon_gk20a.h"
+
+#include "falcon_ga10b.h"
+
+u32 ga10b_falcon_dmemc_blk_mask(void)
+{
+	return falcon_falcon_dmemc_blk_m();
+}
+
+u32 ga10b_falcon_imemc_blk_field(u32 blk)
+{
+	return falcon_falcon_imemc_blk_f(blk);
+}
+
+bool ga10b_falcon_is_cpu_halted(struct nvgpu_falcon *flcn)
+{
+	if (flcn->is_falcon2_enabled) {
+		return (priscv_priscv_cpuctl_halted_v(
+			nvgpu_riscv_readl(flcn, priscv_priscv_cpuctl_r())) != 0U);
+	} else {
+		return ((nvgpu_falcon_readl(flcn, falcon_falcon_cpuctl_r()) &
+			falcon_falcon_cpuctl_halt_intr_m()) != 0U);
+	}
+}
+
+void ga10b_falcon_set_bcr(struct nvgpu_falcon *flcn)
+{
+	nvgpu_riscv_writel(flcn, priscv_priscv_bcr_ctrl_r(), 0x11);
+}
+
+void ga10b_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector)
+{
+	/* Need to check this through fuse/SW policy*/
+	if (flcn->is_falcon2_enabled) {
+		nvgpu_log_info(flcn->g, "boot riscv core");
+		nvgpu_riscv_writel(flcn, priscv_priscv_cpuctl_r(),
+			priscv_priscv_cpuctl_startcpu_true_f());
+	} else {
+		nvgpu_log_info(flcn->g, "falcon boot vec 0x%x", boot_vector);
+
+		nvgpu_falcon_writel(flcn, falcon_falcon_dmactl_r(),
+			falcon_falcon_dmactl_require_ctx_f(0));
+
+		nvgpu_falcon_writel(flcn, falcon_falcon_bootvec_r(),
+			falcon_falcon_bootvec_vec_f(boot_vector));
+
+		nvgpu_falcon_writel(flcn, falcon_falcon_cpuctl_r(),
+			falcon_falcon_cpuctl_startcpu_f(1));
+	}
+}
+
+void ga10b_falcon_dump_brom_stats(struct nvgpu_falcon *flcn)
+{
+	u32 reg;
+
+        reg = nvgpu_riscv_readl(flcn, priscv_priscv_bcr_ctrl_r());
+        nvgpu_info(flcn->g, "Bootrom Configuration: 0x%08x", reg);
+
+        reg = nvgpu_falcon_readl(flcn, falcon_falcon_hwcfg2_r());
+        nvgpu_pmu_dbg(flcn->g, "HWCFG2: 0x%08x", reg);
+
+	if (falcon_falcon_hwcfg2_riscv_br_priv_lockdown_v(reg) ==
+		falcon_falcon_hwcfg2_riscv_br_priv_lockdown_lock_v()) {
+		nvgpu_info(flcn->g, "PRIV LOCKDOWN enabled");
+	} else {
+		nvgpu_info(flcn->g, "PRIV LOCKDOWN disabled");
+	}
+
+        reg = nvgpu_riscv_readl(flcn, priscv_priscv_br_retcode_r());
+        nvgpu_log_info(flcn->g,"RISCV BROM RETCODE: 0x%08x", reg);
+}
+
+u32 ga10b_falcon_get_brom_retcode(struct nvgpu_falcon *flcn)
+{
+	return nvgpu_riscv_readl(flcn, priscv_priscv_br_retcode_r());
+}
+
+bool ga10b_falcon_is_priv_lockdown(struct nvgpu_falcon *flcn)
+{
+	u32 reg = nvgpu_falcon_readl(flcn, falcon_falcon_hwcfg2_r());
+
+	if (falcon_falcon_hwcfg2_riscv_br_priv_lockdown_v(reg) ==
+		falcon_falcon_hwcfg2_riscv_br_priv_lockdown_lock_v()) {
+		return true;
+	}
+
+	return false;
+}
+
+bool ga10b_falcon_check_brom_passed(u32 retcode)
+{
+	return (priscv_priscv_br_retcode_result_v(retcode) ==
+			priscv_priscv_br_retcode_result_pass_f()) ||
+			(priscv_priscv_br_retcode_result_v(retcode) ==
+				priscv_priscv_br_retcode_result_fail_f());
+}
+
+void ga10b_falcon_brom_config(struct nvgpu_falcon *flcn, u64 fmc_code_addr,
+		u64 fmc_data_addr, u64 manifest_addr)
+{
+	nvgpu_riscv_writel(flcn, priscv_priscv_bcr_dmaaddr_fmccode_lo_r(),
+			u64_lo32(fmc_code_addr));
+	nvgpu_riscv_writel(flcn, priscv_priscv_bcr_dmaaddr_fmccode_hi_r(),
+			u64_hi32(fmc_code_addr));
+
+	nvgpu_riscv_writel(flcn, priscv_priscv_bcr_dmaaddr_fmcdata_lo_r(),
+			u64_lo32(fmc_data_addr));
+	nvgpu_riscv_writel(flcn, priscv_priscv_bcr_dmaaddr_fmcdata_hi_r(),
+			u64_hi32(fmc_data_addr));
+
+	nvgpu_riscv_writel(flcn, priscv_priscv_bcr_dmaaddr_pkcparam_lo_r(),
+			u64_lo32(manifest_addr));
+	nvgpu_riscv_writel(flcn, priscv_priscv_bcr_dmaaddr_pkcparam_hi_r(),
+			u64_hi32(manifest_addr));
+
+	nvgpu_riscv_writel(flcn, priscv_priscv_bcr_dmacfg_r(),
+			priscv_priscv_bcr_dmacfg_target_noncoherent_system_f() |
+			priscv_priscv_bcr_dmacfg_lock_locked_f());
+
+	nvgpu_riscv_writel(flcn, priscv_priscv_bcr_ctrl_r(), 0x111);
+}
+
+#ifdef CONFIG_NVGPU_FALCON_DEBUG
+static void ga10b_riscv_dump_stats(struct nvgpu_falcon *flcn)
+{
+	struct gk20a *g = NULL;
+
+	g = flcn->g;
+
+	nvgpu_err(g, "<<< FALCON id-%d RISCV DEBUG INFORMATION - START >>>",
+			flcn->flcn_id);
+
+	nvgpu_err(g, " RISCV REGISTERS DUMP");
+	nvgpu_err(g, "riscv_riscv_mailbox0_r : 0x%x",
+		nvgpu_falcon_readl(flcn, falcon_falcon_mailbox0_r()));
+	nvgpu_err(g, "riscv_riscv_mailbox1_r : 0x%x",
+		nvgpu_falcon_readl(flcn, falcon_falcon_mailbox1_r()));
+	nvgpu_err(g, "priscv_priscv_cpuctl_r : 0x%x",
+		nvgpu_riscv_readl(flcn, priscv_priscv_cpuctl_r()));
+	nvgpu_err(g, "priscv_riscv_irqmask_r : 0x%x",
+		nvgpu_riscv_readl(flcn, priscv_riscv_irqmask_r()));
+	nvgpu_err(g, "priscv_riscv_irqdest_r : 0x%x",
+		nvgpu_riscv_readl(flcn, priscv_riscv_irqdest_r()));
+}
+
+void ga10b_falcon_dump_stats(struct nvgpu_falcon *flcn)
+{
+	if (flcn->is_falcon2_enabled) {
+		ga10b_riscv_dump_stats(flcn);
+	} else {
+		gk20a_falcon_dump_stats(flcn);
+	}
+}
+
+bool ga10b_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn)
+{
+	u32 hwcfg = 0U;
+
+	hwcfg = nvgpu_falcon_readl(flcn, falcon_falcon_hwcfg2_r());
+
+	if (falcon_falcon_hwcfg2_mem_scrubbing_v(hwcfg) ==
+		falcon_falcon_hwcfg2_mem_scrubbing_pending_v()) {
+		return false;
+	} else {
+		return true;
+	}
+}
+
+bool ga10b_is_falcon_idle(struct nvgpu_falcon *flcn)
+{
+	u32 reg = 0U;
+
+	if (flcn->is_falcon2_enabled == false) {
+		return gk20a_is_falcon_idle(flcn);
+	} else {
+		reg = nvgpu_falcon_readl(flcn, falcon_falcon_hwcfg2_r());
+		nvgpu_pmu_dbg(flcn->g, "HWCFG2: 0x%08x", reg);
+
+		if (falcon_falcon_hwcfg2_riscv_br_priv_lockdown_v(reg) ==
+			falcon_falcon_hwcfg2_riscv_br_priv_lockdown_lock_v()) {
+			nvgpu_pmu_dbg(flcn->g, "PRIV LOCKDOWN enabled");
+			return true;
+		}
+	}
+	return true;
+}
+#endif /* CONFIG_NVGPU_FALCON_DEBUG */
diff --git a/drivers/gpu/nvgpu/hal/fb/ecc/fb_ecc_ga10b.h b/drivers/gpu/nvgpu/hal/fb/ecc/fb_ecc_ga10b.h
new file mode 100644
index 000000000..844ed6983
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/ecc/fb_ecc_ga10b.h
@@ -0,0 +1,35 @@
+/*
+ * GA10B FB ECC
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FB_ECC_GA10B_H
+#define NVGPU_FB_ECC_GA10B_H
+
+struct gk20a;
+
+int ga10b_fb_ecc_init(struct gk20a *g);
+void ga10b_fb_ecc_free(struct gk20a *g);
+void ga10b_fb_ecc_l2tlb_error_mask(u32 *corrected_error_mask,
+		u32 *uncorrected_error_mask);
+
+#endif /* NVGPU_FB_ECC_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fb/ecc/fb_ecc_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fb/ecc/fb_ecc_ga10b_fusa.c
new file mode 100644
index 000000000..46b80ce41
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/ecc/fb_ecc_ga10b_fusa.c
@@ -0,0 +1,119 @@
+/*
+ * GA10B FB ECC
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/static_analysis.h>
+
+#include "hal/fb/ecc/fb_ecc_gv11b.h"
+#include "fb_ecc_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_fb_ga10b.h>
+
+#define FB_ECC_L2TLB_CORRECTED_ERROR_MASK \
+	(\
+	 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m() |\
+	 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb1_sa_data_m() \
+	)
+
+#define FB_ECC_L2TLB_UNCORRECTED_ERROR_MASK \
+	(\
+	 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m() |\
+	 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb1_sa_data_m() \
+	)
+
+int ga10b_fb_ecc_init(struct gk20a *g)
+{
+	int err = 0;
+
+	err = gv11b_fb_ecc_init(g);
+	if (err != 0) {
+		goto init_fb_gv11b_counters_fail;
+	}
+	err = NVGPU_ECC_COUNTER_INIT_FB(mmu_l2tlb_ecc_uncorrected_unique_err_count);
+	if (err != 0) {
+		goto init_l2tlb_ecc_uncorrected_unique_fail;
+	}
+	err = NVGPU_ECC_COUNTER_INIT_FB(mmu_l2tlb_ecc_corrected_unique_err_count);
+	if (err != 0) {
+		goto init_l2tlb_ecc_corrected_unique_fail;
+	}
+	err = NVGPU_ECC_COUNTER_INIT_FB(mmu_hubtlb_ecc_uncorrected_unique_err_count);
+	if (err != 0) {
+		goto init_hubtlb_ecc_uncorrected_unique_fail;
+	}
+	err = NVGPU_ECC_COUNTER_INIT_FB(mmu_hubtlb_ecc_corrected_unique_err_count);
+	if (err != 0) {
+		goto init_hubtlb_ecc_corrected_unique_fail;
+	}
+	err = NVGPU_ECC_COUNTER_INIT_FB(mmu_fillunit_ecc_uncorrected_unique_err_count);
+	if (err != 0) {
+		goto init_fillunit_ecc_uncorrected_unique_fail;
+	}
+	err = NVGPU_ECC_COUNTER_INIT_FB(mmu_fillunit_ecc_corrected_unique_err_count);
+	if (err != 0) {
+		goto init_fillunit_ecc_corrected_unique_fail;
+	}
+
+	return 0;
+
+init_fillunit_ecc_corrected_unique_fail:
+	NVGPU_ECC_COUNTER_FREE_FB(mmu_fillunit_ecc_uncorrected_unique_err_count);
+init_fillunit_ecc_uncorrected_unique_fail:
+	NVGPU_ECC_COUNTER_FREE_FB(mmu_hubtlb_ecc_corrected_unique_err_count);
+init_hubtlb_ecc_corrected_unique_fail:
+	NVGPU_ECC_COUNTER_FREE_FB(mmu_hubtlb_ecc_uncorrected_unique_err_count);
+init_hubtlb_ecc_uncorrected_unique_fail:
+	NVGPU_ECC_COUNTER_FREE_FB(mmu_l2tlb_ecc_corrected_unique_err_count);
+init_l2tlb_ecc_corrected_unique_fail:
+	NVGPU_ECC_COUNTER_FREE_FB(mmu_l2tlb_ecc_uncorrected_unique_err_count);
+init_l2tlb_ecc_uncorrected_unique_fail:
+	gv11b_fb_ecc_free(g);
+init_fb_gv11b_counters_fail:
+	return err;
+}
+
+void ga10b_fb_ecc_free(struct gk20a *g)
+{
+	struct nvgpu_ecc *ecc = &g->ecc;
+
+	nvgpu_kfree(g, ecc->fb.mmu_l2tlb_ecc_corrected_unique_err_count);
+	nvgpu_kfree(g, ecc->fb.mmu_l2tlb_ecc_uncorrected_unique_err_count);
+	nvgpu_kfree(g, ecc->fb.mmu_hubtlb_ecc_corrected_unique_err_count);
+	nvgpu_kfree(g, ecc->fb.mmu_hubtlb_ecc_uncorrected_unique_err_count);
+	nvgpu_kfree(g, ecc->fb.mmu_fillunit_ecc_corrected_unique_err_count);
+	nvgpu_kfree(g, ecc->fb.mmu_fillunit_ecc_uncorrected_unique_err_count);
+	gv11b_fb_ecc_free(g);
+}
+
+void ga10b_fb_ecc_l2tlb_error_mask(u32 *corrected_error_mask,
+		u32 *uncorrected_error_mask)
+{
+	*corrected_error_mask = FB_ECC_L2TLB_CORRECTED_ERROR_MASK;
+
+	*uncorrected_error_mask = FB_ECC_L2TLB_UNCORRECTED_ERROR_MASK;
+
+	return;
+}
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_ga100.c b/drivers/gpu/nvgpu/hal/fb/fb_ga100.c
new file mode 100644
index 000000000..d523afd82
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/fb_ga100.c
@@ -0,0 +1,80 @@
+/*
+ * GA100 FB
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/nvgpu_init.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/sizes.h>
+
+#include "hal/fb/fb_ga100.h"
+#include <nvgpu/hw/ga100/hw_fb_ga100.h>
+
+#define SIZE_256K			(SZ_1K << 8U)
+
+#define HW_SCRUB_TIMEOUT_DEFAULT	100 /* usec */
+#define HW_SCRUB_TIMEOUT_MAX		2000000 /* usec */
+
+void ga100_fb_init_fs_state(struct gk20a *g)
+{
+	u32 retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT;
+	/* wait for memory to be accessible */
+	do {
+		u32 w = nvgpu_readl(g, fb_niso_scrub_status_r());
+		if (fb_niso_scrub_status_flag_v(w) != 0U) {
+			nvgpu_log_fn(g, "done");
+			break;
+		}
+		nvgpu_udelay(HW_SCRUB_TIMEOUT_DEFAULT);
+		--retries;
+	} while (retries != 0);
+
+}
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+u64 ga100_fb_compression_page_size(struct gk20a *g)
+{
+	return SIZE_256K;
+}
+
+bool ga100_fb_is_comptagline_mode_enabled(struct gk20a *g)
+{
+	u32 reg = 0U;
+	bool result = true;
+
+	gk20a_busy_noresume(g);
+	if (nvgpu_is_powered_off(g)) {
+		goto done;
+	}
+
+	reg = nvgpu_readl(g, fb_mmu_hypervisor_ctl_r());
+
+	result = (fb_mmu_hypervisor_ctl_force_cbc_raw_mode_v(reg) ==
+		fb_mmu_hypervisor_ctl_force_cbc_raw_mode_disable_v());
+
+done:
+	gk20a_idle_nosuspend(g);
+	return result;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_ga100.h b/drivers/gpu/nvgpu/hal/fb/fb_ga100.h
new file mode 100644
index 000000000..0b84b79eb
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/fb_ga100.h
@@ -0,0 +1,37 @@
+/*
+ * GA100 FB
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FB_GA100_H
+#define NVGPU_FB_GA100_H
+
+struct gk20a;
+
+void ga100_fb_init_fs_state(struct gk20a *g);
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+u64 ga100_fb_compression_page_size(struct gk20a *g);
+bool ga100_fb_is_comptagline_mode_enabled(struct gk20a *g);
+#endif
+
+#endif /* NVGPU_FB_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_ga10b.c b/drivers/gpu/nvgpu/hal/fb/fb_ga10b.c
new file mode 100644
index 000000000..54517c828
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/fb_ga10b.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/io.h>
+#include <nvgpu/device.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/soc.h>
+
+#include "fb_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_fb_ga10b.h>
+
+#ifdef CONFIG_NVGPU_MIG
+#include <nvgpu/grmgr.h>
+#endif
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+void ga10b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
+{
+	u64 base_divisor;
+	u64 compbit_store_base;
+	u64 compbit_store_pa;
+	u32 cbc_max;
+
+	compbit_store_pa = nvgpu_mem_get_addr(g, &cbc->compbit_store.mem);
+	base_divisor = g->ops.cbc.get_base_divisor(g);
+	compbit_store_base = DIV_ROUND_UP(compbit_store_pa, base_divisor);
+
+	cbc_max = nvgpu_readl(g, fb_mmu_cbc_max_r());
+	cbc_max = set_field(cbc_max,
+		  fb_mmu_cbc_max_comptagline_m(),
+		  fb_mmu_cbc_max_comptagline_f(cbc->max_comptag_lines));
+	nvgpu_writel(g, fb_mmu_cbc_max_r(), cbc_max);
+
+	nvgpu_assert(compbit_store_base < U64(U32_MAX));
+	nvgpu_writel(g, fb_mmu_cbc_base_r(),
+		fb_mmu_cbc_base_address_f(U32(compbit_store_base)));
+
+	nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
+		"compbit base.pa: 0x%x,%08x cbc_base:0x%llx\n",
+		(u32)(compbit_store_pa >> 32),
+		(u32)(compbit_store_pa & 0xffffffffU),
+		compbit_store_base);
+
+	cbc->compbit_store.base_hw = compbit_store_base;
+}
+#endif
+
+#ifdef CONFIG_NVGPU_MIG
+int ga10b_fb_config_veid_smc_map(struct gk20a *g, bool enable)
+{
+	u32 reg_val;
+	u32 gpu_instance_id;
+	struct nvgpu_gpu_instance *gpu_instance;
+	struct nvgpu_gr_syspipe *gr_syspipe;
+	u32 veid_enable_mask = fb_mmu_hypervisor_ctl_use_smc_veid_tables_f(
+		fb_mmu_hypervisor_ctl_use_smc_veid_tables_disable_v());
+	u32 default_remote_swizid = 0U;
+
+	if (enable) {
+		for (gpu_instance_id = 0U;
+				gpu_instance_id < g->mig.num_gpu_instances;
+				++gpu_instance_id) {
+
+			if (!nvgpu_grmgr_is_mig_type_gpu_instance(
+					&g->mig.gpu_instance[gpu_instance_id])) {
+				nvgpu_log(g, gpu_dbg_mig, "skip physical instance[%u]",
+					gpu_instance_id);
+				continue;
+			}
+
+			gpu_instance =
+				&g->mig.gpu_instance[gpu_instance_id];
+			gr_syspipe = &gpu_instance->gr_syspipe;
+
+			reg_val = nvgpu_readl(g,
+				fb_mmu_smc_eng_cfg_0_r(gr_syspipe->gr_syspipe_id));
+
+			if (gpu_instance->is_memory_partition_supported) {
+				default_remote_swizid = gpu_instance->gpu_instance_id;
+			}
+
+			reg_val = set_field(reg_val,
+				fb_mmu_smc_eng_cfg_0_remote_swizid_m(),
+				fb_mmu_smc_eng_cfg_0_remote_swizid_f(
+					default_remote_swizid));
+
+			reg_val = set_field(reg_val,
+				fb_mmu_smc_eng_cfg_0_mmu_eng_veid_offset_m(),
+				fb_mmu_smc_eng_cfg_0_mmu_eng_veid_offset_f(
+					gr_syspipe->veid_start_offset));
+
+			reg_val = set_field(reg_val,
+				fb_mmu_smc_eng_cfg_0_veid_max_m(),
+				fb_mmu_smc_eng_cfg_0_veid_max_f(
+					nvgpu_safe_sub_u32(
+						gr_syspipe->max_veid_count_per_tsg, 1U)));
+
+			nvgpu_writel(g,
+				fb_mmu_smc_eng_cfg_0_r(gr_syspipe->gr_syspipe_id),
+				reg_val);
+			nvgpu_log(g, gpu_dbg_mig,
+				"[%d] gpu_instance_id[%u] default_remote_swizid[%u] "
+					"gr_instance_id[%u] gr_syspipe_id[%u] "
+					"veid_start_offset[%u] veid_end_offset[%u] "
+					"reg_val[%x] ",
+				gpu_instance_id,
+				g->mig.gpu_instance[gpu_instance_id].gpu_instance_id,
+				default_remote_swizid,
+				gr_syspipe->gr_instance_id,
+				gr_syspipe->gr_syspipe_id,
+				gr_syspipe->veid_start_offset,
+				nvgpu_safe_sub_u32(
+					nvgpu_safe_add_u32(gr_syspipe->veid_start_offset,
+						gr_syspipe->max_veid_count_per_tsg), 1U),
+				reg_val);
+		}
+		veid_enable_mask = fb_mmu_hypervisor_ctl_use_smc_veid_tables_f(
+			fb_mmu_hypervisor_ctl_use_smc_veid_tables_enable_v());
+	}
+	reg_val = nvgpu_readl(g, fb_mmu_hypervisor_ctl_r());
+	reg_val &= ~fb_mmu_hypervisor_ctl_use_smc_veid_tables_m();
+
+	reg_val |= veid_enable_mask;
+
+	nvgpu_writel(g, fb_mmu_hypervisor_ctl_r(), reg_val);
+
+	nvgpu_log(g, gpu_dbg_mig,
+		"state[%d] reg_val[%x] ",
+		enable, reg_val);
+	return 0;
+}
+
+int ga10b_fb_set_smc_eng_config(struct gk20a *g, bool enable)
+{
+	u32 reg_val;
+	u32 index;
+	u32 local_id;
+	u32 logical_gpc_id_mask;
+	struct nvgpu_gr_syspipe *gr_syspipe;
+
+	for (index = 0U; index < g->mig.num_gpu_instances; index++) {
+		if (!nvgpu_grmgr_is_mig_type_gpu_instance(
+				&g->mig.gpu_instance[index])) {
+			nvgpu_log(g, gpu_dbg_mig, "skip physical instance[%u]",
+				index);
+			continue;
+		}
+		gr_syspipe = &g->mig.gpu_instance[index].gr_syspipe;
+		logical_gpc_id_mask = 0U;
+
+		if (enable) {
+			for (local_id = 0U; local_id < gr_syspipe->num_gpc;
+					local_id++) {
+				logical_gpc_id_mask |= BIT32(
+					gr_syspipe->gpcs[local_id].logical_id);
+			}
+		}
+		reg_val = nvgpu_readl(g, fb_mmu_smc_eng_cfg_1_r(
+			gr_syspipe->gr_syspipe_id));
+		reg_val = set_field(reg_val,
+			fb_mmu_smc_eng_cfg_1_gpc_mask_m(),
+			fb_mmu_smc_eng_cfg_1_gpc_mask_f(
+				logical_gpc_id_mask));
+
+		nvgpu_writel(g, fb_mmu_smc_eng_cfg_1_r(
+			gr_syspipe->gr_syspipe_id), reg_val);
+
+		nvgpu_log(g, gpu_dbg_mig,
+			"[%d] gpu_instance_id[%u] gr_syspipe_id[%u] "
+				"gr_instance_id[%u] logical_gpc_id_mask[%x] "
+				"reg_val[%x] enable[%d] ",
+			index,
+			g->mig.gpu_instance[index].gpu_instance_id,
+			gr_syspipe->gr_syspipe_id,
+			gr_syspipe->gr_instance_id,
+			logical_gpc_id_mask,
+			reg_val,
+			enable);
+	}
+
+	return 0;
+}
+
+int ga10b_fb_set_remote_swizid(struct gk20a *g, bool enable)
+{
+	u32 reg_val;
+	u32 index;
+	u32 lce_id;
+	struct nvgpu_gr_syspipe *gr_syspipe;
+	u32 default_remote_swizid = 0U;
+	struct nvgpu_gpu_instance *gpu_instance;
+	u32 pbdma_id_mask;
+	struct nvgpu_next_pbdma_info pbdma_info;
+	u32 pbdma_index;
+
+	for (index = 0U; index < g->mig.num_gpu_instances; index++) {
+		const struct nvgpu_device *gr_dev =
+			g->mig.gpu_instance[index].gr_syspipe.gr_dev;
+		gpu_instance = &g->mig.gpu_instance[index];
+		gr_syspipe = &gpu_instance->gr_syspipe;
+		pbdma_id_mask = 0U;
+
+		if (!nvgpu_grmgr_is_mig_type_gpu_instance(
+				&g->mig.gpu_instance[index])) {
+			nvgpu_log(g, gpu_dbg_mig, "skip physical instance[%u]",
+				index);
+			continue;
+		}
+
+		/* Set remote swizid for gr */
+		reg_val = nvgpu_readl(g,
+			fb_mmu_smc_eng_cfg_0_r(gr_syspipe->gr_syspipe_id));
+		reg_val &= ~fb_mmu_smc_eng_cfg_0_remote_swizid_m();
+
+		if (enable) {
+			if (gpu_instance->is_memory_partition_supported) {
+				default_remote_swizid =
+					g->mig.gpu_instance[index].gpu_instance_id;
+			}
+			reg_val |= fb_mmu_smc_eng_cfg_0_remote_swizid_f(
+				default_remote_swizid);
+		}
+
+		nvgpu_writel(g,
+			fb_mmu_smc_eng_cfg_0_r(gr_syspipe->gr_syspipe_id),
+			reg_val);
+
+		g->ops.runlist.get_pbdma_info(g,
+				gr_dev->next.rl_pri_base,
+				&pbdma_info);
+
+		for (pbdma_index = 0U; pbdma_index < PBDMA_PER_RUNLIST_SIZE;
+				++pbdma_index) {
+			if (pbdma_info.pbdma_id[pbdma_index] !=
+					NVGPU_INVALID_PBDMA_ID) {
+				pbdma_id_mask |=
+					BIT32(pbdma_info.pbdma_id[pbdma_index]);
+
+				nvgpu_log(g, gpu_dbg_mig,
+					"gr-[%d %d] gpu_instance_id[%u] gr_syspipe_id[%u] "
+						"pbdma_id[%u] pbdma_id_mask[%x] enable[%d] ",
+					index,
+					pbdma_index,
+					g->mig.gpu_instance[index].gpu_instance_id,
+					gr_syspipe->gr_syspipe_id,
+					pbdma_info.pbdma_id[pbdma_index],
+					pbdma_id_mask,
+					enable);
+			}
+		}
+
+		nvgpu_log(g, gpu_dbg_mig,
+			"gr-[%d] gpu_instance_id[%u] gr_syspipe_id[%u] "
+				"gr_instance_id[%u] pbdma_id_mask[%x] reg_val[%x] "
+				 "enable[%d] ",
+			index,
+			g->mig.gpu_instance[index].gpu_instance_id,
+			gr_syspipe->gr_syspipe_id,
+			gr_syspipe->gr_instance_id,
+			pbdma_id_mask, reg_val, enable);
+
+		/* Set remote swizid for lces */
+		for (lce_id = 0U; lce_id < gpu_instance->num_lce;
+				lce_id++) {
+			const struct nvgpu_device *lce =
+				gpu_instance->lce_devs[lce_id];
+
+			reg_val = nvgpu_readl(g,
+				fb_mmu_mmu_eng_id_cfg_r(lce->fault_id));
+			reg_val &= ~fb_mmu_mmu_eng_id_cfg_remote_swizid_m();
+
+			if (enable) {
+				reg_val |= fb_mmu_mmu_eng_id_cfg_remote_swizid_f(
+					default_remote_swizid);
+			}
+
+			g->ops.runlist.get_pbdma_info(g,
+					lce->next.rl_pri_base,
+					&pbdma_info);
+
+			for (pbdma_index = 0U; pbdma_index < PBDMA_PER_RUNLIST_SIZE;
+					++pbdma_index) {
+				if (pbdma_info.pbdma_id[pbdma_index] !=
+						NVGPU_INVALID_PBDMA_ID) {
+					pbdma_id_mask |=
+						BIT32(pbdma_info.pbdma_id[pbdma_index]);
+
+					nvgpu_log(g, gpu_dbg_mig,
+						"lce-[%d %d] gpu_instance_id[%u] gr_syspipe_id[%u] "
+							"pbdma_id[%u] pbdma_id_mask[%x] enable[%d] ",
+						index,
+						pbdma_index,
+						g->mig.gpu_instance[index].gpu_instance_id,
+						gr_syspipe->gr_syspipe_id,
+						pbdma_info.pbdma_id[pbdma_index],
+						pbdma_id_mask, enable);
+				}
+			}
+
+			nvgpu_writel(g,
+				fb_mmu_mmu_eng_id_cfg_r(lce->fault_id),
+				reg_val);
+
+			nvgpu_log(g, gpu_dbg_mig,
+				"lce-[%d] gpu_instance_id[%u] gr_syspipe_id[%u] "
+					"gr_instance_id[%u] engine_id[%u] inst_id[%u] "
+					"fault_id[%u] pbdma_id_mask[%x] reg_val[%x] "
+					"enable[%d] ",
+				index,
+				g->mig.gpu_instance[index].gpu_instance_id,
+				gr_syspipe->gr_syspipe_id,
+				gr_syspipe->gr_instance_id,
+				lce->engine_id, lce->inst_id,
+				lce->fault_id, pbdma_id_mask,
+				reg_val, enable);
+		}
+
+		/* Set remote swizid for its pbdma */
+		while (pbdma_id_mask != 0U) {
+			u32 fault_id;
+			u32 pbdma_id = nvgpu_safe_sub_u32(
+				nvgpu_ffs(pbdma_id_mask), 1UL);
+
+			fault_id =
+				g->ops.pbdma.get_mmu_fault_id(g, pbdma_id);
+
+			reg_val = nvgpu_readl(g,
+				fb_mmu_mmu_eng_id_cfg_r(fault_id));
+			reg_val &= ~fb_mmu_mmu_eng_id_cfg_remote_swizid_m();
+
+			if (enable) {
+				reg_val |= fb_mmu_mmu_eng_id_cfg_remote_swizid_f(
+					default_remote_swizid);
+			}
+
+			nvgpu_writel(g,
+				fb_mmu_mmu_eng_id_cfg_r(fault_id),
+				reg_val);
+
+			nvgpu_log(g, gpu_dbg_mig,
+				"gpu_instance_id[%u] gr_syspipe_id[%u] "
+					"pbdma_id[%u] fault_id[%u] pbdma_id_mask[%x] "
+					"reg_val[%x] enable[%d] ",
+				g->mig.gpu_instance[index].gpu_instance_id,
+				gr_syspipe->gr_syspipe_id,
+				pbdma_id, fault_id, pbdma_id_mask,
+				reg_val, enable);
+
+			pbdma_id_mask ^= BIT32(pbdma_id);
+		}
+	}
+
+	return 0;
+}
+#endif
+
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_ga10b.h b/drivers/gpu/nvgpu/hal/fb/fb_ga10b.h
new file mode 100644
index 000000000..e5a34d4d1
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/fb_ga10b.h
@@ -0,0 +1,63 @@
+/*
+ * GA10B FB
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FB_GA10B_H
+#define NVGPU_FB_GA10B_H
+
+#define VPR_INFO_FETCH_POLL_MS	5U
+#define ALIGN_HI32(x)	nvgpu_safe_sub_u32(32U, (x))
+
+struct gk20a;
+
+void ga10b_fb_init_fs_state(struct gk20a *g);
+void ga10b_fb_init_hw(struct gk20a *g);
+u32 ga10b_fb_get_num_active_ltcs(struct gk20a *g);
+void ga10b_fb_dump_vpr_info(struct gk20a *g);
+void ga10b_fb_dump_wpr_info(struct gk20a *g);
+void ga10b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size);
+int ga10b_fb_vpr_info_fetch(struct gk20a *g);
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
+#if defined(__KERNEL__)
+void ga10b_init_nvlink_soc_credits(struct gk20a *g);
+#else
+static inline void ga10b_init_nvlink_soc_credits(struct gk20a *g)
+{
+
+}
+#endif
+#endif
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+void ga10b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc);
+#endif
+
+#ifdef CONFIG_NVGPU_MIG
+int ga10b_fb_config_veid_smc_map(struct gk20a *g, bool enable);
+int ga10b_fb_set_smc_eng_config(struct gk20a *g, bool enable);
+int ga10b_fb_set_remote_swizid(struct gk20a *g, bool enable);
+#endif
+
+int ga10b_fb_set_atomic_mode(struct gk20a *g);
+
+#endif /* NVGPU_FB_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fb/fb_ga10b_fusa.c
new file mode 100644
index 000000000..4cfbebe2a
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/fb_ga10b_fusa.c
@@ -0,0 +1,313 @@
+/*
+ * GA10B FB
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/errata.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/static_analysis.h>
+
+#include "hal/fb/fb_gm20b.h"
+#include "hal/fb/fb_ga10b.h"
+#include "intr/fb_intr_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_fb_ga10b.h>
+
+#define HSHUB_ID_0	0U
+
+int ga10b_fb_set_atomic_mode(struct gk20a *g)
+{
+	u32 reg_val;
+	u32 num_hshubs = 0U;
+	u32 hshub_ltcs, fbhub_ltcs;
+	u32 i;
+
+	/*
+	 * NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE
+	 * NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2
+	 */
+	reg_val = nvgpu_readl(g, fb_mmu_ctrl_r());
+	reg_val = set_field(reg_val, fb_mmu_ctrl_atomic_capability_mode_m(),
+		fb_mmu_ctrl_atomic_capability_mode_rmw_f());
+	reg_val = set_field(reg_val,
+		fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(),
+		fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f());
+	nvgpu_writel(g, fb_mmu_ctrl_r(), reg_val);
+
+	/* NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW */
+	reg_val = nvgpu_readl(g, fb_fbhub_num_active_ltcs_r());
+	reg_val = set_field(reg_val,
+		fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(),
+		fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f());
+	nvgpu_writel(g, fb_fbhub_num_active_ltcs_r(), reg_val);
+	nvgpu_writel(g, fb_hshub_num_active_ltcs_r(HSHUB_ID_0), reg_val);
+
+	/*
+	 * Note: For iGPU, num_hshubs should be 1.
+	 * For num_hshubs = 1, NVLINK_CAPABILITY bits are invalid and
+	 * are ignored.
+	 */
+	reg_val = nvgpu_readl(g, fb_hshub_prg_config_r(HSHUB_ID_0));
+	num_hshubs = fb_hshub_prg_config_num_hshubs_v(reg_val);
+
+	nvgpu_assert(num_hshubs == 1U);
+
+	/*
+	 * HW expects that SW copies the value of
+	 * FBHUB registers over into HSHUBs since
+	 * they are supposed to have the exact same fields.
+	 */
+	fbhub_ltcs = nvgpu_readl(g, fb_fbhub_num_active_ltcs_r());
+	for (i = 0U; i < num_hshubs; i++) {
+		hshub_ltcs = nvgpu_readl(g, fb_hshub_num_active_ltcs_r(i));
+		if (hshub_ltcs != fbhub_ltcs) {
+			nvgpu_writel(g,
+				fb_hshub_num_active_ltcs_r(i), fbhub_ltcs);
+		}
+	}
+
+	return 0;
+
+}
+
+static void ga10b_fb_check_ltcs_count(struct gk20a *g)
+{
+	u32 reg_val;
+	u32 ltcs_count;
+
+	/*
+	 * Number of active ltcs should be same in below registers
+	 * - pri_ringmaster_enum_ltc_r
+	 * - fb_mmu_num_active_ltcs_r
+	 * - fb_fbhub_num_active_ltcs_r
+	 *
+	 * top_num_ltcs_r gives max number of ltcs. If chip is floorswept
+	 * then max ltcs count may not match active ltcs count.
+	 */
+	ltcs_count = g->ops.priv_ring.enum_ltc(g);
+
+	if (fb_mmu_num_active_ltcs_count_v(
+		nvgpu_readl(g, fb_mmu_num_active_ltcs_r())) != ltcs_count) {
+		nvgpu_err(g,
+			"mmu_num_active_ltcs = %u not equal to enum_ltc() = %u",
+			fb_mmu_num_active_ltcs_count_v(
+				nvgpu_readl(g, fb_mmu_num_active_ltcs_r())),
+			ltcs_count);
+	} else {
+		nvgpu_log(g, gpu_dbg_info, "mmu active ltcs %u",
+			fb_mmu_num_active_ltcs_count_v(
+			nvgpu_readl(g, fb_mmu_num_active_ltcs_r())));
+	}
+
+	reg_val = nvgpu_readl(g, fb_fbhub_num_active_ltcs_r());
+	if (fb_fbhub_num_active_ltcs_count_v(reg_val) != ltcs_count) {
+		nvgpu_err(g,
+			"fbhub active_ltcs = %u != ringmaster_enum_ltc() = %u",
+				fb_fbhub_num_active_ltcs_count_v(reg_val),
+				ltcs_count);
+		/*
+		 * set num_active_ltcs = ltcs count in pri_ringmaster_enum_ltc_r
+		 */
+		if (nvgpu_is_errata_present(g, NVGPU_ERRATA_2969956)) {
+			reg_val = set_field(reg_val,
+				fb_fbhub_num_active_ltcs_count_m(),
+				fb_fbhub_num_active_ltcs_count_f(ltcs_count));
+			nvgpu_writel(g, fb_fbhub_num_active_ltcs_r(), reg_val);
+
+			nvgpu_err(g, "Updated fbhub active ltcs 0x%x",
+				nvgpu_readl(g, fb_fbhub_num_active_ltcs_r()));
+		}
+	} else {
+		nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs 0x%x",
+			nvgpu_readl(g, fb_fbhub_num_active_ltcs_r()));
+	}
+}
+
+void ga10b_fb_init_fs_state(struct gk20a *g)
+{
+	nvgpu_log(g, gpu_dbg_fn, "initialize ga10b fb");
+
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
+	ga10b_init_nvlink_soc_credits(g);
+#endif
+	ga10b_fb_check_ltcs_count(g);
+
+	if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
+		/* Bypass MMU check for non-secure boot. For
+		 * secure-boot,this register write has no-effect
+		 */
+		nvgpu_writel(g, fb_priv_mmu_phy_secure_r(), U32_MAX);
+	}
+}
+
+void ga10b_fb_init_hw(struct gk20a *g)
+{
+
+	gm20b_fb_init_hw(g);
+
+	ga10b_fb_intr_vectorid_init(g);
+
+	if (g->ops.fb.intr.enable != NULL) {
+		g->ops.fb.intr.enable(g);
+	}
+}
+
+u32 ga10b_fb_get_num_active_ltcs(struct gk20a *g)
+{
+	return nvgpu_readl(g, fb_mmu_num_active_ltcs_r());
+}
+
+void ga10b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size)
+{
+	u32 val = 0U;
+	u64 wpr_start = 0U;
+	u64 wpr_end = 0U;
+
+	val = fb_mmu_wpr1_addr_lo_val_v(
+			nvgpu_readl(g, fb_mmu_wpr1_addr_lo_r()));
+	wpr_start = hi32_lo32_to_u64(
+		(val >> ALIGN_HI32(fb_mmu_wpr1_addr_lo_val_alignment_v())),
+		(val << fb_mmu_wpr1_addr_lo_val_alignment_v()));
+
+	val = fb_mmu_wpr1_addr_hi_val_v(
+			nvgpu_readl(g, fb_mmu_wpr1_addr_hi_r()));
+	wpr_end = hi32_lo32_to_u64(
+		(val >> ALIGN_HI32(fb_mmu_wpr1_addr_hi_val_alignment_v())),
+		(val << fb_mmu_wpr1_addr_hi_val_alignment_v()));
+
+	*wpr_base = wpr_start;
+	*wpr_size = nvgpu_safe_sub_u64(wpr_end, wpr_start);
+}
+
+void ga10b_fb_dump_wpr_info(struct gk20a *g)
+{
+	u32 val;
+	u32 allow_read, allow_write;
+	u64 wpr1_addr_lo, wpr1_addr_hi;
+	u64 wpr2_addr_lo, wpr2_addr_hi;
+
+	allow_read = nvgpu_readl(g, fb_mmu_wpr_allow_read_r());
+	allow_write = nvgpu_readl(g, fb_mmu_wpr_allow_write_r());
+
+	val = fb_mmu_wpr1_addr_lo_val_v(nvgpu_readl(g, fb_mmu_wpr1_addr_lo_r()));
+	wpr1_addr_lo = hi32_lo32_to_u64(
+		(val >> ALIGN_HI32(fb_mmu_wpr1_addr_lo_val_alignment_v())),
+		(val << fb_mmu_wpr1_addr_lo_val_alignment_v()));
+
+	val = fb_mmu_wpr1_addr_hi_val_v(nvgpu_readl(g, fb_mmu_wpr1_addr_hi_r()));
+	wpr1_addr_hi = hi32_lo32_to_u64(
+		(val >> ALIGN_HI32(fb_mmu_wpr1_addr_hi_val_alignment_v())),
+		(val << fb_mmu_wpr1_addr_hi_val_alignment_v()));
+
+	val = fb_mmu_wpr2_addr_lo_val_v(nvgpu_readl(g, fb_mmu_wpr2_addr_lo_r()));
+	wpr2_addr_lo = hi32_lo32_to_u64(
+		(val >> ALIGN_HI32(fb_mmu_wpr2_addr_lo_val_alignment_v())),
+		(val << fb_mmu_wpr2_addr_lo_val_alignment_v()));
+
+	val = fb_mmu_wpr2_addr_hi_val_v(nvgpu_readl(g, fb_mmu_wpr2_addr_hi_r()));
+	wpr2_addr_hi = hi32_lo32_to_u64(
+		(val >> ALIGN_HI32(fb_mmu_wpr2_addr_hi_val_alignment_v())),
+		(val << fb_mmu_wpr2_addr_hi_val_alignment_v()));
+
+	nvgpu_err(g, "WPR: allow_read: 0x%08x allow_write: 0x%08x "
+		"wpr1_addr_lo: 0x%08llx wpr1_addr_hi: 0x%08llx "
+		"wpr2_addr_lo: 0x%08llx wpr2_addr_hi: 0x%08llx",
+		allow_read, allow_write,
+		wpr1_addr_lo, wpr1_addr_hi,
+		wpr2_addr_lo, wpr2_addr_hi);
+}
+
+void ga10b_fb_dump_vpr_info(struct gk20a *g)
+{
+	u32 val;
+	u32 cya_lo, cya_hi;
+	u64 addr_lo, addr_hi;
+
+	val = fb_mmu_vpr_addr_lo_val_v(
+		nvgpu_readl(g, fb_mmu_vpr_addr_lo_r()));
+	addr_lo = hi32_lo32_to_u64(
+		(val >> ALIGN_HI32(fb_mmu_vpr_addr_lo_val_alignment_v())),
+		(val << fb_mmu_vpr_addr_lo_val_alignment_v()));
+
+	val = fb_mmu_vpr_addr_hi_val_v(
+		nvgpu_readl(g, fb_mmu_vpr_addr_hi_r()));
+	addr_hi = hi32_lo32_to_u64(
+		(val >> ALIGN_HI32(fb_mmu_vpr_addr_hi_val_alignment_v())),
+		(val << fb_mmu_vpr_addr_hi_val_alignment_v()));
+
+	cya_lo = nvgpu_readl(g, fb_mmu_vpr_cya_lo_r());
+	cya_hi = nvgpu_readl(g, fb_mmu_vpr_cya_hi_r());
+
+	nvgpu_err(g, "VPR: addr_lo: 0x%08llx addr_hi: 0x%08llx "
+		"cya_lo: 0x%08x cya_hi: 0x%08x",
+		addr_lo, addr_hi, cya_lo, cya_hi);
+}
+
+static int ga10b_fb_vpr_mode_fetch_poll(struct gk20a *g, unsigned int poll_ms)
+{
+	struct nvgpu_timeout timeout;
+	int err = 0;
+	u32 val = 0U;
+	u32 delay = POLL_DELAY_MIN_US;
+
+	err = nvgpu_timeout_init(g, &timeout, poll_ms, NVGPU_TIMER_CPU_TIMER);
+	if (err != 0) {
+		nvgpu_err(g, "nvgpu_timeout_init failed err=%d", err);
+		return err;
+	}
+
+	do {
+		val = nvgpu_readl(g, fb_mmu_vpr_mode_r());
+		if (fb_mmu_vpr_mode_fetch_v(val) ==
+		    fb_mmu_vpr_mode_fetch_false_v()) {
+			return 0;
+		}
+
+		nvgpu_usleep_range(delay, delay * 2U);
+		delay = min_t(u32, delay << 1, POLL_DELAY_MAX_US);
+
+	} while (nvgpu_timeout_expired(&timeout) == 0);
+
+	return -ETIMEDOUT;
+}
+
+int ga10b_fb_vpr_info_fetch(struct gk20a *g)
+{
+	int err;
+
+	err = ga10b_fb_vpr_mode_fetch_poll(g, VPR_INFO_FETCH_POLL_MS);
+	if (err != 0) {
+		return err;
+	}
+
+	nvgpu_writel(g, fb_mmu_vpr_mode_r(),
+			fb_mmu_vpr_mode_fetch_true_f());
+
+	err = ga10b_fb_vpr_mode_fetch_poll(g, VPR_INFO_FETCH_POLL_MS);
+	if (err != 0) {
+		nvgpu_err(g, "ga10b_fb_vpr_mode_fetch_poll failed!");
+	}
+	return err;
+}
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_ga10b.h b/drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_ga10b.h
new file mode 100644
index 000000000..271db0496
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_ga10b.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FB_MMU_FAULT_GA10B_H
+#define NVGPU_FB_MMU_FAULT_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void ga10b_fb_handle_mmu_fault(struct gk20a *g, u32 intr_unit_bitmask);
+
+#endif /* NVGPU_FB_MMU_FAULT_GA10B_H */
+
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_ga10b_fusa.c
new file mode 100644
index 000000000..18c76f62d
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_ga10b_fusa.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/types.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/mmu_fault.h>
+#include <nvgpu/cic.h>
+
+#include "hal/fb/fb_mmu_fault_gv11b.h"
+#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
+
+#include "fb_mmu_fault_ga10b.h"
+
+#include "nvgpu/hw/ga10b/hw_fb_ga10b.h"
+
+void ga10b_fb_handle_mmu_fault(struct gk20a *g, u32 intr_unit_bitmask)
+{
+	u32 fault_status = g->ops.fb.read_mmu_fault_status(g);
+
+	nvgpu_log(g, gpu_dbg_intr, "mmu_fault_status = 0x%08x", fault_status);
+
+	if ((intr_unit_bitmask & BIT32(NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT)) != 0) {
+
+		gv11b_fb_handle_dropped_mmu_fault(g, fault_status);
+		gv11b_mm_mmu_fault_handle_other_fault_notify(g, fault_status);
+	}
+
+	if (gv11b_fb_is_fault_buf_enabled(g,
+			NVGPU_MMU_FAULT_NONREPLAY_REG_INDX)) {
+		if ((intr_unit_bitmask &
+			BIT32(NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT)) != 0) {
+
+			gv11b_mm_mmu_fault_handle_nonreplay_replay_fault(g,
+					fault_status,
+					NVGPU_MMU_FAULT_NONREPLAY_REG_INDX);
+
+			/*
+			 * When all the faults are processed,
+			 * GET and PUT will have same value and mmu fault status
+			 * bit will be reset by HW
+			 */
+		}
+
+		if ((intr_unit_bitmask &
+			BIT32(NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR)) != 0) {
+
+			gv11b_fb_handle_nonreplay_fault_overflow(g,
+				 fault_status);
+		}
+	}
+
+#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
+	if (gv11b_fb_is_fault_buf_enabled(g,
+			NVGPU_MMU_FAULT_REPLAY_REG_INDX)) {
+		if ((intr_unit_bitmask &
+			BIT32(NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT)) != 0) {
+
+			gv11b_mm_mmu_fault_handle_nonreplay_replay_fault(g,
+					fault_status,
+					NVGPU_MMU_FAULT_REPLAY_REG_INDX);
+		}
+
+		if ((intr_unit_bitmask &
+			BIT32(NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR)) != 0) {
+
+			gv11b_fb_handle_replay_fault_overflow(g,
+				 fault_status);
+		}
+	}
+#endif
+
+	nvgpu_log(g, gpu_dbg_intr, "clear mmu fault status");
+	g->ops.fb.write_mmu_fault_status(g,
+				fb_mmu_fault_status_valid_clear_f());
+}
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_ga10b.h b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_ga10b.h
new file mode 100644
index 000000000..024956359
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_ga10b.h
@@ -0,0 +1,34 @@
+/*
+ * GA10B FB INTR ECC
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FB_INTR_ECC_GA10B_H
+#define NVGPU_FB_INTR_ECC_GA10B_H
+
+struct gk20a;
+
+void ga10b_fb_intr_handle_ecc_l2tlb(struct gk20a *g, u32 ecc_status);
+void ga10b_fb_intr_handle_ecc_hubtlb(struct gk20a *g, u32 ecc_status);
+void ga10b_fb_intr_handle_ecc_fillunit(struct gk20a *g, u32 ecc_status);
+
+#endif /* NVGPU_FB_INTR_ECC_GA10B_H */
\ No newline at end of file
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_ga10b_fusa.c
new file mode 100644
index 000000000..ea0410003
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_ga10b_fusa.c
@@ -0,0 +1,194 @@
+/*
+ * GA10B FB INTR ECC
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+
+#include "hal/fb/intr/fb_intr_ecc_gv11b.h"
+#include "fb_intr_ecc_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_fb_ga10b.h>
+
+void ga10b_fb_intr_handle_ecc_l2tlb(struct gk20a *g, u32 ecc_status)
+{
+	u32 corrected_cnt, uncorrected_cnt;
+	u32 unique_corrected_delta, unique_uncorrected_delta;
+	u32 unique_corrected_overflow, unique_uncorrected_overflow;
+
+	/*
+	 * The unique counters tracks the instances of ecc (un)corrected errors
+	 * where the present, previous error addresses are different.
+	 */
+	corrected_cnt = nvgpu_readl(g,
+		fb_mmu_l2tlb_ecc_corrected_err_count_r());
+	uncorrected_cnt = nvgpu_readl(g,
+		fb_mmu_l2tlb_ecc_uncorrected_err_count_r());
+
+	unique_corrected_delta =
+		fb_mmu_l2tlb_ecc_corrected_err_count_unique_v(corrected_cnt);
+	unique_uncorrected_delta =
+		fb_mmu_l2tlb_ecc_uncorrected_err_count_unique_v(uncorrected_cnt);
+	unique_corrected_overflow = ecc_status &
+		fb_mmu_l2tlb_ecc_status_corrected_err_unique_counter_overflow_m();
+
+	unique_uncorrected_overflow = ecc_status &
+		fb_mmu_l2tlb_ecc_status_uncorrected_err_unique_counter_overflow_m();
+
+	/* Handle overflow */
+	if (unique_corrected_overflow != 0U) {
+		unique_corrected_delta +=
+			BIT32(fb_mmu_l2tlb_ecc_corrected_err_count_unique_s());
+	}
+	if (unique_uncorrected_overflow != 0U) {
+		unique_uncorrected_delta +=
+			BIT32(fb_mmu_l2tlb_ecc_uncorrected_err_count_unique_s());
+	}
+
+	g->ecc.fb.mmu_l2tlb_ecc_corrected_unique_err_count[0].counter =
+	nvgpu_safe_add_u32(
+		g->ecc.fb.mmu_l2tlb_ecc_corrected_unique_err_count[0].counter,
+		unique_corrected_delta);
+	g->ecc.fb.mmu_l2tlb_ecc_uncorrected_unique_err_count[0].counter =
+	nvgpu_safe_add_u32(
+	       g->ecc.fb.mmu_l2tlb_ecc_uncorrected_unique_err_count[0].counter,
+	       unique_uncorrected_delta);
+
+	if ((unique_corrected_overflow != 0U) || (unique_uncorrected_overflow != 0U)) {
+		nvgpu_info(g, "mmu l2tlb ecc counter overflow!");
+	}
+
+	/*
+	 * Handle the legacy counters.
+	 */
+	gv11b_fb_intr_handle_ecc_l2tlb(g, ecc_status);
+}
+
+void ga10b_fb_intr_handle_ecc_hubtlb(struct gk20a *g, u32 ecc_status)
+{
+	u32 corrected_cnt, uncorrected_cnt;
+	u32 unique_corrected_delta, unique_uncorrected_delta;
+	u32 unique_corrected_overflow, unique_uncorrected_overflow;
+
+	/*
+	 * The unique counters tracks the instances of ecc (un)corrected errors
+	 * where the present, previous error addresses are different.
+	 */
+	corrected_cnt = nvgpu_readl(g,
+		fb_mmu_hubtlb_ecc_corrected_err_count_r());
+	uncorrected_cnt = nvgpu_readl(g,
+		fb_mmu_hubtlb_ecc_uncorrected_err_count_r());
+
+	unique_corrected_delta =
+		fb_mmu_hubtlb_ecc_corrected_err_count_unique_v(corrected_cnt);
+	unique_uncorrected_delta =
+		fb_mmu_hubtlb_ecc_uncorrected_err_count_unique_v(uncorrected_cnt);
+	unique_corrected_overflow = ecc_status &
+		fb_mmu_hubtlb_ecc_status_corrected_err_unique_counter_overflow_m();
+
+	unique_uncorrected_overflow = ecc_status &
+		fb_mmu_hubtlb_ecc_status_uncorrected_err_unique_counter_overflow_m();
+
+	/* Handle overflow */
+	if (unique_corrected_overflow != 0U) {
+		unique_corrected_delta +=
+			BIT32(fb_mmu_hubtlb_ecc_corrected_err_count_unique_s());
+	}
+	if (unique_uncorrected_overflow != 0U) {
+		unique_uncorrected_delta +=
+			BIT32(fb_mmu_hubtlb_ecc_uncorrected_err_count_unique_s());
+	}
+
+	g->ecc.fb.mmu_hubtlb_ecc_corrected_unique_err_count[0].counter =
+	nvgpu_safe_add_u32(
+		g->ecc.fb.mmu_hubtlb_ecc_corrected_unique_err_count[0].counter,
+		unique_corrected_delta);
+	g->ecc.fb.mmu_hubtlb_ecc_uncorrected_unique_err_count[0].counter =
+	nvgpu_safe_add_u32(
+	       g->ecc.fb.mmu_hubtlb_ecc_uncorrected_unique_err_count[0].counter,
+	       unique_uncorrected_delta);
+
+	if ((unique_corrected_overflow != 0U) || (unique_uncorrected_overflow != 0U)) {
+		nvgpu_info(g, "mmu hubtlb ecc counter overflow!");
+	}
+
+	/*
+	 * Handle the legacy counters.
+	 */
+	gv11b_fb_intr_handle_ecc_hubtlb(g, ecc_status);
+}
+
+void ga10b_fb_intr_handle_ecc_fillunit(struct gk20a *g, u32 ecc_status)
+{
+	u32 corrected_cnt, uncorrected_cnt;
+	u32 unique_corrected_delta, unique_uncorrected_delta;
+	u32 unique_corrected_overflow, unique_uncorrected_overflow;
+
+	/*
+	 * The unique counters tracks the instances of ecc (un)corrected errors
+	 * where the present, previous error addresses are different.
+	 */
+	corrected_cnt = nvgpu_readl(g,
+		fb_mmu_fillunit_ecc_corrected_err_count_r());
+	uncorrected_cnt = nvgpu_readl(g,
+		fb_mmu_fillunit_ecc_uncorrected_err_count_r());
+
+	unique_corrected_delta =
+		fb_mmu_fillunit_ecc_corrected_err_count_unique_v(corrected_cnt);
+	unique_uncorrected_delta =
+		fb_mmu_fillunit_ecc_uncorrected_err_count_unique_v(uncorrected_cnt);
+	unique_corrected_overflow = ecc_status &
+		fb_mmu_fillunit_ecc_status_corrected_err_unique_counter_overflow_m();
+
+	unique_uncorrected_overflow = ecc_status &
+		fb_mmu_fillunit_ecc_status_uncorrected_err_unique_counter_overflow_m();
+
+	/* Handle overflow */
+	if (unique_corrected_overflow != 0U) {
+		unique_corrected_delta +=
+			BIT32(fb_mmu_fillunit_ecc_corrected_err_count_unique_s());
+	}
+	if (unique_uncorrected_overflow != 0U) {
+		unique_uncorrected_delta +=
+			BIT32(fb_mmu_fillunit_ecc_uncorrected_err_count_unique_s());
+	}
+
+	g->ecc.fb.mmu_fillunit_ecc_corrected_unique_err_count[0].counter =
+	nvgpu_safe_add_u32(
+		g->ecc.fb.mmu_fillunit_ecc_corrected_unique_err_count[0].counter,
+		unique_corrected_delta);
+	g->ecc.fb.mmu_fillunit_ecc_uncorrected_unique_err_count[0].counter =
+	nvgpu_safe_add_u32(
+	       g->ecc.fb.mmu_fillunit_ecc_uncorrected_unique_err_count[0].counter,
+	       unique_uncorrected_delta);
+
+	if ((unique_corrected_overflow != 0U) || (unique_uncorrected_overflow != 0U)) {
+		nvgpu_info(g, "mmu fillunit ecc counter overflow!");
+	}
+
+	/*
+	 * Handle the legacy counters.
+	 */
+	gv11b_fb_intr_handle_ecc_fillunit(g, ecc_status);
+}
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ga10b.h b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ga10b.h
new file mode 100644
index 000000000..5e4c191b8
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ga10b.h
@@ -0,0 +1,35 @@
+/*
+ * GA10B FB INTR
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FB_INTR_GA10B_H
+#define NVGPU_FB_INTR_GA10B_H
+
+struct gk20a;
+
+void ga10b_fb_intr_vectorid_init(struct gk20a *g);
+void ga10b_fb_intr_enable(struct gk20a *g);
+void ga10b_fb_intr_disable(struct gk20a *g);
+void ga10b_fb_intr_isr(struct gk20a *g, u32 intr_unit_bitmask);
+
+#endif /* NVGPU_FB_INTR_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ga10b_fusa.c
new file mode 100644
index 000000000..8eb9bfcd2
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ga10b_fusa.c
@@ -0,0 +1,133 @@
+/*
+ * GA10B FB
+ *
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/mc.h>
+#include <nvgpu/cic.h>
+
+#include "hal/fb/intr/fb_intr_ecc_gv11b.h"
+#include "hal/fb/fb_mmu_fault_ga10b.h"
+#include "fb_intr_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_fb_ga10b.h>
+
+void ga10b_fb_intr_vectorid_init(struct gk20a *g)
+{
+	u32 ecc_error, info_fault, nonreplay_fault;
+#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
+	u32 replay_fault;
+#endif
+	u32 vectorid;
+
+	ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r());
+	vectorid = fb_mmu_int_vector_ecc_error_vector_v(ecc_error);
+	nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR,
+			&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
+
+	info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r());
+	vectorid = fb_mmu_int_vector_info_fault_vector_v(info_fault);
+	nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT,
+			&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
+
+	nonreplay_fault = nvgpu_readl(g, fb_mmu_int_vector_fault_r(
+				NVGPU_MMU_FAULT_NONREPLAY_REG_INDX));
+	vectorid = fb_mmu_int_vector_fault_notify_v(nonreplay_fault);
+	nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT,
+			&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
+
+	vectorid = fb_mmu_int_vector_fault_error_v(nonreplay_fault);
+	nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR,
+			&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
+
+#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
+	replay_fault = nvgpu_readl(g, fb_mmu_int_vector_fault_r(
+				NVGPU_MMU_FAULT_REPLAY_REG_INDX));
+	vectorid = fb_mmu_int_vector_fault_notify_v(replay_fault);
+	nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT,
+			&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
+
+	vectorid = fb_mmu_int_vector_fault_error_v(replay_fault);
+	nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR,
+			&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
+#endif
+
+	/* TBD hub_access_cntr_intr */
+}
+
+void ga10b_fb_intr_enable(struct gk20a *g)
+{
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR, NVGPU_CIC_INTR_ENABLE);
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT, NVGPU_CIC_INTR_ENABLE);
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT, NVGPU_CIC_INTR_ENABLE);
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR, NVGPU_CIC_INTR_ENABLE);
+#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT, NVGPU_CIC_INTR_ENABLE);
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR, NVGPU_CIC_INTR_ENABLE);
+#endif
+	/* TBD hub_access_cntr_intr */
+}
+
+void ga10b_fb_intr_disable(struct gk20a *g)
+{
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR, NVGPU_CIC_INTR_DISABLE);
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT, NVGPU_CIC_INTR_DISABLE);
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT, NVGPU_CIC_INTR_DISABLE);
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR, NVGPU_CIC_INTR_DISABLE);
+#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT, NVGPU_CIC_INTR_DISABLE);
+	nvgpu_cic_intr_stall_unit_config(g,
+		NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR, NVGPU_CIC_INTR_DISABLE);
+#endif
+	/* TBD hub_access_cntr_intr */
+
+}
+
+void ga10b_fb_intr_isr(struct gk20a *g, u32 intr_unit_bitmask)
+{
+	nvgpu_mutex_acquire(&g->mm.hub_isr_mutex);
+
+	nvgpu_log(g, gpu_dbg_intr, "MMU Fault");
+
+	if ((intr_unit_bitmask & BIT32(NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR)) !=
+			0U) {
+		g->ops.fb.intr.handle_ecc(g);
+	}
+
+	ga10b_fb_handle_mmu_fault(g, intr_unit_bitmask);
+
+	nvgpu_mutex_release(&g->mm.hub_isr_mutex);
+}
diff --git a/drivers/gpu/nvgpu/hal/fb/vab/vab_ga10b.c b/drivers/gpu/nvgpu/hal/fb/vab/vab_ga10b.c
new file mode 100644
index 000000000..5af9dac92
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/vab/vab_ga10b.c
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/bitops.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/io.h>
+#include <nvgpu/kmem.h>
+#include <nvgpu/static_analysis.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/fuse.h>
+#include <nvgpu/fb.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/dma.h>
+
+#include "hal/fb/vab/vab_ga10b.h"
+#include <nvgpu/hw/ga10b/hw_fb_ga10b.h>
+
+#define GA10B_VAB_ENTRY			512U	/* = vab_size * 2 */
+#define GA10B_VAB_WRITE_PACKETS		8U	/* = num_range_checkers */
+#define GA10B_VAB_WRITE_PACKET_DWORDS	8U	/* 512/8 = 64 bytes = 16 words = 8 double words*/
+#define GA10B_VAB_WRITE_PACKET_ACCESS_DWORDS	4U
+
+int ga10b_fb_vab_init(struct gk20a *g)
+{
+	/* - allocate buffer and mapped in bar2
+	 * - single entry is 2K bits i.e. 256 bytes
+	 * - write buffer address to NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_LO_ADDR
+	 * and NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_HI_ADDR
+	 * - write NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_VAL
+	 */
+	int err = 0;
+	size_t num_vab_entries = 2U;
+	struct vm_gk20a *vm = g->mm.bar2.vm;
+	struct nvgpu_mem *vab_buf = &g->mm.vab.buffer;
+	u64 buf_addr = 0ULL;
+
+	if (!nvgpu_mem_is_valid(&g->mm.vab.buffer)) {
+
+		err = nvgpu_dma_alloc_map_sys(vm,
+			num_vab_entries * GA10B_VAB_ENTRY, vab_buf);
+		if (err != 0) {
+			nvgpu_err(g, "Error in vab buffer alloc in bar2 vm ");
+			return -ENOMEM;
+		}
+	}
+	buf_addr = ((u64)(uintptr_t)vab_buf->gpu_va);
+	nvgpu_log(g, gpu_dbg_vab, "buf_addr 0x%llx", buf_addr);
+
+	nvgpu_writel(g, fb_mmu_vidmem_access_bit_buffer_hi_r(),
+		fb_mmu_vidmem_access_bit_buffer_hi_addr_f(u64_hi32(buf_addr)));
+	nvgpu_writel(g, fb_mmu_vidmem_access_bit_buffer_lo_r(),
+		(fb_mmu_vidmem_access_bit_buffer_lo_addr_m() &
+			u64_lo32(buf_addr)));
+	nvgpu_writel(g, fb_mmu_vidmem_access_bit_buffer_size_r(),
+		fb_mmu_vidmem_access_bit_buffer_size_val_f(num_vab_entries));
+
+	return 0;
+}
+
+static int ga10b_fb_vab_config_address_range(struct gk20a *g,
+	u32 num_range_checkers,
+	struct nvgpu_vab_range_checker *vab_range_checker)
+{
+	/*
+	 * - read num_range_checker, verify user passed range_checker_num
+	 * - for each range_checker,
+	 *   - calculate granularity log from actual granularity
+	 *   - drop (granularity_shift_bits + bitmask_size_shift_bits) bits from
+	 *     start address
+	 *   - add granularity and start address lo/hi
+	 */
+	/*
+	 * check range address is not in VPR
+	 */
+	u32 i = 0U;
+	u32 max_range_checkers = fb_mmu_vidmem_access_bit_num_range_checker_v();
+	u32 granularity_shift_bits_base = 16U; /* log(64KB) */
+	u32 granularity_shift_bits = 0U;
+	int err = 0U;
+
+	nvgpu_err(g, " ");
+
+	g->mm.vab.user_num_range_checkers = num_range_checkers;
+	nvgpu_log(g, gpu_dbg_vab, "num_range_checkers %u", num_range_checkers);
+
+	nvgpu_assert(num_range_checkers <= max_range_checkers);
+
+	for (i = 0U; i < num_range_checkers; i++) {
+		if (vab_range_checker[i].granularity_shift <
+			granularity_shift_bits_base) {
+			err = -EINVAL;
+			break;
+		}
+
+		granularity_shift_bits =
+			vab_range_checker[i].granularity_shift -
+			granularity_shift_bits_base;
+
+		nvgpu_log(g, gpu_dbg_vab, "\t%u: granularity_shift 0x%x",
+			i, vab_range_checker[i].granularity_shift);
+		nvgpu_log(g, gpu_dbg_vab, "\t%u: start_phys_addr 0x%llx",
+			i, vab_range_checker[i].start_phys_addr);
+
+		nvgpu_writel(g, fb_mmu_vidmem_access_bit_start_addr_hi_r(i),
+			U32(vab_range_checker[i].start_phys_addr >> 32U));
+
+		nvgpu_writel(g, fb_mmu_vidmem_access_bit_start_addr_lo_r(i),
+			(vab_range_checker[i].start_phys_addr &
+			fb_mmu_vidmem_access_bit_start_addr_lo_val_m()) |
+			fb_mmu_vidmem_access_bit_start_addr_lo_granularity_f(
+				granularity_shift_bits));
+	}
+	return err;
+}
+
+int ga10b_fb_vab_reserve(struct gk20a *g, u32 vab_mode, u32 num_range_checkers,
+	struct nvgpu_vab_range_checker *vab_range_checker)
+{
+	u32 vab_buf_size_reg = 0U;
+	u32 vab_reg = 0U;
+	int err = 0U;
+
+	nvgpu_log_fn(g, " ");
+
+	err = ga10b_fb_vab_config_address_range(g, num_range_checkers,
+		vab_range_checker);
+	if (err != 0) {
+		nvgpu_err(g, "VAB range range checker config failed");
+		goto fail;
+	}
+
+	/*
+	 * - set NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_ENABLE
+	 */
+	vab_buf_size_reg = nvgpu_readl(g,
+		fb_mmu_vidmem_access_bit_buffer_size_r());
+	vab_buf_size_reg = set_field(vab_buf_size_reg,
+		fb_mmu_vidmem_access_bit_buffer_size_enable_m(),
+		fb_mmu_vidmem_access_bit_buffer_size_enable_f(
+			fb_mmu_vidmem_access_bit_buffer_size_enable_true_v()));
+
+	nvgpu_writel(g, fb_mmu_vidmem_access_bit_buffer_size_r(),
+		vab_buf_size_reg);
+
+	/*
+	 * - Update NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT settings
+	 */
+	vab_reg = nvgpu_readl(g, fb_mmu_vidmem_access_bit_r());
+	nvgpu_log(g, gpu_dbg_vab, "vab size %u",
+		fb_mmu_vidmem_access_bit_size_v(vab_reg));
+
+	/* disable_mode_clear: after logging is disabled, MMU clears bitmask */
+	vab_reg = set_field(vab_reg, fb_mmu_vidmem_access_bit_disable_mode_m(),
+		fb_mmu_vidmem_access_bit_disable_mode_f(
+			fb_mmu_vidmem_access_bit_disable_mode_clear_v()));
+
+	/* set NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_MODE to access or dirty */
+	if (vab_mode == NVGPU_VAB_MODE_ACCESS) {
+		vab_reg = set_field(vab_reg, fb_mmu_vidmem_access_bit_mode_m(),
+		fb_mmu_vidmem_access_bit_mode_f(
+			fb_mmu_vidmem_access_bit_mode_access_v()));
+	} else if (vab_mode == NVGPU_VAB_MODE_DIRTY) {
+		vab_reg = set_field(vab_reg, fb_mmu_vidmem_access_bit_mode_m(),
+		fb_mmu_vidmem_access_bit_mode_f(
+			fb_mmu_vidmem_access_bit_mode_dirty_v()));
+	} else {
+		nvgpu_err(g, "Unknown vab mode");
+		err = -EINVAL;
+		goto fail;
+	}
+
+	/* Enable VAB */
+	vab_reg = set_field(vab_reg, fb_mmu_vidmem_access_bit_enable_m(),
+		fb_mmu_vidmem_access_bit_enable_f(
+			fb_mmu_vidmem_access_bit_enable_true_v()));
+
+	nvgpu_writel(g, fb_mmu_vidmem_access_bit_r(), vab_reg);
+
+	/*
+	 * Enable VAB in GPC
+	 */
+	g->ops.gr.vab_init(g, vab_reg);
+
+fail:
+	return err;
+}
+
+int ga10b_fb_vab_dump_and_clear(struct gk20a *g, u64 *user_buf,
+	u64 user_buf_size)
+{
+	/*
+	 * set NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DUMP_TRIGGER
+	 * poll NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DUMP_TRIGGER to be cleared
+	 * clear what? buffer or access bits or buffer_put_ptr
+	 */
+	int err;
+	struct nvgpu_mem *vab_buf = &g->mm.vab.buffer;
+	u64 buffer_offset = 0ULL;
+	u64 req_buf_size = 0U;
+	u32 i = 0U, j = 0U;
+	u32 user_dword_offset = 0U;
+	u32 user_buf_dwords = 0U;
+	u32 vab_size = 0U;
+	u32 vab_dump_reg = 0U;
+	u32 vab_put_ptr = 0U;
+	u32 delay = POLL_DELAY_MIN_US;
+	struct nvgpu_timeout timeout;
+	u32 max_range_checkers = fb_mmu_vidmem_access_bit_num_range_checker_v();
+	u32 trigger_set = fb_mmu_vidmem_access_bit_dump_trigger_f(
+			fb_mmu_vidmem_access_bit_dump_trigger_true_v());
+	u32 trigger_reset = fb_mmu_vidmem_access_bit_dump_trigger_f(
+			fb_mmu_vidmem_access_bit_dump_trigger_false_v());
+	u64 *wr_pkt = nvgpu_kzalloc(g, nvgpu_safe_mult_u32(sizeof(u64),
+			GA10B_VAB_WRITE_PACKET_DWORDS)); /* 64B write packet */
+	u32 valid_wr = 0U;
+	u32 valid_mask = 0x80000000U;
+	u64 valid_offset = 0ULL;
+	u64 vab_offset = 0ULL;
+
+	/* Get buffer address */
+	vab_put_ptr = nvgpu_readl(g, fb_mmu_vidmem_access_bit_buffer_put_r());
+
+	nvgpu_log(g, gpu_dbg_vab, "vab_put_ptr 0x%x", vab_put_ptr);
+
+	buffer_offset = U64(nvgpu_safe_mult_u32(
+			fb_mmu_vidmem_access_bit_buffer_put_ptr_v(vab_put_ptr),
+			GA10B_VAB_ENTRY));
+	nvgpu_log(g, gpu_dbg_vab, "buffer_offset 0x%llx", buffer_offset);
+
+	vab_size = fb_mmu_vidmem_access_bit_size_v(nvgpu_readl(g,
+		fb_mmu_vidmem_access_bit_r()));
+	/* 1024/8 bytes * 2^vab_size */
+	req_buf_size = nvgpu_safe_mult_u64(128ULL, (1ULL << vab_size));
+	/* buffer size will correspond to user range checker count */
+	req_buf_size = (req_buf_size/max_range_checkers) *
+		g->mm.vab.user_num_range_checkers;
+
+	nvgpu_assert(user_buf_size >= req_buf_size);
+
+	/* bytes to dwords */
+	user_buf_dwords = user_buf_size/8;
+
+	/* Set trigger to start vab dump */
+	nvgpu_writel(g, fb_mmu_vidmem_access_bit_dump_r(), trigger_set);
+
+	vab_dump_reg = nvgpu_readl(g, fb_mmu_vidmem_access_bit_dump_r());
+	nvgpu_log(g, gpu_dbg_vab, "vab_dump_reg 0x%x", vab_dump_reg);
+
+	err = nvgpu_timeout_init(g, &timeout, 1000U, NVGPU_TIMER_CPU_TIMER);
+	if (err != 0) {
+		nvgpu_err(g, "Timeout init failed");
+		return err;
+	}
+
+	/* Check if trigger is cleared vab bits collection complete */
+	do {
+		nvgpu_usleep_range(delay, delay * 2U);
+		delay = min_t(u32, delay << 1, POLL_DELAY_MAX_US);
+
+		vab_dump_reg = nvgpu_readl(g, fb_mmu_vidmem_access_bit_dump_r());
+		nvgpu_log(g, gpu_dbg_vab, "vab_dump_reg 0x%x", vab_dump_reg);
+	} while((fb_mmu_vidmem_access_bit_dump_trigger_v(vab_dump_reg) !=
+			trigger_reset) &&
+		(nvgpu_timeout_expired(&timeout) == 0));
+
+	user_dword_offset = 0U;
+
+	for (i = 0U; i < GA10B_VAB_WRITE_PACKETS; i++) {
+		/* Poll valid bit for write packet i */
+		valid_offset = (buffer_offset / 4ULL) +
+			((i+1) * (GA10B_VAB_WRITE_PACKET_DWORDS * 2)) - 1;
+		nvgpu_log(g, gpu_dbg_vab, "Read valid bit at 0x%llx offset",
+			valid_offset);
+
+		do {
+			valid_wr = nvgpu_mem_rd32(g, vab_buf, valid_offset);
+		} while (valid_wr != valid_mask);
+
+		/* Read VAB bits */
+		vab_offset = buffer_offset +
+			(i * GA10B_VAB_WRITE_PACKET_DWORDS * 8U);
+		nvgpu_mem_rd_n(g, vab_buf, vab_offset , (void *)wr_pkt,
+			GA10B_VAB_WRITE_PACKET_DWORDS * 8U);
+
+		/* Copy and print access bits to user buffer */
+		for (j = 0U; j < GA10B_VAB_WRITE_PACKET_DWORDS; j++) {
+
+			if ((user_dword_offset < user_buf_dwords) &&
+			    (j < GA10B_VAB_WRITE_PACKET_ACCESS_DWORDS)) {
+				user_buf[user_dword_offset++] = wr_pkt[j];
+			}
+			nvgpu_log(g, gpu_dbg_vab, "wr_pkt %d: 0x%016llx",
+				j, wr_pkt[j]);
+		}
+
+		/* Clear MSB valid bit to indicate packet read complete */
+		nvgpu_mem_wr32(g, vab_buf, valid_offset,
+			(valid_wr & ~valid_mask));
+	}
+
+	nvgpu_kfree(g, wr_pkt);
+	return 0;
+}
+
+int ga10b_fb_vab_release(struct gk20a *g)
+{
+	/*
+	 * - reset NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_ENABLE
+	 * - reset NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE
+	 */
+	u32 vab_buf_size_reg = 0U;
+	u32 vab_reg = 0U;
+
+	nvgpu_err(g, " ");
+
+	vab_buf_size_reg = nvgpu_readl(g,
+		fb_mmu_vidmem_access_bit_buffer_size_r());
+	vab_buf_size_reg = set_field(vab_buf_size_reg,
+		fb_mmu_vidmem_access_bit_buffer_size_enable_m(),
+		fb_mmu_vidmem_access_bit_buffer_size_enable_f(
+			fb_mmu_vidmem_access_bit_buffer_size_enable_false_v()));
+	nvgpu_writel(g, fb_mmu_vidmem_access_bit_buffer_size_r(), vab_buf_size_reg);
+
+	vab_reg = nvgpu_readl(g, fb_mmu_vidmem_access_bit_r());
+	vab_reg = set_field(vab_reg, fb_mmu_vidmem_access_bit_enable_m(),
+		fb_mmu_vidmem_access_bit_enable_f(
+			fb_mmu_vidmem_access_bit_enable_false_v()));
+	nvgpu_writel(g, fb_mmu_vidmem_access_bit_r(), vab_reg);
+
+	/*
+	 * - Disable VAB in GPC
+	 */
+	g->ops.gr.vab_release(g, vab_reg);
+
+	return 0;
+}
+
+int ga10b_fb_vab_teardown(struct gk20a *g)
+{
+	/*
+	 * free vab buffer
+	 */
+	struct vm_gk20a *vm = g->mm.bar2.vm;
+	struct nvgpu_mem *vab_buf = &g->mm.vab.buffer;
+
+	if (nvgpu_mem_is_valid(vab_buf)) {
+		nvgpu_dma_unmap_free(vm, vab_buf);
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/nvgpu/hal/fb/vab/vab_ga10b.h b/drivers/gpu/nvgpu/hal/fb/vab/vab_ga10b.h
new file mode 100644
index 000000000..6b6427445
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/vab/vab_ga10b.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef HAL_FB_VAB_GA10B_H
+#define HAL_FB_VAB_GA10B_H
+
+struct gk20a;
+struct nvgpu_vab_range_checker;
+
+int ga10b_fb_vab_init(struct gk20a *g);
+int ga10b_fb_vab_reserve(struct gk20a *g, u32 vab_mode, u32 num_range_checkers,
+	struct nvgpu_vab_range_checker *vab_range_checker);
+int ga10b_fb_vab_dump_and_clear(struct gk20a *g, u64 *user_buf,
+	u64 user_buf_size);
+int ga10b_fb_vab_release(struct gk20a *g);
+int ga10b_fb_vab_teardown(struct gk20a *g);
+
+#endif /* HAL_FB_VAB_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_ga100.h b/drivers/gpu/nvgpu/hal/fifo/channel_ga100.h
new file mode 100644
index 000000000..cad0f1476
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/channel_ga100.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef FIFO_CHANNEL_GA100_H
+#define FIFO_CHANNEL_GA100_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+u32 ga100_channel_count(struct gk20a *g);
+
+#endif /* FIFO_CHANNEL_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_ga100_fusa.c b/drivers/gpu/nvgpu/hal/fifo/channel_ga100_fusa.c
new file mode 100644
index 000000000..ede879088
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/channel_ga100_fusa.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#include <nvgpu/log.h>
+#include <nvgpu/gk20a.h>
+
+#include "channel_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_runlist_ga100.h>
+
+u32 ga100_channel_count(struct gk20a *g)
+{
+	u32 num_channels = 0;
+
+	num_channels = ((0x1U) << runlist_channel_config_num_channels_log2_2k_v());
+	nvgpu_log(g, gpu_dbg_info, "Number of channels supported by hw = %u",
+		num_channels);
+
+	return num_channels;
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h
new file mode 100644
index 000000000..b77b2a60d
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef FIFO_CHANNEL_GA10B_H
+#define FIFO_CHANNEL_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_channel;
+struct nvgpu_channel_hw_state;
+
+u32 ga10b_channel_count(struct gk20a *g);
+void ga10b_channel_enable(struct nvgpu_channel *ch);
+void ga10b_channel_disable(struct nvgpu_channel *ch);
+void ga10b_channel_bind(struct nvgpu_channel *ch);
+void ga10b_channel_unbind(struct nvgpu_channel *ch);
+void ga10b_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch,
+					struct nvgpu_channel_hw_state *state);
+void ga10b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch,
+		bool eng, bool pbdma);
+void ga10b_channel_force_ctx_reload(struct nvgpu_channel *ch);
+
+#endif /* FIFO_CHANNEL_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c
new file mode 100644
index 000000000..8fb1ac77b
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#include <nvgpu/channel.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/log.h>
+#include <nvgpu/atomic.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+
+#include <hal/fifo/fifo_utils_ga10b.h>
+#include "channel_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_runlist_ga10b.h>
+
+#define NUM_CHANNELS		512U
+#define CHANNEL_BOUND		1
+#define CHANNEL_UNBOUND		0
+
+u32 ga10b_channel_count(struct gk20a *g)
+{
+	/* Limit number of channels, avoids unnecessary memory allocation */
+	nvgpu_log(g, gpu_dbg_info, "Number of channels supported by hw = %u",
+		((0x1U) << runlist_channel_config_num_channels_log2_2k_v()));
+
+	nvgpu_log(g, gpu_dbg_info, "Number of channels supported by sw = %u",
+		NUM_CHANNELS);
+
+	return NUM_CHANNELS;
+}
+
+void ga10b_channel_enable(struct nvgpu_channel *ch)
+{
+	struct gk20a *g = ch->g;
+	struct nvgpu_runlist *runlist = NULL;
+
+	runlist = ch->runlist;
+
+	nvgpu_chram_bar0_writel(g, runlist, runlist_chram_channel_r(ch->chid),
+		runlist_chram_channel_update_f(
+			runlist_chram_channel_update_enable_channel_v()));
+}
+
+void ga10b_channel_disable(struct nvgpu_channel *ch)
+{
+	struct gk20a *g = ch->g;
+	struct nvgpu_runlist *runlist = NULL;
+
+	runlist = ch->runlist;
+
+	nvgpu_chram_bar0_writel(g, runlist, runlist_chram_channel_r(ch->chid),
+		runlist_chram_channel_update_f(
+			runlist_chram_channel_update_disable_channel_v()));
+}
+
+void ga10b_channel_bind(struct nvgpu_channel *ch)
+{
+	struct gk20a *g = ch->g;
+	struct nvgpu_runlist *runlist = NULL;
+
+	runlist = ch->runlist;
+
+	/* Enable channel */
+	nvgpu_chram_bar0_writel(g, runlist, runlist_chram_channel_r(ch->chid),
+		runlist_chram_channel_update_f(
+			runlist_chram_channel_update_enable_channel_v()));
+
+	nvgpu_atomic_set(&ch->bound, CHANNEL_BOUND);
+}
+
+/*
+ * The instance associated with a channel is specified in the channel's
+ * runlist entry. Ampere has no notion of binding/unbinding channels
+ * to instances. When tearing down a channel or migrating its chid,
+ * after ensuring it is unloaded and unrunnable, SW must clear the
+ * channel's entry in the channel RAM by writing
+ * NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL to NV_CHRAM_CHANNEL(chid).
+ *
+ * Note: From GA10x onwards, channel RAM clear is one of the
+ * important steps in RC recovery and channel removal.
+ * Channel Removal Sequence:
+ * SW may also need to remove some channels from a TSG in order to
+ * support shutdown of a specific subcontext in that TSG.  In this case
+ * it's important for SW to take care to properly clear the channel RAM
+ * state of the removed channels and to transfer CTX_RELOAD to some
+ * other channel that will not be removed. The procedure is as follows:
+ * 1. Disable all the channels in the TSG (or disable scheduling on the
+ *    runlist)
+ * 2. Preempt the TSG (or runlist)
+ * 3. Poll for completion of the preempt (possibly making use of the
+ *    appropriate PREEMPT interrupt to avoid the spin loop).
+ *    While polling, SW must check for interrupts and hangs.
+ *    If a teardown is required, stop following this sequence and
+ *    continue with the teardown sequence from step 4.
+ * 4. Read the channel RAM for the removed channels to see if CTX_RELOAD
+ *    is set on any of them. If so, force CTX_RELOAD on some other
+ *    channel that isn't being removed by writing
+ *    NV_CHRAM_CHANNEL_UPDATE_FORCE_CTX_RELOAD to chosen channel's chram
+ * 5. Write NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL to removed channels.
+ *    This ensures the channels are ready for reuse without confusing
+ *    esched's tracking.
+ * 6. Submit a new runlist without the removed channels and reenable
+ *    scheduling if disabled in step 1.
+ * 7. Re-enable all the non-removed channels in the TSG.
+ */
+void ga10b_channel_unbind(struct nvgpu_channel *ch)
+{
+	struct gk20a *g = ch->g;
+	struct nvgpu_runlist *runlist = NULL;
+
+	runlist = ch->runlist;
+
+	if (nvgpu_atomic_cmpxchg(&ch->bound, CHANNEL_BOUND, CHANNEL_UNBOUND) !=
+			0) {
+		nvgpu_chram_bar0_writel(g, runlist,
+			runlist_chram_channel_r(ch->chid),
+			runlist_chram_channel_update_f(
+			runlist_chram_channel_update_clear_channel_v()));
+	}
+}
+
+static const char * const chram_status_str[] = {
+	[runlist_chram_channel_status_idle_v()] = "idle",
+	[runlist_chram_channel_status_pending_v()] = "pending",
+	[runlist_chram_channel_status_pending_ctx_reload_v()] =
+		"pending_ctx_reload",
+	[runlist_chram_channel_status_pending_acquire_fail_v()] =
+		"pending_acquire_fail",
+	[runlist_chram_channel_status_pending_acquire_fail_ctx_reload_v()] =
+		"pending_acq_fail_ctx_reload",
+	[runlist_chram_channel_status_pbdma_busy_v()] = "pbdma_busy",
+	[runlist_chram_channel_status_pbdma_busy_and_eng_busy_v()] =
+		"pbdma_and_eng_busy",
+	[runlist_chram_channel_status_eng_busy_v()] = "eng_busy",
+	[runlist_chram_channel_status_eng_busy_pending_acquire_fail_v()] =
+		"eng_busy_pending_acquire_fail",
+	[runlist_chram_channel_status_eng_busy_pending_v()] = "eng_busy_pending",
+	[runlist_chram_channel_status_pbdma_busy_ctx_reload_v()] =
+		"pbdma_busy_ctx_reload",
+	[runlist_chram_channel_status_pbdma_busy_eng_busy_ctx_reload_v()] =
+		"pbdma_and_eng_busy_ctx_reload",
+	[runlist_chram_channel_status_busy_ctx_reload_v()] = "busy_ctx_reload",
+	[runlist_chram_channel_status_eng_busy_pending_ctx_reload_v()] =
+		"eng_busy_pending_ctx_reload",
+	[runlist_chram_channel_status_eng_busy_pending_acquire_fail_ctx_reload_v()] =
+		"eng_busy_pending_acq_fail_ctx_reload",
+};
+
+void ga10b_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch,
+			struct nvgpu_channel_hw_state *state)
+{
+	struct nvgpu_runlist *runlist = NULL;
+	u32 reg = 0U;
+	u32 status = 0U;
+
+	runlist = ch->runlist;
+
+	reg = nvgpu_chram_bar0_readl(g, runlist,
+			runlist_chram_channel_r(ch->chid));
+	status = runlist_chram_channel_status_v(reg);
+
+	state->next = runlist_chram_channel_next_v(reg) ==
+				runlist_chram_channel_next_true_v();
+	state->enabled = runlist_chram_channel_enable_v(reg) ==
+				runlist_chram_channel_enable_in_use_v();
+        state->ctx_reload = runlist_chram_channel_ctx_reload_v(reg) ==
+				runlist_chram_channel_ctx_reload_true_v();
+        state->busy = runlist_chram_channel_busy_v(reg) ==
+				runlist_chram_channel_busy_true_v();
+	state->pending_acquire =
+		(status ==
+			runlist_chram_channel_status_pending_acquire_fail_v()) ||
+		(status ==
+			runlist_chram_channel_status_eng_busy_pending_acquire_fail_ctx_reload_v()) ||
+		(status ==
+			runlist_chram_channel_status_pending_acquire_fail_ctx_reload_v());
+
+	state->eng_faulted = runlist_chram_channel_eng_faulted_v(reg) ==
+				runlist_chram_channel_eng_faulted_true_v();
+	state->status_string = chram_status_str[status] == NULL ? "N/A" :
+						chram_status_str[status];
+
+	nvgpu_log_info(g, "Channel id:%d state next:%s enabled:%s ctx_reload:%s"
+		" busy:%s pending_acquire:%s eng_faulted:%s status_string:%s",
+		ch->chid,
+		state->next ? "true" : "false",
+		state->enabled ? "true" : "false",
+		state->ctx_reload ? "true" : "false",
+		state->busy ? "true" : "false",
+		state->pending_acquire ? "true" : "false",
+		state->eng_faulted ? "true" : "false", state->status_string);
+}
+
+void ga10b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch,
+		bool eng, bool pbdma)
+{
+	struct nvgpu_runlist *runlist = NULL;
+
+	runlist = ch->runlist;
+
+	if (eng) {
+		nvgpu_chram_bar0_writel(g, runlist,
+			runlist_chram_channel_r(ch->chid),
+			runlist_chram_channel_update_f(
+			runlist_chram_channel_update_reset_eng_faulted_v()));
+	}
+	if (pbdma) {
+		nvgpu_chram_bar0_writel(g, runlist,
+			runlist_chram_channel_r(ch->chid),
+			runlist_chram_channel_update_f(
+			runlist_chram_channel_update_reset_pbdma_faulted_v()));
+	}
+
+	/*
+	 * At this point the fault is handled and *_FAULTED bit is cleared.
+	 * However, if the runlist has gone idle, then the esched unit
+	 * will remain idle and will not schedule the runlist unless its
+	 * doorbell is written or a new runlist is submitted. Hence, ring the
+	 * runlist doorbell once the fault is cleared.
+	 */
+	g->ops.usermode.ring_doorbell(ch);
+
+}
+
+void ga10b_channel_force_ctx_reload(struct nvgpu_channel *ch)
+{
+	struct gk20a *g = ch->g;
+	struct nvgpu_runlist *runlist = NULL;
+
+	runlist = ch->runlist;
+
+	nvgpu_chram_bar0_writel(g, runlist, runlist_chram_channel_r(ch->chid),
+		runlist_chram_channel_update_f(
+			runlist_chram_channel_update_force_ctx_reload_v()));
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b.h
new file mode 100644
index 000000000..b088a21dd
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_CTXSW_TIMEOUT_GA10B_H
+#define NVGPU_CTXSW_TIMEOUT_GA10B_H
+
+#include <nvgpu/types.h>
+
+#define MS_TO_US	1000U
+
+struct gk20a;
+
+void ga10b_fifo_ctxsw_timeout_enable(struct gk20a *g, bool enable);
+void ga10b_fifo_ctxsw_timeout_isr(struct gk20a *g,
+			struct nvgpu_runlist *runlist);
+
+#endif /* NVGPU_CTXSW_TIMEOUT_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c
new file mode 100644
index 000000000..d5813de8e
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/log.h>
+#include <nvgpu/io.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/ptimer.h>
+#include <nvgpu/tsg.h>
+#include <nvgpu/rc.h>
+#include <nvgpu/nvgpu_err.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/device.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/static_analysis.h>
+
+#include "fifo_utils_ga10b.h"
+#include "ctxsw_timeout_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_runlist_ga10b.h>
+
+static void ga10b_fifo_ctxsw_timeout_clear_and_enable(struct gk20a *g,
+			u32 timeout)
+{
+	u32 i, rleng;
+	struct nvgpu_runlist *runlist;
+	const struct nvgpu_device *dev;
+
+	for (i = 0U; i < g->fifo.num_runlists; i++) {
+		runlist = &g->fifo.active_runlists[i];
+		for (rleng = 0U;
+			rleng < runlist_engine_ctxsw_timeout_config__size_1_v();
+			rleng++) {
+			/* clear ctxsw timeout interrupt */
+			nvgpu_runlist_writel(g, runlist,
+				runlist_intr_0_r(),
+				runlist_intr_0_ctxsw_timeout_eng_reset_f(rleng));
+
+			dev = runlist->nvgpu_next.rl_dev_list[rleng];
+			if (dev == NULL) {
+				continue;
+			}
+			/* enable ctxsw timeout interrupt */
+			nvgpu_runlist_writel(g, runlist,
+				runlist_engine_ctxsw_timeout_config_r(
+				dev->next.rleng_id),
+				timeout);
+			nvgpu_log_info(g, "ctxsw timeout enable "
+				       "rleng: %u timeout_config_val: 0x%08x",
+				       dev->next.rleng_id, timeout);
+		}
+	}
+}
+
+static void ga10b_fifo_ctxsw_timeout_disable_and_clear(struct gk20a *g,
+			u32 timeout)
+{
+	u32 i, rleng;
+	struct nvgpu_runlist *runlist;
+
+	for (i = 0U; i < g->fifo.num_runlists; i++) {
+		runlist = &g->fifo.active_runlists[i];
+		for (rleng = 0U;
+			rleng < runlist_engine_ctxsw_timeout_config__size_1_v();
+			rleng++) {
+			/* disable ctxsw timeout interrupt */
+			nvgpu_runlist_writel(g, runlist,
+				runlist_engine_ctxsw_timeout_config_r(rleng),
+				timeout);
+			/* clear ctxsw timeout interrupt */
+			nvgpu_runlist_writel(g, runlist,
+				runlist_intr_0_r(),
+				runlist_intr_0_ctxsw_timeout_eng_reset_f(rleng));
+		}
+	}
+}
+
+void ga10b_fifo_ctxsw_timeout_enable(struct gk20a *g, bool enable)
+{
+	u32 timeout;
+
+	nvgpu_log_fn(g, " ");
+
+	if (enable) {
+		if (nvgpu_platform_is_silicon(g)) {
+			timeout = nvgpu_safe_mult_u32(
+					g->ctxsw_timeout_period_ms, MS_TO_US);
+			timeout = scale_ptimer(timeout,
+				ptimer_scalingfactor10x(g->ptimer_src_freq));
+			timeout =
+			 runlist_engine_ctxsw_timeout_config_period_f(timeout) |
+			 runlist_engine_ctxsw_timeout_config_detection_enabled_f();
+		} else {
+			timeout =
+			 runlist_engine_ctxsw_timeout_config_period_max_f() |
+			 runlist_engine_ctxsw_timeout_config_detection_enabled_f();
+		}
+		ga10b_fifo_ctxsw_timeout_clear_and_enable(g, timeout);
+
+	} else {
+		timeout =
+			runlist_engine_ctxsw_timeout_config_detection_disabled_f();
+		timeout |=
+			runlist_engine_ctxsw_timeout_config_period_max_f();
+
+		ga10b_fifo_ctxsw_timeout_disable_and_clear(g, timeout);
+	}
+}
+
+static u32 ga10b_fifo_ctxsw_timeout_info(struct gk20a *g,
+		struct nvgpu_runlist *runlist,
+		u32 rleng_id, u32 *info_status)
+{
+	u32 tsgid = NVGPU_INVALID_TSG_ID;
+	u32 info;
+	u32 ctx_status;
+
+	info = nvgpu_runlist_readl(g, runlist,
+			 runlist_engine_ctxsw_timeout_info_r(rleng_id));
+
+	/*
+	 * ctxsw_state and tsgid are snapped at the point of the timeout and
+	 * will not change while the corresponding INTR_CTXSW_TIMEOUT_ENGINE bit
+	 * is PENDING.
+	 */
+	ctx_status = runlist_engine_ctxsw_timeout_info_ctxsw_state_v(info);
+	if (ctx_status ==
+		runlist_engine_ctxsw_timeout_info_ctxsw_state_load_v()) {
+
+		tsgid = runlist_engine_ctxsw_timeout_info_next_tsgid_v(info);
+	} else if ((ctx_status ==
+			runlist_engine_ctxsw_timeout_info_ctxsw_state_switch_v()) ||
+		(ctx_status ==
+			runlist_engine_ctxsw_timeout_info_ctxsw_state_save_v())) {
+
+		tsgid = runlist_engine_ctxsw_timeout_info_prev_tsgid_v(info);
+	} else {
+		nvgpu_log_info(g, "ctxsw_timeout_info_ctxsw_state: 0x%08x",
+			ctx_status);
+	}
+	nvgpu_log_info(g, "ctxsw timeout info: tsgid = %d", tsgid);
+
+	/*
+	 * STATUS indicates whether the context request ack was eventually
+	 * received and whether a subsequent request timed out.  This field is
+	 * updated live while the corresponding INTR_CTXSW_TIMEOUT_ENGINE bit
+	 * is PENDING. STATUS starts in AWAITING_ACK, and progresses to
+	 * ACK_RECEIVED and finally ends with DROPPED_TIMEOUT.
+	 *
+	 * AWAITING_ACK - context request ack still not returned from engine.
+	 * ENG_WAS_RESET - The engine was reset via a PRI write to NV_PMC_ENABLE
+	 * or NV_PMC_ELPG_ENABLE prior to receiving the ack.  Host will not
+	 * expect ctx ack to return, but if it is already in flight, STATUS will
+	 * transition shortly to ACK_RECEIVED unless the interrupt is cleared
+	 * first.  Once the engine is reset, additional context switches can
+	 * occur; if one times out, STATUS will transition to DROPPED_TIMEOUT
+	 * if the interrupt isn't cleared first.
+	 * ACK_RECEIVED - The ack for the timed-out context request was
+	 * received between the point of the timeout and this register being
+	 * read.  Note this STATUS can be reported during the load stage of the
+	 * same context switch that timed out if the timeout occurred during the
+	 * save half of a context switch.  Additional context requests may have
+	 * completed or may be outstanding, but no further context timeout has
+	 * occurred.  This simplifies checking for spurious context switch
+	 * timeouts.
+	 * DROPPED_TIMEOUT - The originally timed-out context request acked,
+	 * but a subsequent context request then timed out.
+	 * Information about the subsequent timeout is not stored; in fact, that
+	 * context request may also have already been acked by the time SW
+	 * SW reads this register.  If not, there is a chance SW can get the
+	 * dropped information by clearing the corresponding
+	 * INTR_CTXSW_TIMEOUT_ENGINE bit and waiting for the timeout to occur
+	 * again. Note, however, that if the engine does time out again,
+	 * it may not be from the  original request that caused the
+	 * DROPPED_TIMEOUT state, as that request may
+	 * be acked in the interim.
+	 */
+	*info_status = runlist_engine_ctxsw_timeout_info_status_v(info);
+	if (*info_status ==
+		 runlist_engine_ctxsw_timeout_info_status_ack_received_v()) {
+
+		nvgpu_log_info(g, "ctxsw timeout info: ack received");
+		/* no need to recover */
+		tsgid = NVGPU_INVALID_TSG_ID;
+	} else if (*info_status ==
+		runlist_engine_ctxsw_timeout_info_status_dropped_timeout_v()) {
+
+		nvgpu_log_info(g, "ctxsw timeout info: dropped timeout");
+		/* no need to recover */
+		tsgid = NVGPU_INVALID_TSG_ID;
+	} else {
+		nvgpu_log_info(g, "ctxsw timeout info status: 0x%08x",
+			*info_status);
+	}
+
+	return tsgid;
+}
+
+void ga10b_fifo_ctxsw_timeout_isr(struct gk20a *g,
+			struct nvgpu_runlist *runlist)
+{
+	u32 rleng, reg_val, timeout;
+	u32 active_eng_id;
+	u32 ms = 0U;
+	bool recover = false;
+	u32 info_status;
+	u32 tsgid = NVGPU_INVALID_TSG_ID;
+	const struct nvgpu_device *dev;
+	struct nvgpu_tsg *tsg = NULL;
+
+#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
+	bool debug_dump = false;
+	const char *const ctxsw_timeout_status_desc[] = {
+		"awaiting ack",
+		"eng was reset",
+		"ack received",
+		"dropped timeout"
+	};
+#endif
+
+	for (rleng = 0U;
+		rleng < runlist_engine_ctxsw_timeout_info__size_1_v();
+		rleng++) {
+		reg_val = nvgpu_runlist_readl(g, runlist, runlist_intr_0_r());
+		if ((reg_val &
+			runlist_intr_0_ctxsw_timeout_eng_pending_f(rleng))
+				== 0U) {
+			/* ctxsw timeout not pending for this rleng */
+			continue;
+		}
+		dev = runlist->nvgpu_next.rl_dev_list[rleng];
+		if (dev == NULL) {
+			nvgpu_err(g, "ctxsw timeout for rleng: %u but "
+				"dev is invalid", rleng);
+			/* interupt will still be cleared */
+			continue;
+		}
+		/* dump ctxsw timeout for rleng. useful for debugging */
+		reg_val = nvgpu_runlist_readl(g, runlist,
+			runlist_engine_ctxsw_timeout_config_r(
+			dev->next.rleng_id));
+		timeout = runlist_engine_ctxsw_timeout_config_period_v(reg_val);
+		nvgpu_log_info(g, "rleng: %u ctxsw timeout period = 0x%x",
+			dev->next.rleng_id, timeout);
+
+		/* handle ctxsw timeout */
+		tsgid = ga10b_fifo_ctxsw_timeout_info(g, runlist, rleng,
+						&info_status);
+		tsg = nvgpu_tsg_check_and_get_from_id(g, tsgid);
+		if (tsg == NULL) {
+			continue;
+		}
+
+		nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
+				0, GPU_HOST_PFIFO_CTXSW_TIMEOUT_ERROR, tsgid);
+
+#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
+		recover = g->ops.tsg.check_ctxsw_timeout(tsg, &debug_dump, &ms);
+		if (recover) {
+			const char *info_status_str = "invalid";
+			if (info_status <
+				ARRAY_SIZE(ctxsw_timeout_status_desc)) {
+				info_status_str =
+				ctxsw_timeout_status_desc[info_status];
+			}
+			active_eng_id = dev->engine_id;
+			nvgpu_err(g, "ctxsw timeout error: "
+				"active engine id =%u, %s=%d, info: %s ms=%u",
+				active_eng_id, "tsg", tsgid, info_status_str,
+				ms);
+			if (active_eng_id != NVGPU_INVALID_ENG_ID) {
+				nvgpu_rc_ctxsw_timeout(g, BIT32(active_eng_id),
+					tsg, debug_dump);
+			}
+			continue;
+		}
+#endif
+		nvgpu_log_info(g, "fifo is waiting for ctxsw switch: "
+			"for %d ms, %s=%d", ms, "tsg", tsgid);
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b.h
new file mode 100644
index 000000000..47a72e6db
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_ENGINE_STATUS_GA10B_H
+#define NVGPU_ENGINE_STATUS_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_engine_status_info;
+
+void ga10b_read_engine_status_info(struct gk20a *g, u32 engine_id,
+		struct nvgpu_engine_status_info *status);
+
+#endif /* NVGPU_ENGINE_STATUS_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b_fusa.c
new file mode 100644
index 000000000..ca531d1e3
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b_fusa.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/debug.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/engine_status.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/device.h>
+#include <nvgpu/fifo.h>
+
+#include "engine_status_ga10b.h"
+#include <nvgpu/hw/ga10b/hw_runlist_ga10b.h>
+
+static void populate_invalid_ctxsw_status_info(
+		struct nvgpu_engine_status_info *status_info)
+{
+	status_info->ctx_id = ENGINE_STATUS_CTX_ID_INVALID;
+	status_info->ctx_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID;
+	status_info->ctx_next_id =
+		ENGINE_STATUS_CTX_NEXT_ID_INVALID;
+	status_info->ctx_next_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID;
+	status_info->ctxsw_status = NVGPU_CTX_STATUS_INVALID;
+}
+
+static void populate_valid_ctxsw_status_info(
+		struct nvgpu_engine_status_info *status_info)
+{
+	status_info->ctx_id =
+		runlist_engine_status0_tsgid_v(status_info->reg_data);
+	status_info->ctx_id_type = ENGINE_STATUS_CTX_ID_TYPE_TSGID;
+	status_info->ctx_next_id =
+		ENGINE_STATUS_CTX_NEXT_ID_INVALID;
+	status_info->ctx_next_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID;
+	status_info->ctxsw_status = NVGPU_CTX_STATUS_VALID;
+}
+
+static void populate_load_ctxsw_status_info(
+		struct nvgpu_engine_status_info *status_info)
+{
+	status_info->ctx_id = ENGINE_STATUS_CTX_ID_INVALID;
+	status_info->ctx_id_type = ENGINE_STATUS_CTX_ID_TYPE_INVALID;
+	status_info->ctx_next_id =
+		runlist_engine_status0_next_tsgid_v(status_info->reg_data);
+	status_info->ctx_next_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_TSGID;
+	status_info->ctxsw_status = NVGPU_CTX_STATUS_CTXSW_LOAD;
+}
+
+static void populate_save_ctxsw_status_info(
+		struct nvgpu_engine_status_info *status_info)
+{
+	status_info->ctx_id =
+		runlist_engine_status0_tsgid_v(status_info->reg_data);
+	status_info->ctx_id_type = ENGINE_STATUS_CTX_ID_TYPE_TSGID;
+	status_info->ctx_next_id =
+		ENGINE_STATUS_CTX_NEXT_ID_INVALID;
+	status_info->ctx_next_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID;
+	status_info->ctxsw_status = NVGPU_CTX_STATUS_CTXSW_SAVE;
+}
+
+static void populate_switch_ctxsw_status_info(
+		struct nvgpu_engine_status_info *status_info)
+{
+	status_info->ctx_id =
+		runlist_engine_status0_tsgid_v(status_info->reg_data);
+	status_info->ctx_id_type = ENGINE_STATUS_CTX_ID_TYPE_TSGID;
+	status_info->ctx_next_id =
+		runlist_engine_status0_next_tsgid_v(status_info->reg_data);
+	status_info->ctx_next_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_TSGID;
+	status_info->ctxsw_status = NVGPU_CTX_STATUS_CTXSW_SWITCH;
+}
+
+void ga10b_read_engine_status_info(struct gk20a *g, u32 engine_id,
+		struct nvgpu_engine_status_info *status)
+{
+	u32 engine_reg0_data;
+	u32 engine_reg1_data;
+	u32 ctxsw_state;
+	const struct nvgpu_device *dev;
+
+	(void) memset(status, 0U, sizeof(*status));
+
+	if (!nvgpu_engine_check_valid_id(g, engine_id)) {
+		/* just return NULL info */
+		return;
+	}
+
+	dev = g->fifo.host_engines[engine_id];
+
+	engine_reg0_data = nvgpu_readl(g, nvgpu_safe_add_u32(
+		dev->next.rl_pri_base,
+		runlist_engine_status0_r(dev->next.rleng_id)));
+
+	engine_reg1_data = nvgpu_readl(g, nvgpu_safe_add_u32(
+		dev->next.rl_pri_base,
+		runlist_engine_status1_r(dev->next.rleng_id)));
+
+	status->reg_data = engine_reg0_data;
+	status->nvgpu_next.reg1_data = engine_reg1_data;
+
+	/* populate the engine_state enum */
+	status->is_busy = runlist_engine_status0_engine_v(engine_reg0_data) ==
+			runlist_engine_status0_engine_busy_v();
+
+	/* populate the engine_faulted_state enum */
+	status->is_faulted =
+			runlist_engine_status0_faulted_v(engine_reg0_data) ==
+			runlist_engine_status0_faulted_true_v();
+
+	/* populate the ctxsw_in_progress_state */
+	status->ctxsw_in_progress = ((engine_reg0_data &
+			runlist_engine_status0_ctxsw_in_progress_f()) != 0U);
+
+	/* populate the ctxsw related info */
+	ctxsw_state = runlist_engine_status0_ctx_status_v(engine_reg0_data);
+
+	status->ctxsw_state = ctxsw_state;
+
+	/* check for ctx_status switch/load/save before valid */
+	if (ctxsw_state ==
+			runlist_engine_status0_ctx_status_switch_v()) {
+		populate_switch_ctxsw_status_info(status);
+	} else if (ctxsw_state ==
+			runlist_engine_status0_ctx_status_load_v()) {
+		populate_load_ctxsw_status_info(status);
+	} else if (ctxsw_state ==
+			runlist_engine_status0_ctx_status_save_v()) {
+		populate_save_ctxsw_status_info(status);
+	} else if (ctxsw_state == runlist_engine_status0_ctx_status_valid_v()) {
+		populate_valid_ctxsw_status_info(status);
+	} else {
+		populate_invalid_ctxsw_status_info(status);
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/fifo_ga10b.h
new file mode 100644
index 000000000..cef1d26d3
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/fifo_ga10b.h
@@ -0,0 +1,36 @@
+/*
+ * GA10B Fifo
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FIFO_GA10B_H
+#define NVGPU_FIFO_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+int ga10b_init_fifo_reset_enable_hw(struct gk20a *g);
+int ga10b_init_fifo_setup_hw(struct gk20a *g);
+u32 ga10b_fifo_mmu_fault_id_to_pbdma_id(struct gk20a *g, u32 mmu_fault_id);
+
+#endif /* NVGPU_FIFO_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/fifo_ga10b_fusa.c
new file mode 100644
index 000000000..8a24adda3
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/fifo_ga10b_fusa.c
@@ -0,0 +1,154 @@
+/*
+ * GA10B Fifo
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/power_features/cg.h>
+
+#include <nvgpu/hw/ga10b/hw_runlist_ga10b.h>
+#include <nvgpu/hw/ga10b/hw_ctrl_ga10b.h>
+
+#include "fifo_utils_ga10b.h"
+#include "fifo_ga10b.h"
+#include "fifo_intr_ga10b.h"
+
+static void enable_fifo_interrupts(struct gk20a *g)
+{
+	g->ops.fifo.intr_top_enable(g, NVGPU_CIC_INTR_ENABLE);
+	g->ops.fifo.intr_0_enable(g, true);
+	g->ops.fifo.intr_1_enable(g, true);
+}
+
+int ga10b_init_fifo_reset_enable_hw(struct gk20a *g)
+{
+	int err;
+
+	nvgpu_log_fn(g, " ");
+
+	/* enable pmc pfifo */
+	err = nvgpu_mc_reset_units(g, NVGPU_UNIT_FIFO);
+	if (err != 0) {
+		nvgpu_err(g, "Failed to reset FIFO unit");
+	}
+
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+	if (g->ops.mc.elpg_enable != NULL) {
+		g->ops.mc.elpg_enable(g);
+	}
+#endif
+
+	nvgpu_cg_slcg_ce2_load_enable(g);
+
+	nvgpu_cg_slcg_fifo_load_enable(g);
+
+	nvgpu_cg_blcg_fifo_load_enable(g);
+
+	if (g->ops.pbdma.setup_hw != NULL) {
+		g->ops.pbdma.setup_hw(g);
+	}
+
+	if (g->ops.pbdma.pbdma_force_ce_split != NULL) {
+		g->ops.pbdma.pbdma_force_ce_split(g);
+	}
+
+	nvgpu_log_fn(g, "done");
+
+	return 0;
+}
+
+static void ga10b_fifo_config_userd_writeback_timer(struct gk20a *g)
+{
+	struct nvgpu_runlist *runlist = NULL;
+	u32 reg_val = 0U;
+	u32 i = 0U;
+	u32 max_runlists = g->fifo.max_runlists;
+
+	for (i = 0U; i < max_runlists; i++) {
+		runlist = g->fifo.runlists[i];
+		if (runlist == NULL) {
+			continue;
+		}
+
+		reg_val = runlist_userd_writeback_timescale_0_f() |
+			runlist_userd_writeback_timer_100us_f();
+
+		nvgpu_runlist_writel(g, runlist, runlist_userd_writeback_r(),
+				reg_val);
+	}
+}
+
+int ga10b_init_fifo_setup_hw(struct gk20a *g)
+{
+	struct nvgpu_fifo *f = &g->fifo;
+
+	nvgpu_log_fn(g, " ");
+
+	/*
+	 * Current Flow:
+	 * Nvgpu Init sequence:
+	 * g->ops.fifo.reset_enable_hw
+	 * ....
+	 * g->ops.fifo.fifo_init_support
+	 *
+	 * Fifo Init Sequence called from g->ops.fifo.fifo_init_support:
+	 * fifo.reset_enable_hw   -> enables interrupts
+	 * fifo.fifo_init_support -> fifo.setup_sw (Sets up runlist info)
+	 * fifo.fifo_init_support -> fifo.init_fifo_setup_hw
+	 *
+	 * Runlist info is required for getting vector id and enabling
+	 * interrupts at top level.
+	 * Get vector ids before enabling interrupts at top level to make sure
+	 * vectorids are initialized in nvgpu_mc struct before intr_top_enable
+	 * is called.
+	 */
+	ga10b_fifo_runlist_intr_vectorid_init(g);
+
+	f->max_subctx_count = g->ops.gr.init.get_max_subctx_count();
+
+	g->ops.usermode.setup_hw(g);
+
+	enable_fifo_interrupts(g);
+
+	ga10b_fifo_config_userd_writeback_timer(g);
+
+	return 0;
+}
+
+u32 ga10b_fifo_mmu_fault_id_to_pbdma_id(struct gk20a *g, u32 mmu_fault_id)
+{
+	u32 pbdma_id;
+
+	for (pbdma_id = 0U; pbdma_id < g->ops.pbdma.get_num_of_pbdmas();
+				pbdma_id = nvgpu_safe_add_u32(pbdma_id, 1U)) {
+		if (g->ops.pbdma.get_mmu_fault_id(g, pbdma_id) ==
+							mmu_fault_id) {
+			return pbdma_id;
+		}
+	}
+
+	return INVAL_ID;
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b.h
new file mode 100644
index 000000000..fad9272d2
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FIFO_INTR_GA10B_H
+#define NVGPU_FIFO_INTR_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void ga10b_fifo_runlist_intr_vectorid_init(struct gk20a *g);
+void ga10b_fifo_intr_top_enable(struct gk20a *g, bool enable);
+void ga10b_fifo_intr_0_enable(struct gk20a *g, bool enable);
+void ga10b_fifo_intr_1_enable(struct gk20a *g, bool enable);
+void ga10b_fifo_intr_0_isr(struct gk20a *g);
+
+void ga10b_fifo_intr_set_recover_mask(struct gk20a *g);
+void ga10b_fifo_intr_unset_recover_mask(struct gk20a *g);
+
+void ga10b_fifo_pbdma_isr(struct gk20a *g, struct nvgpu_runlist *runlist, u32 pbdma_idx);
+void ga10b_fifo_runlist_intr_retrigger(struct gk20a *g, u32 intr_tree);
+
+#endif /* NVGPU_FIFO_INTR_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b_fusa.c
new file mode 100644
index 000000000..47a9f1201
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b_fusa.c
@@ -0,0 +1,485 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/log.h>
+#include <nvgpu/io.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/mc.h>
+#include <nvgpu/nvgpu_err.h>
+#include <nvgpu/cic.h>
+#include <nvgpu/rc.h>
+
+#include "fifo_utils_ga10b.h"
+#include "fifo_intr_ga10b.h"
+#include "ctxsw_timeout_ga10b.h"
+#include "pbdma_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_runlist_ga10b.h>
+
+/**
+ *     [runlist's tree 0 bit] <---------. .---------> [runlist's tree 1 bit]
+ *                                       Y
+ *                                       |
+ *                                       |
+ *     [runlist intr tree 0]             ^             [runlist intr tree 1]
+ *                       ______________/   \______________
+ *                      /                                  |
+ *     NV_RUNLIST_INTR_VECTORID(0) msg       NV_RUNLIST_INTR_VECTORID(1) msg
+ *                     |                                   |
+ *               ______^______                       ______^______
+ *              /             \                     /             \
+ *             '_______________'                   '_______________'
+ *              |||||||       |                     |       |||||||
+ *            other tree0     |                     |     other tree1
+ *          ANDed intr bits   ^                     ^   ANDed intr bits
+ *                           AND                   AND
+ *                           | |                   | |
+ *                    _______. .______      _______. .________
+ *                   /                 \   /                  \
+ *RUNLIST_INTR_0_EN_SET_TREE(0)_intr_bit Y RUNLIST_INTR_0_EN_SET_TREE(1)_intr_bit
+ *                                       |
+ *                           NV_RUNLIST_INTR_0_intr_bit
+ */
+
+
+#define RUNLIST_INTR_0_MASK \
+		(runlist_intr_0_en_set_tree_ctxsw_timeout_eng0_enabled_f() | \
+		runlist_intr_0_en_set_tree_ctxsw_timeout_eng1_enabled_f() | \
+		runlist_intr_0_en_set_tree_ctxsw_timeout_eng2_enabled_f() | \
+		runlist_intr_0_en_set_tree_pbdma0_intr_tree_0_enabled_f() | \
+		runlist_intr_0_en_set_tree_pbdma1_intr_tree_0_enabled_f() | \
+		runlist_intr_0_en_set_tree_bad_tsg_enabled_f())
+
+#define RUNLIST_INTR_0_RECOVER_MASK \
+		(runlist_intr_0_en_clear_tree_ctxsw_timeout_eng0_enabled_f() | \
+		runlist_intr_0_en_clear_tree_ctxsw_timeout_eng1_enabled_f() | \
+		runlist_intr_0_en_clear_tree_ctxsw_timeout_eng2_enabled_f())
+
+#define RUNLIST_INTR_0_RECOVER_UNMASK \
+		(runlist_intr_0_en_set_tree_ctxsw_timeout_eng0_enabled_f() | \
+		runlist_intr_0_en_set_tree_ctxsw_timeout_eng1_enabled_f() | \
+		runlist_intr_0_en_set_tree_ctxsw_timeout_eng2_enabled_f())
+
+#define RUNLIST_INTR_0_CTXSW_TIMEOUT_MASK \
+		( \
+		runlist_intr_0_en_clear_tree_ctxsw_timeout_eng0_enabled_f() | \
+		runlist_intr_0_en_clear_tree_ctxsw_timeout_eng1_enabled_f() | \
+		runlist_intr_0_en_clear_tree_ctxsw_timeout_eng2_enabled_f() \
+		)
+
+
+#define RUNLIST_INTR_0_PBDMA_MASK \
+		( \
+		runlist_intr_0_en_set_tree_pbdma0_intr_tree_0_enabled_f() | \
+		runlist_intr_0_en_set_tree_pbdma1_intr_tree_0_enabled_f() \
+		)
+
+static const char *const ga10b_bad_tsg_error_str[] = {
+	"no_error",
+	"zero_length_tsg",
+	"max_length_exceeded",
+	"runlist_overflow",
+	"expected_a_chid_entry",
+	"expected_a_tsg_header",
+	"invalid_runqueue",
+};
+
+void ga10b_fifo_runlist_intr_vectorid_init(struct gk20a *g)
+{
+	u32 i, intr_tree, reg_val, intr_unit;
+	u32 vectorid_tree[NVGPU_CIC_INTR_VECTORID_SIZE_MAX];
+	u32 num_vectorid;
+	struct nvgpu_runlist *runlist;
+
+	for (intr_tree = 0U; intr_tree < runlist_intr_vectorid__size_1_v();
+			intr_tree++) {
+
+		intr_unit = NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0 + intr_tree;
+
+		if (nvgpu_cic_intr_is_unit_info_valid(g, intr_unit) == true) {
+			/* intr_unit_info is already set by s/w */
+			continue;
+		}
+		num_vectorid = 0U;
+		for (i = 0U; i < g->fifo.num_runlists; i++) {
+
+			runlist = &g->fifo.active_runlists[i];
+
+			reg_val = nvgpu_runlist_readl(g, runlist,
+				runlist_intr_vectorid_r(intr_tree));
+			vectorid_tree[i] =
+				runlist_intr_vectorid_vector_v(reg_val);
+
+			num_vectorid ++;
+
+			nvgpu_log_info(g,
+				"init runlist: %u intr_tree_%d vectorid",
+				i, intr_tree);
+		}
+		nvgpu_cic_intr_unit_vectorid_init(g, intr_unit,
+			vectorid_tree, num_vectorid);
+	}
+
+}
+
+void ga10b_fifo_intr_top_enable(struct gk20a *g, bool enable)
+{
+	if (enable) {
+		nvgpu_cic_intr_stall_unit_config(g,
+			NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0, NVGPU_CIC_INTR_ENABLE);
+
+		/**
+		 * RUNLIST_TREE_1 interrupts are not enabled as all runlist
+		 * interrupts are routed to runlist_tree_0
+		 */
+		nvgpu_cic_intr_stall_unit_config(g,
+			NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_1, NVGPU_CIC_INTR_DISABLE);
+	} else {
+		nvgpu_cic_intr_stall_unit_config(g,
+				NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0, NVGPU_CIC_INTR_DISABLE);
+	}
+}
+
+static void ga10b_fifo_runlist_intr_disable(struct gk20a *g)
+{
+	u32 i, intr_tree, reg_val;
+	struct nvgpu_runlist *runlist;
+
+	/** Disable raising interrupt for both runlist trees to CPU and GSP */
+	for (i = 0U; i < g->fifo.num_runlists; i++) {
+		runlist = &g->fifo.active_runlists[i];
+		for (intr_tree = 0U;
+			intr_tree < runlist_intr_vectorid__size_1_v();
+			intr_tree++) {
+
+			reg_val = nvgpu_runlist_readl(g, runlist,
+				runlist_intr_vectorid_r(intr_tree));
+			reg_val &= ~(runlist_intr_vectorid_cpu_enable_f() |
+					runlist_intr_vectorid_gsp_enable_f());
+			nvgpu_runlist_writel(g, runlist,
+				runlist_intr_vectorid_r(intr_tree), reg_val);
+			nvgpu_log_info(g, "intr_vectorid_r[tree_%u]: 0x%08x",
+				i + intr_tree, reg_val);
+		}
+		/** Clear interrupts */
+		reg_val = nvgpu_runlist_readl(g, runlist, runlist_intr_0_r());
+
+		nvgpu_runlist_writel(g, runlist, runlist_intr_0_r(), reg_val);
+	}
+}
+
+static void ga10b_fifo_runlist_intr_enable(struct gk20a *g)
+{
+	u32 i, intr_tree_0, intr_tree_1, reg_val;
+	u32 intr0_en_mask;
+	struct nvgpu_runlist *runlist;
+
+	intr_tree_0 = 0U;
+	intr_tree_1 = 1U;
+	intr0_en_mask = RUNLIST_INTR_0_MASK;
+
+	for (i = 0U; i < g->fifo.num_runlists; i++) {
+		runlist = &g->fifo.active_runlists[i];
+		/**
+		 * runlist_intr_0 interrupts can be routed to either
+		 * tree0 or tree1 vector using runlist_intr_0_en_set_tree(0) or
+		 * runlist_intr_0_en_set_tree(1) register. For now route all
+		 * interrupts to tree0.
+		 */
+		/** Clear interrupts */
+		reg_val = nvgpu_runlist_readl(g, runlist, runlist_intr_0_r());
+
+		nvgpu_runlist_writel(g, runlist, runlist_intr_0_r(), reg_val);
+
+		/** Enable interrupts in tree(0) */
+		nvgpu_runlist_writel(g, runlist,
+			runlist_intr_0_en_set_tree_r(intr_tree_0),
+			intr0_en_mask);
+		/** Disable all interrupts in tree(1) */
+		nvgpu_runlist_writel(g, runlist,
+			runlist_intr_0_en_clear_tree_r(intr_tree_1),
+			U32_MAX);
+
+		reg_val = nvgpu_runlist_readl(g, runlist,
+			runlist_intr_vectorid_r(intr_tree_0));
+		/** disable raising interrupt to gsp */
+		reg_val &= ~(runlist_intr_vectorid_gsp_enable_f());
+
+		/** enable raising interrupt to cpu */
+		reg_val |= runlist_intr_vectorid_cpu_enable_f();
+
+		/** enable runlist tree 0 interrupts at runlist level */
+		nvgpu_runlist_writel(g, runlist,
+				runlist_intr_vectorid_r(intr_tree_0), reg_val);
+
+		reg_val = nvgpu_runlist_readl(g, runlist,
+			runlist_intr_vectorid_r(intr_tree_1));
+
+		/** disable raising interrupt to gsp */
+		reg_val &= ~(runlist_intr_vectorid_gsp_enable_f());
+
+		/** disable raising interrupt to cpu */
+		reg_val &= ~(runlist_intr_vectorid_cpu_enable_f());
+
+		/** Disable runlist tree 1 interrupts at runlist level */
+		nvgpu_runlist_writel(g, runlist,
+				runlist_intr_vectorid_r(intr_tree_1), reg_val);
+	}
+}
+void ga10b_fifo_intr_0_enable(struct gk20a *g, bool enable)
+{
+
+	ga10b_fifo_runlist_intr_disable(g);
+
+	if (!enable) {
+		g->ops.fifo.ctxsw_timeout_enable(g, false);
+		g->ops.pbdma.intr_enable(g, false);
+		return;
+	}
+
+	/* Enable interrupts */
+	g->ops.fifo.ctxsw_timeout_enable(g, true);
+	g->ops.pbdma.intr_enable(g, true);
+
+	ga10b_fifo_runlist_intr_enable(g);
+
+}
+
+void ga10b_fifo_intr_1_enable(struct gk20a *g, bool enable)
+{
+	return;
+}
+
+static void ga10b_fifo_handle_bad_tsg(struct gk20a *g,
+			struct nvgpu_runlist *runlist)
+{
+	u32 bad_tsg;
+	u32 bad_tsg_code;
+
+	bad_tsg = nvgpu_runlist_readl(g, runlist, runlist_intr_bad_tsg_r());
+	bad_tsg_code = runlist_intr_bad_tsg_code_v(bad_tsg);
+
+	if (bad_tsg_code < ARRAY_SIZE(ga10b_bad_tsg_error_str)) {
+		nvgpu_err(g, "runlist bad tsg error: %s",
+			ga10b_bad_tsg_error_str[bad_tsg_code]);
+	} else {
+		nvgpu_err(g, "runlist bad tsg error code not supported");
+	}
+
+	nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
+			0, GPU_HOST_PFIFO_SCHED_ERROR, bad_tsg_code);
+
+	/* id is unknown, preempt all runlists and do recovery */
+	/* TBD: nvgpu_rc_sched_error_bad_tsg(g); */
+}
+
+static void ga10b_fifo_runlist_intr_clear(struct gk20a *g)
+{
+	u32 i, intr_0;
+	struct nvgpu_runlist *runlist;
+
+	for (i = 0U; i < g->fifo.num_runlists; i++) {
+		runlist = &g->fifo.active_runlists[i];
+
+		intr_0 = nvgpu_runlist_readl(g, runlist, runlist_intr_0_r());
+
+		nvgpu_err(g, "unhandled runlist(%d) intr_0: 0x%08x", i, intr_0);
+
+		nvgpu_runlist_writel(g, runlist, runlist_intr_0_r(), intr_0);
+	}
+}
+
+void ga10b_fifo_intr_0_isr(struct gk20a *g)
+{
+	u32 i, intr_0, handled_intr_0 = 0U;
+	u32 intr_0_en_mask = 0U;
+	u32 pbdma_idx = 0U;
+	u32 intr_tree_0 = 0U, intr_tree_1 = 1U;
+	struct nvgpu_runlist *runlist;
+
+	/* TODO: sw_ready is needed only for recovery part */
+	if (!g->fifo.sw_ready) {
+		ga10b_fifo_runlist_intr_clear(g);
+		return;
+	}
+	/* note we're not actually in an "isr", but rather
+	 * in a threaded interrupt context... */
+	nvgpu_mutex_acquire(&g->fifo.intr.isr.mutex);
+
+	for (i = 0U; i < g->fifo.num_runlists; i++) {
+		runlist = &g->fifo.active_runlists[i];
+
+		intr_0 = nvgpu_runlist_readl(g, runlist, runlist_intr_0_r());
+
+		if (intr_0 & runlist_intr_0_bad_tsg_pending_f()) {
+			ga10b_fifo_handle_bad_tsg(g, runlist);
+			handled_intr_0 |= runlist_intr_0_bad_tsg_pending_f();
+		}
+
+		for (pbdma_idx = 0U;
+			pbdma_idx < runlist_intr_0_pbdmai_intr_tree_j__size_1_v();
+			pbdma_idx++) {
+			if (intr_0 &
+				runlist_intr_0_pbdmai_intr_tree_j_pending_f(pbdma_idx, intr_tree_0)) {
+				ga10b_fifo_pbdma_isr(g, runlist, pbdma_idx);
+				handled_intr_0 |= runlist_intr_0_pbdmai_intr_tree_j_pending_f(pbdma_idx, intr_tree_0);
+			}
+		}
+
+		if (intr_0 & RUNLIST_INTR_0_CTXSW_TIMEOUT_MASK) {
+			ga10b_fifo_ctxsw_timeout_isr(g, runlist);
+			handled_intr_0 |=
+				(RUNLIST_INTR_0_CTXSW_TIMEOUT_MASK & intr_0);
+		}
+
+		/*
+		 * The runlist_intr_0_r register can have bits set for which
+		 * interrupts are not enabled by the SW. Hence, create a mask
+		 * of all the runlist interrupts enabled on both runlist
+		 * tree0,1 and consider only these bits when detecting
+		 * unhandled interrupts.
+		 */
+		intr_0_en_mask = nvgpu_runlist_readl(g, runlist,
+				runlist_intr_0_en_set_tree_r(intr_tree_0));
+		intr_0_en_mask |= nvgpu_runlist_readl(g, runlist,
+				runlist_intr_0_en_set_tree_r(intr_tree_1));
+
+		if (handled_intr_0 != (intr_0 & intr_0_en_mask)) {
+			nvgpu_err(g,
+				"unhandled runlist(%d) intr_0: 0x%08x "
+				"handled: 0x%08x",
+				i, intr_0 & intr_0_en_mask, handled_intr_0);
+		}
+
+		handled_intr_0 = 0U;
+		/** Clear interrupts */
+		nvgpu_runlist_writel(g, runlist, runlist_intr_0_r(), intr_0);
+	}
+	nvgpu_mutex_release(&g->fifo.intr.isr.mutex);
+
+}
+
+void ga10b_fifo_intr_set_recover_mask(struct gk20a *g)
+{
+
+	u32 i, intr_tree_0;
+	struct nvgpu_runlist *runlist;
+
+	/*
+	 * ctxsw timeout error prevents recovery, and ctxsw error will retrigger
+	 * every 100ms. Disable ctxsw timeout error to allow recovery.
+	 */
+
+	intr_tree_0 = 0U;
+
+	for (i = 0U; i < g->fifo.num_runlists; i++) {
+		runlist = &g->fifo.active_runlists[i];
+		/**
+		 * runlist_intr_0 interrupts can be routed to either
+		 * tree0 or tree1 vector using runlist_intr_0_en_set_tree(0) or
+		 * runlist_intr_0_en_set_tree(1) register. For now route all
+		 * interrupts are routed to tree0.
+		 */
+
+		/*
+		 * Disable ctxsw interrupts in tree(0) using en_clear_tree_r(0).
+		 * Writes of 1 disables reporting of corresponding interrupt,
+		 * whereas writes with 0 are ignored. Read returns enabled
+		 * interrupts instead of the previous write value.
+		 */
+		nvgpu_runlist_writel(g, runlist,
+			runlist_intr_0_en_clear_tree_r(intr_tree_0),
+			RUNLIST_INTR_0_RECOVER_MASK);
+	}
+}
+
+void ga10b_fifo_intr_unset_recover_mask(struct gk20a *g)
+{
+	u32 i, intr_tree_0;
+	struct nvgpu_runlist *runlist;
+
+	/*
+	 * ctxsw timeout error prevents recovery, and ctxsw error will retrigger
+	 * every 100ms. To allow recovery, ctxsw timeout is disabled. Enable
+	 * the same after recovery is done.
+	 */
+
+	intr_tree_0 = 0U;
+
+	for (i = 0U; i < g->fifo.num_runlists; i++) {
+		runlist = &g->fifo.active_runlists[i];
+		/**
+		 * runlist_intr_0 interrupts can be routed to either
+		 * tree0 or tree1 vector using runlist_intr_0_en_set_tree(0) or
+		 * runlist_intr_0_en_set_tree(1) register. For now route all
+		 * interrupts are routed to tree0.
+		 */
+
+		/*
+		 * Enable ctxsw interrupts in tree(0) using en_set_tree_r(0).
+		 * Writes of 1 enables reporting of corresponding interrupt,
+		 * whereas writes with 0 are ignored. Read returns enabled
+		 * interrupts instead of the previous write value.
+		 */
+		nvgpu_runlist_writel(g, runlist,
+			runlist_intr_0_en_set_tree_r(intr_tree_0),
+			RUNLIST_INTR_0_RECOVER_UNMASK);
+	}
+
+}
+
+
+void ga10b_fifo_pbdma_isr(struct gk20a *g, struct nvgpu_runlist *runlist, u32 pbdma_idx)
+{
+	u32 pbdma_id;
+	const struct nvgpu_next_pbdma_info *pbdma_info;
+
+	if (pbdma_idx >= PBDMA_PER_RUNLIST_SIZE) {
+		nvgpu_err(g, "pbdma_idx(%d) >= max_pbdmas_per_runlist(%d)",
+				pbdma_idx, PBDMA_PER_RUNLIST_SIZE);
+		return;
+	}
+	pbdma_info = runlist->nvgpu_next.pbdma_info;
+	pbdma_id = pbdma_info->pbdma_id[pbdma_idx];
+	if (pbdma_id == PBDMA_ID_INVALID) {
+		nvgpu_err(g, "runlist_id(%d), pbdma_idx(%d): invalid PBDMA",
+				runlist->id, pbdma_idx);
+		return;
+	}
+	g->ops.pbdma.handle_intr(g, pbdma_id, true);
+}
+
+void ga10b_fifo_runlist_intr_retrigger(struct gk20a *g, u32 intr_tree)
+{
+	u32 i = 0U;
+	struct nvgpu_runlist *runlist;
+
+	for (i = 0U; i < g->fifo.num_runlists; i++) {
+		runlist = &g->fifo.active_runlists[i];
+
+		nvgpu_runlist_writel(g, runlist,
+				runlist_intr_retrigger_r(intr_tree),
+				runlist_intr_retrigger_trigger_true_f());
+	}
+
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b.h
new file mode 100644
index 000000000..af94d82d0
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef FIFO_UTILS_GA10B_H
+#define FIFO_UTILS_GA10B_H
+
+struct gk20a;
+struct nvgpu_runlist;
+
+u32 nvgpu_runlist_readl(struct gk20a *g, struct nvgpu_runlist *runlist,
+			u32 r);
+void nvgpu_runlist_writel(struct gk20a *g, struct nvgpu_runlist *runlist,
+			u32 r, u32 v);
+u32 nvgpu_chram_bar0_readl(struct gk20a *g, struct nvgpu_runlist *runlist,
+			u32 r);
+void nvgpu_chram_bar0_writel(struct gk20a *g,
+			struct nvgpu_runlist *runlist, u32 r, u32 v);
+
+#endif /* FIFO_UTILS_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b_fusa.c
new file mode 100644
index 000000000..8ab37ae2c
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b_fusa.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/bug.h>
+#include <nvgpu/io.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/runlist.h>
+
+#include "fifo_utils_ga10b.h"
+
+u32 nvgpu_runlist_readl(struct gk20a *g, struct nvgpu_runlist *runlist,
+			u32 r)
+{
+	u32 runlist_pri_base = 0U;
+
+	nvgpu_assert(runlist != NULL);
+	runlist_pri_base = runlist->nvgpu_next.runlist_pri_base;
+	nvgpu_assert(runlist_pri_base != 0U);
+
+	return nvgpu_readl(g, nvgpu_safe_add_u32(runlist_pri_base, r));
+}
+
+void nvgpu_runlist_writel(struct gk20a *g, struct nvgpu_runlist *runlist,
+			u32 r, u32 v)
+{
+	u32 runlist_pri_base = 0U;
+
+	nvgpu_assert(runlist != NULL);
+	runlist_pri_base = runlist->nvgpu_next.runlist_pri_base;
+	nvgpu_assert(runlist_pri_base != 0U);
+
+	nvgpu_writel(g, nvgpu_safe_add_u32(runlist_pri_base, r), v);
+}
+
+u32 nvgpu_chram_bar0_readl(struct gk20a *g, struct nvgpu_runlist *runlist,
+			u32 r)
+{
+	u32 chram_bar0_offset = 0U;
+
+	nvgpu_assert(runlist != NULL);
+	chram_bar0_offset = runlist->nvgpu_next.chram_bar0_offset;
+	nvgpu_assert(chram_bar0_offset != 0U);
+
+	return nvgpu_readl(g, nvgpu_safe_add_u32(chram_bar0_offset, r));
+}
+
+void nvgpu_chram_bar0_writel(struct gk20a *g,
+			struct nvgpu_runlist *runlist, u32 r, u32 v)
+{
+	u32 chram_bar0_offset = 0U;
+
+	nvgpu_assert(runlist != NULL);
+	chram_bar0_offset = runlist->nvgpu_next.chram_bar0_offset;
+	nvgpu_assert(chram_bar0_offset != 0U);
+
+	nvgpu_writel(g, nvgpu_safe_add_u32(chram_bar0_offset, r), v);
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga100.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga100.h
new file mode 100644
index 000000000..d48f081d5
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga100.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020-21, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PBDMA_GA100_H
+#define NVGPU_PBDMA_GA100_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_device;
+
+u32 ga100_pbdma_set_clear_intr_offsets(struct gk20a *g,
+			u32 set_clear_size);
+u32 ga100_pbdma_get_fc_target(const struct nvgpu_device *dev);
+void ga100_pbdma_force_ce_split(struct gk20a *g);
+u32 ga100_pbdma_read_data(struct gk20a *g, u32 pbdma_id);
+u32 ga100_pbdma_get_num_of_pbdmas(void);
+
+#endif /* NVGPU_PBDMA_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga100_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga100_fusa.c
new file mode 100644
index 000000000..9b9f39a11
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga100_fusa.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/bitops.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/pbdma_status.h>
+#include <nvgpu/nvgpu_err.h>
+#include <nvgpu/device.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/io.h>
+
+#include "pbdma_ga10b.h"
+#include "pbdma_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_pbdma_ga100.h>
+
+u32 ga100_pbdma_set_clear_intr_offsets(struct gk20a *g,
+			u32 set_clear_size)
+{
+	u32 ret = 0U;
+	switch(set_clear_size) {
+		case INTR_SIZE:
+			ret = pbdma_intr_0__size_1_v();
+			break;
+		case INTR_SET_SIZE:
+			ret = pbdma_intr_0_en_set_tree__size_1_v();
+			break;
+		case INTR_CLEAR_SIZE:
+			ret = pbdma_intr_0_en_clear_tree__size_1_v();
+			break;
+		default:
+			nvgpu_err(g, "Invalid input for set_clear_intr_offset");
+			break;
+	}
+
+	return ret;
+}
+
+u32 ga100_pbdma_get_fc_target(const struct nvgpu_device *dev)
+{
+	return (pbdma_target_engine_f(dev->next.rleng_id) |
+			pbdma_target_eng_ctx_valid_true_f() |
+			pbdma_target_ce_ctx_valid_true_f());
+}
+
+static void ga100_pbdma_force_ce_split_set(struct gk20a *g,
+		struct nvgpu_runlist *runlist)
+{
+	u32 reg;
+	u32 i;
+	u32 pbdma_id;
+	const struct nvgpu_next_pbdma_info *pbdma_info = NULL;
+
+	pbdma_info = runlist->nvgpu_next.pbdma_info;
+	for (i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) {
+		pbdma_id = pbdma_info->pbdma_id[i];
+		if (pbdma_id == U32_MAX) {
+			continue;
+		}
+
+		reg = nvgpu_readl(g, pbdma_secure_config_r(pbdma_id));
+		reg = set_field(reg, pbdma_secure_config_force_ce_split_m(),
+			 pbdma_secure_config_force_ce_split_true_f());
+		nvgpu_writel(g, pbdma_secure_config_r(pbdma_id), reg);
+	}
+}
+
+void ga100_pbdma_force_ce_split(struct gk20a *g)
+{
+	struct nvgpu_runlist *runlist = NULL;
+	u32 i;
+
+	for (i = 0U; i < g->fifo.num_runlists; i++) {
+		runlist = g->fifo.runlists[i];
+		ga100_pbdma_force_ce_split_set(g, runlist);
+	}
+}
+
+u32 ga100_pbdma_read_data(struct gk20a *g, u32 pbdma_id)
+{
+	return nvgpu_readl(g, pbdma_hdr_shadow_r(pbdma_id));
+}
+
+u32 ga100_pbdma_get_num_of_pbdmas(void)
+{
+	return pbdma_cfg0__size_1_v();
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.c
new file mode 100644
index 000000000..60454203b
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/log2.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/io.h>
+#include <nvgpu/bitops.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/debug.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/pbdma_status.h>
+
+#include <nvgpu/hw/ga10b/hw_pbdma_ga10b.h>
+
+#include "pbdma_ga10b.h"
+
+void ga10b_pbdma_dump_status(struct gk20a *g, struct nvgpu_debug_context *o)
+{
+	u32 i, host_num_pbdma;
+	struct nvgpu_pbdma_status_info pbdma_status;
+
+	host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
+
+	gk20a_debug_output(o, "PBDMA Status - chip %-5s", g->name);
+	gk20a_debug_output(o, "-------------------------");
+
+	for (i = 0U; i < host_num_pbdma; i++) {
+		g->ops.pbdma_status.read_pbdma_status_info(g, i,
+			&pbdma_status);
+
+		gk20a_debug_output(o, "pbdma %d:", i);
+		gk20a_debug_output(o,
+			"  id: %d - %-9s next_id: - %d %-9s | status: %s",
+			pbdma_status.id,
+			nvgpu_pbdma_status_is_id_type_tsg(&pbdma_status) ?
+				   "[tsg]" : "[channel]",
+			pbdma_status.next_id,
+			nvgpu_pbdma_status_is_next_id_type_tsg(
+				&pbdma_status) ?
+				   "[tsg]" : "[channel]",
+			nvgpu_fifo_decode_pbdma_ch_eng_status(
+				pbdma_status.pbdma_channel_status));
+		gk20a_debug_output(o,
+			"  PBDMA_PUT %016llx PBDMA_GET %016llx",
+			(u64)nvgpu_readl(g, pbdma_put_r(i)) +
+			((u64)nvgpu_readl(g, pbdma_put_hi_r(i)) << 32ULL),
+			(u64)nvgpu_readl(g, pbdma_get_r(i)) +
+			((u64)nvgpu_readl(g, pbdma_get_hi_r(i)) << 32ULL));
+		gk20a_debug_output(o,
+			"  GP_PUT    %08x  GP_GET  %08x  "
+			"FETCH   %08x HEADER %08x",
+			nvgpu_readl(g, pbdma_gp_put_r(i)),
+			nvgpu_readl(g, pbdma_gp_get_r(i)),
+			nvgpu_readl(g, pbdma_gp_fetch_r(i)),
+			nvgpu_readl(g, pbdma_pb_header_r(i)));
+		gk20a_debug_output(o,
+			"  HDR       %08x  SHADOW0 %08x  SHADOW1 %08x",
+			g->ops.pbdma.read_data(g, i),
+			nvgpu_readl(g, pbdma_gp_shadow_0_r(i)),
+			nvgpu_readl(g, pbdma_gp_shadow_1_r(i)));
+	}
+
+	gk20a_debug_output(o, " ");
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
new file mode 100644
index 000000000..e5545c8bd
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PBDMA_GA10B_H
+#define NVGPU_PBDMA_GA10B_H
+
+#include <nvgpu/types.h>
+
+#define HW_PBDMA_STRIDE			2048U
+#define HW_PBDMA_BASE			0x040000U
+
+#define PBDMA_PRI_BASE_INVALID		U32_MAX
+#define PBDMA_ID_INVALID		U32_MAX
+
+#define INTR_SIZE			0U
+#define INTR_SET_SIZE			1U
+#define INTR_CLEAR_SIZE			2U
+
+struct gk20a;
+struct nvgpu_debug_context;
+struct nvgpu_pbdma_status_info;
+struct nvgpu_device;
+
+void ga10b_pbdma_intr_enable(struct gk20a *g, bool enable);
+void ga10b_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id, bool recover);
+bool ga10b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0,
+			u32 *error_notifier);
+bool ga10b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1,
+			u32 *error_notifier);
+
+u32 ga10b_pbdma_read_data(struct gk20a *g, u32 pbdma_id);
+void ga10b_pbdma_reset_header(struct gk20a *g, u32 pbdma_id);
+void ga10b_pbdma_reset_method(struct gk20a *g, u32 pbdma_id,
+			u32 pbdma_method_index);
+
+void ga10b_pbdma_clear_all_intr(struct gk20a *g, u32 pbdma_id);
+void ga10b_pbdma_disable_and_clear_all_intr(struct gk20a *g);
+u32 ga10b_pbdma_channel_fatal_0_intr_descs(void);
+u32 ga10b_pbdma_device_fatal_0_intr_descs(void);
+
+u32 ga10b_pbdma_set_channel_info_chid(u32 chid);
+u32 ga10b_pbdma_set_intr_notify(u32 eng_intr_vector);
+u32 ga10b_pbdma_set_clear_intr_offsets(struct gk20a *g,
+			u32 set_clear_size);
+
+u32 ga10b_pbdma_get_fc_target(const struct nvgpu_device *dev);
+
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+void ga10b_pbdma_dump_status(struct gk20a *g, struct nvgpu_debug_context *o);
+#endif
+
+u32 ga10b_pbdma_get_mmu_fault_id(struct gk20a *g, u32 pbdma_id);
+u32 ga10b_pbdma_get_num_of_pbdmas(void);
+
+#endif /* NVGPU_PBDMA_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c
new file mode 100644
index 000000000..86399dda4
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c
@@ -0,0 +1,615 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/log2.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/io.h>
+#include <nvgpu/bitops.h>
+#include <nvgpu/error_notifier.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/pbdma_status.h>
+#include <nvgpu/static_analysis.h>
+#include <nvgpu/nvgpu_err.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/rc.h>
+#include <nvgpu/device.h>
+
+#include "pbdma_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_pbdma_ga10b.h>
+
+#define PBDMA_INTR_0_EN_SET_TREE_MASK \
+		( \
+			pbdma_intr_0_en_set_tree_gpfifo_enabled_f()    | \
+			pbdma_intr_0_en_set_tree_gpptr_enabled_f()     | \
+			pbdma_intr_0_en_set_tree_gpentry_enabled_f()   | \
+			pbdma_intr_0_en_set_tree_gpcrc_enabled_f()     | \
+			pbdma_intr_0_en_set_tree_pbptr_enabled_f()     | \
+			pbdma_intr_0_en_set_tree_pbentry_enabled_f()   | \
+			pbdma_intr_0_en_set_tree_pbcrc_enabled_f()     | \
+			pbdma_intr_0_en_set_tree_method_enabled_f()    | \
+			pbdma_intr_0_en_set_tree_device_enabled_f()    | \
+			pbdma_intr_0_en_set_tree_eng_reset_enabled_f() | \
+			pbdma_intr_0_en_set_tree_semaphore_enabled_f() | \
+			pbdma_intr_0_en_set_tree_acquire_enabled_f()   | \
+			pbdma_intr_0_en_set_tree_pri_enabled_f()       | \
+			pbdma_intr_0_en_set_tree_pbseg_enabled_f()     | \
+			pbdma_intr_0_en_set_tree_signature_enabled_f()  \
+		)
+
+#define PBDMA_INTR_0_EN_CLEAR_TREE_MASK \
+		( \
+			pbdma_intr_0_en_clear_tree_gpfifo_enabled_f()    | \
+			pbdma_intr_0_en_clear_tree_gpptr_enabled_f()     | \
+			pbdma_intr_0_en_clear_tree_gpentry_enabled_f()   | \
+			pbdma_intr_0_en_clear_tree_gpcrc_enabled_f()     | \
+			pbdma_intr_0_en_clear_tree_pbptr_enabled_f()     | \
+			pbdma_intr_0_en_clear_tree_pbentry_enabled_f()   | \
+			pbdma_intr_0_en_clear_tree_pbcrc_enabled_f()     | \
+			pbdma_intr_0_en_clear_tree_method_enabled_f()    | \
+			pbdma_intr_0_en_clear_tree_device_enabled_f()    | \
+			pbdma_intr_0_en_clear_tree_eng_reset_enabled_f() | \
+			pbdma_intr_0_en_clear_tree_semaphore_enabled_f() | \
+			pbdma_intr_0_en_clear_tree_acquire_enabled_f()   | \
+			pbdma_intr_0_en_clear_tree_pri_enabled_f()       | \
+			pbdma_intr_0_en_clear_tree_pbseg_enabled_f()     | \
+			pbdma_intr_0_en_clear_tree_signature_enabled_f()  \
+		)
+
+#define PBDMA_INTR_1_EN_SET_TREE_MASK \
+		( \
+			pbdma_intr_1_en_set_tree_hce_re_illegal_op_enabled_f() | \
+			pbdma_intr_1_en_set_tree_hce_re_alignb_enabled_f()     | \
+			pbdma_intr_1_en_set_tree_hce_priv_enabled_f()          | \
+			pbdma_intr_1_en_set_tree_hce_illegal_mthd_enabled_f()  | \
+			pbdma_intr_1_en_set_tree_hce_illegal_class_enabled_f() | \
+			pbdma_intr_1_en_set_tree_ctxnotvalid_enabled_f()   \
+		)
+
+#define PBDMA_INTR_1_EN_CLEAR_TREE_MASK \
+		( \
+			pbdma_intr_1_en_clear_tree_hce_re_illegal_op_enabled_f() | \
+			pbdma_intr_1_en_clear_tree_hce_re_alignb_enabled_f()     | \
+			pbdma_intr_1_en_clear_tree_hce_priv_enabled_f()          | \
+			pbdma_intr_1_en_clear_tree_hce_illegal_mthd_enabled_f()  | \
+			pbdma_intr_1_en_clear_tree_hce_illegal_class_enabled_f() | \
+			pbdma_intr_1_en_clear_tree_ctxnotvalid_enabled_f() \
+		)
+/**
+ * nvgpu will route all pbdma intr to tree_0
+ * The interrupt registers NV_PPBDMA_INTR_* contain and control the interrupt
+ * state for each PBDMA. Interrupts are set by events and are cleared by software
+ * running on the CPU or GSP.
+ *
+ * Interrupts in the PBDMA are divided into two interrupt trees:
+ * RUNLIST_INTR_0_PBDMAn_INTR_TREE_0   RUNLIST_INTR_0_PBDMAn_INTR_TREE_1
+ *                      |                                   |
+ *                ______^______                       ______^______
+ *               /             \                     /             \
+ *              |      OR       |                   |      OR       |
+ *              '_______________'                   '_______________'
+ *               |||||||       |                     |       |||||||
+ *             other tree0     |                     |     other tree1
+ *           ANDed intr bits   ^                     ^   ANDed intr bits
+ *                            AND                   AND
+ *                            | |                   | |
+ *                     _______. .______      _______. .________
+ *                    /                 \   /                  \
+ *                   |                   \ /                    |
+ * PPBDMA_INTR_0/1_EN_SET_TREE(p,0)_intr  Y  PPBDMA_INTR_0/1_EN_SET_TREE(p,1)_intr
+ *                                        |
+ *                           NV_PPBDMA_INTR_0/1_intr_bit
+ */
+
+
+/* TBD: NVGPU-4516: Update fault_type_desc */
+static const char *const pbdma_intr_fault_type_desc[] = {
+	"MEMREQ timeout", "MEMACK_TIMEOUT", "MEMACK_EXTRA acks",
+	"MEMDAT_TIMEOUT", "MEMDAT_EXTRA acks", "MEMFLUSH noack",
+	"MEMOP noack", "LBCONNECT noack", "NONE - was LBREQ",
+	"LBACK_TIMEOUT", "LBACK_EXTRA acks", "LBDAT_TIMEOUT",
+	"LBDAT_EXTRA acks", "GPFIFO won't fit", "GPPTR invalid",
+	"GPENTRY invalid", "GPCRC mismatch", "PBPTR get>put",
+	"PBENTRY invld", "PBCRC mismatch", "NONE - was XBARC",
+	"METHOD invld", "METHODCRC mismat", "DEVICE sw method",
+	"[ENGINE]", "SEMAPHORE invlid", "ACQUIRE timeout",
+	"PRI forbidden", "ILLEGAL SYNCPT", "[NO_CTXSW_SEG]",
+	"PBSEG badsplit", "SIGNATURE bad"
+};
+
+static bool ga10b_pbdma_is_sw_method_subch(struct gk20a *g, u32 pbdma_id,
+						u32 pbdma_method_index)
+{
+	u32 pbdma_method_stride;
+	u32 pbdma_method_reg, pbdma_method_subch;
+
+	pbdma_method_stride = nvgpu_safe_sub_u32(pbdma_method1_r(pbdma_id),
+				pbdma_method0_r(pbdma_id));
+
+	pbdma_method_reg = nvgpu_safe_add_u32(pbdma_method0_r(pbdma_id),
+				nvgpu_safe_mult_u32(pbdma_method_index,
+					pbdma_method_stride));
+
+	pbdma_method_subch = pbdma_method0_subch_v(
+			nvgpu_readl(g, pbdma_method_reg));
+
+	if ((pbdma_method_subch == 5U) ||
+		(pbdma_method_subch == 6U) ||
+		(pbdma_method_subch == 7U)) {
+		return true;
+	}
+
+	return false;
+}
+
+u32 ga10b_pbdma_set_clear_intr_offsets(struct gk20a *g,
+			u32 set_clear_size)
+{
+	u32 ret = 0U;
+	switch(set_clear_size) {
+		case INTR_SIZE:
+			ret = pbdma_intr_0__size_1_v();
+			break;
+		case INTR_SET_SIZE:
+			ret = pbdma_intr_0_en_set_tree__size_1_v();
+			break;
+		case INTR_CLEAR_SIZE:
+			ret = pbdma_intr_0_en_clear_tree__size_1_v();
+			break;
+		default:
+			nvgpu_err(g, "Invalid input for set_clear_intr_offset");
+			break;
+	}
+
+	return ret;
+}
+
+static void ga10b_pbdma_disable_all_intr(struct gk20a *g)
+{
+	u32 pbdma_id = 0U;
+	u32 tree = 0U;
+	u32 pbdma_id_max =
+			g->ops.pbdma.set_clear_intr_offsets(g, INTR_CLEAR_SIZE);
+
+	for (pbdma_id = 0U; pbdma_id < pbdma_id_max; pbdma_id++) {
+		for (tree = 0U; tree < pbdma_intr_0_en_clear_tree__size_2_v();
+			tree++) {
+			nvgpu_writel(g, pbdma_intr_0_en_clear_tree_r(pbdma_id,
+				tree), PBDMA_INTR_0_EN_CLEAR_TREE_MASK);
+			nvgpu_writel(g, pbdma_intr_1_en_clear_tree_r(pbdma_id,
+				tree), PBDMA_INTR_1_EN_CLEAR_TREE_MASK);
+		}
+	}
+}
+
+void ga10b_pbdma_clear_all_intr(struct gk20a *g, u32 pbdma_id)
+{
+	nvgpu_writel(g, pbdma_intr_0_r(pbdma_id), U32_MAX);
+	nvgpu_writel(g, pbdma_intr_1_r(pbdma_id), U32_MAX);
+}
+
+void ga10b_pbdma_disable_and_clear_all_intr(struct gk20a *g)
+{
+	u32 pbdma_id = 0U;
+	u32 pbdma_id_max =
+		g->ops.pbdma.set_clear_intr_offsets(g, INTR_SIZE);
+
+	ga10b_pbdma_disable_all_intr(g);
+
+	for (pbdma_id = 0U; pbdma_id < pbdma_id_max; pbdma_id++) {
+		ga10b_pbdma_clear_all_intr(g, pbdma_id);
+	}
+}
+
+static void ga10b_pbdma_dump_intr_0(struct gk20a *g, u32 pbdma_id,
+				u32 pbdma_intr_0)
+{
+	u32 header = nvgpu_readl(g, pbdma_pb_header_r(pbdma_id));
+	u32 data = g->ops.pbdma.read_data(g, pbdma_id);
+	u32 shadow_0 = nvgpu_readl(g, pbdma_gp_shadow_0_r(pbdma_id));
+	u32 shadow_1 = nvgpu_readl(g, pbdma_gp_shadow_1_r(pbdma_id));
+	u32 method0 = nvgpu_readl(g, pbdma_method0_r(pbdma_id));
+	u32 method1 = nvgpu_readl(g, pbdma_method1_r(pbdma_id));
+	u32 method2 = nvgpu_readl(g, pbdma_method2_r(pbdma_id));
+	u32 method3 = nvgpu_readl(g, pbdma_method3_r(pbdma_id));
+
+	nvgpu_err(g,
+		"pbdma_intr_0(%d):0x%08x PBH: %08x "
+		"SHADOW: %08x gp shadow0: %08x gp shadow1: %08x"
+		"M0: %08x %08x %08x %08x ",
+		pbdma_id, pbdma_intr_0, header, data,
+		shadow_0, shadow_1, method0, method1, method2, method3);
+}
+
+/* Copied static function */
+static u32 pbdma_get_intr_descs(struct gk20a *g)
+{
+	struct nvgpu_fifo *f = &g->fifo;
+	u32 intr_descs = (f->intr.pbdma.device_fatal_0 |
+				f->intr.pbdma.channel_fatal_0 |
+				f->intr.pbdma.restartable_0);
+
+	return intr_descs;
+}
+
+void ga10b_pbdma_reset_header(struct gk20a *g, u32 pbdma_id)
+{
+	nvgpu_writel(g, pbdma_pb_header_r(pbdma_id),
+			pbdma_pb_header_first_true_f() |
+			pbdma_pb_header_type_non_inc_f());
+}
+
+void ga10b_pbdma_reset_method(struct gk20a *g, u32 pbdma_id,
+			u32 pbdma_method_index)
+{
+	u32 pbdma_method_stride;
+	u32 pbdma_method_reg;
+
+	pbdma_method_stride = nvgpu_safe_sub_u32(pbdma_method1_r(pbdma_id),
+				pbdma_method0_r(pbdma_id));
+
+	pbdma_method_reg = nvgpu_safe_add_u32(pbdma_method0_r(pbdma_id),
+				nvgpu_safe_mult_u32(pbdma_method_index,
+					pbdma_method_stride));
+
+	nvgpu_writel(g, pbdma_method_reg,
+			pbdma_method0_valid_true_f() |
+			pbdma_method0_first_true_f() |
+			pbdma_method0_addr_f(
+			     U32(pbdma_udma_nop_r()) >> 2U));
+}
+
+u32 ga10b_pbdma_read_data(struct gk20a *g, u32 pbdma_id)
+{
+	return nvgpu_readl(g, pbdma_hdr_shadow_r(pbdma_id));
+}
+
+static void report_pbdma_error(struct gk20a *g, u32 pbdma_id,
+		u32 pbdma_intr_0)
+{
+	u32 err_type = GPU_HOST_INVALID_ERROR;
+
+	/*
+	 * Multiple errors have been grouped as part of a single
+	 * top-level error.
+	 */
+	if ((pbdma_intr_0 & (
+		pbdma_intr_0_gpfifo_pending_f() |
+		pbdma_intr_0_gpptr_pending_f() |
+		pbdma_intr_0_gpentry_pending_f() |
+		pbdma_intr_0_gpcrc_pending_f() |
+		pbdma_intr_0_pbptr_pending_f() |
+		pbdma_intr_0_pbentry_pending_f() |
+		pbdma_intr_0_pbcrc_pending_f())) != 0U) {
+			err_type = GPU_HOST_PBDMA_GPFIFO_PB_ERROR;
+	}
+	if ((pbdma_intr_0 & (
+		pbdma_intr_0_method_pending_f() |
+		pbdma_intr_0_device_pending_f() |
+		pbdma_intr_0_eng_reset_pending_f() |
+		pbdma_intr_0_semaphore_pending_f() |
+		pbdma_intr_0_acquire_pending_f() |
+		pbdma_intr_0_pri_pending_f() |
+		pbdma_intr_0_pbseg_pending_f())) != 0U) {
+			err_type = GPU_HOST_PBDMA_METHOD_ERROR;
+	}
+	if ((pbdma_intr_0 &
+		pbdma_intr_0_signature_pending_f()) != 0U) {
+			err_type = GPU_HOST_PBDMA_SIGNATURE_ERROR;
+	}
+	if (err_type != GPU_HOST_INVALID_ERROR) {
+		nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
+				pbdma_id, err_type, pbdma_intr_0);
+	}
+	return;
+}
+
+void ga10b_pbdma_intr_enable(struct gk20a *g, bool enable)
+{
+	u32 pbdma_id = 0U;
+	u32 tree = 0U;
+	u32 pbdma_id_max =
+		g->ops.pbdma.set_clear_intr_offsets(g, INTR_SET_SIZE);
+
+	if (!enable) {
+		ga10b_pbdma_disable_and_clear_all_intr(g);
+		return;
+	}
+
+	for (pbdma_id = 0U; pbdma_id < pbdma_id_max; pbdma_id++) {
+
+		ga10b_pbdma_clear_all_intr(g, pbdma_id);
+
+		/* enable pbdma interrupts and route to tree_0 */
+		nvgpu_writel(g, pbdma_intr_0_en_set_tree_r(pbdma_id,
+			tree), PBDMA_INTR_0_EN_SET_TREE_MASK);
+		nvgpu_writel(g, pbdma_intr_1_en_set_tree_r(pbdma_id,
+			tree), PBDMA_INTR_1_EN_SET_TREE_MASK);
+	}
+}
+
+
+void ga10b_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id, bool recover)
+{
+	struct nvgpu_pbdma_status_info pbdma_status;
+	u32 intr_error_notifier = NVGPU_ERR_NOTIFIER_PBDMA_ERROR;
+
+	u32 pbdma_intr_0 = nvgpu_readl(g, pbdma_intr_0_r(pbdma_id));
+	u32 pbdma_intr_1 = nvgpu_readl(g, pbdma_intr_1_r(pbdma_id));
+
+	if (pbdma_intr_0 != 0U) {
+		nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
+			"pbdma id %d intr_0 0x%08x pending",
+			pbdma_id, pbdma_intr_0);
+
+		if (g->ops.pbdma.handle_intr_0(g, pbdma_id, pbdma_intr_0,
+			&intr_error_notifier)) {
+			g->ops.pbdma_status.read_pbdma_status_info(g,
+				pbdma_id, &pbdma_status);
+			if (recover) {
+				nvgpu_rc_pbdma_fault(g, pbdma_id,
+						intr_error_notifier,
+						&pbdma_status);
+			}
+		}
+		nvgpu_writel(g, pbdma_intr_0_r(pbdma_id), pbdma_intr_0);
+	}
+
+	if (pbdma_intr_1 != 0U) {
+		nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
+			"pbdma id %d intr_1 0x%08x pending",
+			pbdma_id, pbdma_intr_1);
+
+		if (g->ops.pbdma.handle_intr_1(g, pbdma_id, pbdma_intr_1,
+			&intr_error_notifier)) {
+			g->ops.pbdma_status.read_pbdma_status_info(g,
+				pbdma_id, &pbdma_status);
+			if (recover) {
+				nvgpu_rc_pbdma_fault(g, pbdma_id,
+						intr_error_notifier,
+						&pbdma_status);
+			}
+		}
+		nvgpu_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1);
+	}
+}
+
+static bool ga10b_pbdma_handle_intr_0_legacy(struct gk20a *g, u32 pbdma_id,
+			u32 pbdma_intr_0, u32 *error_notifier)
+{
+
+	bool recover = false;
+	u32 i;
+	unsigned long pbdma_intr_err;
+	unsigned long bit;
+	u32 intr_descs = pbdma_get_intr_descs(g);
+
+	if ((intr_descs & pbdma_intr_0) != 0U) {
+
+		pbdma_intr_err = (unsigned long)pbdma_intr_0;
+		for_each_set_bit(bit, &pbdma_intr_err, 32U) {
+			nvgpu_err(g, "PBDMA intr %s Error",
+				pbdma_intr_fault_type_desc[bit]);
+		}
+
+		ga10b_pbdma_dump_intr_0(g, pbdma_id, pbdma_intr_0);
+
+		recover = true;
+	}
+
+	if ((pbdma_intr_0 & pbdma_intr_0_acquire_pending_f()) != 0U) {
+		u32 val = nvgpu_readl(g, pbdma_acquire_r(pbdma_id));
+
+		val &= ~pbdma_acquire_timeout_en_enable_f();
+		nvgpu_writel(g, pbdma_acquire_r(pbdma_id), val);
+		if (nvgpu_is_timeouts_enabled(g)) {
+			recover = true;
+			nvgpu_err(g, "semaphore acquire timeout!");
+
+			/*
+			 * Note: the error_notifier can be overwritten if
+			 * semaphore_timeout is triggered with pbcrc_pending
+			 * interrupt below
+			 */
+			*error_notifier =
+				NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT;
+		}
+	}
+
+	if ((pbdma_intr_0 & pbdma_intr_0_pbentry_pending_f()) != 0U) {
+		g->ops.pbdma.reset_header(g, pbdma_id);
+		ga10b_pbdma_reset_method(g, pbdma_id, 0);
+		recover = true;
+	}
+
+	if ((pbdma_intr_0 & pbdma_intr_0_method_pending_f()) != 0U) {
+		ga10b_pbdma_reset_method(g, pbdma_id, 0);
+		recover = true;
+	}
+
+	if ((pbdma_intr_0 & pbdma_intr_0_pbcrc_pending_f()) != 0U) {
+		*error_notifier =
+			NVGPU_ERR_NOTIFIER_PBDMA_PUSHBUFFER_CRC_MISMATCH;
+		recover = true;
+	}
+
+	if ((pbdma_intr_0 & pbdma_intr_0_device_pending_f()) != 0U) {
+		g->ops.pbdma.reset_header(g, pbdma_id);
+
+		for (i = 0U; i < 4U; i++) {
+			if (ga10b_pbdma_is_sw_method_subch(g,
+					pbdma_id, i)) {
+				ga10b_pbdma_reset_method(g,
+						pbdma_id, i);
+			}
+		}
+		recover = true;
+	}
+
+	return recover;
+}
+
+
+bool ga10b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0,
+			u32 *error_notifier)
+{
+	bool recover = ga10b_pbdma_handle_intr_0_legacy(g, pbdma_id,
+			 pbdma_intr_0, error_notifier);
+
+	if ((pbdma_intr_0 & pbdma_intr_0_eng_reset_pending_f()) != 0U) {
+		nvgpu_log(g, gpu_dbg_intr, "eng reset intr on pbdma id %d",
+				 pbdma_id);
+		recover = true;
+	}
+	report_pbdma_error(g, pbdma_id, pbdma_intr_0);
+	return recover;
+}
+
+/*
+ * Pbdma which encountered the ctxnotvalid interrupt will stall and
+ * prevent the channel which was loaded at the time the interrupt fired
+ * from being swapped out until the interrupt is cleared.
+ * CTXNOTVALID pbdma interrupt indicates error conditions related
+ * to the *_CTX_VALID fields for a channel.  The following
+ * conditions trigger the interrupt:
+ * * CTX_VALID bit for the targeted engine is FALSE
+ * * At channel start/resume, all preemptible eng have CTX_VALID FALSE but:
+ *       - CTX_RELOAD is set in CCSR_CHANNEL_STATUS,
+ *       - PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT is TRUE, or
+ *       - PBDMA_TARGET_NEEDS_HOST_TSG_EVENT is TRUE
+ * The field is left NOT_PENDING and the interrupt is not raised if the PBDMA is
+ * currently halted.  This allows SW to unblock the PBDMA and recover.
+ * SW may read METHOD0, CHANNEL_STATUS and TARGET to determine whether the
+ * interrupt was due to an engine method, CTX_RELOAD, SHOULD_SEND_HOST_TSG_EVENT
+ * or NEEDS_HOST_TSG_EVENT.  If METHOD0 VALID is TRUE, lazy context creation
+ * can be used or the TSG may be destroyed.
+ * If METHOD0 VALID is FALSE, the error is likely a bug in SW, and the TSG
+ * will have to be destroyed.
+ */
+
+bool ga10b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1,
+			u32 *error_notifier)
+{
+	bool recover = false;
+
+	u32 pbdma_intr_1_current = nvgpu_readl(g, pbdma_intr_1_r(pbdma_id));
+
+	/* minimize race with the gpu clearing the pending interrupt */
+	if ((pbdma_intr_1_current &
+	     pbdma_intr_1_ctxnotvalid_pending_f()) == 0U) {
+		pbdma_intr_1 &= ~pbdma_intr_1_ctxnotvalid_pending_f();
+	}
+
+	if (pbdma_intr_1 == 0U) {
+		return recover;
+	}
+
+	recover = true;
+
+	nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST, pbdma_id,
+			GPU_HOST_PBDMA_HCE_ERROR, pbdma_intr_1);
+
+	if ((pbdma_intr_1 & pbdma_intr_1_ctxnotvalid_pending_f()) != 0U) {
+		nvgpu_log(g, gpu_dbg_intr, "ctxnotvalid intr on pbdma id %d",
+				 pbdma_id);
+		nvgpu_err(g, "pbdma_intr_1(%d)= 0x%08x ",
+				pbdma_id, pbdma_intr_1);
+	} else{
+		/*
+		 * rest of the interrupts in _intr_1 are "host copy engine"
+		 * related, which is not supported. For now just make them
+		 * channel fatal.
+		 */
+		nvgpu_err(g, "hce err: pbdma_intr_1(%d):0x%08x",
+			pbdma_id, pbdma_intr_1);
+	}
+
+	return recover;
+}
+
+u32 ga10b_pbdma_channel_fatal_0_intr_descs(void)
+{
+	/*
+	 * These are data parsing, framing errors or others which can be
+	 * recovered from with intervention... or just resetting the
+	 * channel
+	 */
+	u32 channel_fatal_0_intr_descs =
+		pbdma_intr_0_gpfifo_pending_f() |
+		pbdma_intr_0_gpptr_pending_f() |
+		pbdma_intr_0_gpentry_pending_f() |
+		pbdma_intr_0_gpcrc_pending_f() |
+		pbdma_intr_0_pbptr_pending_f() |
+		pbdma_intr_0_pbentry_pending_f() |
+		pbdma_intr_0_pbcrc_pending_f() |
+		pbdma_intr_0_method_pending_f() |
+		pbdma_intr_0_pbseg_pending_f() |
+		pbdma_intr_0_eng_reset_pending_f() |
+		pbdma_intr_0_semaphore_pending_f() |
+		pbdma_intr_0_signature_pending_f();
+
+	return channel_fatal_0_intr_descs;
+}
+
+u32 ga10b_pbdma_device_fatal_0_intr_descs(void)
+{
+	/*
+	 * These are all errors which indicate something really wrong
+	 * going on in the device.
+	 */
+	u32 fatal_device_0_intr_descs = pbdma_intr_0_pri_pending_f();
+
+	return fatal_device_0_intr_descs;
+}
+
+u32 ga10b_pbdma_set_channel_info_chid(u32 chid)
+{
+	return pbdma_set_channel_info_chid_f(chid);
+}
+
+u32 ga10b_pbdma_set_intr_notify(u32 eng_intr_vector)
+{
+	return pbdma_intr_notify_vector_f(eng_intr_vector) |
+		pbdma_intr_notify_ctrl_gsp_disable_f() |
+		pbdma_intr_notify_ctrl_cpu_enable_f();
+}
+
+u32 ga10b_pbdma_get_fc_target(const struct nvgpu_device *dev)
+{
+	return (pbdma_target_engine_f(dev->next.rleng_id) |
+			pbdma_target_eng_ctx_valid_true_f() |
+			pbdma_target_ce_ctx_valid_true_f());
+}
+
+u32 ga10b_pbdma_get_mmu_fault_id(struct gk20a *g, u32 pbdma_id)
+{
+	u32 pbdma_cfg0 = nvgpu_readl(g, pbdma_cfg0_r(pbdma_id));
+
+	return pbdma_cfg0_pbdma_fault_id_v(pbdma_cfg0);
+}
+
+u32 ga10b_pbdma_get_num_of_pbdmas(void)
+{
+	return pbdma_cfg0__size_1_v();
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_status_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_status_ga10b.h
new file mode 100644
index 000000000..048e248bc
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_status_ga10b.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PBDMA_STATUS_GA10B_H
+#define NVGPU_PBDMA_STATUS_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_pbdma_status_info;
+
+void ga10b_read_pbdma_status_info(struct gk20a *g, u32 pbdma_id,
+		struct nvgpu_pbdma_status_info *status);
+
+#endif /* NVGPU_PBDMA_STATUS_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_status_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_status_ga10b_fusa.c
new file mode 100644
index 000000000..5c20aad9e
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_status_ga10b_fusa.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/pbdma_status.h>
+
+#include "pbdma_status_ga10b.h"
+#include <nvgpu/hw/ga10b/hw_pbdma_ga10b.h>
+
+static void populate_invalid_chsw_status_info(
+		struct nvgpu_pbdma_status_info *status_info)
+{
+	status_info->id = PBDMA_STATUS_ID_INVALID;
+	status_info->id_type = PBDMA_STATUS_ID_TYPE_INVALID;
+	status_info->next_id = PBDMA_STATUS_NEXT_ID_INVALID;
+	status_info->next_id_type = PBDMA_STATUS_NEXT_ID_TYPE_INVALID;
+	status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_INVALID;
+}
+
+static void populate_valid_chsw_status_info(
+		struct nvgpu_pbdma_status_info *status_info)
+{
+	u32 engine_status = status_info->pbdma_reg_status;
+
+	status_info->id = pbdma_status_sched_tsgid_v(engine_status);
+	status_info->id_type = PBDMA_STATUS_ID_TYPE_TSGID;
+	status_info->next_id = PBDMA_STATUS_NEXT_ID_INVALID;
+	status_info->next_id_type = PBDMA_STATUS_NEXT_ID_TYPE_INVALID;
+	status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_VALID;
+}
+
+static void populate_load_chsw_status_info(
+		struct nvgpu_pbdma_status_info *status_info)
+{
+	u32 engine_status = status_info->pbdma_reg_status;
+
+	status_info->id = PBDMA_STATUS_ID_INVALID;
+	status_info->id_type = PBDMA_STATUS_ID_TYPE_INVALID;
+	status_info->next_id = pbdma_status_sched_next_tsgid_v(engine_status);
+	status_info->next_id_type = PBDMA_STATUS_NEXT_ID_TYPE_TSGID;
+	status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_LOAD;
+}
+
+static void populate_save_chsw_status_info(
+		struct nvgpu_pbdma_status_info *status_info)
+{
+	u32 engine_status = status_info->pbdma_reg_status;
+
+	status_info->id = pbdma_status_sched_tsgid_v(engine_status);
+	status_info->id_type = PBDMA_STATUS_ID_TYPE_TSGID;
+	status_info->next_id = PBDMA_STATUS_NEXT_ID_INVALID;
+	status_info->next_id_type = PBDMA_STATUS_NEXT_ID_TYPE_INVALID;
+	status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_SAVE;
+}
+
+static void populate_switch_chsw_status_info(
+		struct nvgpu_pbdma_status_info *status_info)
+{
+	u32 engine_status = status_info->pbdma_reg_status;
+
+	status_info->id = pbdma_status_sched_tsgid_v(engine_status);
+	status_info->id_type = PBDMA_STATUS_ID_TYPE_TSGID;
+	status_info->next_id = pbdma_status_sched_next_tsgid_v(engine_status);
+	status_info->next_id_type = PBDMA_STATUS_NEXT_ID_TYPE_TSGID;
+	status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_SWITCH;
+}
+
+void ga10b_read_pbdma_status_info(struct gk20a *g, u32 pbdma_id,
+		struct nvgpu_pbdma_status_info *status)
+{
+	u32 pbdma_reg_status;
+	u32 pbdma_channel_status;
+
+	(void) memset(status, 0, sizeof(*status));
+
+	pbdma_reg_status = nvgpu_readl(g, pbdma_status_sched_r(pbdma_id));
+
+	status->pbdma_reg_status = pbdma_reg_status;
+
+	/* populate the chsw related info */
+	pbdma_channel_status = pbdma_status_sched_chan_status_v(
+		pbdma_reg_status);
+
+	status->pbdma_channel_status = pbdma_channel_status;
+
+	if (pbdma_channel_status == pbdma_status_sched_chan_status_valid_v()) {
+		populate_valid_chsw_status_info(status);
+	} else if (pbdma_channel_status ==
+			pbdma_status_sched_chan_status_chsw_load_v()) {
+		populate_load_chsw_status_info(status);
+	} else if (pbdma_channel_status ==
+			pbdma_status_sched_chan_status_chsw_save_v()) {
+		populate_save_chsw_status_info(status);
+	} else if (pbdma_channel_status ==
+			pbdma_status_sched_chan_status_chsw_switch_v()) {
+		populate_switch_chsw_status_info(status);
+	} else {
+		populate_invalid_chsw_status_info(status);
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/preempt_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/preempt_ga10b.h
new file mode 100644
index 000000000..0db9492a5
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/preempt_ga10b.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef FIFO_PREEMPT_GA10B_H
+#define FIFO_PREEMPT_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void ga10b_fifo_preempt_trigger(struct gk20a *g, u32 id, unsigned int id_type);
+
+#endif /* FIFO_PREEMPT_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/preempt_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/preempt_ga10b_fusa.c
new file mode 100644
index 000000000..4704365f1
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/preempt_ga10b_fusa.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/fifo.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/preempt.h>
+#include <nvgpu/nvgpu_err.h>
+
+#include "fifo_utils_ga10b.h"
+#include "preempt_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_runlist_ga10b.h>
+
+void ga10b_fifo_preempt_trigger(struct gk20a *g, u32 id, unsigned int id_type)
+{
+	struct nvgpu_runlist *runlist = NULL;
+
+	if (id == INVAL_ID) {
+		nvgpu_log(g, gpu_dbg_info, "Invalid id, cannot preempt");
+		return;
+	}
+
+	if (id_type == ID_TYPE_TSG) {
+		struct nvgpu_tsg *tsg = &g->fifo.tsg[id];
+		nvgpu_runlist_writel(g, tsg->runlist, runlist_preempt_r(),
+					runlist_preempt_id_f(id) |
+					runlist_preempt_type_tsg_f());
+	} else if (id_type == ID_TYPE_RUNLIST) {
+		runlist = g->fifo.runlists[id];
+		nvgpu_runlist_writel(g, runlist, runlist_preempt_r(),
+				runlist_preempt_type_runlist_f());
+	} else {
+		nvgpu_log_info(g, "id_type=%u preempt is noop", id_type);
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b.h
new file mode 100644
index 000000000..3d25473bc
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_RAMFC_GA10B_H
+#define NVGPU_RAMFC_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct nvgpu_channel;
+struct nvgpu_channel_dump_info;
+
+int ga10b_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base,
+		u32 gpfifo_entries, u64 pbdma_acquire_timeout, u32 flags);
+void ga10b_ramfc_capture_ram_dump(struct gk20a *g, struct nvgpu_channel *ch,
+				  struct nvgpu_channel_dump_info *info);
+#endif /* NVGPU_RAMFC_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b_fusa.c
new file mode 100644
index 000000000..f108958c5
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b_fusa.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/log2.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/runlist.h>
+
+#include "hal/fifo/ramfc_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_ram_ga10b.h>
+
+int ga10b_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base,
+		u32 gpfifo_entries, u64 pbdma_acquire_timeout, u32 flags)
+{
+	struct gk20a *g = ch->g;
+	struct nvgpu_mem *mem = &ch->inst_block;
+	u32 data;
+	u32 engine_id = 0U;
+	u32 eng_intr_mask = 0U;
+	u32 eng_intr_vector = 0U;
+	u32 eng_bitmask = 0U;
+	bool replayable = false;
+
+	nvgpu_log_fn(g, " ");
+
+	/*
+	 * ga10b can have max 3 engines on a runlist and only
+	 * runlist 0 has more than 1 engine(gr0, grcopy0 and grcopy1).
+	 * Since grcopy0 and grcopy1 can't schedule work directly, it
+	 * is always safe to assume that first active engine on runlist
+	 * will trigger pbdma intr notify.
+	 * TODO: Add helper function to get active engine mask for
+	 * runlist - NVGPU-5219
+	 */
+	eng_bitmask = ch->runlist->eng_bitmask;
+	engine_id = nvgpu_safe_sub_u32(
+		nvgpu_safe_cast_u64_to_u32(nvgpu_ffs(eng_bitmask)), 1U);
+
+	nvgpu_memset(g, mem, 0U, 0U, ram_fc_size_val_v());
+
+#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
+	if ((flags & NVGPU_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE) != 0U) {
+		replayable = true;
+	}
+#endif
+
+	nvgpu_log_info(g, "%llu %u", pbdma_acquire_timeout,
+		g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
+
+	g->ops.ramin.init_subctx_pdb(g, mem, ch->vm->pdb.mem,
+		replayable, nvgpu_channel_get_max_subctx_count(ch));
+
+	nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(),
+		g->ops.pbdma.get_gp_base(gpfifo_base));
+
+	nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
+		g->ops.pbdma.get_gp_base_hi(gpfifo_base, gpfifo_entries));
+
+	nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
+		ch->g->ops.pbdma.get_signature(ch->g));
+
+	nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(),
+		g->ops.pbdma.get_fc_pb_header());
+
+	nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(),
+		g->ops.pbdma.get_fc_subdevice());
+
+	nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
+		g->ops.pbdma.get_fc_target(
+			nvgpu_engine_get_active_eng_info(g, engine_id)));
+
+	nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
+		g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
+
+	data = nvgpu_mem_rd32(g, mem, ram_fc_set_channel_info_w());
+
+	data = data | (g->ops.pbdma.set_channel_info_veid(ch->subctx_id) |
+		   g->ops.pbdma.set_channel_info_chid(ch->chid));
+	nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), data);
+	nvgpu_mem_wr32(g, mem, ram_in_engine_wfi_veid_w(),
+		ram_in_engine_wfi_veid_f(ch->subctx_id));
+
+	/* get engine interrupt vector */
+	eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, engine_id);
+	eng_intr_vector = nvgpu_safe_sub_u32(
+		nvgpu_safe_cast_u64_to_u32(nvgpu_ffs(eng_intr_mask)), 1U);
+
+	/*
+	 * engine_intr_vector can be value between 0 and 255.
+	 * For example, engine_intr_vector x translates to subtree x/64,
+	 * leaf (x % 64)/32 and leaf entry interrupt bit(x % 64)%32.
+	 * ga10b engine_intr_vectors are 0,1,2,3,4,5. They map to
+	 * subtree_0 and leaf_0(Engine non-stall interrupts) interrupt
+	 * bits.
+	 */
+	data = g->ops.pbdma.set_intr_notify(eng_intr_vector);
+	nvgpu_mem_wr32(g, mem, ram_fc_intr_notify_w(), data);
+
+	if (ch->is_privileged_channel) {
+		/* Set privilege level for channel */
+		nvgpu_mem_wr32(g, mem, ram_fc_config_w(),
+			g->ops.pbdma.get_config_auth_level_privileged());
+
+		/* Enable HCE priv mode for phys mode transfer */
+		nvgpu_mem_wr32(g, mem, ram_fc_hce_ctrl_w(),
+			g->ops.pbdma.get_ctrl_hce_priv_mode_yes());
+	}
+
+	/* Enable userd writeback */
+	data = nvgpu_mem_rd32(g, mem, ram_fc_config_w());
+	data = g->ops.pbdma.config_userd_writeback_enable(data);
+	nvgpu_mem_wr32(g, mem, ram_fc_config_w(), data);
+
+	return 0;
+}
+
+void ga10b_ramfc_capture_ram_dump(struct gk20a *g, struct nvgpu_channel *ch,
+				  struct nvgpu_channel_dump_info *info)
+{
+	struct nvgpu_mem *mem = &ch->inst_block;
+
+	info->inst.pb_top_level_get = nvgpu_mem_rd32_pair(g, mem,
+			ram_fc_pb_top_level_get_w(),
+			ram_fc_pb_top_level_get_hi_w());
+	info->inst.pb_put = nvgpu_mem_rd32_pair(g, mem,
+			ram_fc_pb_put_w(),
+			ram_fc_pb_put_hi_w());
+	info->inst.pb_get = nvgpu_mem_rd32_pair(g, mem,
+			ram_fc_pb_get_w(),
+			ram_fc_pb_get_hi_w());
+	info->inst.pb_header = nvgpu_mem_rd32(g, mem,
+			ram_fc_pb_header_w());
+	info->inst.pb_count = nvgpu_mem_rd32(g, mem,
+			ram_fc_pb_count_w());
+	info->inst.sem_addr = nvgpu_mem_rd32_pair(g, mem,
+			ram_fc_sem_addr_lo_w(),
+			ram_fc_sem_addr_hi_w());
+	info->inst.sem_payload = nvgpu_mem_rd32_pair(g, mem,
+			ram_fc_sem_payload_lo_w(),
+			ram_fc_sem_payload_hi_w());
+	info->inst.sem_execute = nvgpu_mem_rd32(g, mem,
+			ram_fc_sem_execute_w());
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b.h
new file mode 100644
index 000000000..2c6f78fea
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_RAMIN_GA10B_H
+#define NVGPU_RAMIN_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_mem;
+
+void ga10b_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
+		u64 pdb_addr, struct nvgpu_mem *pdb_mem);
+
+#endif /* NVGPU_RAMIN_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b_fusa.c
new file mode 100644
index 000000000..6f23303dc
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b_fusa.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/channel.h>
+
+#include "hal/fifo/ramin_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_ram_ga10b.h>
+
+void ga10b_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
+		u64 pdb_addr, struct nvgpu_mem *pdb_mem)
+{
+	u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
+	u32 pdb_addr_hi = u64_hi32(pdb_addr);
+
+	nvgpu_log_info(g, "pde pa=0x%llx", pdb_addr);
+
+	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(),
+		nvgpu_aperture_mask(g, pdb_mem,
+				ram_in_page_dir_base_target_sys_mem_ncoh_f(),
+				ram_in_page_dir_base_target_sys_mem_coh_f(),
+				ram_in_page_dir_base_target_vid_mem_f()) |
+		ram_in_page_dir_base_vol_true_f() |
+		ram_in_big_page_size_64kb_f() |
+		ram_in_page_dir_base_lo_f(pdb_addr_lo) |
+		ram_in_use_ver2_pt_format_true_f());
+
+	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
+		ram_in_page_dir_base_hi_f(pdb_addr_hi));
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga100.h b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga100.h
new file mode 100644
index 000000000..192e8d254
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga100.h
@@ -0,0 +1,35 @@
+/*
+ * GA100 runlist
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_RUNLIST_FIFO_GA100_H
+#define NVGPU_RUNLIST_FIFO_GA100_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+u32 ga100_runlist_count_max(struct gk20a *g);
+void ga100_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
+					u32 count, u32 buffer_index);
+#endif /* NVGPU_RUNLIST_FIFO_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga100_fusa.c b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga100_fusa.c
new file mode 100644
index 000000000..196eb9a22
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga100_fusa.c
@@ -0,0 +1,71 @@
+/*
+ * GA100 Runlist
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/soc.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/runlist.h>
+
+#include <nvgpu/hw/ga100/hw_runlist_ga100.h>
+
+#include "fifo_utils_ga10b.h"
+#include "runlist_fifo_ga100.h"
+
+u32 ga100_runlist_count_max(struct gk20a *g)
+{
+	return nvgpu_get_litter_value(g, GPU_LIT_MAX_RUNLISTS_SUPPORTED);
+}
+
+void ga100_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
+				u32 count, u32 buffer_index)
+{
+	struct nvgpu_runlist *runlist = NULL;
+	u64 runlist_iova;
+	u32 runlist_iova_lo, runlist_iova_hi;
+
+	runlist = g->fifo.runlists[runlist_id];
+
+	runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[buffer_index]);
+	runlist_iova_lo = u64_lo32(runlist_iova) >>
+			runlist_submit_base_lo_ptr_align_shift_v();
+	runlist_iova_hi = u64_hi32(runlist_iova);
+
+	if (count != 0U) {
+		nvgpu_runlist_writel(g, runlist, runlist_submit_base_lo_r(),
+			runlist_submit_base_lo_ptr_lo_f(runlist_iova_lo) |
+			nvgpu_aperture_mask(g, &runlist->mem[buffer_index],
+			runlist_submit_base_lo_target_sys_mem_noncoherent_f(),
+			runlist_submit_base_lo_target_sys_mem_coherent_f(),
+			runlist_submit_base_lo_target_vid_mem_f()));
+
+		nvgpu_runlist_writel(g, runlist, runlist_submit_base_hi_r(),
+			runlist_submit_base_hi_ptr_hi_f(runlist_iova_hi));
+	}
+
+	/* TODO offset in runlist support */
+	nvgpu_runlist_writel(g, runlist, runlist_submit_r(),
+			runlist_submit_offset_f(0U) |
+			runlist_submit_length_f(count));
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b.c b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b.c
new file mode 100644
index 000000000..b2cdcfb10
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/channel.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/engine_status.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/device.h>
+#include <nvgpu/gr/gr_falcon.h>
+
+#include "fifo_utils_ga10b.h"
+#include "runlist_fifo_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_runlist_ga10b.h>
+
+#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
+#define FECS_MAILBOX_0_ACK_RESTORE 0x4U
+
+/* trigger host preempt of GR pending load ctx if that ctx is not for ch */
+int ga10b_fifo_reschedule_preempt_next(struct nvgpu_channel *ch,
+		bool wait_preempt)
+{
+	struct gk20a *g = ch->g;
+	struct nvgpu_runlist *runlist = ch->runlist;
+	u32 fecsstat0 = 0, fecsstat1 = 0;
+	u32 preempt_id;
+	u32 preempt_type = 0;
+	u32 i = 0U, eng_bitmask = 0U;
+	const struct nvgpu_device *dev;
+	struct nvgpu_engine_status_info engine_status;
+
+	/* TODO: [Jira NVGPU-5039] Re-arch function */
+
+	for (i = 0U; i < nvgpu_device_count(g, NVGPU_DEVTYPE_GRAPHICS); i++) {
+		dev = nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS, i);
+		nvgpu_assert(dev != NULL);
+
+		eng_bitmask |= BIT32(dev->engine_id);
+	}
+
+	if ((runlist->eng_bitmask & eng_bitmask) == 0U) {
+		/* Given runlist doesn't serve any GR engines */
+		return 0;
+	}
+
+	if (wait_preempt) {
+		u32 val = nvgpu_runlist_readl(g, runlist, runlist_preempt_r());
+
+		if ((val & runlist_preempt_runlist_preempt_pending_true_f()) ||
+			(val & runlist_preempt_tsg_preempt_pending_true_f()) !=
+			0U) {
+			/* Current runlist/tsg preemption is pending */
+			return 0;
+		}
+	}
+
+	fecsstat0 = g->ops.gr.falcon.read_fecs_ctxsw_mailbox(g,
+			NVGPU_GR_FALCON_FECS_CTXSW_MAILBOX0);
+	g->ops.engine_status.read_engine_status_info(g, nvgpu_safe_sub_u32(
+		nvgpu_ffs(runlist->eng_bitmask & eng_bitmask), 1U),
+		&engine_status);
+	if (nvgpu_engine_status_is_ctxsw_switch(&engine_status)) {
+		nvgpu_engine_status_get_next_ctx_id_type(&engine_status,
+			&preempt_id, &preempt_type);
+	} else {
+		/* GR engine is in CTXSW state */
+		return 0;
+	}
+	if ((preempt_id == ch->tsgid) &&
+		(preempt_type != ENGINE_STATUS_CTX_ID_TYPE_TSGID)) {
+		/* Next ctx is not TSG type */
+		return 0;
+	}
+	fecsstat1 = g->ops.gr.falcon.read_fecs_ctxsw_mailbox(g,
+			NVGPU_GR_FALCON_FECS_CTXSW_MAILBOX0);
+	if (fecsstat0 != FECS_MAILBOX_0_ACK_RESTORE ||
+		fecsstat1 != FECS_MAILBOX_0_ACK_RESTORE) {
+		/* preempt useless if FECS acked save and started restore */
+		return 0;
+	}
+
+	g->ops.fifo.preempt_trigger(g, preempt_id, preempt_type != 0U);
+#ifdef TRACEPOINTS_ENABLED
+	trace_gk20a_reschedule_preempt_next(ch->chid, fecsstat0,
+		engine_status.reg_data, fecsstat1,
+		g->ops.gr.falcon.read_fecs_ctxsw_mailbox(g,
+			NVGPU_GR_FALCON_FECS_CTXSW_MAILBOX0),
+		nvgpu_runlist_readl(g, runlist, runlist_preempt_r());
+#endif
+	if (wait_preempt) {
+		if (g->ops.fifo.is_preempt_pending(g, preempt_id,
+			preempt_type, false) != 0) {
+			nvgpu_err(g, "fifo preempt timed out");
+			/*
+			 * This function does not care if preempt
+			 * times out since it is here only to improve
+			 * latency. If a timeout happens, it will be
+			 * handled by other fifo handling code.
+			 */
+		}
+	}
+#ifdef TRACEPOINTS_ENABLED
+	trace_gk20a_reschedule_preempted_next(ch->chid);
+#endif
+	return 0;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b.h
new file mode 100644
index 000000000..faf9fe6ca
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b.h
@@ -0,0 +1,44 @@
+/*
+ * GA10B runlist
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_RUNLIST_FIFO_GA10B_H
+#define NVGPU_RUNLIST_FIFO_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+u32 ga10b_runlist_count_max(struct gk20a *g);
+u32 ga10b_runlist_length_max(struct gk20a *g);
+void ga10b_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
+					u32 count, u32 buffer_index);
+int ga10b_runlist_wait_pending(struct gk20a *g, u32 runlist_id);
+void ga10b_runlist_write_state(struct gk20a *g, u32 runlists_mask,
+				u32 runlist_state);
+#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
+int ga10b_fifo_reschedule_preempt_next(struct nvgpu_channel *ch,
+		bool wait_preempt);
+#endif
+
+#endif /* NVGPU_RUNLIST_FIFO_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b_fusa.c
new file mode 100644
index 000000000..94b0d173c
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b_fusa.c
@@ -0,0 +1,135 @@
+/*
+ * GA10B Runlist
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/power_features/cg.h>
+#include <nvgpu/static_analysis.h>
+#include <nvgpu/mc.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/runlist.h>
+
+#include <nvgpu/hw/ga10b/hw_runlist_ga10b.h>
+
+#include "fifo_utils_ga10b.h"
+#include "runlist_fifo_ga10b.h"
+
+u32 ga10b_runlist_count_max(struct gk20a *g)
+{
+	/* TODO Needs to be read from litter values */
+	return 4U;
+}
+
+u32 ga10b_runlist_length_max(struct gk20a *g)
+{
+	return runlist_submit_length_max_v();
+}
+
+void ga10b_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
+				u32 count, u32 buffer_index)
+{
+	struct nvgpu_runlist *runlist = NULL;
+	u64 runlist_iova;
+	u32 runlist_iova_lo, runlist_iova_hi;
+
+	runlist = g->fifo.runlists[runlist_id];
+
+	runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[buffer_index]);
+	runlist_iova_lo = u64_lo32(runlist_iova) >>
+			runlist_submit_base_lo_ptr_align_shift_v();
+	runlist_iova_hi = u64_hi32(runlist_iova);
+
+	if (count != 0U) {
+		nvgpu_runlist_writel(g, runlist, runlist_submit_base_lo_r(),
+			runlist_submit_base_lo_ptr_lo_f(runlist_iova_lo) |
+			nvgpu_aperture_mask(g, &runlist->mem[buffer_index],
+			runlist_submit_base_lo_target_sys_mem_noncoherent_f(),
+			runlist_submit_base_lo_target_sys_mem_coherent_f(),
+			runlist_submit_base_lo_target_vid_mem_f()));
+
+		nvgpu_runlist_writel(g, runlist, runlist_submit_base_hi_r(),
+			runlist_submit_base_hi_ptr_hi_f(runlist_iova_hi));
+	}
+
+	/* TODO offset in runlist support */
+	nvgpu_runlist_writel(g, runlist, runlist_submit_r(),
+			runlist_submit_offset_f(0U) |
+			runlist_submit_length_f(count));
+}
+
+int ga10b_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
+{
+	struct nvgpu_timeout timeout;
+	u32 delay = POLL_DELAY_MIN_US;
+	int ret;
+	struct nvgpu_runlist *runlist = NULL;
+
+	runlist = g->fifo.runlists[runlist_id];
+
+	ret = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
+				NVGPU_TIMER_CPU_TIMER);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = -ETIMEDOUT;
+	do {
+		if ((nvgpu_runlist_readl(g, runlist, runlist_submit_info_r()) &
+			runlist_submit_info_pending_true_f()) == 0U) {
+			ret = 0;
+			break;
+		}
+
+		nvgpu_usleep_range(delay, delay * 2U);
+		delay = min_t(u32, delay << 1, POLL_DELAY_MAX_US);
+	} while (nvgpu_timeout_expired(&timeout) == 0);
+
+	return ret;
+}
+
+void ga10b_runlist_write_state(struct gk20a *g, u32 runlists_mask,
+						u32 runlist_state)
+{
+	u32 reg_val;
+	u32 runlist_id = 0U;
+	struct nvgpu_runlist *runlist = NULL;
+
+	if (runlist_state == RUNLIST_DISABLED) {
+		reg_val = runlist_sched_disable_runlist_disabled_v();
+	} else {
+		reg_val = runlist_sched_disable_runlist_enabled_v();
+	}
+
+	while (runlists_mask != 0U) {
+		if ((runlists_mask & BIT32(runlist_id)) != 0U) {
+			runlist = g->fifo.runlists[runlist_id];
+			nvgpu_runlist_writel(g, runlist,
+				runlist_sched_disable_r(), reg_val);
+		}
+		runlists_mask &= ~BIT32(runlist_id);
+		runlist_id++;
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b.h
new file mode 100644
index 000000000..0e8a73e8f
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_RUNLIST_GA10B_H
+#define NVGPU_RUNLIST_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_next_pbdma_info;
+
+u32 ga10b_runlist_get_runlist_id(struct gk20a *g, u32 runlist_pri_base);
+u32 ga10b_runlist_get_engine_id_from_rleng_id(struct gk20a *g,
+			u32 rleng_id, u32 runlist_pri_base);
+u32 ga10b_runlist_get_chram_bar0_offset(struct gk20a *g, u32 runlist_pri_base);
+void ga10b_runlist_get_pbdma_info(struct gk20a *g, u32 runlist_pri_base,
+		struct nvgpu_next_pbdma_info *pbdma_info);
+u32 ga10b_runlist_get_engine_intr_id(struct gk20a *g, u32 runlist_pri_base,
+		u32 rleng_id);
+u32 ga10b_runlist_get_esched_fb_thread_id(struct gk20a *g, u32 runlist_pri_base);
+
+#endif /* NVGPU_RUNLIST_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b_fusa.c
new file mode 100644
index 000000000..251bbb7cc
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b_fusa.c
@@ -0,0 +1,114 @@
+/*
+ * GA10B runlist
+ *
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/static_analysis.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/pbdma.h>
+
+#include "runlist_ga10b.h"
+#include "pbdma_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_runlist_ga10b.h>
+
+u32 ga10b_runlist_get_runlist_id(struct gk20a *g, u32 runlist_pri_base)
+{
+	u32 doorbell_config = nvgpu_readl(g, nvgpu_safe_add_u32(
+			runlist_pri_base, runlist_doorbell_config_r()));
+
+	return runlist_doorbell_config_id_v(doorbell_config);
+}
+
+u32 ga10b_runlist_get_engine_id_from_rleng_id(struct gk20a *g,
+					u32 rleng_id, u32 runlist_pri_base)
+{
+	u32 engine_status_debug = nvgpu_readl(g, nvgpu_safe_add_u32(
+			runlist_pri_base,
+			runlist_engine_status_debug_r(rleng_id)));
+
+	return runlist_engine_status_debug_engine_id_v(engine_status_debug);
+}
+
+u32 ga10b_runlist_get_chram_bar0_offset(struct gk20a *g, u32 runlist_pri_base)
+{
+	u32 channel_config = nvgpu_readl(g, nvgpu_safe_add_u32(
+			runlist_pri_base, runlist_channel_config_r()));
+
+	return (runlist_channel_config_chram_bar0_offset_v(channel_config)
+			<< runlist_channel_config_chram_bar0_offset_b());
+}
+
+/*
+ * Use u32 runlist_pri_base instead of struct nvgpu_runlist *runlist
+ * as input paramter, because by the time this hal is called, runlist_info
+ * is not populated.
+ */
+void ga10b_runlist_get_pbdma_info(struct gk20a *g, u32 runlist_pri_base,
+			struct nvgpu_next_pbdma_info *pbdma_info)
+{
+	u32 i, pbdma_config;
+
+	if (runlist_pbdma_config__size_1_v() != PBDMA_PER_RUNLIST_SIZE) {
+		nvgpu_warn(g, "mismatch: h/w & s/w for pbdma_per_runlist_size");
+	}
+	for (i = 0U; i < runlist_pbdma_config__size_1_v(); i++) {
+		pbdma_config = nvgpu_readl(g, nvgpu_safe_add_u32(
+				runlist_pri_base, runlist_pbdma_config_r(i)));
+		if (runlist_pbdma_config_valid_v(pbdma_config) ==
+				runlist_pbdma_config_valid_true_v()) {
+			pbdma_info->pbdma_pri_base[i] =
+			runlist_pbdma_config_pbdma_bar0_offset_v(pbdma_config);
+			pbdma_info->pbdma_id[i] =
+				runlist_pbdma_config_id_v(pbdma_config);
+		} else {
+			pbdma_info->pbdma_pri_base[i] =
+						NVGPU_INVALID_PBDMA_PRI_BASE;
+			pbdma_info->pbdma_id[i] = NVGPU_INVALID_PBDMA_ID;
+		}
+	}
+}
+
+u32 ga10b_runlist_get_engine_intr_id(struct gk20a *g, u32 runlist_pri_base,
+			u32 rleng_id)
+{
+	u32 engine_status1;
+
+	engine_status1  = nvgpu_readl(g, nvgpu_safe_add_u32(
+			runlist_pri_base, runlist_engine_status1_r(rleng_id)));
+	/**
+	 * intr_id indicates the engine's default interrupt bit position in the
+	 * engine_stall and engine_non_stall leaf registers within the top interrupt
+	 * trees.
+	 */
+	return (runlist_engine_status1_intr_id_v(engine_status1));
+}
+
+u32 ga10b_runlist_get_esched_fb_thread_id(struct gk20a *g, u32 runlist_pri_base)
+{
+	u32 esched_fb_config = nvgpu_readl(g, nvgpu_safe_add_u32(
+			runlist_pri_base, runlist_fb_config_r()));
+
+	return runlist_fb_config_fb_thread_id_v(esched_fb_config);
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/tsg_ga10b.c b/drivers/gpu/nvgpu/hal/fifo/tsg_ga10b.c
new file mode 100644
index 000000000..08b7babca
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/tsg_ga10b.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/channel.h>
+#include <nvgpu/dma.h>
+#include <nvgpu/gk20a.h>
+
+#include "hal/fifo/tsg_ga10b.h"
+
+int ga10b_tsg_unbind_channel_check_hw_next(struct nvgpu_channel *ch,
+		struct nvgpu_channel_hw_state *hw_state)
+{
+	if (hw_state->next) {
+		nvgpu_log_info(ch->g, "Channel %d to be removed "
+			"from TSG %d has NEXT set!",
+			ch->chid, ch->tsgid);
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/tsg_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/tsg_ga10b.h
new file mode 100644
index 000000000..b15ab9ee1
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/tsg_ga10b.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_TSG_GA10B_H
+#define NVGPU_TSG_GA10B_H
+
+struct nvgpu_channel;
+struct nvgpu_channel_hw_state;
+
+int ga10b_tsg_unbind_channel_check_hw_next(struct nvgpu_channel *ch,
+		struct nvgpu_channel_hw_state *hw_state);
+
+#endif /* NVGPU_TSG_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/userd_ga10b.c b/drivers/gpu/nvgpu/hal/fifo/userd_ga10b.c
new file mode 100644
index 000000000..a2a00a66f
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/userd_ga10b.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/bug.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/nvgpu_mem.h>
+
+#include "userd_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_ram_ga10b.h>
+
+#ifdef CONFIG_NVGPU_USERD
+void ga10b_userd_init_mem(struct gk20a *g, struct nvgpu_channel *c)
+{
+	struct nvgpu_mem *mem = c->userd_mem;
+	u32 offset = c->userd_offset / U32(sizeof(u32));
+
+	nvgpu_log_fn(g, " ");
+
+	nvgpu_mem_wr32(g, mem, offset + ram_userd_put_w(), 0);
+	nvgpu_mem_wr32(g, mem, offset + ram_userd_get_w(), 0);
+	nvgpu_mem_wr32(g, mem, offset + ram_userd_ref_w(), 0);
+	nvgpu_mem_wr32(g, mem, offset + ram_userd_put_hi_w(), 0);
+	nvgpu_mem_wr32(g, mem, offset + ram_userd_top_level_get_w(), 0);
+	nvgpu_mem_wr32(g, mem, offset + ram_userd_top_level_get_hi_w(), 0);
+	nvgpu_mem_wr32(g, mem, offset + ram_userd_get_hi_w(), 0);
+	nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_get_w(), 0);
+	nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_put_w(), 0);
+}
+#endif /* CONFIG_NVGPU_USERD */
diff --git a/drivers/gpu/nvgpu/hal/fifo/userd_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/userd_ga10b.h
new file mode 100644
index 000000000..c43dad6f6
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/userd_ga10b.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef USERD_GA10B_H
+#define USERD_GK10B_H
+
+#ifdef CONFIG_NVGPU_USERD
+struct gk20a;
+struct nvgpu_channel;
+
+void ga10b_userd_init_mem(struct gk20a *g, struct nvgpu_channel *c);
+#endif
+
+#endif /* USERD_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/usermode_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/usermode_ga10b.h
new file mode 100644
index 000000000..24e4b60bd
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/usermode_ga10b.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_USERMODE_GA10B_H
+#define NVGPU_USERMODE_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void ga10b_usermode_setup_hw(struct gk20a *g);
+
+#endif /* NVGPU_USERMODE_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/usermode_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/usermode_ga10b_fusa.c
new file mode 100644
index 000000000..ef06978a7
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fifo/usermode_ga10b_fusa.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/runlist.h>
+
+#include "usermode_ga10b.h"
+
+#include "hal/fifo/fifo_utils_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_runlist_ga10b.h>
+
+#define GFID_INSTANCE_0		0U
+
+/*
+ * nvgpu_fifo.max_runlists:
+ *      - Maximum runlists supported by hardware.
+ * nvgpu_fifo.num_runlists:
+ *      - Number of valid runlists detected during device info parsing and
+ *        connected to a valid engine.
+ * nvgpu_fifo.runlists[]:
+ *      - This is an array of pointers to nvgpu_runlist_info structure.
+ *      - This is indexed by hardware runlist_id from 0 to max_runlists.
+ * nvgpu_fifo.active_runlists[]:
+ *      - This is an array of nvgpu_runlist_info structure.
+ *      - This is indexed by software [consecutive] runlist_ids from 0 to
+ *        num_runlists.
+ *
+ * runlists[] pointers at valid runlist_id indices contain valid
+ * nvgpu_runlist structures. runlist[] pointers at invalid runlist_id
+ * indexes point to NULL. This is explained in the example below.
+ *
+ * for example: max_runlists = 10, num_runlists = 4
+ *              say valid runlist_ids are = {0, 2, 3, 7}
+ *
+ *         runlist_info                           active_runlists
+ *      0 ________________                  0 ___________________________
+ *       |________________|----------------->|___________________________|
+ *       |________________|   |------------->|___________________________|
+ *       |________________|---|  |---------->|___________________________|
+ *       |________________|------|  |------->|___________________________|
+ *       |________________|         |    num_runlists
+ *       |________________|         |
+ *       |________________|         |
+ *       |________________|---------|
+ *       |________________|
+ *       |________________|
+ *  max_runlists
+ *
+ */
+
+void ga10b_usermode_setup_hw(struct gk20a *g)
+{
+	struct nvgpu_runlist *runlist = NULL;
+	u32 reg_val = 0U;
+	u32 i = 0U;
+	u32 max_runlist = g->ops.runlist.count_max(g);
+
+	for (i = 0U; i < max_runlist; i++) {
+		runlist = g->fifo.runlists[i];
+		if (runlist == NULL) {
+			continue;
+		}
+
+		/*
+		 * At this moment, we are not supporting multiple GFIDs.
+		 * Only GFID 0 is supported and passed to
+		 * runlist_virtual_channel_cfg_r()
+		 */
+		reg_val = nvgpu_runlist_readl(g, runlist,
+				runlist_virtual_channel_cfg_r(GFID_INSTANCE_0));
+		reg_val |= runlist_virtual_channel_cfg_mask_hw_mask_hw_init_f();
+		reg_val |= runlist_virtual_channel_cfg_pending_enable_true_f();
+
+		nvgpu_runlist_writel(g, runlist,
+			runlist_virtual_channel_cfg_r(GFID_INSTANCE_0),
+			reg_val);
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/func/func_ga10b.c b/drivers/gpu/nvgpu/hal/func/func_ga10b.c
new file mode 100644
index 000000000..2d3f0a969
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/func/func_ga10b.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/gk20a.h>
+
+#include "hal/func/func_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_func_ga10b.h>
+
+u32 ga10b_func_get_full_phys_offset(struct gk20a *g)
+{
+	return func_full_phys_offset_v();
+}
diff --git a/drivers/gpu/nvgpu/hal/func/func_ga10b.h b/drivers/gpu/nvgpu/hal/func/func_ga10b.h
new file mode 100644
index 000000000..815b72376
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/func/func_ga10b.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef FUNC_GA10B_H
+#define FUNC_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+u32 ga10b_func_get_full_phys_offset(struct gk20a *g);
+
+#endif /* FUNC_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.c b/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.c
new file mode 100644
index 000000000..bf2f5576f
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.c
@@ -0,0 +1,67 @@
+/*
+ * GA100 FUSE
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/types.h>
+#include <nvgpu/io.h>
+#include <nvgpu/falcon.h>
+
+#include "fuse_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_fuse_ga100.h>
+
+u32 ga100_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp)
+{
+	return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp));
+}
+
+int ga100_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi)
+{
+	u32 lo = nvgpu_readl(g, fuse_opt_pdi_0_r());
+	u32 hi = nvgpu_readl(g, fuse_opt_pdi_1_r());
+
+	*pdi = ((u64)lo) | (((u64)hi) << 32);
+
+	return 0;
+}
+
+int ga100_read_ucode_version(struct gk20a *g, u32 falcon_id, u32 *ucode_version)
+{
+	u32 err = 0;
+
+	switch (falcon_id) {
+	case FALCON_ID_GSPLITE:
+		*ucode_version = nvgpu_readl(g, fuse_gsp_ucode1_version_r());
+		break;
+	case FALCON_ID_SEC2:
+		*ucode_version = nvgpu_readl(g, fuse_sec2_ucode1_version_r());
+		break;
+	default:
+		err = -EINVAL;
+		nvgpu_err(g, "Invalid/Unsupported falcon ID %x", falcon_id);
+		break;
+	}
+
+	return err;
+}
diff --git a/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.h b/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.h
new file mode 100644
index 000000000..603c13b4d
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.h
@@ -0,0 +1,35 @@
+/*
+ * GA100 FUSE
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FUSE_GA100_H
+#define NVGPU_FUSE_GA100_H
+
+struct gk20a;
+
+u32 ga100_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp);
+int ga100_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi);
+int ga100_read_ucode_version(struct gk20a *g, u32 falcon_id,
+		u32 *ucode_version);
+
+#endif /* NVGPU_FUSE_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.c b/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.c
new file mode 100644
index 000000000..346d85336
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.c
@@ -0,0 +1,438 @@
+/*
+ * GA10B FUSE
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/fuse.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/io.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/gk20a.h>
+
+#include "fuse_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_fuse_ga10b.h>
+
+#define AES_ALGO BIT(0)
+#define PKC_ALGO BIT(1)
+
+int ga10b_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
+{
+	u32 reg_val = 0U;
+	int fuse_val = 0;
+
+	/*
+	 * SOC FUSE_GCPLEX_CONFIG_FUSE_0 bit(2) mapped to
+	 * fuse_opt_wpr_enabled igpu fuse register
+	 */
+	reg_val = nvgpu_readl(g, fuse_opt_wpr_enabled_r());
+	fuse_val |= (fuse_opt_wpr_enabled_data_v(reg_val) << 2U);
+
+	/*
+	 * SOC FUSE_GCPLEX_CONFIG_FUSE_0 bit(1) mapped to
+	 * fuse_opt_vpr_enabled igpu fuse register
+	 */
+	reg_val = nvgpu_readl(g, fuse_opt_vpr_enabled_r());
+	fuse_val |= (fuse_opt_vpr_enabled_data_v(reg_val) << 1U);
+
+	/*
+	 * SOC FUSE_GCPLEX_CONFIG_FUSE_0 bit(0) mapped to
+	 * fuse_opt_vpr_auto_fetch_disable
+	 */
+	reg_val = nvgpu_readl(g, fuse_opt_vpr_auto_fetch_disable_r());
+	fuse_val |= fuse_opt_vpr_auto_fetch_disable_data_v(reg_val);
+
+	*val = fuse_val;
+
+	return 0;
+}
+
+bool ga10b_fuse_is_opt_ecc_enable(struct gk20a *g)
+{
+	return nvgpu_readl(g, fuse_opt_ecc_en_r()) != 0U;
+}
+
+bool ga10b_fuse_is_opt_feature_override_disable(struct gk20a *g)
+{
+	return nvgpu_readl(g,
+			fuse_opt_feature_fuses_override_disable_r()) != 0U;
+}
+
+u32 ga10b_fuse_status_opt_gpc(struct gk20a *g)
+{
+	return nvgpu_readl(g, fuse_status_opt_gpc_r());
+}
+
+u32 ga10b_fuse_status_opt_fbio(struct gk20a *g)
+{
+	return nvgpu_readl(g, fuse_status_opt_fbio_r());
+}
+
+u32 ga10b_fuse_status_opt_fbp(struct gk20a *g)
+{
+	return nvgpu_readl(g, fuse_status_opt_fbp_r());
+}
+
+u32 ga10b_fuse_status_opt_rop_gpc(struct gk20a *g, u32 fbp)
+{
+	return nvgpu_readl(g, fuse_status_opt_rop_gpc_r(fbp));
+}
+
+u32 ga10b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc)
+{
+	return nvgpu_readl(g, fuse_status_opt_tpc_gpc_r(gpc));
+}
+
+void ga10b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val)
+{
+	nvgpu_writel(g, fuse_ctrl_opt_tpc_gpc_r(gpc), val);
+}
+
+u32 ga10b_fuse_opt_priv_sec_en(struct gk20a *g)
+{
+	return nvgpu_readl(g, fuse_opt_priv_sec_en_r());
+}
+
+u32 ga10b_fuse_opt_sm_ttu_en(struct gk20a *g)
+{
+	return nvgpu_readl(g, fuse_opt_sm_ttu_en_r());
+}
+
+void ga10b_fuse_write_feature_override_ecc(struct gk20a *g, u32 val)
+{
+	nvgpu_writel(g, fuse_feature_override_ecc_r(), val);
+}
+
+void ga10b_fuse_write_feature_override_ecc_1(struct gk20a *g, u32 val)
+{
+	nvgpu_writel(g, fuse_feature_override_ecc_1_r(), val);
+}
+
+static void ga10b_fuse_read_feature_override_ecc_1(struct gk20a *g,
+			struct nvgpu_fuse_feature_override_ecc *ecc_feature)
+{
+	u32 ecc_1 = nvgpu_readl(g, fuse_feature_override_ecc_1_r());
+
+	ecc_feature->sm_l0_icache_enable =
+		fuse_feature_override_ecc_1_sm_l0_icache_v(ecc_1) ==
+			fuse_feature_override_ecc_1_sm_l0_icache_enabled_v();
+	ecc_feature->sm_l0_icache_override =
+		fuse_feature_override_ecc_1_sm_l0_icache_override_v(ecc_1) ==
+		    fuse_feature_override_ecc_1_sm_l0_icache_override_true_v();
+
+	ecc_feature->sm_l1_icache_enable =
+		fuse_feature_override_ecc_1_sm_l1_icache_v(ecc_1) ==
+			fuse_feature_override_ecc_1_sm_l1_icache_enabled_v();
+	ecc_feature->sm_l1_icache_override =
+		fuse_feature_override_ecc_1_sm_l1_icache_override_v(ecc_1) ==
+		    fuse_feature_override_ecc_1_sm_l1_icache_override_true_v();
+}
+
+void ga10b_fuse_read_feature_override_ecc(struct gk20a *g,
+			struct nvgpu_fuse_feature_override_ecc *ecc_feature)
+{
+	u32 ecc = nvgpu_readl(g, fuse_feature_override_ecc_r());
+
+	ecc_feature->sm_lrf_enable =
+		fuse_feature_override_ecc_sm_lrf_v(ecc) ==
+			fuse_feature_override_ecc_sm_lrf_enabled_v();
+	ecc_feature->sm_lrf_override =
+		fuse_feature_override_ecc_sm_lrf_override_v(ecc) ==
+			fuse_feature_override_ecc_sm_lrf_override_true_v();
+
+	ecc_feature->sm_l1_data_enable =
+		fuse_feature_override_ecc_sm_l1_data_v(ecc) ==
+			fuse_feature_override_ecc_sm_l1_data_enabled_v();
+	ecc_feature->sm_l1_data_override =
+		fuse_feature_override_ecc_sm_l1_data_override_v(ecc) ==
+			fuse_feature_override_ecc_sm_l1_data_override_true_v();
+
+	ecc_feature->sm_l1_tag_enable =
+		fuse_feature_override_ecc_sm_l1_tag_v(ecc) ==
+			fuse_feature_override_ecc_sm_l1_tag_enabled_v();
+	ecc_feature->sm_l1_tag_override =
+		fuse_feature_override_ecc_sm_l1_tag_override_v(ecc) ==
+			fuse_feature_override_ecc_sm_l1_tag_override_true_v();
+
+	ecc_feature->ltc_enable =
+		fuse_feature_override_ecc_ltc_v(ecc) ==
+			fuse_feature_override_ecc_ltc_enabled_v();
+	ecc_feature->ltc_override =
+		fuse_feature_override_ecc_ltc_override_v(ecc) ==
+			fuse_feature_override_ecc_ltc_override_true_v();
+
+	ecc_feature->dram_enable =
+		fuse_feature_override_ecc_dram_v(ecc) ==
+			fuse_feature_override_ecc_dram_enabled_v();
+	ecc_feature->dram_override =
+		fuse_feature_override_ecc_dram_override_v(ecc) ==
+			fuse_feature_override_ecc_dram_override_true_v();
+
+	ecc_feature->sm_cbu_enable =
+		fuse_feature_override_ecc_sm_cbu_v(ecc) ==
+			fuse_feature_override_ecc_sm_cbu_enabled_v();
+	ecc_feature->sm_cbu_override =
+		fuse_feature_override_ecc_sm_cbu_override_v(ecc) ==
+			fuse_feature_override_ecc_sm_cbu_override_true_v();
+
+	ga10b_fuse_read_feature_override_ecc_1(g, ecc_feature);
+}
+
+int ga10b_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi)
+{
+	u32 lo = 0U;
+	u32 hi = 0U;
+	u32 pdi_loaded = 0U;
+	u32 retries = GA10B_FUSE_READ_DEVICE_IDENTIFIER_RETRIES;
+
+	if (nvgpu_platform_is_silicon(g)) {
+		do {
+			pdi_loaded = fuse_p2prx_pdi_loaded_v(
+				nvgpu_readl(g, fuse_p2prx_pdi_r()));
+			retries = nvgpu_safe_sub_u32(retries, 1U);
+		} while ((pdi_loaded != fuse_p2prx_pdi_loaded_true_v()) &&
+			retries > 0U);
+
+		if (retries == 0U) {
+			nvgpu_err(g, "Device identifier load failed");
+			return -EAGAIN;
+		}
+	}
+
+	lo = nvgpu_readl(g, fuse_opt_pdi_0_r());
+	hi = nvgpu_readl(g, fuse_opt_pdi_1_r());
+
+	*pdi = ((u64)lo) | (((u64)hi) << 32);
+
+	return 0;
+}
+
+u32 ga10b_fuse_opt_sec_debug_en(struct gk20a *g)
+{
+	return nvgpu_readl(g, fuse_opt_sec_debug_en_r());
+}
+
+u32 ga10b_fuse_opt_secure_source_isolation_en(struct gk20a *g)
+{
+	return nvgpu_readl(g, fuse_opt_secure_source_isolation_en_r());
+}
+
+/*
+ * This function is same as gp10b_fuse_check_priv_security.
+ * The only addition is check for secure_source_isolation_en fuse.
+ */
+int ga10b_fuse_check_priv_security(struct gk20a *g)
+{
+	u32 gcplex_config;
+	bool is_wpr_enabled = false;
+	bool is_auto_fetch_disable = false;
+
+	if (g->ops.fuse.read_gcplex_config_fuse(g, &gcplex_config) != 0) {
+		nvgpu_err(g, "err reading gcplex config fuse, check fuse clk");
+		return -EINVAL;
+	}
+
+	if (g->ops.fuse.fuse_opt_priv_sec_en(g) != 0U) {
+		nvgpu_log_info(g, "priv_sec_en = 1");
+		if (g->ops.fuse.opt_sec_source_isolation_en != NULL) {
+			if (g->ops.fuse.opt_sec_source_isolation_en(g) == 0U) {
+				nvgpu_err(g, "priv_sec_en is set but "
+					"secure_source_isolation_en is 0");
+				return -EINVAL;
+			}
+			nvgpu_log_info(g, "secure_source_isolation_en = 1");
+		}
+		/*
+		 * all falcons have to boot in LS mode and this needs
+		 * wpr_enabled set to 1 and vpr_auto_fetch_disable
+		 * set to 0. In this case gmmu tries to pull wpr
+		 * and vpr settings from tegra mc
+		 */
+		nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
+		nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
+#ifdef CONFIG_NVGPU_SIM
+		if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
+			/*
+			 * Do not check other fuses as they are not yet modeled
+                         * on FMODEL.
+			 */
+			return 0;
+		}
+#endif
+		is_wpr_enabled = (gcplex_config &
+			GCPLEX_CONFIG_WPR_ENABLED_MASK) != 0U;
+		is_auto_fetch_disable = (gcplex_config &
+			GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK) != 0U;
+		if (is_wpr_enabled && !is_auto_fetch_disable) {
+			if (g->ops.fuse.fuse_opt_sec_debug_en(g) != 0U) {
+				nvgpu_log(g, gpu_dbg_info,
+						"gcplex_config = 0x%08x, "
+						"secure mode: ACR debug",
+						gcplex_config);
+			} else {
+				nvgpu_log(g, gpu_dbg_info,
+						"gcplex_config = 0x%08x, "
+						"secure mode: ACR non debug",
+						gcplex_config);
+			}
+
+		} else {
+			nvgpu_err(g, "gcplex_config = 0x%08x "
+				"invalid wpr_enabled/vpr_auto_fetch_disable "
+				"with priv_sec_en", gcplex_config);
+			/* do not try to boot GPU */
+			return -EINVAL;
+		}
+	} else {
+		nvgpu_log_info(g, "secure mode: priv_sec_en = 0");
+		nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
+		nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
+		nvgpu_log(g, gpu_dbg_info,
+				"gcplex_config = 0x%08x, non secure mode",
+				gcplex_config);
+	}
+
+	return 0;
+}
+
+static void check_and_update_fuse_settings(struct gk20a *g, u32 fuse,
+	u32 falcon_feature, unsigned long *fuse_settings)
+{
+	nvgpu_readl(g, fuse) ?
+		nvgpu_set_bit(falcon_feature, fuse_settings) :
+		nvgpu_clear_bit(falcon_feature, fuse_settings);
+}
+
+int ga10b_fetch_falcon_fuse_settings(struct gk20a *g, u32 falcon_id,
+		unsigned long *fuse_settings)
+{
+	int err = 0;
+
+	switch (falcon_id) {
+	case FALCON_ID_PMU:
+	case FALCON_ID_PMU_NEXT_CORE:
+		check_and_update_fuse_settings(g, fuse_pmu_fcd_r(),
+			FCD, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_pmu_enen_r(),
+			FENEN, fuse_settings);
+
+		check_and_update_fuse_settings(g,
+			fuse_pmu_nvriscv_bre_en_r(),
+			NVRISCV_BRE_EN, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_pmu_nvriscv_devd_r(),
+			NVRISCV_DEVD, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_pmu_nvriscv_pld_r(),
+			NVRISCV_PLD, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_pmu_dcs_r(),
+			DCS, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_pmu_nvriscv_sen_r(),
+			NVRISCV_SEN, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_pmu_nvriscv_sa_r(),
+			NVRISCV_SA, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_pmu_nvriscv_sh_r(),
+			NVRISCV_SH, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_pmu_nvriscv_si_r(),
+			NVRISCV_SI, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_secure_pmu_dbgd_r(),
+			SECURE_DBGD, fuse_settings);
+
+		/*
+		 * Bit[0] for AES; Bit[1] for PKC. When this fuse is not blown,
+		 * both AES and PKC are enabled
+		 */
+		nvgpu_readl(g, fuse_pkc_pmu_algo_dis_r()) & AES_ALGO ?
+			nvgpu_set_bit(AES_ALGO_DIS, fuse_settings) :
+			nvgpu_clear_bit(AES_ALGO_DIS, fuse_settings);
+
+		nvgpu_readl(g, fuse_pkc_pmu_algo_dis_r()) & PKC_ALGO ?
+			nvgpu_set_bit(PKC_ALGO_DIS, fuse_settings) :
+			nvgpu_clear_bit(PKC_ALGO_DIS, fuse_settings);
+
+		break;
+	case FALCON_ID_GSPLITE:
+		check_and_update_fuse_settings(g, fuse_gsp_fcd_r(),
+			FCD, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_gsp_enen_r(),
+			FENEN, fuse_settings);
+
+		check_and_update_fuse_settings(g,
+			fuse_gsp_nvriscv_bre_en_r(),
+			NVRISCV_BRE_EN, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_gsp_nvriscv_devd_r(),
+			NVRISCV_DEVD, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_gsp_nvriscv_pld_r(),
+			NVRISCV_PLD, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_gsp_dcs_r(),
+			DCS, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_gsp_nvriscv_sen_r(),
+			NVRISCV_SEN, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_gsp_nvriscv_sa_r(),
+			NVRISCV_SA, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_gsp_nvriscv_sh_r(),
+			NVRISCV_SH, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_gsp_nvriscv_si_r(),
+			NVRISCV_SI, fuse_settings);
+
+		check_and_update_fuse_settings(g, fuse_secure_gsp_dbgd_r(),
+			SECURE_DBGD, fuse_settings);
+
+		/*
+		 * Bit[0] for AES; Bit[1] for PKC. When this fuse is not blown,
+		 * both AES and PKC are enabled
+		 */
+		nvgpu_readl(g, fuse_pkc_gsp_algo_dis_r()) & AES_ALGO ?
+			nvgpu_set_bit(AES_ALGO_DIS, fuse_settings) :
+			nvgpu_clear_bit(AES_ALGO_DIS, fuse_settings);
+
+		nvgpu_readl(g, fuse_pkc_gsp_algo_dis_r()) & PKC_ALGO ?
+			nvgpu_set_bit(PKC_ALGO_DIS, fuse_settings) :
+			nvgpu_clear_bit(PKC_ALGO_DIS, fuse_settings);
+		break;
+	default:
+		err = -EINVAL;
+		nvgpu_err(g, "Invalid/Unsupported falcon ID %x", falcon_id);
+		break;
+	}
+
+	nvgpu_info(g, "falcon ID-%x fuse-settings 0x%lx",
+			falcon_id, *fuse_settings);
+
+	return err;
+}
diff --git a/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.h b/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.h
new file mode 100644
index 000000000..9c8e5d3b6
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.h
@@ -0,0 +1,55 @@
+/*
+ * GA10B FUSE
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FUSE_GA10B_H
+#define NVGPU_FUSE_GA10B_H
+
+#define GA10B_FUSE_READ_DEVICE_IDENTIFIER_RETRIES 100000U
+
+struct gk20a;
+struct nvgpu_fuse_feature_override_ecc;
+
+int ga10b_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val);
+bool ga10b_fuse_is_opt_ecc_enable(struct gk20a *g);
+bool ga10b_fuse_is_opt_feature_override_disable(struct gk20a *g);
+u32 ga10b_fuse_status_opt_gpc(struct gk20a *g);
+u32 ga10b_fuse_status_opt_fbio(struct gk20a *g);
+u32 ga10b_fuse_status_opt_fbp(struct gk20a *g);
+u32 ga10b_fuse_status_opt_rop_gpc(struct gk20a *g, u32 fbp);
+u32 ga10b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc);
+void ga10b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val);
+u32 ga10b_fuse_opt_priv_sec_en(struct gk20a *g);
+u32 ga10b_fuse_opt_sm_ttu_en(struct gk20a *g);
+void ga10b_fuse_write_feature_override_ecc(struct gk20a *g, u32 val);
+void ga10b_fuse_write_feature_override_ecc_1(struct gk20a *g, u32 val);
+void ga10b_fuse_read_feature_override_ecc(struct gk20a *g,
+		struct nvgpu_fuse_feature_override_ecc *ecc_feature);
+int ga10b_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi);
+u32 ga10b_fuse_opt_sec_debug_en(struct gk20a *g);
+u32 ga10b_fuse_opt_secure_source_isolation_en(struct gk20a *g);
+int ga10b_fuse_check_priv_security(struct gk20a *g);
+int ga10b_fetch_falcon_fuse_settings(struct gk20a *g, u32 falcon_id,
+		unsigned long *fuse_settings);
+
+#endif /* NVGPU_FUSE_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.c
new file mode 100644
index 000000000..264cfb892
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/nvgpu_mem.h>
+
+#include <nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h>
+
+#ifdef CONFIG_DEBUG_FS
+void ga100_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g,
+	struct nvgpu_mem *ctx_mem)
+{
+	nvgpu_err(g, "ctxsw_prog_main_image_magic_value_1_o: %x (expect %x)",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_magic_value_1_o()),
+		ctxsw_prog_main_image_magic_value_1_v_value_v());
+
+	nvgpu_err(g, "ctxsw_prog_main_image_magic_value_2_o: %x (expect %x)",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_magic_value_2_o()),
+		ctxsw_prog_main_image_magic_value_2_v_value_v());
+
+	nvgpu_err(g, "ctxsw_prog_main_image_magic_value_3_o: %x (expect %x)",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_magic_value_3_o()),
+		ctxsw_prog_main_image_magic_value_3_v_value_v());
+
+	nvgpu_err(g, "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi: %x",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o()));
+
+	nvgpu_err(g, "ctxsw_prog_main_image_context_timestamp_buffer_ptr: %x",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_context_timestamp_buffer_ptr_o()));
+
+	nvgpu_err(g, "ctxsw_prog_main_image_context_timestamp_buffer_control: %x",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_context_timestamp_buffer_control_o()));
+
+	nvgpu_err(g, "NUM_SAVE_OPERATIONS: %d",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_num_save_ops_o()));
+	nvgpu_err(g, "WFI_SAVE_OPERATIONS: %d",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_num_wfi_save_ops_o()));
+	nvgpu_err(g, "CTA_SAVE_OPERATIONS: %d",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_num_cta_save_ops_o()));
+	nvgpu_err(g, "GFXP_SAVE_OPERATIONS: %d",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_num_gfxp_save_ops_o()));
+	nvgpu_err(g, "CILP_SAVE_OPERATIONS: %d",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_num_cilp_save_ops_o()));
+	nvgpu_err(g,
+		"image gfx preemption option (GFXP is 1) %x",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_graphics_preemption_options_o()));
+	nvgpu_err(g,
+		"image compute preemption option (CTA is 1) %x",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_compute_preemption_options_o()));
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.h
new file mode 100644
index 000000000..c8ef806ef
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_CTXSW_PROG_GA100_H
+#define NVGPU_CTXSW_PROG_GA100_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_mem;
+
+u32 ga100_ctxsw_prog_hw_get_fecs_header_size(void);
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+u32 ga100_ctxsw_prog_hw_get_gpccs_header_size(void);
+bool ga100_ctxsw_prog_check_main_image_header_magic(u32 *context);
+bool ga100_ctxsw_prog_check_local_header_magic(u32 *context);
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#ifdef CONFIG_DEBUG_FS
+void ga100_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g,
+	struct nvgpu_mem *ctx_mem);
+#endif
+
+#endif /* NVGPU_CTXSW_PROG_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.c
new file mode 100644
index 000000000..804277ec3
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/utils.h>
+
+#include "ctxsw_prog_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h>
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+u32 ga100_ctxsw_prog_hw_get_gpccs_header_size(void)
+{
+	return ctxsw_prog_gpccs_header_stride_v();
+}
+
+bool ga100_ctxsw_prog_check_main_image_header_magic(u32 *context)
+{
+	u32 magic_1, magic_2, magic_3;
+
+	magic_1 = *(context + (ctxsw_prog_main_image_magic_value_1_o() >> 2));
+	magic_2 = *(context + (ctxsw_prog_main_image_magic_value_2_o() >> 2));
+	magic_3 = *(context + (ctxsw_prog_main_image_magic_value_3_o() >> 2));
+
+	if (magic_1 != ctxsw_prog_main_image_magic_value_1_v_value_v()) {
+		return false;
+	}
+	if (magic_2 != ctxsw_prog_main_image_magic_value_2_v_value_v()) {
+		return false;
+	}
+	if (magic_3 != ctxsw_prog_main_image_magic_value_3_v_value_v()) {
+		return false;
+	}
+	return true;
+}
+
+bool ga100_ctxsw_prog_check_local_header_magic(u32 *context)
+{
+	u32 magic_1, magic_2, magic_3;
+
+	magic_1 = *(context + (ctxsw_prog_local_magic_value_1_o() >> 2));
+	magic_2 = *(context + (ctxsw_prog_local_magic_value_2_o() >> 2));
+	magic_3 = *(context + (ctxsw_prog_local_magic_value_3_o() >> 2));
+
+	if (magic_1 != ctxsw_prog_local_magic_value_1_v_value_v()) {
+		return false;
+	}
+	if (magic_2 != ctxsw_prog_local_magic_value_2_v_value_v()) {
+		return false;
+	}
+	if (magic_3 != ctxsw_prog_local_magic_value_3_v_value_v()) {
+		return false;
+	}
+	return true;
+}
+
+#endif /* CONFIG_NVGPU_DEBUGGER */
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c
new file mode 100644
index 000000000..78ad4e7b6
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/utils.h>
+
+#include "ctxsw_prog_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h>
+
+u32 ga100_ctxsw_prog_hw_get_fecs_header_size(void)
+{
+	return ctxsw_prog_fecs_header_v();
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b.c
new file mode 100644
index 000000000..c65194eb6
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/nvgpu_mem.h>
+
+#include <nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h>
+
+#ifdef CONFIG_DEBUG_FS
+void ga10b_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g,
+	struct nvgpu_mem *ctx_mem)
+{
+	nvgpu_err(g, "ctxsw_prog_main_image_magic_value_1_o: %x (expect %x)",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_magic_value_1_o()),
+		ctxsw_prog_main_image_magic_value_1_v_value_v());
+
+	nvgpu_err(g, "ctxsw_prog_main_image_magic_value_2_o: %x (expect %x)",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_magic_value_2_o()),
+		ctxsw_prog_main_image_magic_value_2_v_value_v());
+
+	nvgpu_err(g, "ctxsw_prog_main_image_magic_value_3_o: %x (expect %x)",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_magic_value_3_o()),
+		ctxsw_prog_main_image_magic_value_3_v_value_v());
+
+	nvgpu_err(g, "ctxsw_prog_main_image_magic_value_4_o: %x (expect %x)",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_magic_value_4_o()),
+		ctxsw_prog_main_image_magic_value_4_v_value_v());
+
+	nvgpu_err(g, "ctxsw_prog_main_image_magic_value_5_o: %x (expect %x)",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_magic_value_5_o()),
+		ctxsw_prog_main_image_magic_value_5_v_value_v());
+
+	nvgpu_err(g, "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi: %x",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o()));
+
+	nvgpu_err(g, "ctxsw_prog_main_image_context_timestamp_buffer_ptr: %x",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_context_timestamp_buffer_ptr_o()));
+
+	nvgpu_err(g, "ctxsw_prog_main_image_context_timestamp_buffer_control: %x",
+		nvgpu_mem_rd(g, ctx_mem,
+				ctxsw_prog_main_image_context_timestamp_buffer_control_o()));
+
+	nvgpu_err(g, "NUM_SAVE_OPERATIONS: %d",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_num_save_ops_o()));
+	nvgpu_err(g, "WFI_SAVE_OPERATIONS: %d",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_num_wfi_save_ops_o()));
+	nvgpu_err(g, "CTA_SAVE_OPERATIONS: %d",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_num_cta_save_ops_o()));
+	nvgpu_err(g, "GFXP_SAVE_OPERATIONS: %d",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_num_gfxp_save_ops_o()));
+	nvgpu_err(g, "CILP_SAVE_OPERATIONS: %d",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_num_cilp_save_ops_o()));
+	nvgpu_err(g,
+		"image gfx preemption option (GFXP is 1) %x",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_graphics_preemption_options_o()));
+	nvgpu_err(g,
+		"image compute preemption option (CTA is 1) %x",
+		nvgpu_mem_rd(g, ctx_mem,
+			ctxsw_prog_main_image_compute_preemption_options_o()));
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h
new file mode 100644
index 000000000..55e664494
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_CTXSW_PROG_GA10B_H
+#define NVGPU_CTXSW_PROG_GA10B_H
+
+#include <nvgpu/types.h>
+
+#define BYTE_TO_DW_SHIFT	(2U)
+
+struct gk20a;
+struct nvgpu_mem;
+
+u32 ga10b_ctxsw_prog_hw_get_fecs_header_size(void);
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+u32 ga10b_ctxsw_prog_hw_get_gpccs_header_size(void);
+bool ga10b_ctxsw_prog_check_main_image_header_magic(u32 *context);
+bool ga10b_ctxsw_prog_check_local_header_magic(u32 *context);
+u32 ga10b_ctxsw_prog_hw_get_main_header_size(void);
+u32 ga10b_ctxsw_prog_hw_get_gpccs_header_stride(void);
+u32 ga10b_ctxsw_prog_get_compute_sysreglist_offset(u32 *fecs_hdr);
+u32 ga10b_ctxsw_prog_get_gfx_sysreglist_offset(u32 *fecs_hdr);
+u32 ga10b_ctxsw_prog_get_ltsreglist_offset(u32 *fecs_hdr);
+u32 ga10b_ctxsw_prog_get_compute_gpcreglist_offset(u32 *gpccs_hdr);
+u32 ga10b_ctxsw_prog_get_gfx_gpcreglist_offset(u32 *gpccs_hdr) ;
+u32 ga10b_ctxsw_prog_get_compute_ppcreglist_offset(u32 *gpccs_hdr);
+u32 ga10b_ctxsw_prog_get_gfx_ppcreglist_offset(u32 *gpccs_hdr);
+u32 ga10b_ctxsw_prog_get_compute_tpcreglist_offset(u32 *gpccs_hdr, u32 tpc_num);
+u32 ga10b_ctxsw_prog_get_gfx_tpcreglist_offset(u32 *gpccs_hdr, u32 tpc_num);
+u32 ga10b_ctxsw_prog_get_compute_etpcreglist_offset(u32 *gpccs_hdr);
+u32 ga10b_ctxsw_prog_get_gfx_etpcreglist_offset(u32 *gpccs_hdr);
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#ifdef CONFIG_DEBUG_FS
+void ga10b_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g,
+	struct nvgpu_mem *ctx_mem);
+#endif
+
+#endif /* NVGPU_CTXSW_PROG_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.c
new file mode 100644
index 000000000..5d069fd18
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/utils.h>
+
+#include "ctxsw_prog_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h>
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+u32 ga10b_ctxsw_prog_hw_get_gpccs_header_size(void)
+{
+	return ctxsw_prog_gpccs_header_stride_v();
+}
+
+bool ga10b_ctxsw_prog_check_main_image_header_magic(u32 *context)
+{
+	u32 magic_1, magic_2, magic_3, magic_4, magic_5;
+
+	magic_1 = *(context + (ctxsw_prog_main_image_magic_value_1_o() >> 2));
+	magic_2 = *(context + (ctxsw_prog_main_image_magic_value_2_o() >> 2));
+	magic_3 = *(context + (ctxsw_prog_main_image_magic_value_3_o() >> 2));
+	magic_4 = *(context + (ctxsw_prog_main_image_magic_value_4_o() >> 2));
+	magic_5 = *(context + (ctxsw_prog_main_image_magic_value_5_o() >> 2));
+
+	if (magic_1 != ctxsw_prog_main_image_magic_value_1_v_value_v()) {
+		return false;
+	}
+	if (magic_2 != ctxsw_prog_main_image_magic_value_2_v_value_v()) {
+		return false;
+	}
+	if (magic_3 != ctxsw_prog_main_image_magic_value_3_v_value_v()) {
+		return false;
+	}
+	if (magic_4 != ctxsw_prog_main_image_magic_value_4_v_value_v()) {
+		return false;
+	}
+	if (magic_5 != ctxsw_prog_main_image_magic_value_5_v_value_v()) {
+		return false;
+	}
+	return true;
+}
+
+bool ga10b_ctxsw_prog_check_local_header_magic(u32 *context)
+{
+	u32 magic_1, magic_2, magic_3, magic_4, magic_5;
+
+	magic_1 = *(context + (ctxsw_prog_local_magic_value_1_o() >> 2));
+	magic_2 = *(context + (ctxsw_prog_local_magic_value_2_o() >> 2));
+	magic_3 = *(context + (ctxsw_prog_local_magic_value_3_o() >> 2));
+	magic_4 = *(context + (ctxsw_prog_local_magic_value_4_o() >> 2));
+	magic_5 = *(context + (ctxsw_prog_local_magic_value_5_o() >> 2));
+
+	if (magic_1 != ctxsw_prog_local_magic_value_1_v_value_v()) {
+		return false;
+	}
+	if (magic_2 != ctxsw_prog_local_magic_value_2_v_value_v()) {
+		return false;
+	}
+	if (magic_3 != ctxsw_prog_local_magic_value_3_v_value_v()) {
+		return false;
+	}
+	if (magic_4 != ctxsw_prog_local_magic_value_4_v_value_v()) {
+		return false;
+	}
+	if (magic_5 != ctxsw_prog_local_magic_value_5_v_value_v()) {
+		return false;
+	}
+	return true;
+}
+
+#endif /* CONFIG_NVGPU_DEBUGGER */
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c
new file mode 100644
index 000000000..b16e50e62
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/utils.h>
+
+#include "ctxsw_prog_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h>
+
+#define CTXSWBUF_SEGMENT_BLKSIZE	(256U)
+
+u32 ga10b_ctxsw_prog_hw_get_fecs_header_size(void)
+{
+	return ctxsw_prog_fecs_header_size_in_bytes_v();
+}
+
+u32 ga10b_ctxsw_prog_hw_get_main_header_size(void)
+{
+	return ctxsw_prog_ctxsw_header_size_in_bytes_v();
+}
+
+u32 ga10b_ctxsw_prog_hw_get_gpccs_header_stride(void)
+{
+	return ctxsw_prog_gpccs_header_stride_v();
+}
+
+u32 ga10b_ctxsw_prog_get_compute_sysreglist_offset(u32 *fecs_hdr)
+{
+	return ctxsw_prog_local_sys_reglist_offset_compute_v(
+		fecs_hdr[ctxsw_prog_local_sys_reglist_offset_o() >>
+		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
+}
+
+u32 ga10b_ctxsw_prog_get_gfx_sysreglist_offset(u32 *fecs_hdr)
+{
+	return ctxsw_prog_local_sys_reglist_offset_graphics_v(
+		fecs_hdr[ctxsw_prog_local_sys_reglist_offset_o() >>
+		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
+}
+
+u32 ga10b_ctxsw_prog_get_ltsreglist_offset(u32 *fecs_hdr)
+{
+	return ctxsw_prog_local_lts_reglist_offset_v_v(
+		fecs_hdr[ctxsw_prog_local_lts_reglist_offset_o() >>
+		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
+}
+
+u32 ga10b_ctxsw_prog_get_compute_gpcreglist_offset(u32 *gpccs_hdr)
+{
+	return ctxsw_prog_local_gpc_reglist_offset_compute_v(
+		gpccs_hdr[ctxsw_prog_local_gpc_reglist_offset_o() >>
+		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
+}
+
+u32 ga10b_ctxsw_prog_get_gfx_gpcreglist_offset(u32 *gpccs_hdr)
+{
+	return ctxsw_prog_local_gpc_reglist_offset_graphics_v(
+		gpccs_hdr[ctxsw_prog_local_gpc_reglist_offset_o() >>
+		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
+}
+
+u32 ga10b_ctxsw_prog_get_compute_ppcreglist_offset(u32 *gpccs_hdr)
+{
+	return ctxsw_prog_local_ppc_reglist_offset_compute_v(
+		gpccs_hdr[ctxsw_prog_local_ppc_reglist_offset_o() >>
+		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
+}
+
+u32 ga10b_ctxsw_prog_get_gfx_ppcreglist_offset(u32 *gpccs_hdr)
+{
+	return ctxsw_prog_local_ppc_reglist_offset_graphics_v(
+		gpccs_hdr[ctxsw_prog_local_ppc_reglist_offset_o() >>
+		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
+}
+
+u32 ga10b_ctxsw_prog_get_compute_tpcreglist_offset(u32 *gpccs_hdr, u32 tpc_num)
+{
+	return ctxsw_prog_local_tpc_reglist_offset_compute_v(
+		gpccs_hdr[ctxsw_prog_local_tpc_reglist_offset_r(tpc_num) >>
+		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
+}
+
+u32 ga10b_ctxsw_prog_get_gfx_tpcreglist_offset(u32 *gpccs_hdr, u32 tpc_num)
+{
+	return ctxsw_prog_local_tpc_reglist_offset_graphics_v(
+		gpccs_hdr[ctxsw_prog_local_tpc_reglist_offset_r(tpc_num) >>
+		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
+}
+
+u32 ga10b_ctxsw_prog_get_compute_etpcreglist_offset(u32 *gpccs_hdr)
+{
+	return ctxsw_prog_local_ext_tpc_reglist_offset_compute_v(
+		gpccs_hdr[ctxsw_prog_local_ext_tpc_reglist_offset_o() >>
+		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
+}
+
+u32 ga10b_ctxsw_prog_get_gfx_etpcreglist_offset(u32 *gpccs_hdr)
+{
+	return ctxsw_prog_local_ext_tpc_reglist_offset_graphics_v(
+		gpccs_hdr[ctxsw_prog_local_ext_tpc_reglist_offset_o() >>
+		BYTE_TO_DW_SHIFT]) * CTXSWBUF_SEGMENT_BLKSIZE;
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.c b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.c
new file mode 100644
index 000000000..f4f52fe1e
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+
+#include "hal/gr/ecc/ecc_gv11b.h"
+#include "ecc_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_gr_ga10b.h>
+
+static inline u32 pri_gpc0_mmu0_l1tlb_ecc_control_r(void)
+{
+	return gr_gpc0_mmu0_l1tlb_ecc_control_r();
+}
+
+static inline u32 pri_gpc0_mmu0_l1tlb_ecc_control_inject_uncorrected_err_f(u32 v)
+{
+	return gr_gpc0_mmu0_l1tlb_ecc_control_inject_uncorrected_err_f(v);
+}
+
+struct nvgpu_hw_err_inject_info mmu_ecc_err_desc[] = {
+	/*
+	 * NV_SCAL_LITTER_NUM_GPCMMU_PER_GPC only shows 1 GPCMMU per GPC.
+	 * Add support to GPC_MMU0_L1TLB, GPC_MMU L1TLB not handled here.
+	 */
+
+	NVGPU_ECC_ERR("l1tlb_sa_data_ecc_uncorrected",
+		gv11b_gr_intr_inject_mmu_ecc_error,
+		pri_gpc0_mmu0_l1tlb_ecc_control_r,
+		pri_gpc0_mmu0_l1tlb_ecc_control_inject_uncorrected_err_f),
+};
+
+struct nvgpu_hw_err_inject_info_desc mmu_err_desc;
+
+struct nvgpu_hw_err_inject_info_desc *
+		ga10b_gr_ecc_get_mmu_err_desc(struct gk20a *g)
+{
+	mmu_err_desc.info_ptr = mmu_ecc_err_desc;
+	mmu_err_desc.info_size = nvgpu_safe_cast_u64_to_u32(
+				sizeof(mmu_ecc_err_desc) /
+				sizeof(struct nvgpu_hw_err_inject_info));
+
+	return &mmu_err_desc;
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.h b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.h
new file mode 100644
index 000000000..a462b7fd3
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_ECC_GA10B_H
+#define NVGPU_ECC_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+#ifdef CONFIG_NVGPU_INJECT_HWERR
+struct nvgpu_hw_err_inject_info_desc;
+
+struct nvgpu_hw_err_inject_info_desc *
+		ga10b_gr_ecc_get_mmu_err_desc(struct gk20a *g);
+#endif /* CONFIG_NVGPU_INJECT_HWERR */
+
+void ga10b_ecc_detect_enabled_units(struct gk20a *g);
+int ga10b_gr_gpc_tpc_ecc_init(struct gk20a *g);
+
+#endif /* NVGPU_ECC_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b_fusa.c
new file mode 100644
index 000000000..2d1b91c38
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_ga10b_fusa.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/fuse.h>
+#include <nvgpu/gr/gr_ecc.h>
+#include <hal/gr/ecc/ecc_gv11b.h>
+
+#include "ecc_ga10b.h"
+
+static void ga10b_ecc_enable_sm_lrf(struct gk20a *g,
+	struct nvgpu_fuse_feature_override_ecc *ecc_feature, bool opt_ecc_en)
+{
+	if (ecc_feature->sm_lrf_override) {
+		if (ecc_feature->sm_lrf_enable) {
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_LRF, true);
+		}
+	} else {
+		if (opt_ecc_en) {
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_LRF, true);
+		}
+	}
+}
+
+static void ga10b_ecc_enable_sm_l1_data(struct gk20a *g,
+	struct nvgpu_fuse_feature_override_ecc *ecc_feature, bool opt_ecc_en)
+{
+	if (ecc_feature->sm_l1_data_override) {
+		if (ecc_feature->sm_l1_data_enable) {
+		  nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_L1_DATA, true);
+		}
+	} else {
+		if (opt_ecc_en) {
+		  nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_L1_DATA, true);
+		}
+	}
+}
+
+static void ga10b_ecc_enable_sm_l1_tag(struct gk20a *g,
+	struct nvgpu_fuse_feature_override_ecc *ecc_feature, bool opt_ecc_en)
+{
+	if (ecc_feature->sm_l1_tag_override) {
+		if (ecc_feature->sm_l1_tag_enable) {
+		       nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_L1_TAG, true);
+		}
+	} else {
+		if (opt_ecc_en) {
+		       nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_L1_TAG, true);
+		}
+	}
+}
+
+static void ga10b_ecc_enable_sm_icache(struct gk20a *g,
+	struct nvgpu_fuse_feature_override_ecc *ecc_feature, bool opt_ecc_en)
+{
+	if (ecc_feature->sm_l0_icache_override &&
+	    ecc_feature->sm_l1_icache_override) {
+		if (ecc_feature->sm_l0_icache_enable &&
+		    ecc_feature->sm_l1_icache_enable) {
+		       nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_ICACHE, true);
+		}
+	} else {
+		if (opt_ecc_en) {
+		       nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_ICACHE, true);
+		}
+	}
+}
+
+static void ga10b_ecc_enable_ltc(struct gk20a *g,
+	struct nvgpu_fuse_feature_override_ecc *ecc_feature, bool opt_ecc_en)
+{
+	if (ecc_feature->ltc_override) {
+		if (ecc_feature->ltc_enable) {
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
+		}
+	} else {
+		if (opt_ecc_en) {
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
+		}
+	}
+}
+
+static void ga10b_ecc_enable_sm_cbu(struct gk20a *g,
+	struct nvgpu_fuse_feature_override_ecc *ecc_feature, bool opt_ecc_en)
+{
+	if (ecc_feature->sm_cbu_override) {
+		if (ecc_feature->sm_cbu_enable) {
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true);
+		}
+	} else {
+		if (opt_ecc_en) {
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true);
+		}
+	}
+}
+
+void ga10b_ecc_detect_enabled_units(struct gk20a *g)
+{
+	struct nvgpu_fuse_feature_override_ecc ecc_feature;
+	bool opt_ecc_en = g->ops.fuse.is_opt_ecc_enable(g);
+	bool opt_feature_fuses_override_disable =
+		g->ops.fuse.is_opt_feature_override_disable(g);
+
+	(void) memset(&ecc_feature, 0,
+			sizeof(struct nvgpu_fuse_feature_override_ecc));
+	g->ops.fuse.read_feature_override_ecc(g, &ecc_feature);
+
+	if (opt_feature_fuses_override_disable) {
+		if (opt_ecc_en) {
+			nvgpu_set_enabled(g,
+					NVGPU_ECC_ENABLED_SM_LRF, true);
+			nvgpu_set_enabled(g,
+					NVGPU_ECC_ENABLED_SM_L1_DATA, true);
+			nvgpu_set_enabled(g,
+					NVGPU_ECC_ENABLED_SM_L1_TAG, true);
+			nvgpu_set_enabled(g,
+					NVGPU_ECC_ENABLED_SM_ICACHE, true);
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true);
+		}
+	} else {
+		/* SM LRF */
+		ga10b_ecc_enable_sm_lrf(g, &ecc_feature, opt_ecc_en);
+		/* SM L1 DATA*/
+		ga10b_ecc_enable_sm_l1_data(g, &ecc_feature, opt_ecc_en);
+		/* SM L1 TAG*/
+		ga10b_ecc_enable_sm_l1_tag(g, &ecc_feature, opt_ecc_en);
+		/* SM ICACHE*/
+		ga10b_ecc_enable_sm_icache(g, &ecc_feature, opt_ecc_en);
+		/* LTC */
+		ga10b_ecc_enable_ltc(g, &ecc_feature, opt_ecc_en);
+		/* SM CBU */
+		ga10b_ecc_enable_sm_cbu(g, &ecc_feature, opt_ecc_en);
+		/*
+		 * Further feature override checking tracked by
+		 * https://jirasw.nvidia.com/browse/NVGPU-5284
+		 */
+	}
+}
+
+int ga10b_gr_gpc_tpc_ecc_init(struct gk20a *g)
+{
+	gv11b_gr_gpc_tpc_ecc_init(g);
+	NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_rams_ecc_corrected_err_count);
+	NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_rams_ecc_uncorrected_err_count);
+
+	return 0;
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga100.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga100.c
new file mode 100644
index 000000000..c6f6189f6
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga100.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gr/gr_falcon.h>
+
+#include "hal/gr/falcon/gr_falcon_gm20b.h"
+#include "hal/gr/falcon/gr_falcon_tu104.h"
+#include "hal/gr/falcon/gr_falcon_ga100.h"
+#include "common/gr/gr_falcon_priv.h"
+
+#include <nvgpu/hw/ga100/hw_gr_ga100.h>
+
+int ga100_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
+		u32 data, u32 *ret_val)
+{
+	struct nvgpu_fecs_method_op op = {
+		.mailbox = { .id = 0U, .data = 0U, .ret = NULL,
+			     .clr = ~U32(0U), .ok = 0U, .fail = 0U},
+		.method.data = 0U,
+		.cond.ok = GR_IS_UCODE_OP_NOT_EQUAL,
+		.cond.fail = GR_IS_UCODE_OP_SKIP,
+	};
+	u32 flags = 0U;
+
+	int ret;
+
+	nvgpu_log_info(g, "fecs method %d data 0x%x ret_val %p",
+				fecs_method, data, ret_val);
+
+	switch (fecs_method) {
+	case NVGPU_GR_FALCON_METHOD_SET_WATCHDOG_TIMEOUT:
+		op.method.addr =
+			gr_fecs_method_push_adr_set_watchdog_timeout_f();
+		op.method.data = data;
+		op.cond.ok = GR_IS_UCODE_OP_SKIP;
+		op.mailbox.ok = gr_fecs_ctxsw_mailbox_value_pass_v();
+		flags |= NVGPU_GR_FALCON_SUBMIT_METHOD_F_LOCKED;
+
+		ret = gm20b_gr_falcon_submit_fecs_method_op(g, op, flags);
+		break;
+
+	default:
+		ret = tu104_gr_falcon_ctrl_ctxsw(g, fecs_method,
+				data, ret_val);
+		break;
+	}
+	return ret;
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga100.h b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga100.h
new file mode 100644
index 000000000..909bff634
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga100.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_FALCON_GA100_H
+#define NVGPU_GR_FALCON_GA100_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+int ga100_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
+		u32 data, u32 *ret_val);
+
+#endif /* NVGPU_GR_FALCON_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b.c
new file mode 100644
index 000000000..daced48da
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+
+#include "gr_falcon_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_gr_ga10b.h>
+
+#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
+void ga10b_gr_falcon_gpccs_dmemc_write(struct gk20a *g, u32 port, u32 offs,
+	u32 blk, u32 ainc)
+{
+	nvgpu_writel(g, gr_gpccs_dmemc_r(port),
+			gr_gpccs_dmemc_offs_f(offs) |
+			gr_gpccs_dmemc_blk_f(blk) |
+			gr_gpccs_dmemc_aincw_f(ainc));
+}
+
+void ga10b_gr_falcon_gpccs_imemc_write(struct gk20a *g, u32 port, u32 offs,
+	u32 blk, u32 ainc)
+{
+	nvgpu_writel(g, gr_gpccs_imemc_r(port),
+			gr_gpccs_imemc_offs_f(offs) |
+			gr_gpccs_imemc_blk_f(blk) |
+			gr_gpccs_imemc_aincw_f(ainc));
+}
+
+void ga10b_gr_falcon_fecs_imemc_write(struct gk20a *g, u32 port, u32 offs,
+	u32 blk, u32 ainc)
+{
+	nvgpu_writel(g, gr_fecs_imemc_r(port),
+			gr_fecs_imemc_offs_f(offs) |
+			gr_fecs_imemc_blk_f(blk) |
+			gr_fecs_imemc_aincw_f(ainc));
+}
+
+#endif
diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b.h b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b.h
new file mode 100644
index 000000000..dff7b795c
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_FALCON_GA10B_H
+#define NVGPU_GR_FALCON_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+u32 ga10b_gr_falcon_get_fecs_ctxsw_mailbox_size(void);
+void ga10b_gr_falcon_fecs_ctxsw_clear_mailbox(struct gk20a *g,
+						u32 reg_index, u32 clear_val);
+void ga10b_gr_falcon_dump_stats(struct gk20a *g);
+#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
+void ga10b_gr_falcon_gpccs_dmemc_write(struct gk20a *g, u32 port, u32 offs,
+	u32 blk, u32 ainc);
+void ga10b_gr_falcon_fecs_dmemc_write(struct gk20a *g, u32 reg_offset, u32 port,
+	u32 offs, u32 blk, u32 ainc);
+void ga10b_gr_falcon_gpccs_imemc_write(struct gk20a *g, u32 port, u32 offs,
+	u32 blk, u32 ainc);
+void ga10b_gr_falcon_load_fecs_imem(struct gk20a *g,
+			const u32 *ucode_u32_data, u32 ucode_u32_size);
+void ga10b_gr_falcon_fecs_imemc_write(struct gk20a *g, u32 port, u32 offs,
+	u32 blk, u32 ainc);
+#endif
+#endif /* NVGPU_GR_FALCON_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b_fusa.c
new file mode 100644
index 000000000..2dcba068a
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b_fusa.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/static_analysis.h>
+#include <nvgpu/gr/gr_utils.h>
+#include <nvgpu/gr/config.h>
+
+#include "gr_falcon_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_gr_ga10b.h>
+
+u32 ga10b_gr_falcon_get_fecs_ctxsw_mailbox_size(void)
+{
+	return gr_fecs_ctxsw_mailbox__size_1_v();
+}
+
+void ga10b_gr_falcon_fecs_ctxsw_clear_mailbox(struct gk20a *g,
+					u32 reg_index, u32 clear_val)
+{
+	u32 reg_val = 0U;
+
+	/* Clear by writing 0 to corresponding bit(s) in mailbox register */
+	reg_val = nvgpu_readl(g, gr_fecs_ctxsw_mailbox_r(reg_index));
+	reg_val &= ~(clear_val);
+	nvgpu_writel(g, gr_fecs_ctxsw_mailbox_r(reg_index), reg_val);
+}
+
+static void ga10b_gr_falcon_fecs_dump_stats(struct gk20a *g)
+{
+	unsigned int i;
+
+#ifdef CONFIG_NVGPU_FALCON_DEBUG
+	nvgpu_falcon_dump_stats(&g->fecs_flcn);
+#endif
+
+	for (i = 0U; i < g->ops.gr.falcon.fecs_ctxsw_mailbox_size(); i++) {
+		nvgpu_err(g, "gr_fecs_ctxsw_mailbox_r(%d): 0x%x",
+			i, nvgpu_readl(g, gr_fecs_ctxsw_mailbox_r(i)));
+	}
+
+	for (i = 0U; i < gr_fecs_ctxsw_func_tracing_mailbox__size_1_v(); i++) {
+		nvgpu_err(g, "gr_fecs_ctxsw_func_tracing_mailbox_r(%d): 0x%x",
+			i, nvgpu_readl(g,
+				gr_fecs_ctxsw_func_tracing_mailbox_r(i)));
+	}
+}
+
+static void ga10b_gr_falcon_gpccs_dump_stats(struct gk20a *g)
+{
+	unsigned int i;
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
+	u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr_config);
+	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+	u32 gpc = 0U, offset = 0U;
+
+	for (gpc = 0U; gpc < gpc_count; gpc++) {
+		offset = nvgpu_safe_mult_u32(gpc_stride, gpc);
+		for (i = 0U; i < gr_gpccs_ctxsw_mailbox__size_1_v(); i++) {
+			nvgpu_err(g,
+				"gr_gpc%d_gpccs_ctxsw_mailbox_r(%d): 0x%x",
+				gpc, i,
+				nvgpu_readl(g, nvgpu_safe_add_u32(
+					gr_gpc0_gpccs_ctxsw_mailbox_r(i),
+					offset)));
+		}
+	}
+
+	for (gpc = 0U; gpc < gpc_count; gpc++) {
+		offset = nvgpu_safe_mult_u32(gpc_stride, gpc);
+		for (i = 0U;
+			i < gr_gpc0_gpccs_ctxsw_func_tracing_mailbox__size_1_v();
+			i++) {
+			nvgpu_err(g,
+			"gr_gpc%d_gpccs_ctxsw_func_tracing_mailbox_r(%d): 0x%x",
+				gpc, i,
+				nvgpu_readl(g, nvgpu_safe_add_u32(
+					gr_gpc0_gpccs_ctxsw_func_tracing_mailbox_r(i),
+					offset)));
+		}
+	}
+}
+
+void ga10b_gr_falcon_dump_stats(struct gk20a *g)
+{
+	ga10b_gr_falcon_fecs_dump_stats(g);
+	ga10b_gr_falcon_gpccs_dump_stats(g);
+}
+
+#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
+void ga10b_gr_falcon_fecs_dmemc_write(struct gk20a *g, u32 reg_offset, u32 port,
+	u32 offs, u32 blk, u32 ainc)
+{
+	nvgpu_writel(g, nvgpu_safe_add_u32(reg_offset, gr_fecs_dmemc_r(port)),
+			gr_fecs_dmemc_offs_f(offs) |
+			gr_fecs_dmemc_blk_f(blk) |
+			gr_fecs_dmemc_aincw_f(ainc));
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c
new file mode 100644
index 000000000..89528fc2f
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c
@@ -0,0 +1,665 @@
+/*
+ * GA100 GPU GR
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/dma.h>
+#include <nvgpu/log.h>
+#include <nvgpu/debug.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/fuse.h>
+#include <nvgpu/debugger.h>
+#include <nvgpu/error_notifier.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/bitops.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/regops.h>
+#include <nvgpu/gr/ctx.h>
+#include <nvgpu/gr/config.h>
+#include <nvgpu/gr/gr.h>
+#include <nvgpu/gr/gr_instances.h>
+#include <nvgpu/gr/warpstate.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/engine_status.h>
+#include <nvgpu/fbp.h>
+#include <nvgpu/nvgpu_err.h>
+#include <nvgpu/netlist.h>
+#include <nvgpu/gr/obj_ctx.h>
+
+#include "gr_ga100.h"
+#include "hal/gr/gr/gr_gk20a.h"
+#include "hal/gr/gr/gr_pri_gk20a.h"
+#include "common/gr/gr_priv.h"
+
+#include <nvgpu/hw/ga100/hw_gr_ga100.h>
+#include <nvgpu/hw/ga100/hw_proj_ga100.h>
+
+static void gr_ga100_dump_gr_per_sm_regs(struct gk20a *g,
+			struct nvgpu_debug_context *o,
+			u32 gpc, u32 tpc, u32 sm, u32 offset)
+{
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_WARP_ESR: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_hww_warp_esr_r(),
+				   offset)));
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_WARP_ESR_REPORT_MASK: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(),
+				   offset)));
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_GLOBAL_ESR: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_hww_global_esr_r(),
+				   offset)));
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_GLOBAL_ESR_REPORT_MASK: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(),
+				   offset)));
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_DBGR_CONTROL0: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_dbgr_control0_r(),
+				   offset)));
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_DBGR_STATUS0: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_dbgr_status0_r(),
+				   offset)));
+}
+
+static void gr_ga100_dump_gr_sm_regs(struct gk20a *g,
+			   struct nvgpu_debug_context *o)
+{
+	u32 gpc, tpc, sm, sm_per_tpc;
+	u32 gpc_offset, tpc_offset, offset;
+	struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK: 0x%x\n",
+		nvgpu_readl(g,
+		gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_hww_global_esr_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_dbgr_control0_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_dbgr_status0_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK_0: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK_1: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r()));
+
+	sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
+	for (gpc = 0U;
+	     gpc < nvgpu_gr_config_get_gpc_count(gr->config); gpc++) {
+		gpc_offset = nvgpu_gr_gpc_offset(g, gpc);
+
+		for (tpc = 0U;
+		     tpc < nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc);
+		     tpc++) {
+			tpc_offset = nvgpu_gr_tpc_offset(g, tpc);
+
+			for (sm = 0U; sm < sm_per_tpc; sm++) {
+				offset = nvgpu_safe_add_u32(
+						nvgpu_safe_add_u32(gpc_offset,
+								   tpc_offset),
+						nvgpu_gr_sm_offset(g, sm));
+
+				gr_ga100_dump_gr_per_sm_regs(g, o,
+					gpc, tpc, sm, offset);
+			}
+		}
+	}
+}
+
+static void gr_ga100_dump_tpc_activity_regs(struct gk20a *g,
+					    struct nvgpu_debug_context *o)
+{
+	struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
+	u32 gpc_index = 0U;
+	u32 tpc_count = 0U, tpc_stride = 0U;
+	u32 reg_index = 0U, offset = 0U;
+	u32 i = 0U;
+
+	if (nvgpu_gr_config_get_gpc_tpc_count_base(gr->config) == NULL) {
+		return;
+	}
+
+	tpc_count = nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc_index);
+	tpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
+
+	for (i = 0U; i < tpc_count; i++) {
+		offset = nvgpu_safe_mult_u32(tpc_stride, i);
+		reg_index = nvgpu_safe_add_u32(offset,
+				gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r());
+
+		gk20a_debug_output(o,
+			"NV_PGRAPH_PRI_GPC0_TPC%d_TPCCS_TPC_ACTIVITY0: 0x%x\n",
+			i, nvgpu_readl(g, reg_index));
+	}
+}
+
+int gr_ga100_dump_gr_status_regs(struct gk20a *g,
+				 struct nvgpu_debug_context *o)
+{
+	u32 gr_engine_id;
+	struct nvgpu_engine_status_info engine_status;
+
+	gr_engine_id = nvgpu_engine_get_gr_id(g);
+
+	gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n",
+		nvgpu_readl(g, gr_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_STATUS1: 0x%x\n",
+		nvgpu_readl(g, gr_status_1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_ENGINE_STATUS: 0x%x\n",
+		nvgpu_readl(g, gr_engine_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_STATUS : 0x%x\n",
+		nvgpu_readl(g, gr_gpfifo_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_CONTROL : 0x%x\n",
+		nvgpu_readl(g, gr_gpfifo_ctl_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_STATUS : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_host_int_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_EXCEPTION  : 0x%x\n",
+		nvgpu_readl(g, gr_exception_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR  : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_intr_r()));
+	g->ops.engine_status.read_engine_status_info(g, gr_engine_id,
+		&engine_status);
+	gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n",
+		engine_status.reg_data);
+	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n",
+		nvgpu_readl(g, gr_activity_0_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n",
+		nvgpu_readl(g, gr_activity_1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY4: 0x%x\n",
+		nvgpu_readl(g, gr_activity_4_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_SKED_ACTIVITY: 0x%x\n",
+		nvgpu_readl(g, gr_pri_sked_activity_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_activity0_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_activity1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_activity2_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r()));
+
+	gr_ga100_dump_tpc_activity_regs(g,o);
+
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_gpccs_gpc_activity_0_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_gpccs_gpc_activity_1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_gpccs_gpc_activity_2_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r()));
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		gk20a_debug_output(o, "NV_PGRAPH_PRI_DS_MPIPE_STATUS: 0x%x\n",
+			nvgpu_readl(g, gr_pri_ds_mpipe_status_r()));
+	}
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT : 0x%x\n",
+		nvgpu_readl(g, gr_fe_go_idle_timeout_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_INFO : 0x%x\n",
+		nvgpu_readl(g, gr_pri_fe_go_idle_info_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n",
+		nvgpu_readl(g, gr_cwd_fs_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS(0): 0x%x\n",
+		nvgpu_readl(g, gr_fe_tpc_fs_r(0)));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID: 0x%x\n",
+		nvgpu_readl(g, gr_cwd_gpc_tpc_id_r(0)));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n",
+		nvgpu_readl(g, gr_cwd_sm_id_r(0)));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0: 0x%x\n",
+		g->ops.gr.falcon.read_fecs_ctxsw_status0(g));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1: 0x%x\n",
+		g->ops.gr.falcon.read_fecs_ctxsw_status1(g));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0: 0x%x\n",
+		nvgpu_readl(g, gr_gpc0_gpccs_ctxsw_status_gpc_0_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1: 0x%x\n",
+		nvgpu_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_ctxsw_idlestate_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE : 0x%x\n",
+		nvgpu_readl(g, gr_gpc0_gpccs_ctxsw_idlestate_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CURRENT_CTX : 0x%x\n",
+		g->ops.gr.falcon.get_current_ctx(g));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_new_ctx_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_host_int_enable_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_STATUS : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_host_int_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_exception_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_exception_en_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r()));
+
+	gr_ga100_dump_gr_sm_regs(g, o);
+
+	return 0;
+}
+
+void gr_ga100_set_circular_buffer_size(struct gk20a *g, u32 data)
+{
+	struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
+	u32 gpc_index, ppc_index, stride, val;
+	u32 cb_size_steady = data * 4U, cb_size;
+	u32 attrib_cb_size = g->ops.gr.init.get_attrib_cb_size(g,
+		nvgpu_gr_config_get_tpc_count(gr->config));
+
+	nvgpu_log_fn(g, " ");
+
+	if (cb_size_steady > attrib_cb_size) {
+		cb_size_steady = attrib_cb_size;
+	}
+	if (nvgpu_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r()) !=
+		nvgpu_readl(g,
+			gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r())) {
+		cb_size = cb_size_steady +
+			(gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
+			 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
+	} else {
+		cb_size = cb_size_steady;
+	}
+
+	nvgpu_writel(g, gr_ds_tga_constraintlogic_beta_r(),
+		(nvgpu_readl(g, gr_ds_tga_constraintlogic_beta_r()) &
+		 ~gr_ds_tga_constraintlogic_beta_cbsize_f(~U32(0U))) |
+		 gr_ds_tga_constraintlogic_beta_cbsize_f(cb_size_steady));
+
+	for (gpc_index = 0;
+	     gpc_index < nvgpu_gr_config_get_gpc_count(gr->config);
+	     gpc_index++) {
+		stride = proj_gpc_stride_v() * gpc_index;
+
+		for (ppc_index = 0;
+		     ppc_index < nvgpu_gr_config_get_gpc_ppc_count(gr->config, gpc_index);
+		     ppc_index++) {
+
+			val = nvgpu_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() +
+				stride +
+				proj_ppc_in_gpc_stride_v() * ppc_index);
+
+			val = set_field(val,
+				gr_gpc0_ppc0_cbm_beta_cb_size_v_m(),
+				gr_gpc0_ppc0_cbm_beta_cb_size_v_f(cb_size *
+					nvgpu_gr_config_get_pes_tpc_count(gr->config,
+						gpc_index, ppc_index)));
+
+			nvgpu_writel(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() +
+				stride +
+				proj_ppc_in_gpc_stride_v() * ppc_index, val);
+
+			nvgpu_writel(g, proj_ppc_in_gpc_stride_v() * ppc_index +
+				gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() +
+				stride,
+				gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(
+					cb_size_steady));
+
+			val = nvgpu_readl(g, gr_gpcs_swdx_tc_beta_cb_size_r(
+						ppc_index + gpc_index));
+
+			val = set_field(val,
+				gr_gpcs_swdx_tc_beta_cb_size_v_m(),
+				gr_gpcs_swdx_tc_beta_cb_size_v_f(
+					cb_size_steady *
+					nvgpu_gr_config_get_gpc_ppc_count(gr->config, gpc_index)));
+
+			nvgpu_writel(g, gr_gpcs_swdx_tc_beta_cb_size_r(
+						ppc_index + gpc_index), val);
+		}
+	}
+}
+
+/*
+ * The sys, tpc, etpc, ppc and gpc ctxsw_reg bundles are divided into compute
+ * and gfx. These registers are stored contigously in a single buffer segment.
+ * For example priv_sys_segment contains: sys_compute followed by sys_graphics,
+ * similarly gpccs_priv_segment contains: tpc_compute followed by tpc_graphics
+ * and so on. However, the indices within the *_compute and *_graphics list are
+ * not contiguous i.e the graphics list index start from 0, does not continue
+ * from the index of the last register in the compute list. Hence, while
+ * calculating the offset of registers witin *_graphics list, the
+ * computation should account for *_compute registers that preceed it.
+ */
+int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g,
+					     enum ctxsw_addr_type addr_type,
+					     u32 pri_addr,
+					     u32 gpc_num, u32 num_tpcs,
+					     u32 num_ppcs, u32 ppc_mask,
+					     u32 *priv_offset)
+{
+	u32 i;
+	u32 address, base_address;
+	u32 sys_offset, gpc_offset, tpc_offset, ppc_offset;
+	u32 ppc_num, tpc_num, tpc_addr, gpc_addr, ppc_addr;
+	struct netlist_aiv_list *list;
+	struct netlist_aiv *reg;
+	u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE);
+	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+	u32 ppc_in_gpc_base = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_BASE);
+	u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE);
+	u32 tpc_in_gpc_base = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_BASE);
+	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
+
+	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "pri_addr=0x%x", pri_addr);
+
+	if (!g->netlist_valid) {
+		return -EINVAL;
+	}
+
+	/* Process the SYS/BE segment. */
+	if ((addr_type == CTXSW_ADDR_TYPE_SYS) ||
+	    (addr_type == CTXSW_ADDR_TYPE_ROP)) {
+		list = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
+			address    = reg->addr;
+			sys_offset = reg->index;
+
+			if (pri_addr == address) {
+				*priv_offset = sys_offset;
+				return 0;
+			}
+		}
+#ifdef CONFIG_NVGPU_GRAPHICS
+		list = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
+			address    = reg->addr;
+			sys_offset = reg->index;
+
+			if (pri_addr == address) {
+				*priv_offset = sys_offset +
+					       nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count * 4U;
+				return 0;
+			}
+		}
+#endif
+	}
+
+	/*
+	 * Process the LTS segment.
+	 *
+	 * The LTS registers are stored after the ctx_regs_compute/graphics.
+	 * Hence, compute the sysoffset taking into account their count. Each
+	 * count represents an entry of 4 bytes.
+	 */
+	if (addr_type == CTXSW_ADDR_TYPE_LTS_MAIN) {
+		sys_offset = nvgpu_next_netlist_get_sys_ctxsw_regs_count(g);
+		sys_offset <<= 2;
+		list = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
+			address = reg->addr;
+			sys_offset += reg->index;
+
+			if (pri_addr == address) {
+				*priv_offset = sys_offset;
+				return 0;
+			}
+		}
+	}
+
+	/* Process the TPC segment. */
+	if (addr_type == CTXSW_ADDR_TYPE_TPC) {
+		for (tpc_num = 0; tpc_num < num_tpcs; tpc_num++) {
+			list = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				tpc_addr = pri_tpccs_addr_mask(g, address);
+				base_address = gpc_base +
+					(gpc_num * gpc_stride) +
+					tpc_in_gpc_base +
+					(tpc_num * tpc_in_gpc_stride);
+				address = base_address + tpc_addr;
+				/*
+				 * The data for the TPCs is interleaved in the context buffer.
+				 * Example with num_tpcs = 2
+				 * 0    1    2    3    4    5    6    7    8    9    10   11 ...
+				 * 0-0  1-0  0-1  1-1  0-2  1-2  0-3  1-3  0-4  1-4  0-5  1-5 ...
+				 */
+				tpc_offset = (reg->index * num_tpcs) + (tpc_num * 4U);
+
+				if (pri_addr == address) {
+					*priv_offset = tpc_offset;
+					return 0;
+				}
+			}
+#ifdef CONFIG_NVGPU_GRAPHICS
+			list = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				tpc_addr = pri_tpccs_addr_mask(g, address);
+				base_address = gpc_base +
+					(gpc_num * gpc_stride) +
+					tpc_in_gpc_base +
+					(tpc_num * tpc_in_gpc_stride);
+				address = base_address + tpc_addr;
+				/*
+				 * The data for the TPCs is interleaved in the context buffer.
+				 * Example with num_tpcs = 2
+				 * 0    1    2    3    4    5    6    7    8    9    10   11 ...
+				 * 0-0  1-0  0-1  1-1  0-2  1-2  0-3  1-3  0-4  1-4  0-5  1-5 ...
+				 */
+				tpc_offset = (reg->index * num_tpcs) + (tpc_num * 4U);
+
+				if (pri_addr == address) {
+					*priv_offset = tpc_offset +
+						nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count * num_tpcs * 4U;
+					return 0;
+				}
+			}
+#endif
+		}
+	} else if ((addr_type == CTXSW_ADDR_TYPE_EGPC) ||
+		(addr_type == CTXSW_ADDR_TYPE_ETPC)) {
+		if (g->ops.gr.get_egpc_base == NULL) {
+			return -EINVAL;
+		}
+
+		for (tpc_num = 0; tpc_num < num_tpcs; tpc_num++) {
+			list = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				tpc_addr = pri_tpccs_addr_mask(g, address);
+				base_address = g->ops.gr.get_egpc_base(g) +
+					(gpc_num * gpc_stride) +
+					tpc_in_gpc_base +
+					(tpc_num * tpc_in_gpc_stride);
+				address = base_address + tpc_addr;
+				/*
+				 * The data for the TPCs is interleaved in the context buffer.
+				 * Example with num_tpcs = 2
+				 * 0    1    2    3    4    5    6    7    8    9    10   11 ...
+				 * 0-0  1-0  0-1  1-1  0-2  1-2  0-3  1-3  0-4  1-4  0-5  1-5 ...
+				 */
+				tpc_offset = (reg->index * num_tpcs) + (tpc_num * 4U);
+
+				if (pri_addr == address) {
+					*priv_offset = tpc_offset;
+					nvgpu_log(g,
+						gpu_dbg_fn | gpu_dbg_gpu_dbg,
+						"egpc/etpc compute priv_offset=0x%#08x",
+						*priv_offset);
+					return 0;
+				}
+			}
+#ifdef CONFIG_NVGPU_GRAPHICS
+			list = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				tpc_addr = pri_tpccs_addr_mask(g, address);
+				base_address = g->ops.gr.get_egpc_base(g) +
+					(gpc_num * gpc_stride) +
+					tpc_in_gpc_base +
+					(tpc_num * tpc_in_gpc_stride);
+				address = base_address + tpc_addr;
+				/*
+				 * The data for the TPCs is interleaved in the context buffer.
+				 * Example with num_tpcs = 2
+				 * 0    1    2    3    4    5    6    7    8    9    10   11 ...
+				 * 0-0  1-0  0-1  1-1  0-2  1-2  0-3  1-3  0-4  1-4  0-5  1-5 ...
+				 */
+				tpc_offset = (reg->index * num_tpcs) + (tpc_num * 4U);
+
+				if (pri_addr == address) {
+					*priv_offset = tpc_offset +
+						nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count * num_tpcs * 4U;
+					nvgpu_log(g,
+						gpu_dbg_fn | gpu_dbg_gpu_dbg,
+						"egpc/etpc gfx priv_offset=0x%#08x",
+						*priv_offset);
+					return 0;
+				}
+			}
+#endif
+		}
+	}
+
+
+	/* Process the PPC segment. */
+	if (addr_type == CTXSW_ADDR_TYPE_PPC) {
+		for (ppc_num = 0; ppc_num < num_ppcs; ppc_num++) {
+			list = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				ppc_addr = pri_ppccs_addr_mask(address);
+				base_address = gpc_base +
+					(gpc_num * gpc_stride) +
+					ppc_in_gpc_base +
+					(ppc_num * ppc_in_gpc_stride);
+				address = base_address + ppc_addr;
+				/*
+				 * The data for the PPCs is interleaved in the context buffer.
+				 * Example with numPpcs = 2
+				 * 0    1    2    3    4    5    6    7    8    9    10   11 ...
+				 * 0-0  1-0  0-1  1-1  0-2  1-2  0-3  1-3  0-4  1-4  0-5  1-5 ...
+				 */
+				ppc_offset = (reg->index * num_ppcs) + (ppc_num * 4U);
+
+				if (pri_addr == address)  {
+					*priv_offset = ppc_offset;
+					return 0;
+				}
+			}
+#ifdef CONFIG_NVGPU_GRAPHICS
+			list = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				ppc_addr = pri_ppccs_addr_mask(address);
+				base_address = gpc_base +
+					(gpc_num * gpc_stride) +
+					ppc_in_gpc_base +
+					(ppc_num * ppc_in_gpc_stride);
+				address = base_address + ppc_addr;
+				/*
+				 * The data for the PPCs is interleaved in the context buffer.
+				 * Example with numPpcs = 2
+				 * 0    1    2    3    4    5    6    7    8    9    10   11 ...
+				 * 0-0  1-0  0-1  1-1  0-2  1-2  0-3  1-3  0-4  1-4  0-5  1-5 ...
+				 */
+				ppc_offset = (reg->index * num_ppcs) + (ppc_num * 4U);
+
+				if (pri_addr == address)  {
+					*priv_offset = ppc_offset +
+						nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count * num_ppcs * 4U;
+					return 0;
+				}
+			}
+#endif
+		}
+	}
+
+	/* Process the GPC segment. */
+	if (addr_type == CTXSW_ADDR_TYPE_GPC) {
+		list = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
+
+			address = reg->addr;
+			gpc_addr = pri_gpccs_addr_mask(g, address);
+			gpc_offset = reg->index;
+
+			base_address = gpc_base + (gpc_num * gpc_stride);
+			address = base_address + gpc_addr;
+
+			if (pri_addr == address) {
+				*priv_offset = gpc_offset;
+				return 0;
+			}
+		}
+#ifdef CONFIG_NVGPU_GRAPHICS
+		list = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
+
+			address = reg->addr;
+			gpc_addr = pri_gpccs_addr_mask(g, address);
+			gpc_offset = reg->index;
+
+			base_address = gpc_base + (gpc_num * gpc_stride);
+			address = base_address + gpc_addr;
+
+			if (pri_addr == address) {
+				*priv_offset = gpc_offset +
+					nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count * 4U;
+				return 0;
+			}
+		}
+#endif
+	}
+	return -EINVAL;
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.h
new file mode 100644
index 000000000..b40763a7d
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.h
@@ -0,0 +1,42 @@
+/*
+ * GA100 GPU GR
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_GA100_H
+#define NVGPU_GR_GA100_H
+
+struct gk20a;
+struct nvgpu_debug_context;
+
+int gr_ga100_dump_gr_status_regs(struct gk20a *g,
+				 struct nvgpu_debug_context *o);
+void gr_ga100_set_circular_buffer_size(struct gk20a *g, u32 data);
+#ifdef CONFIG_NVGPU_DEBUGGER
+int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g,
+					     enum ctxsw_addr_type addr_type,
+					     u32 pri_addr,
+					     u32 gpc_num, u32 num_tpcs,
+					     u32 num_ppcs, u32 ppc_mask,
+					     u32 *priv_offset);
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#endif /* NVGPU_GR_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c
new file mode 100644
index 000000000..be2d856cf
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c
@@ -0,0 +1,1075 @@
+/*
+ * GA10b GPU GR
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/dma.h>
+#include <nvgpu/log.h>
+#include <nvgpu/debug.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/fuse.h>
+#include <nvgpu/debugger.h>
+#include <nvgpu/error_notifier.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/bitops.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/regops.h>
+#include <nvgpu/gr/ctx.h>
+#include <nvgpu/gr/config.h>
+#include <nvgpu/gr/gr.h>
+#include <nvgpu/gr/gr_instances.h>
+#include <nvgpu/gr/warpstate.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/engine_status.h>
+#include <nvgpu/fbp.h>
+#include <nvgpu/nvgpu_err.h>
+#include <nvgpu/netlist.h>
+#include <nvgpu/gr/obj_ctx.h>
+#include <nvgpu/nvgpu_next_litter.h>
+
+#include "gr_ga10b.h"
+#include "hal/gr/gr/gr_gk20a.h"
+#include "hal/gr/gr/gr_gv11b.h"
+#include "hal/gr/gr/gr_pri_gk20a.h"
+#include "hal/gr/gr/gr_pri_ga10b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h"
+#include "common/gr/gr_priv.h"
+
+#include <nvgpu/hw/ga10b/hw_gr_ga10b.h>
+#include <nvgpu/hw/ga10b/hw_proj_ga10b.h>
+
+#define ILLEGAL_ID	~U32(0U)
+
+static void gr_ga10b_dump_gr_per_sm_regs(struct gk20a *g,
+			struct nvgpu_debug_context *o,
+			u32 gpc, u32 tpc, u32 sm, u32 offset)
+{
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_WARP_ESR: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_hww_warp_esr_r(),
+				   offset)));
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_WARP_ESR_REPORT_MASK: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(),
+				   offset)));
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_GLOBAL_ESR: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_hww_global_esr_r(),
+				   offset)));
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_GLOBAL_ESR_REPORT_MASK: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(),
+				   offset)));
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_DBGR_CONTROL0: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_dbgr_control0_r(),
+				   offset)));
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_DBGR_STATUS0: 0x%x\n",
+		gpc, tpc, sm, nvgpu_readl(g,
+		nvgpu_safe_add_u32(gr_gpc0_tpc0_sm0_dbgr_status0_r(),
+				   offset)));
+}
+
+static void gr_ga10b_dump_gr_sm_regs(struct gk20a *g,
+			   struct nvgpu_debug_context *o)
+{
+	u32 gpc, tpc, sm, sm_per_tpc;
+	u32 gpc_offset, tpc_offset, offset;
+	struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
+
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK: 0x%x\n",
+		nvgpu_readl(g,
+		gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_hww_global_esr_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_dbgr_control0_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_dbgr_status0_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK_0: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r()));
+	gk20a_debug_output(o,
+		"NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK_1: 0x%x\n",
+		nvgpu_readl(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r()));
+
+	sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
+	for (gpc = 0U;
+	     gpc < nvgpu_gr_config_get_gpc_count(gr->config); gpc++) {
+		gpc_offset = nvgpu_gr_gpc_offset(g, gpc);
+
+		for (tpc = 0U;
+		     tpc < nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc);
+		     tpc++) {
+			tpc_offset = nvgpu_gr_tpc_offset(g, tpc);
+
+			for (sm = 0U; sm < sm_per_tpc; sm++) {
+				offset = nvgpu_safe_add_u32(
+						nvgpu_safe_add_u32(gpc_offset,
+								   tpc_offset),
+						nvgpu_gr_sm_offset(g, sm));
+
+				gr_ga10b_dump_gr_per_sm_regs(g, o,
+					gpc, tpc, sm, offset);
+			}
+		}
+	}
+}
+
+static void gr_ga10b_dump_tpc_activity_regs(struct gk20a *g,
+					    struct nvgpu_debug_context *o)
+{
+	struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
+	u32 gpc_index = 0U;
+	u32 tpc_count = 0U, tpc_stride = 0U;
+	u32 reg_index = 0U, offset = 0U;
+	u32 i = 0U;
+
+	if (nvgpu_gr_config_get_gpc_tpc_count_base(gr->config) == NULL) {
+		return;
+	}
+
+	tpc_count = nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc_index);
+	tpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
+
+	for (i = 0U; i < tpc_count; i++) {
+		offset = nvgpu_safe_mult_u32(tpc_stride, i);
+		reg_index = nvgpu_safe_add_u32(offset,
+				gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r());
+
+		gk20a_debug_output(o,
+			"NV_PGRAPH_PRI_GPC0_TPC%d_TPCCS_TPC_ACTIVITY0: 0x%x\n",
+			i, nvgpu_readl(g, reg_index));
+	}
+}
+
+int gr_ga10b_dump_gr_status_regs(struct gk20a *g,
+				 struct nvgpu_debug_context *o)
+{
+	u32 gr_engine_id;
+	struct nvgpu_engine_status_info engine_status;
+
+	gr_engine_id = nvgpu_engine_get_gr_id(g);
+
+	gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n",
+		nvgpu_readl(g, gr_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_STATUS1: 0x%x\n",
+		nvgpu_readl(g, gr_status_1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_ENGINE_STATUS: 0x%x\n",
+		nvgpu_readl(g, gr_engine_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_STATUS : 0x%x\n",
+		nvgpu_readl(g, gr_gpfifo_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_CONTROL : 0x%x\n",
+		nvgpu_readl(g, gr_gpfifo_ctl_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_STATUS : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_host_int_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_EXCEPTION  : 0x%x\n",
+		nvgpu_readl(g, gr_exception_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR  : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_intr_r()));
+	g->ops.engine_status.read_engine_status_info(g, gr_engine_id,
+		&engine_status);
+	gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n",
+		engine_status.reg_data);
+	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n",
+		nvgpu_readl(g, gr_activity_0_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n",
+		nvgpu_readl(g, gr_activity_1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY4: 0x%x\n",
+		nvgpu_readl(g, gr_activity_4_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_SKED_ACTIVITY: 0x%x\n",
+		nvgpu_readl(g, gr_pri_sked_activity_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_activity0_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_activity1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_activity2_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_activity4_r()));
+
+	gr_ga10b_dump_tpc_activity_regs(g,o);
+
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_gpccs_gpc_activity_0_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_gpccs_gpc_activity_1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_gpccs_gpc_activity_2_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_gpccs_gpc_activity_4_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r()));
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		gk20a_debug_output(o, "NV_PGRAPH_PRI_DS_MPIPE_STATUS: 0x%x\n",
+			nvgpu_readl(g, gr_pri_ds_mpipe_status_r()));
+	}
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT : 0x%x\n",
+		nvgpu_readl(g, gr_fe_go_idle_timeout_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_INFO : 0x%x\n",
+		nvgpu_readl(g, gr_pri_fe_go_idle_info_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n",
+		nvgpu_readl(g, gr_cwd_fs_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS(0): 0x%x\n",
+		nvgpu_readl(g, gr_fe_tpc_fs_r(0)));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID: 0x%x\n",
+		nvgpu_readl(g, gr_cwd_gpc_tpc_id_r(0)));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n",
+		nvgpu_readl(g, gr_cwd_sm_id_r(0)));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0: 0x%x\n",
+		g->ops.gr.falcon.read_fecs_ctxsw_status0(g));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1: 0x%x\n",
+		g->ops.gr.falcon.read_fecs_ctxsw_status1(g));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0: 0x%x\n",
+		nvgpu_readl(g, gr_gpc0_gpccs_ctxsw_status_gpc_0_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1: 0x%x\n",
+		nvgpu_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_ctxsw_idlestate_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE : 0x%x\n",
+		nvgpu_readl(g, gr_gpc0_gpccs_ctxsw_idlestate_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CURRENT_CTX : 0x%x\n",
+		g->ops.gr.falcon.get_current_ctx(g));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_new_ctx_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_host_int_enable_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_STATUS : 0x%x\n",
+		nvgpu_readl(g, gr_fecs_host_int_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1 : 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_rop0_crop_status1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1 : 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_rops_crop_status1_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS : 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_rop0_zrop_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2 : 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_rop0_zrop_status2_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_ROP1_ZROP_STATUS: 0x%x\n",
+		nvgpu_readl(g, nvgpu_safe_add_u32(
+			gr_pri_gpcs_rop0_zrop_status_r(),
+			nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE))));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_ROP1_ZROP_STATUS2: 0x%x\n",
+		nvgpu_readl(g, nvgpu_safe_add_u32(
+			gr_pri_gpcs_rop0_zrop_status2_r(),
+			nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE))));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS : 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_rops_zrop_status_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2 : 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpcs_rops_zrop_status2_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_exception_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_gpccs_gpc_exception_en_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n",
+		nvgpu_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r()));
+
+	gr_ga10b_dump_gr_sm_regs(g, o);
+
+	return 0;
+}
+
+void gr_ga10b_set_circular_buffer_size(struct gk20a *g, u32 data)
+{
+	struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
+	u32 gpc_index, ppc_index, stride, val;
+	u32 cb_size_steady = data * 4U, cb_size;
+	u32 attrib_cb_size = g->ops.gr.init.get_attrib_cb_size(g,
+		nvgpu_gr_config_get_tpc_count(gr->config));
+
+	nvgpu_log_fn(g, " ");
+
+	if (cb_size_steady > attrib_cb_size) {
+		cb_size_steady = attrib_cb_size;
+	}
+	if (nvgpu_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r()) !=
+		nvgpu_readl(g,
+			gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r())) {
+		cb_size = cb_size_steady +
+			(gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
+			 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
+	} else {
+		cb_size = cb_size_steady;
+	}
+
+	nvgpu_writel(g, gr_ds_tga_constraintlogic_beta_r(),
+		(nvgpu_readl(g, gr_ds_tga_constraintlogic_beta_r()) &
+		 ~gr_ds_tga_constraintlogic_beta_cbsize_f(~U32(0U))) |
+		 gr_ds_tga_constraintlogic_beta_cbsize_f(cb_size_steady));
+
+	for (gpc_index = 0;
+	     gpc_index < nvgpu_gr_config_get_gpc_count(gr->config);
+	     gpc_index++) {
+		stride = proj_gpc_stride_v() * gpc_index;
+
+		for (ppc_index = 0;
+		     ppc_index < nvgpu_gr_config_get_gpc_ppc_count(gr->config, gpc_index);
+		     ppc_index++) {
+
+			val = nvgpu_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() +
+				stride +
+				proj_ppc_in_gpc_stride_v() * ppc_index);
+
+			val = set_field(val,
+				gr_gpc0_ppc0_cbm_beta_cb_size_v_m(),
+				gr_gpc0_ppc0_cbm_beta_cb_size_v_f(cb_size *
+					nvgpu_gr_config_get_pes_tpc_count(gr->config,
+						gpc_index, ppc_index)));
+
+			nvgpu_writel(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() +
+				stride +
+				proj_ppc_in_gpc_stride_v() * ppc_index, val);
+
+			nvgpu_writel(g, proj_ppc_in_gpc_stride_v() * ppc_index +
+				gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() +
+				stride,
+				gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(
+					cb_size_steady));
+
+			val = nvgpu_readl(g, gr_gpcs_swdx_tc_beta_cb_size_r(
+						ppc_index + gpc_index));
+
+			val = set_field(val,
+				gr_gpcs_swdx_tc_beta_cb_size_v_m(),
+				gr_gpcs_swdx_tc_beta_cb_size_v_f(
+					cb_size_steady *
+					nvgpu_gr_config_get_gpc_ppc_count(gr->config, gpc_index)));
+
+			nvgpu_writel(g, gr_gpcs_swdx_tc_beta_cb_size_r(
+						ppc_index + gpc_index), val);
+		}
+	}
+}
+
+void ga10b_gr_set_gpcs_rops_crop_debug4(struct gk20a *g, u32 data)
+{
+	u32 val;
+
+	nvgpu_log_fn(g, " ");
+
+	val = nvgpu_readl(g, gr_pri_gpcs_rops_crop_debug4_r());
+	if ((data & gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_s()) ==
+		gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_to_maxval_v()) {
+		val = set_field(val,
+			gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_m(),
+			gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_to_maxval_f());
+	} else if ((data & gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_s()) ==
+		gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_to_inf_v()) {
+		val = set_field(val,
+			gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_m(),
+			gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_to_inf_f());
+	} else {
+		nvgpu_warn(g,
+			"wrong data sent for crop_debug4: %x08x", data);
+		return;
+	}
+	nvgpu_writel(g, gr_pri_gpcs_rops_crop_debug4_r(), val);
+}
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+bool ga10b_gr_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error)
+{
+	u32 index = 0U;
+	bool esr_err = false;
+
+	struct warp_esr_error_table_s {
+		u32 error_value;
+		const char *error_name;
+	};
+
+	struct warp_esr_error_table_s warp_esr_error_table[] = {
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(),
+				"API STACK ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(),
+				"MISALIGNED PC ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f(),
+				"PC OVERFLOW ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f(),
+				"MISALIGNED REG ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f(),
+				"ILLEGAL INSTRUCTION ENCODING ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f(),
+				"ILLEGAL INSTRUCTION PARAM ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f(),
+				"OOR REG ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f(),
+				"OOR ADDR ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f(),
+				"MISALIGNED ADDR ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f(),
+				"INVALID ADDR SPACE ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f(),
+				"INVALID ADDR LDC ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f(),
+				"MMU FAULT ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f(),
+				"TEX FORMAT ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f(),
+				"TEX LAYOUT ERROR"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(),
+				"MMU NACK"},
+		{ gr_gpc0_tpc0_sm0_hww_warp_esr_error_arrive_f(),
+				"ARRIVE ERROR"},
+	};
+
+	for (index = 0; index < ARRAY_SIZE(warp_esr_error_table); index++) {
+		if (warp_esr_error_table[index].error_value == warp_esr_error) {
+			esr_err = true;
+			nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg,
+				"WARP_ESR %s(0x%x)",
+				warp_esr_error_table[index].error_name,
+				esr_err);
+			break;
+		}
+	}
+
+	return esr_err;
+}
+
+
+/*
+ * The context switched registers are saved as part of the context switch
+ * image.
+ *
+ * The regops interface writes/reads these location within the saved context
+ * switch image when the context is not resident.
+ */
+
+/*
+ * This function will decode a priv address and return the partition
+ * type and numbers
+ */
+int gr_ga10b_decode_priv_addr(struct gk20a *g, u32 addr,
+	enum ctxsw_addr_type *addr_type,
+	u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
+	u32 *broadcast_flags)
+{
+	u32 gpc_addr;
+
+	/*
+	 * Special handling for registers under: ctx_reg_LTS_bc
+	 *
+	 * Unlike the other ltc registers which are stored as part of
+	 * pm_ctxsw buffer these are stored in fecs ctxsw image priv
+	 * segment regionid: NETLIST_REGIONID_CTXREG_LTS.
+	 */
+	if (g->ops.ltc.pri_is_ltc_addr(g, addr) &&
+			g->ops.ltc.pri_is_lts_tstg_addr(g, addr)) {
+		*addr_type = CTXSW_ADDR_TYPE_LTS_MAIN;
+		if (g->ops.ltc.is_ltcs_ltss_addr(g, addr)) {
+			*broadcast_flags |= PRI_BROADCAST_FLAGS_LTCS;
+		} else if (g->ops.ltc.is_ltcn_ltss_addr(g, addr)) {
+			*broadcast_flags |= PRI_BROADCAST_FLAGS_LTSS;
+		}
+		return 0;
+	} else if (nvgpu_is_enabled(g, NVGPU_SUPPORT_ROP_IN_GPC) &&
+			pri_is_gpc_addr(g, addr)) {
+		gpc_addr = pri_gpccs_addr_mask(g, addr);
+		if (pri_is_rop_in_gpc_addr(g, gpc_addr)) {
+			if (pri_is_rop_in_gpc_addr_shared(g, gpc_addr)) {
+				*broadcast_flags |=
+					PRI_BROADCAST_FLAGS_ROP;
+			}
+			*addr_type = CTXSW_ADDR_TYPE_ROP;
+			return 0;
+		}
+	}
+
+	return gr_gv11b_decode_priv_addr(g, addr, addr_type, gpc_num,
+			tpc_num, ppc_num, be_num, broadcast_flags);
+}
+
+int gr_ga10b_create_priv_addr_table(struct gk20a *g,
+					   u32 addr,
+					   u32 *priv_addr_table,
+					   u32 *num_registers)
+{
+	enum ctxsw_addr_type addr_type;
+	u32 gpc_num = 0U, tpc_num = 0U, ppc_num = 0U, be_num = 0U;
+	u32 broadcast_flags = 0U;
+	u32 t;
+	int err;
+
+	t = 0U;
+	*num_registers = 0U;
+
+	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
+
+	err = g->ops.gr.decode_priv_addr(g, addr, &addr_type,
+					&gpc_num, &tpc_num, &ppc_num, &be_num,
+					&broadcast_flags);
+	nvgpu_log(g, gpu_dbg_gpu_dbg, "addr_type = %d", addr_type);
+	if (err != 0) {
+		return err;
+	}
+
+	/*
+	 * The LIST_ctx_reg_LTS_bc contains broadcast registers; So, convert
+	 * LTS unicast addresses of the form LTCnLTSn, LTCSLTSn, LTCnLTSS to
+	 * LTCSLTSS.
+	 */
+	if (addr_type == CTXSW_ADDR_TYPE_LTS_MAIN) {
+		if (broadcast_flags & PRI_BROADCAST_FLAGS_LTCS) {
+			priv_addr_table[t++] = addr;
+		} else {
+			priv_addr_table[t++] =
+				g->ops.ltc.pri_shared_addr(g, addr);
+		}
+		*num_registers = t;
+		return 0;
+	}
+
+	/*
+	 * At present the LIST_pm_ctx_reg_ROP contains only broadcast addresses.
+	 * Hence, ROP unicast addresses are not ctxsw'ed, only broadcast
+	 * addresses are ctxsw'ed. Therefore, convert all ROP unicast addresses
+	 * to broadcast.
+	 */
+	if (addr_type == CTXSW_ADDR_TYPE_ROP) {
+		if (broadcast_flags & PRI_BROADCAST_FLAGS_ROP) {
+			priv_addr_table[t++] = addr;
+		} else {
+			priv_addr_table[t++] =
+				pri_rop_in_gpc_shared_addr(g, addr);
+		}
+		*num_registers = t;
+		return 0;
+	}
+
+	return gr_gv11b_create_priv_addr_table(g, addr, priv_addr_table, num_registers);
+}
+
+/*
+ * The sys, tpc, etpc, ppc and gpc ctxsw_reg bundles are divided into compute
+ * and gfx list. lts being the exception here, which still uses a single list.
+ * So, for any given pri address first search in the compute list
+ * followed by graphics list. On finding a match it returns the following:
+ * - FOUND_IN_CTXSWBUF_PRIV_REGLIST: legacy priv reglist.
+ * - FOUND_IN_CTXSWBUF_PRIV_COMPUTE_REGLIST: new compute priv reglist.
+ * - FOUND_IN_CTXSWBUF_PRIV_GFX_REGLIST: new graphics priv reglist.
+ */
+int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g,
+					     enum ctxsw_addr_type addr_type,
+					     u32 pri_addr,
+					     u32 gpc_num, u32 num_tpcs,
+					     u32 num_ppcs, u32 ppc_mask,
+					     u32 *priv_offset)
+{
+	u32 i;
+	u32 address, base_address;
+	u32 sys_offset, gpc_offset, tpc_offset, ppc_offset;
+	u32 ppc_num, tpc_num, tpc_addr, gpc_addr, ppc_addr;
+	struct netlist_aiv_list *list;
+	struct netlist_aiv *reg;
+	u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE);
+	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+	u32 ppc_in_gpc_base = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_BASE);
+	u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE);
+	u32 tpc_in_gpc_base = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_BASE);
+	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
+
+	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "pri_addr=0x%x", pri_addr);
+
+	if (!g->netlist_valid) {
+		return -EINVAL;
+	}
+
+	/* Process the SYS/BE segment. */
+	if ((addr_type == CTXSW_ADDR_TYPE_SYS) ||
+	    (addr_type == CTXSW_ADDR_TYPE_ROP)) {
+		list = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
+			address    = reg->addr;
+			sys_offset = reg->index;
+
+			if (pri_addr == address) {
+				*priv_offset = sys_offset;
+				return FOUND_IN_CTXSWBUF_PRIV_COMPUTE_REGLIST;
+			}
+		}
+#ifdef CONFIG_NVGPU_GRAPHICS
+		list = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
+			address    = reg->addr;
+			sys_offset = reg->index;
+
+			if (pri_addr == address) {
+				*priv_offset = sys_offset;
+				return FOUND_IN_CTXSWBUF_PRIV_GFX_REGLIST;
+			}
+		}
+#endif
+	}
+
+	/*
+	 * Process the LTS segment.
+	 */
+	if (addr_type == CTXSW_ADDR_TYPE_LTS_MAIN) {
+		list = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
+			address = reg->addr;
+			sys_offset = reg->index;
+
+			if (pri_addr == address) {
+				*priv_offset = sys_offset;
+				return FOUND_IN_CTXSWBUF_PRIV_REGLIST;
+			}
+		}
+	}
+
+	/* Process the TPC segment. */
+	if (addr_type == CTXSW_ADDR_TYPE_TPC) {
+		for (tpc_num = 0; tpc_num < num_tpcs; tpc_num++) {
+			list = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				tpc_addr = pri_tpccs_addr_mask(g, address);
+				base_address = gpc_base +
+					(gpc_num * gpc_stride) +
+					tpc_in_gpc_base +
+					(tpc_num * tpc_in_gpc_stride);
+				address = base_address + tpc_addr;
+				tpc_offset = reg->index;
+
+				if (pri_addr == address) {
+					*priv_offset = tpc_offset;
+					return FOUND_IN_CTXSWBUF_PRIV_COMPUTE_REGLIST;
+				}
+			}
+#ifdef CONFIG_NVGPU_GRAPHICS
+			list = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				tpc_addr = pri_tpccs_addr_mask(g, address);
+				base_address = gpc_base +
+					(gpc_num * gpc_stride) +
+					tpc_in_gpc_base +
+					(tpc_num * tpc_in_gpc_stride);
+				address = base_address + tpc_addr;
+				tpc_offset = reg->index;
+
+				if (pri_addr == address) {
+					*priv_offset = tpc_offset;
+					return FOUND_IN_CTXSWBUF_PRIV_GFX_REGLIST;
+				}
+			}
+#endif
+		}
+	} else if ((addr_type == CTXSW_ADDR_TYPE_EGPC) ||
+		(addr_type == CTXSW_ADDR_TYPE_ETPC)) {
+		if (g->ops.gr.get_egpc_base == NULL) {
+			return -EINVAL;
+		}
+
+		for (tpc_num = 0; tpc_num < num_tpcs; tpc_num++) {
+			list = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				tpc_addr = pri_tpccs_addr_mask(g, address);
+				base_address = g->ops.gr.get_egpc_base(g) +
+					(gpc_num * gpc_stride) +
+					tpc_in_gpc_base +
+					(tpc_num * tpc_in_gpc_stride);
+				address = base_address + tpc_addr;
+				/*
+				 * The data for the TPCs is interleaved in the context buffer.
+				 * Example with num_tpcs = 2
+				 * 0    1    2    3    4    5    6    7    8    9    10   11 ...
+				 * 0-0  1-0  0-1  1-1  0-2  1-2  0-3  1-3  0-4  1-4  0-5  1-5 ...
+				 */
+				tpc_offset = (reg->index * num_tpcs) + (tpc_num * 4U);
+
+				if (pri_addr == address) {
+					*priv_offset = tpc_offset;
+					nvgpu_log(g,
+						gpu_dbg_fn | gpu_dbg_gpu_dbg,
+						"egpc/etpc compute priv_offset=0x%#08x",
+						*priv_offset);
+					return FOUND_IN_CTXSWBUF_PRIV_COMPUTE_REGLIST;
+				}
+			}
+#ifdef CONFIG_NVGPU_GRAPHICS
+			list = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				tpc_addr = pri_tpccs_addr_mask(g, address);
+				base_address = g->ops.gr.get_egpc_base(g) +
+					(gpc_num * gpc_stride) +
+					tpc_in_gpc_base +
+					(tpc_num * tpc_in_gpc_stride);
+				address = base_address + tpc_addr;
+				/*
+				 * The data for the TPCs is interleaved in the context buffer.
+				 * Example with num_tpcs = 2
+				 * 0    1    2    3    4    5    6    7    8    9    10   11 ...
+				 * 0-0  1-0  0-1  1-1  0-2  1-2  0-3  1-3  0-4  1-4  0-5  1-5 ...
+				 */
+				tpc_offset = (reg->index * num_tpcs) + (tpc_num * 4U);
+
+				if (pri_addr == address) {
+					*priv_offset = tpc_offset;
+					nvgpu_log(g,
+						gpu_dbg_fn | gpu_dbg_gpu_dbg,
+						"egpc/etpc gfx priv_offset=0x%#08x",
+						*priv_offset);
+					return FOUND_IN_CTXSWBUF_PRIV_GFX_REGLIST;
+				}
+			}
+#endif
+		}
+	}
+
+
+	/* Process the PPC segment. */
+	if (addr_type == CTXSW_ADDR_TYPE_PPC) {
+		for (ppc_num = 0; ppc_num < num_ppcs; ppc_num++) {
+			list = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				ppc_addr = pri_ppccs_addr_mask(address);
+				base_address = gpc_base +
+					(gpc_num * gpc_stride) +
+					ppc_in_gpc_base +
+					(ppc_num * ppc_in_gpc_stride);
+				address = base_address + ppc_addr;
+				/*
+				 * The data for the PPCs is interleaved in the context buffer.
+				 * Example with numPpcs = 2
+				 * 0    1    2    3    4    5    6    7    8    9    10   11 ...
+				 * 0-0  1-0  0-1  1-1  0-2  1-2  0-3  1-3  0-4  1-4  0-5  1-5 ...
+				 */
+				ppc_offset = (reg->index * num_ppcs) + (ppc_num * 4U);
+
+				if (pri_addr == address)  {
+					*priv_offset = ppc_offset;
+					return FOUND_IN_CTXSWBUF_PRIV_COMPUTE_REGLIST;
+				}
+			}
+#ifdef CONFIG_NVGPU_GRAPHICS
+			list = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
+			for (i = 0; i < list->count; i++) {
+				reg = &list->l[i];
+				address = reg->addr;
+				ppc_addr = pri_ppccs_addr_mask(address);
+				base_address = gpc_base +
+					(gpc_num * gpc_stride) +
+					ppc_in_gpc_base +
+					(ppc_num * ppc_in_gpc_stride);
+				address = base_address + ppc_addr;
+				/*
+				 * The data for the PPCs is interleaved in the context buffer.
+				 * Example with numPpcs = 2
+				 * 0    1    2    3    4    5    6    7    8    9    10   11 ...
+				 * 0-0  1-0  0-1  1-1  0-2  1-2  0-3  1-3  0-4  1-4  0-5  1-5 ...
+				 */
+				ppc_offset = (reg->index * num_ppcs) + (ppc_num * 4U);
+
+				if (pri_addr == address)  {
+					*priv_offset = ppc_offset;
+					return FOUND_IN_CTXSWBUF_PRIV_GFX_REGLIST;
+				}
+			}
+#endif
+		}
+	}
+
+	/* Process the GPC segment. */
+	if (addr_type == CTXSW_ADDR_TYPE_GPC) {
+		list = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
+
+			address = reg->addr;
+			gpc_addr = pri_gpccs_addr_mask(g, address);
+			gpc_offset = reg->index;
+
+			base_address = gpc_base + (gpc_num * gpc_stride);
+			address = base_address + gpc_addr;
+
+			if (pri_addr == address) {
+				*priv_offset = gpc_offset;
+				return FOUND_IN_CTXSWBUF_PRIV_COMPUTE_REGLIST;
+			}
+		}
+#ifdef CONFIG_NVGPU_GRAPHICS
+		list = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
+		for (i = 0; i < list->count; i++) {
+			reg = &list->l[i];
+
+			address = reg->addr;
+			gpc_addr = pri_gpccs_addr_mask(g, address);
+			gpc_offset = reg->index;
+
+			base_address = gpc_base + (gpc_num * gpc_stride);
+			address = base_address + gpc_addr;
+
+			if (pri_addr == address) {
+				*priv_offset = gpc_offset;
+				return FOUND_IN_CTXSWBUF_PRIV_GFX_REGLIST;
+			}
+		}
+#endif
+	}
+	return -EINVAL;
+}
+
+/*
+ * Calculate the offset of pri address within ctxsw buffer by going through the
+ * various pri save segments.
+ */
+int gr_ga10b_find_priv_offset_in_buffer(struct gk20a *g, u32 addr,
+					u32 *context_buffer,
+					u32 context_buffer_size,
+					u32 *priv_offset)
+{
+	int err;
+	enum ctxsw_addr_type addr_type;
+	u32 broadcast_flags = 0U;
+	u32 gpc_num, tpc_num, ppc_num, be_num;
+	u32 num_gpcs, num_tpcs, num_ppcs;
+	u32 offset;
+	u32 ppc_mask, reg_list_ppc_count;
+	u32 *context;
+	u32 segoffset, compute_segoffset;
+	u32 graphics_segoffset;
+	u32 main_hdr_size, fecs_hdr_size, gpccs_hdr_stride;
+
+	err = g->ops.gr.decode_priv_addr(g, addr, &addr_type,
+					&gpc_num, &tpc_num, &ppc_num, &be_num,
+					&broadcast_flags);
+	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg,
+			"addr =0x%x addr_type = %d, broadcast_flags: %08x",
+			addr, addr_type, broadcast_flags);
+	if (err != 0) {
+		return err;
+	}
+
+	context = context_buffer;
+	if (!g->ops.gr.ctxsw_prog.check_main_image_header_magic(context)) {
+		nvgpu_err(g, "invalid main header: magic value");
+		return -EINVAL;
+	}
+
+	main_hdr_size = g->ops.gr.ctxsw_prog.hw_get_main_header_size();
+	fecs_hdr_size = g->ops.gr.ctxsw_prog.hw_get_fecs_header_size();
+	gpccs_hdr_stride = g->ops.gr.ctxsw_prog.hw_get_gpccs_header_stride();
+	num_gpcs = g->ops.gr.ctxsw_prog.get_num_gpcs(context);
+
+	/*
+	 * Check in extended buffer segment of ctxsw buffer. If found, return
+	 * else continue on.
+	 */
+	err = gr_gk20a_find_priv_offset_in_ext_buffer(g,
+				      addr, context_buffer,
+				      context_buffer_size, priv_offset);
+	if (err == 0) {
+		nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg,
+			"offset found in Ext buffer");
+		return err;
+	}
+
+	/* Parse the FECS local header. */
+	context += (main_hdr_size >> 2);
+	if (!g->ops.gr.ctxsw_prog.check_local_header_magic(context)) {
+		nvgpu_err(g,
+			   "Invalid FECS local header: magic value");
+		return -EINVAL;
+	}
+
+	if ((addr_type == CTXSW_ADDR_TYPE_SYS) ||
+		(addr_type == CTXSW_ADDR_TYPE_ROP)) {
+		compute_segoffset =
+			g->ops.gr.ctxsw_prog.get_compute_sysreglist_offset(context);
+		graphics_segoffset =
+			g->ops.gr.ctxsw_prog.get_gfx_sysreglist_offset(context);
+		nvgpu_log(g, gpu_dbg_gpu_dbg, "sys_segment_offsets(0x%x, 0x%x)",
+			compute_segoffset, graphics_segoffset);
+
+		err = g->ops.gr.process_context_buffer_priv_segment(g, addr_type,
+				addr, 0, 0, 0, 0, &offset);
+		if (err < 0) {
+			return err;
+		}
+		segoffset = (err == FOUND_IN_CTXSWBUF_PRIV_COMPUTE_REGLIST) ?
+			compute_segoffset : graphics_segoffset;
+		*priv_offset = (segoffset + offset);
+		return 0;
+
+	} else if (addr_type == CTXSW_ADDR_TYPE_LTS_MAIN) {
+		segoffset = g->ops.gr.ctxsw_prog.get_ltsreglist_offset(context);
+		nvgpu_log(g, gpu_dbg_gpu_dbg, "lts_segment_offset(0x%x)",
+				segoffset);
+
+		err = g->ops.gr.process_context_buffer_priv_segment(g, addr_type,
+				addr, 0, 0, 0, 0, &offset);
+		if (err < 0) {
+			return err;
+		}
+		*priv_offset = (segoffset + offset);
+		return 0;
+	}
+
+	if ((gpc_num + 1U) > num_gpcs)  {
+		nvgpu_err(g,
+			   "GPC %d not in this context buffer.",
+			   gpc_num);
+		return -EINVAL;
+	}
+
+	/*
+	 * Skip ahead to the relevant gpccs segment.
+	 */
+	context += (fecs_hdr_size >> BYTE_TO_DW_SHIFT) +
+		((gpc_num * gpccs_hdr_stride) >> BYTE_TO_DW_SHIFT);
+	if (!g->ops.gr.ctxsw_prog.check_local_header_magic(context)) {
+		nvgpu_err(g,
+			   "Invalid GPCCS header: magic value");
+		return -EINVAL;
+	}
+
+	num_tpcs = g->ops.gr.ctxsw_prog.get_num_tpcs(context);
+	if ((tpc_num + 1U) > num_tpcs) {
+		nvgpu_err(g, "GPC %d TPC %d not in this context buffer.",
+				gpc_num, tpc_num);
+		return -EINVAL;
+	}
+
+	err = gr_gk20a_determine_ppc_configuration(g, context, &num_ppcs,
+			&ppc_mask, &reg_list_ppc_count);
+	if (err != 0) {
+		nvgpu_err(g, "determine ppc configuration failed");
+		return err;
+	}
+
+	if (addr_type == CTXSW_ADDR_TYPE_GPC) {
+		compute_segoffset =
+			g->ops.gr.ctxsw_prog.get_compute_gpcreglist_offset(context);
+		graphics_segoffset =
+			g->ops.gr.ctxsw_prog.get_gfx_gpcreglist_offset(context);
+	} else if (addr_type == CTXSW_ADDR_TYPE_PPC) {
+		compute_segoffset =
+			g->ops.gr.ctxsw_prog.get_compute_ppcreglist_offset(context);
+		graphics_segoffset =
+			g->ops.gr.ctxsw_prog.get_gfx_ppcreglist_offset(context);
+	} else if (addr_type == CTXSW_ADDR_TYPE_TPC) {
+		compute_segoffset =
+			g->ops.gr.ctxsw_prog.get_compute_tpcreglist_offset(context, tpc_num);
+		graphics_segoffset =
+			g->ops.gr.ctxsw_prog.get_gfx_tpcreglist_offset(context, tpc_num);
+	} else if (addr_type == CTXSW_ADDR_TYPE_ETPC) {
+		compute_segoffset =
+			g->ops.gr.ctxsw_prog.get_compute_etpcreglist_offset(context);
+		graphics_segoffset =
+			g->ops.gr.ctxsw_prog.get_gfx_etpcreglist_offset(context);
+	} else {
+		nvgpu_err(g, "invalid addr_type(0x%x)", addr_type);
+		return -EINVAL;
+	}
+	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg,
+		"gpccs_segment_offset(0x%x, 0x%x)", compute_segoffset,
+		graphics_segoffset);
+
+	err = g->ops.gr.process_context_buffer_priv_segment(g, addr_type,
+			addr, gpc_num, num_tpcs, num_ppcs, ppc_mask, &offset);
+	if (err < 0) {
+		return err;
+	}
+
+	segoffset = (err == FOUND_IN_CTXSWBUF_PRIV_COMPUTE_REGLIST) ? compute_segoffset :
+		graphics_segoffset;
+	*priv_offset = (segoffset + offset);
+	return 0;
+}
+
+static const u32 hwpm_cau_init_data[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x00419980,
+	0x00000000,
+	0x00419988,
+	0x00000000,
+	0x0041998c,
+	0x00000000,
+	0x00419990,
+	0x00000000,
+	0x00419994,
+	0x00000000,
+	0x00419998,
+	0x00000000,
+	0x0041999c,
+	0x00000000,
+	0x004199a4,
+	0x00000001,
+};
+
+const u32 *ga10b_gr_get_hwpm_cau_init_data(u32 *count)
+{
+	*count = sizeof(hwpm_cau_init_data) / sizeof(hwpm_cau_init_data[0]);
+	return hwpm_cau_init_data;
+}
+
+#endif /* CONFIG_NVGPU_DEBUGGER */
+
+void ga10b_gr_vab_init(struct gk20a *g, u32 vab_reg)
+{
+	nvgpu_writel(g, gr_gpcs_mmu_vidmem_access_bit_r(), vab_reg);
+}
+
+void ga10b_gr_vab_release(struct gk20a *g, u32 vab_reg)
+{
+	nvgpu_writel(g, gr_gpcs_mmu_vidmem_access_bit_r(), vab_reg);
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.h
new file mode 100644
index 000000000..bac209ba2
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.h
@@ -0,0 +1,67 @@
+/*
+ * GA10B GPU GR
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_GA10B_H
+#define NVGPU_GR_GA10B_H
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+#define FOUND_IN_CTXSWBUF_PRIV_REGLIST		(0)
+#define FOUND_IN_CTXSWBUF_PRIV_COMPUTE_REGLIST	(1)
+#define FOUND_IN_CTXSWBUF_PRIV_GFX_REGLIST	(2)
+#endif /* CONFIG_NVGPU_DEBUGGER */
+
+struct gk20a;
+struct nvgpu_debug_context;
+enum ctxsw_addr_type;
+
+int gr_ga10b_dump_gr_status_regs(struct gk20a *g,
+				 struct nvgpu_debug_context *o);
+void gr_ga10b_set_circular_buffer_size(struct gk20a *g, u32 data);
+void ga10b_gr_set_gpcs_rops_crop_debug4(struct gk20a *g, u32 data);
+void ga10b_gr_vab_init(struct gk20a *g, u32 vab_reg);
+void ga10b_gr_vab_release(struct gk20a *g, u32 vab_reg);
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+int gr_ga10b_create_priv_addr_table(struct gk20a *g,
+					   u32 addr,
+					   u32 *priv_addr_table,
+					   u32 *num_registers);
+int gr_ga10b_decode_priv_addr(struct gk20a *g, u32 addr,
+	enum ctxsw_addr_type *addr_type,
+	u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
+	u32 *broadcast_flags);
+int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g,
+					     enum ctxsw_addr_type addr_type,
+					     u32 pri_addr,
+					     u32 gpc_num, u32 num_tpcs,
+					     u32 num_ppcs, u32 ppc_mask,
+					     u32 *priv_offset);
+bool ga10b_gr_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error);
+int gr_ga10b_find_priv_offset_in_buffer(struct gk20a *g, u32 addr,
+					u32 *context_buffer,
+					u32 context_buffer_size,
+					u32 *priv_offset);
+const u32 *ga10b_gr_get_hwpm_cau_init_data(u32 *count);
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#endif /* NVGPU_GR_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_pri_ga10b.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_pri_ga10b.h
new file mode 100644
index 000000000..a2959c1c0
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_pri_ga10b.h
@@ -0,0 +1,64 @@
+/*
+ * GA10B Graphics Context Pri Register Addressing
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef GR_PRI_GA10B_H
+#define GR_PRI_GA10B_H
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+
+#include <nvgpu/static_analysis.h>
+
+static inline u32 pri_rop_in_gpc_shared_addr(struct gk20a *g, u32 addr)
+{
+	u32 gpc_addr = pri_gpccs_addr_mask(g, addr);
+	u32 gpc_shared_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_SHARED_BASE);
+	u32 rop_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_IN_GPC_BASE);
+	u32 rop_shared_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_IN_GPC_SHARED_BASE);
+	u32 rop_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_IN_GPC_STRIDE);
+
+	return nvgpu_safe_add_u32(
+			nvgpu_safe_add_u32(gpc_shared_base, rop_shared_base),
+			nvgpu_safe_sub_u32(gpc_addr, rop_base) % rop_stride);
+}
+
+static inline bool pri_is_rop_in_gpc_addr_shared(struct gk20a *g, u32 addr)
+{
+	u32 rop_shared_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_IN_GPC_SHARED_BASE);
+	u32 rop_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_IN_GPC_STRIDE);
+
+	return (addr >= rop_shared_base) &&
+		(addr < nvgpu_safe_add_u32(rop_shared_base, rop_stride));
+}
+
+static inline bool pri_is_rop_in_gpc_addr(struct gk20a *g, u32 addr)
+{
+	u32 rop_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_IN_GPC_BASE);
+	u32 rop_shared_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_IN_GPC_SHARED_BASE);
+	u32 rop_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_IN_GPC_STRIDE);
+
+	return (addr >= rop_base) &&
+		(addr < nvgpu_safe_add_u32(rop_shared_base, rop_stride));
+}
+
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#endif /* GR_PRI_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.c
new file mode 100644
index 000000000..e5108e194
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/static_analysis.h>
+
+#include "gr_init_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_gr_ga100.h>
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+u32 ga100_gr_init_get_attrib_cb_gfxp_default_size(struct gk20a *g)
+{
+	return gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
+}
+
+u32 ga100_gr_init_get_attrib_cb_gfxp_size(struct gk20a *g)
+{
+	return gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
+}
+
+u32 ga100_gr_init_get_ctx_spill_size(struct gk20a *g)
+{
+	return  nvgpu_safe_mult_u32(
+		  gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(),
+		  gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v());
+}
+
+u32 ga100_gr_init_get_ctx_betacb_size(struct gk20a *g)
+{
+	return nvgpu_safe_add_u32(
+		g->ops.gr.init.get_attrib_cb_default_size(g),
+		nvgpu_safe_sub_u32(
+			gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(),
+			gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()));
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.h
new file mode 100644
index 000000000..b9f0608fe
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_INIT_GA100_H
+#define NVGPU_GR_INIT_GA100_H
+
+#include <nvgpu/types.h>
+
+#define FECS_CTXSW_RESET_DELAY_US 10U
+
+struct gk20a;
+struct nvgpu_gr_ctx;
+
+void ga100_gr_init_override_context_reset(struct gk20a *g);
+u32 ga100_gr_init_get_min_gpm_fifo_depth(struct gk20a *g);
+u32 ga100_gr_init_get_bundle_cb_token_limit(struct gk20a *g);
+u32 ga100_gr_init_get_attrib_cb_default_size(struct gk20a *g);
+void ga100_gr_init_commit_global_bundle_cb(struct gk20a *g,
+	struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch);
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+u32 ga100_gr_init_get_attrib_cb_gfxp_default_size(struct gk20a *g);
+u32 ga100_gr_init_get_attrib_cb_gfxp_size(struct gk20a *g);
+u32 ga100_gr_init_get_ctx_spill_size(struct gk20a *g);
+u32 ga100_gr_init_get_ctx_betacb_size(struct gk20a *g);
+#endif
+
+#endif /* NVGPU_GR_INIT_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100_fusa.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100_fusa.c
new file mode 100644
index 000000000..31113a731
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100_fusa.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/log.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/static_analysis.h>
+#include <nvgpu/gr/ctx.h>
+
+#include "nvgpu/gr/config.h"
+#include "nvgpu/gr/gr_utils.h"
+
+#include "hal/gr/init/gr_init_gv11b.h"
+#include "gr_init_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_gr_ga100.h>
+
+u32 ga100_gr_init_get_min_gpm_fifo_depth(struct gk20a *g)
+{
+	return gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v();
+}
+
+u32 ga100_gr_init_get_bundle_cb_token_limit(struct gk20a *g)
+{
+	return gr_pd_ab_dist_cfg2_token_limit_init_v();
+}
+
+u32 ga100_gr_init_get_attrib_cb_default_size(struct gk20a *g)
+{
+	return gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v();
+}
+
+void ga100_gr_init_commit_global_bundle_cb(struct gk20a *g,
+	struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch)
+{
+	u32 data;
+	u32 cb_addr;
+	u32 bundle_cb_token_limit = g->ops.gr.init.get_bundle_cb_token_limit(g);
+
+	addr = addr >> gr_scc_bundle_cb_base_addr_39_8_align_bits_v();
+
+	nvgpu_log_info(g, "bundle cb addr : 0x%016llx, size : %u",
+		addr, size);
+
+	cb_addr = nvgpu_safe_cast_u64_to_u32(addr);
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_bundle_cb_base_r(),
+		gr_scc_bundle_cb_base_addr_39_8_f(cb_addr), patch);
+
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_bundle_cb_size_r(),
+		gr_scc_bundle_cb_size_div_256b_f(size) |
+		gr_scc_bundle_cb_size_valid_true_f(), patch);
+
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_swdx_bundle_cb_base_r(),
+		gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(cb_addr), patch);
+
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_swdx_bundle_cb_size_r(),
+		gr_gpcs_swdx_bundle_cb_size_div_256b_f(size) |
+		gr_gpcs_swdx_bundle_cb_size_valid_true_f(), patch);
+
+	/* data for state_limit */
+	data = nvgpu_safe_mult_u32(
+			g->ops.gr.init.get_bundle_cb_default_size(g),
+			gr_scc_bundle_cb_size_div_256b_byte_granularity_v()) /
+		gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v();
+
+	data = min_t(u32, data, g->ops.gr.init.get_min_gpm_fifo_depth(g));
+
+	nvgpu_log_info(g, "bundle cb token limit : %d, state limit : %d",
+		bundle_cb_token_limit, data);
+
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_pd_ab_dist_cfg2_r(),
+		gr_pd_ab_dist_cfg2_token_limit_f(bundle_cb_token_limit) |
+		gr_pd_ab_dist_cfg2_state_limit_f(data), patch);
+}
+
+void ga100_gr_init_override_context_reset(struct gk20a *g)
+{
+	nvgpu_writel(g, gr_fecs_ctxsw_reset_ctl_r(),
+			gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() |
+			gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() |
+			gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f());
+
+	nvgpu_writel(g, gr_gpccs_ctxsw_reset_ctl_r(),
+			gr_gpccs_ctxsw_reset_ctl_gpc_halt_disabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_gpc_reset_disabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_zcull_reset_enabled_f());
+
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		nvgpu_writel(g, gr_bes_becs_ctxsw_be_reset_ctl_r(),
+				gr_bes_becs_ctxsw_be_reset_ctl_be_halt_disabled_f() |
+				gr_bes_becs_ctxsw_be_reset_ctl_be_engine_reset_disabled_f() |
+				gr_bes_becs_ctxsw_be_reset_ctl_be_context_reset_enabled_f());
+	}
+
+	nvgpu_udelay(FECS_CTXSW_RESET_DELAY_US);
+	(void) nvgpu_readl(g, gr_fecs_ctxsw_reset_ctl_r());
+	(void) nvgpu_readl(g, gr_gpccs_ctxsw_reset_ctl_r());
+
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		(void) nvgpu_readl(g, gr_bes_becs_ctxsw_be_reset_ctl_r());
+	}
+
+	/* Deassert reset */
+	nvgpu_writel(g, gr_fecs_ctxsw_reset_ctl_r(),
+			gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() |
+			gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() |
+			gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f());
+
+	nvgpu_writel(g, gr_gpccs_ctxsw_reset_ctl_r(),
+			gr_gpccs_ctxsw_reset_ctl_gpc_halt_disabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_gpc_reset_disabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_zcull_reset_disabled_f());
+
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		nvgpu_writel(g, gr_bes_becs_ctxsw_be_reset_ctl_r(),
+				gr_bes_becs_ctxsw_be_reset_ctl_be_halt_disabled_f() |
+				gr_bes_becs_ctxsw_be_reset_ctl_be_engine_reset_disabled_f() |
+				gr_bes_becs_ctxsw_be_reset_ctl_be_context_reset_disabled_f());
+	}
+
+	nvgpu_udelay(FECS_CTXSW_RESET_DELAY_US);
+	(void) nvgpu_readl(g, gr_fecs_ctxsw_reset_ctl_r());
+	(void) nvgpu_readl(g, gr_gpccs_ctxsw_reset_ctl_r());
+
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		(void) nvgpu_readl(g, gr_bes_becs_ctxsw_be_reset_ctl_r());
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c
new file mode 100644
index 000000000..1758721fb
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/log.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/static_analysis.h>
+
+#include "gr_init_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_gr_ga10b.h>
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+u32 ga10b_gr_init_get_attrib_cb_gfxp_default_size(struct gk20a *g)
+{
+	return gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
+}
+
+u32 ga10b_gr_init_get_attrib_cb_gfxp_size(struct gk20a *g)
+{
+	return gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
+}
+
+u32 ga10b_gr_init_get_ctx_spill_size(struct gk20a *g)
+{
+	return  nvgpu_safe_mult_u32(
+		  gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(),
+		  gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v());
+}
+
+u32 ga10b_gr_init_get_ctx_betacb_size(struct gk20a *g)
+{
+	return nvgpu_safe_add_u32(
+		g->ops.gr.init.get_attrib_cb_default_size(g),
+		nvgpu_safe_sub_u32(
+			gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(),
+			gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()));
+}
+
+#endif
+
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
+void ga10b_gr_init_get_access_map(struct gk20a *g,
+				   u32 **whitelist, u32 *num_entries)
+{
+	static u32 wl_addr_ga10b[] = {
+		/* this list must be sorted (low to high) */
+		0x418380, /* gr_pri_gpcs_rasterarb_line_class  */
+		0x418800, /* gr_pri_gpcs_setup_debug           */
+		0x418830, /* gr_pri_gpcs_setup_debug_z_gamut_offset */
+		0x4188fc, /* gr_pri_gpcs_zcull_ctx_debug       */
+		0x418e00, /* gr_pri_gpcs_swdx_config           */
+		0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+		0x418e44, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+		0x418e48, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+		0x418e4c, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+		0x418e50, /* gr_pri_gpcs_swdx_tc_bundle_laztval_ctrl	*/
+		0x418e58, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e5c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e60, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e64, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e68, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e6c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e70, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e74, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e78, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e7c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e80, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e84, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e88, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e8c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e90, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x418e94, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+		0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */
+		0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg      */
+		0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg     */
+		0x419e84, /* gr_pri_gpcs_tpcs_sms_dbgr_control0 */
+		0x419ba4, /* gr_pri_gpcs_tpcs_sm_disp_ctrl     */
+	};
+	size_t array_size;
+
+	*whitelist = wl_addr_ga10b;
+	array_size = ARRAY_SIZE(wl_addr_ga10b);
+	*num_entries = nvgpu_safe_cast_u64_to_u32(array_size);
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h
new file mode 100644
index 000000000..5f2f439e0
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_INIT_GA10B_H
+#define NVGPU_GR_INIT_GA10B_H
+
+#include <nvgpu/types.h>
+
+#define FECS_CTXSW_RESET_DELAY_US 10U
+
+struct gk20a;
+struct nvgpu_gr_ctx;
+struct nvgpu_gr_config;
+
+void ga10b_gr_init_override_context_reset(struct gk20a *g);
+void ga10b_gr_init_fe_go_idle_timeout(struct gk20a *g, bool enable);
+void ga10b_gr_init_auto_go_idle(struct gk20a *g, bool enable);
+void ga10b_gr_init_gpc_mmu(struct gk20a *g);
+void ga10b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid,
+				struct nvgpu_gr_config *gr_config,
+				struct nvgpu_gr_ctx *gr_ctx,
+				bool patch);
+
+void ga10b_gr_init_commit_global_bundle_cb(struct gk20a *g,
+	struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch);
+
+u32 ga10b_gr_init_get_min_gpm_fifo_depth(struct gk20a *g);
+u32 ga10b_gr_init_get_bundle_cb_token_limit(struct gk20a *g);
+u32 ga10b_gr_init_get_attrib_cb_default_size(struct gk20a *g);
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+
+u32 ga10b_gr_init_get_attrib_cb_gfxp_default_size(struct gk20a *g);
+u32 ga10b_gr_init_get_attrib_cb_gfxp_size(struct gk20a *g);
+
+u32 ga10b_gr_init_get_ctx_spill_size(struct gk20a *g);
+u32 ga10b_gr_init_get_ctx_betacb_size(struct gk20a *g);
+
+#endif /* CONFIG_NVGPU_GRAPHICS */
+
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
+void ga10b_gr_init_get_access_map(struct gk20a *g,
+					u32 **whitelist, u32 *num_entries);
+#endif
+
+void ga10b_gr_init_fs_state(struct gk20a *g);
+void ga10b_gr_init_commit_global_timeslice(struct gk20a *g);
+
+int ga10b_gr_init_wait_idle(struct gk20a *g);
+void ga10b_gr_init_eng_config(struct gk20a *g);
+int ga10b_gr_init_reset_gpcs(struct gk20a *g);
+int ga10b_gr_init_wait_empty(struct gk20a *g);
+
+#endif /* NVGPU_GR_INIT_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b_fusa.c
new file mode 100644
index 000000000..1d614b9ae
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b_fusa.c
@@ -0,0 +1,518 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/log.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/static_analysis.h>
+#include <nvgpu/gr/ctx.h>
+#include <nvgpu/gr/gr_instances.h>
+#include <nvgpu/grmgr.h>
+
+#include "nvgpu/gr/config.h"
+#include "nvgpu/gr/gr_utils.h"
+
+#include "hal/gr/init/gr_init_gv11b.h"
+#include "gr_init_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_gr_ga10b.h>
+
+#define NVGPU_GR_GPCS_RESET_DELAY_US		20U
+
+
+void ga10b_gr_init_override_context_reset(struct gk20a *g)
+{
+	nvgpu_writel(g, gr_fecs_ctxsw_reset_ctl_r(),
+			gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() |
+			gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() |
+			gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f());
+
+	nvgpu_writel(g, gr_gpccs_ctxsw_reset_ctl_r(),
+			gr_gpccs_ctxsw_reset_ctl_gpc_halt_disabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_gpc_reset_disabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_zcull_reset_enabled_f());
+
+	nvgpu_udelay(FECS_CTXSW_RESET_DELAY_US);
+	(void) nvgpu_readl(g, gr_fecs_ctxsw_reset_ctl_r());
+	(void) nvgpu_readl(g, gr_gpccs_ctxsw_reset_ctl_r());
+
+	/* Deassert reset */
+	nvgpu_writel(g, gr_fecs_ctxsw_reset_ctl_r(),
+			gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() |
+			gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() |
+			gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f());
+
+	nvgpu_writel(g, gr_gpccs_ctxsw_reset_ctl_r(),
+			gr_gpccs_ctxsw_reset_ctl_gpc_halt_disabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_gpc_reset_disabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() |
+			gr_gpccs_ctxsw_reset_ctl_zcull_reset_disabled_f());
+
+	nvgpu_udelay(FECS_CTXSW_RESET_DELAY_US);
+	(void) nvgpu_readl(g, gr_fecs_ctxsw_reset_ctl_r());
+	(void) nvgpu_readl(g, gr_gpccs_ctxsw_reset_ctl_r());
+}
+
+void ga10b_gr_init_fe_go_idle_timeout(struct gk20a *g, bool enable)
+{
+	if (enable) {
+#ifdef CONFIG_NVGPU_GRAPHICS
+		nvgpu_writel(g, gr_fe_go_idle_timeout_r(),
+			gr_fe_go_idle_timeout_count_prod_f());
+#endif
+		nvgpu_writel(g, gr_fe_compute_go_idle_timeout_r(),
+			gr_fe_compute_go_idle_timeout_count_init_f());
+	} else {
+#ifdef CONFIG_NVGPU_GRAPHICS
+		nvgpu_writel(g, gr_fe_go_idle_timeout_r(),
+			gr_fe_go_idle_timeout_count_disabled_f());
+#endif
+		nvgpu_writel(g, gr_fe_compute_go_idle_timeout_r(),
+			gr_fe_compute_go_idle_timeout_count_disabled_f());
+	}
+}
+
+void ga10b_gr_init_auto_go_idle(struct gk20a *g, bool enable)
+{
+	u32 data = 0U;
+
+	data =  nvgpu_readl(g, gr_debug_2_r());
+	if (enable) {
+#ifdef CONFIG_NVGPU_GRAPHICS
+		data = set_field(data,
+				gr_debug_2_graphics_auto_go_idle_m(),
+				gr_debug_2_graphics_auto_go_idle_enabled_f());
+#endif
+		data = set_field(data,
+				gr_debug_2_compute_auto_go_idle_m(),
+				gr_debug_2_compute_auto_go_idle_enabled_f());
+	} else {
+#ifdef CONFIG_NVGPU_GRAPHICS
+		data = set_field(data,
+				gr_debug_2_graphics_auto_go_idle_m(),
+				gr_debug_2_graphics_auto_go_idle_disabled_f());
+#endif
+		data = set_field(data,
+				gr_debug_2_compute_auto_go_idle_m(),
+				gr_debug_2_compute_auto_go_idle_disabled_f());
+	}
+
+	nvgpu_writel(g, gr_debug_2_r(), data);
+}
+
+void ga10b_gr_init_gpc_mmu(struct gk20a *g)
+{
+	u32 temp;
+
+	nvgpu_log_info(g, "initialize gpc mmu");
+
+	temp = g->ops.fb.mmu_ctrl(g);
+	temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
+		gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
+		gr_gpcs_pri_mmu_ctrl_comp_fault_m() |
+		gr_gpcs_pri_mmu_ctrl_miss_gran_m() |
+		gr_gpcs_pri_mmu_ctrl_cache_mode_m() |
+		gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m()|
+		gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m();
+	nvgpu_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp);
+	nvgpu_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0);
+	nvgpu_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
+
+	nvgpu_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(),
+			g->ops.fb.mmu_debug_ctrl(g));
+	nvgpu_writel(g, gr_gpcs_pri_mmu_debug_wr_r(),
+			g->ops.fb.mmu_debug_wr(g));
+	nvgpu_writel(g, gr_gpcs_pri_mmu_debug_rd_r(),
+			g->ops.fb.mmu_debug_rd(g));
+	nvgpu_writel(g, gr_gpcs_mmu_num_active_ltcs_r(),
+				g->ops.fb.get_num_active_ltcs(g));
+}
+
+void ga10b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid,
+				struct nvgpu_gr_config *gr_config,
+				struct nvgpu_gr_ctx *gr_ctx,
+				bool patch)
+{
+	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g,
+					GPU_LIT_TPC_IN_GPC_STRIDE);
+	u32 gpc_offset = nvgpu_safe_mult_u32(gpc_stride, gpc);
+	u32 global_tpc_index;
+	u32 tpc_offset;
+	u32 offset_sum = 0U;
+	struct nvgpu_sm_info *sm_info;
+
+	nvgpu_log(g, gpu_dbg_gr, "SM id %u ", smid);
+
+#ifdef CONFIG_NVGPU_SM_DIVERSITY
+	sm_info = (((gr_ctx == NULL) ||
+		(nvgpu_gr_ctx_get_sm_diversity_config(gr_ctx) ==
+		NVGPU_DEFAULT_SM_DIVERSITY_CONFIG)) ?
+			nvgpu_gr_config_get_sm_info(gr_config, smid) :
+			nvgpu_gr_config_get_redex_sm_info(gr_config, smid));
+#else
+		sm_info = nvgpu_gr_config_get_sm_info(gr_config, smid);
+#endif
+	global_tpc_index =
+		nvgpu_gr_config_get_sm_info_global_tpc_index(sm_info);
+
+	tpc = g->ops.gr.init.get_nonpes_aware_tpc(g, gpc, tpc, gr_config);
+	tpc_offset = nvgpu_safe_mult_u32(tpc_in_gpc_stride, tpc);
+
+	offset_sum = nvgpu_safe_add_u32(gpc_offset, tpc_offset);
+
+	nvgpu_gr_ctx_patch_write(g, gr_ctx,
+			nvgpu_safe_add_u32(gr_gpc0_tpc0_sm_cfg_r(), offset_sum),
+			gr_gpc0_tpc0_sm_cfg_tpc_id_f(global_tpc_index),
+			patch);
+	nvgpu_gr_ctx_patch_write(g, gr_ctx,
+			nvgpu_safe_add_u32(
+				gr_gpc0_gpm_pd_sm_id_r(tpc), gpc_offset),
+			gr_gpc0_gpm_pd_sm_id_id_f(global_tpc_index),
+			patch);
+}
+
+void ga10b_gr_init_commit_global_bundle_cb(struct gk20a *g,
+	struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch)
+{
+	u32 data;
+	u32 cb_addr;
+	u32 bundle_cb_token_limit = g->ops.gr.init.get_bundle_cb_token_limit(g);
+
+	addr = addr >> gr_scc_bundle_cb_base_addr_39_8_align_bits_v();
+
+	nvgpu_log_info(g, "bundle cb addr : 0x%016llx, size : %u",
+		addr, size);
+
+	cb_addr = nvgpu_safe_cast_u64_to_u32(addr);
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_bundle_cb_base_r(),
+		gr_scc_bundle_cb_base_addr_39_8_f(cb_addr), patch);
+
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_bundle_cb_size_r(),
+		gr_scc_bundle_cb_size_div_256b_f(size) |
+		gr_scc_bundle_cb_size_valid_true_f(), patch);
+
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_swdx_bundle_cb_base_r(),
+		gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(cb_addr), patch);
+
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_swdx_bundle_cb_size_r(),
+		gr_gpcs_swdx_bundle_cb_size_div_256b_f(size) |
+		gr_gpcs_swdx_bundle_cb_size_valid_true_f(), patch);
+
+	/* data for state_limit */
+	data = nvgpu_safe_mult_u32(
+			g->ops.gr.init.get_bundle_cb_default_size(g),
+			gr_scc_bundle_cb_size_div_256b_byte_granularity_v()) /
+		gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v();
+
+	data = min_t(u32, data, g->ops.gr.init.get_min_gpm_fifo_depth(g));
+
+	nvgpu_log_info(g, "bundle cb token limit : %d, state limit : %d",
+		bundle_cb_token_limit, data);
+
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_pd_ab_dist_cfg2_r(),
+		gr_pd_ab_dist_cfg2_token_limit_f(bundle_cb_token_limit) |
+		gr_pd_ab_dist_cfg2_state_limit_f(data), patch);
+}
+
+u32 ga10b_gr_init_get_min_gpm_fifo_depth(struct gk20a *g)
+{
+	return gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v();
+}
+
+u32 ga10b_gr_init_get_bundle_cb_token_limit(struct gk20a *g)
+{
+	return gr_pd_ab_dist_cfg2_token_limit_init_v();
+}
+
+u32 ga10b_gr_init_get_attrib_cb_default_size(struct gk20a *g)
+{
+	return gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v();
+}
+
+void ga10b_gr_init_fs_state(struct gk20a *g)
+{
+	u32 data;
+#ifdef CONFIG_NVGPU_NON_FUSA
+	u32 ecc_val;
+#endif
+	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
+
+	data = nvgpu_readl(g, gr_gpcs_tpcs_sm_texio_control_r());
+	data = set_field(data,
+		gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(),
+		gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f());
+	nvgpu_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data);
+
+	data = nvgpu_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r());
+	data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(),
+			 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f());
+	nvgpu_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data);
+
+#ifdef CONFIG_NVGPU_NON_FUSA
+	ecc_val = nvgpu_gr_get_override_ecc_val(g);
+	if (ecc_val != 0U) {
+		g->ops.fuse.write_feature_override_ecc(g, ecc_val);
+	}
+#endif
+
+	data = nvgpu_readl(g, gr_debug_0_r());
+	data = set_field(data,
+		gr_debug_0_scg_force_slow_drain_tpc_m(),
+		gr_debug_0_scg_force_slow_drain_tpc_enabled_f());
+	nvgpu_writel(g, gr_debug_0_r(), data);
+
+	/*
+	 * Disable CTA_SUBPARTITION_SKEW to avoid
+	 * load imbalance across subpartitions.
+	 * Refer nvbug 200593339
+	 */
+	data = nvgpu_readl(g, gr_gpcs_tpcs_mpc_pix_debug_r());
+	data = set_field(data,
+		gr_gpcs_tpcs_mpc_pix_debug_cta_subpartition_skew_m(),
+		gr_gpcs_tpcs_mpc_pix_debug_cta_subpartition_skew_disable_f());
+	nvgpu_writel(g, gr_gpcs_tpcs_mpc_pix_debug_r(), data);
+
+}
+
+void ga10b_gr_init_commit_global_timeslice(struct gk20a *g)
+{
+	u32 pd_ab_dist_cfg0 = 0U;
+	u32 pe_vaf;
+	u32 pe_vsc_vpc;
+
+	nvgpu_log_fn(g, " ");
+
+	pe_vaf = nvgpu_readl(g, gr_gpcs_tpcs_pe_vaf_r());
+	pe_vsc_vpc = nvgpu_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r());
+
+	pe_vaf = gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() | pe_vaf;
+	pe_vsc_vpc = gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() |
+		     pe_vsc_vpc;
+
+	nvgpu_gr_ctx_patch_write(g, NULL, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf,
+		false);
+	nvgpu_gr_ctx_patch_write(g, NULL, gr_gpcs_tpcs_pes_vsc_vpc_r(),
+		pe_vsc_vpc, false);
+
+	pd_ab_dist_cfg0 = nvgpu_readl(g, gr_pd_ab_dist_cfg0_r());
+	pd_ab_dist_cfg0 = pd_ab_dist_cfg0 |
+		gr_pd_ab_dist_cfg0_timeslice_enable_en_f();
+	nvgpu_gr_ctx_patch_write(g, NULL, gr_pd_ab_dist_cfg0_r(),
+		pd_ab_dist_cfg0, false);
+}
+
+int ga10b_gr_init_wait_idle(struct gk20a *g)
+{
+	u32 delay = POLL_DELAY_MIN_US;
+	int err = 0;
+	bool gr_busy;
+	struct nvgpu_timeout timeout;
+
+	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
+
+	err = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
+                                 NVGPU_TIMER_CPU_TIMER);
+	if (err != 0) {
+                return err;
+	}
+
+	do {
+		/*
+		 * TODO legacy code has checks for invalid ctx.
+		 * It is guaranteed that graphics is not doing any work if
+		 * the ctx status is invalid. In that case, the busy/idle
+		 * is not valid and can sometimes report busy even when it
+		 * is not. We will detect that case and return early without
+		 * looking at the idle status of the engine. For more details,
+		 * see bugs 1762495, 200364484, 1972403.
+		 */
+
+		gr_busy = (nvgpu_readl(g, gr_status_r()) &
+				gr_status_state_busy_v()) != 0U;
+
+		if (!gr_busy) {
+			nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, "done");
+			return 0;
+		}
+
+		nvgpu_usleep_range(delay, nvgpu_safe_mult_u32(delay, 2U));
+		delay = min_t(u32, delay << 1, POLL_DELAY_MAX_US);
+	} while (nvgpu_timeout_expired(&timeout) == 0);
+
+        nvgpu_err(g, "timeout gr busy : %x", gr_busy);
+
+	return -EAGAIN;
+}
+
+void ga10b_gr_init_eng_config(struct gk20a *g)
+{
+	u32 data = 0U;
+
+	data |= gr_engine_config_supported_compute_true_f();
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		data |= gr_engine_config_supported_i2m_true_f();
+#ifdef CONFIG_NVGPU_GRAPHICS
+		data |= gr_engine_config_supported_2d_true_f();
+		data |= gr_engine_config_supported_3d_true_f();
+#endif
+	}
+	nvgpu_writel(g, gr_engine_config_r(), data);
+}
+
+static void ga10b_gr_init_gpcs_enable(struct gk20a *g, bool enable)
+{
+	u32 reg_val;
+
+	if (enable) {
+		reg_val = gr_gpcs_gpccs_engine_reset_ctl_gpc_engine_reset_enabled_f();
+	} else {
+		reg_val = gr_gpcs_gpccs_engine_reset_ctl_gpc_engine_reset_disabled_f();
+	}
+	nvgpu_writel(g, gr_gpcs_gpccs_engine_reset_ctl_r(), reg_val);
+	/* Read same register back to ensure hw propagation of write */
+	reg_val = nvgpu_readl(g, gr_gpcs_gpccs_engine_reset_ctl_r());
+}
+
+static bool ga10b_gr_init_is_gpcs_enabled(struct gk20a *g)
+{
+	u32 gpc, gpc_offset;
+	u32 enabled_gpcs = 0U;
+	u32 reg_offset;
+	u32 reg_val;
+	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+	u32 cur_gr_instance_id = nvgpu_gr_get_cur_instance_id(g);
+	u32 gpc_count = nvgpu_grmgr_get_gr_num_gpcs(g, cur_gr_instance_id);
+
+	for (gpc = 0U; gpc < gpc_count; gpc++) {
+		gpc_offset = nvgpu_safe_mult_u32(gpc_stride, gpc);
+		reg_offset = nvgpu_safe_add_u32(gpc_offset,
+				gr_gpc0_gpccs_engine_reset_ctl_r());
+		reg_val = nvgpu_readl(g, reg_offset);
+		if (gr_gpc0_gpccs_engine_reset_ctl_gpc_engine_reset_v(reg_val)
+			== gr_gpc0_gpccs_engine_reset_ctl_gpc_engine_reset_disabled_v()) {
+			enabled_gpcs++;
+		}
+	}
+	if (enabled_gpcs == gpc_count) {
+		return true;
+	} else {
+		nvgpu_log_info(g, "total gpc_count %d enabled gpcs %d",
+				gpc_count, enabled_gpcs);
+		return false;
+	}
+}
+
+int ga10b_gr_init_reset_gpcs(struct gk20a *g)
+{
+	int err = 0;
+
+	nvgpu_log(g, gpu_dbg_gr, " ");
+
+	ga10b_gr_init_gpcs_enable(g, true);
+	nvgpu_udelay(NVGPU_GR_GPCS_RESET_DELAY_US);
+	ga10b_gr_init_gpcs_enable(g, false);
+
+	/* After issuing gpcs reset, check if gpcs are enabled */
+	if (!ga10b_gr_init_is_gpcs_enabled(g)) {
+		err = -EIO;
+		nvgpu_err(g, "GPCS are not out of reset");
+	}
+
+	return err;
+}
+
+static bool ga10b_gr_init_activity_empty_or_preempted(u32 val)
+{
+	while (val != 0U) {
+		u32 v = gr_activity_4_gpc0_v(val);
+
+		if ((v != gr_activity_4_gpc0_empty_v()) &&
+			(v != gr_activity_4_gpc0_preempted_v())) {
+			return false;
+		}
+		val >>= gr_activity_4_gpc0_s();
+	}
+
+	return true;
+}
+
+int ga10b_gr_init_wait_empty(struct gk20a *g)
+{
+	u32 delay = POLL_DELAY_MIN_US;
+	bool ctxsw_active;
+	bool gr_busy;
+	u32 gr_status;
+	u32 activity0, activity1, activity4;
+	struct nvgpu_timeout timeout;
+	int err;
+
+	nvgpu_log_fn(g, " ");
+
+	err = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
+				NVGPU_TIMER_CPU_TIMER);
+	if (err != 0) {
+		nvgpu_err(g, "timeout_init failed: %d", err);
+		return err;
+	}
+
+	do {
+		gr_status = nvgpu_readl(g, gr_status_r());
+
+		ctxsw_active = (gr_status_state_v(gr_status) ==
+					gr_status_state_busy_v() ||
+				gr_status_fe_method_upper_v(gr_status) ==
+					gr_status_fe_method_upper_busy_v() ||
+				gr_status_fe_method_lower_v(gr_status) ==
+					gr_status_fe_method_lower_busy_v());
+
+		activity0 = nvgpu_readl(g, gr_activity_0_r());
+		activity1 = nvgpu_readl(g, gr_activity_1_r());
+		activity4 = nvgpu_readl(g, gr_activity_4_r());
+
+		/* activity_1 status start from gr_activity_1_memfmt_b() */
+		activity1 >>= gr_activity_1_memfmt_b();
+
+		gr_busy = !(ga10b_gr_init_activity_empty_or_preempted(activity0)
+			&& ga10b_gr_init_activity_empty_or_preempted(activity1)
+			&&
+			ga10b_gr_init_activity_empty_or_preempted(activity4));
+
+		if (!gr_busy && !ctxsw_active) {
+			nvgpu_log_fn(g, "done");
+			return 0;
+		}
+
+		nvgpu_usleep_range(delay, nvgpu_safe_mult_u32(delay, 2U));
+		delay = min_t(u32, delay << 1, POLL_DELAY_MAX_US);
+	} while (nvgpu_timeout_expired(&timeout) == 0);
+
+	nvgpu_err(g,
+		"timeout, ctxsw busy: %d, gr busy: %d, 0x%08x, 0x%08x, 0x%08x",
+			ctxsw_active, gr_busy, activity0, activity1, activity4);
+
+	return -EAGAIN;
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100.h b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100.h
new file mode 100644
index 000000000..83b986c88
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_INTR_GA100_H
+#define NVGPU_GR_INTR_GA100_H
+
+struct gk20a;
+struct nvgpu_gr_config;
+
+/* Copy required definitions from clc6c0.h class file */
+#define NVC6C0_SET_CB_BASE			0x0220U
+#define NVC6C0_SET_BES_CROP_DEBUG4		0x022cU
+#define NVC6C0_SET_TEX_IN_DBG			0x0238U
+#define NVC6C0_SET_SKEDCHECK			0x023cU
+#define NVC697_SET_SHADER_EXCEPTIONS		0x1528U
+#define NVC6C0_SET_SHADER_EXCEPTIONS		0x1528U
+#define NVC697_SET_CIRCULAR_BUFFER_SIZE		0x1280U
+#define NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE	0x02dcU
+
+/*
+ * Hardware divides sw_method enum value by 2 before passing as "offset".
+ * Left shift given offset by 2 to obtain sw_method enum value.
+ */
+#define NVGPU_GA100_SW_METHOD_SHIFT		2U
+
+int ga100_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
+			u32 class_num, u32 offset, u32 data);
+void ga100_gr_intr_enable_exceptions(struct gk20a *g,
+			struct nvgpu_gr_config *gr_config, bool enable);
+bool ga100_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception);
+void ga100_gr_intr_enable_gpc_exceptions(struct gk20a *g,
+					 struct nvgpu_gr_config *gr_config);
+u32 ga100_gr_intr_enable_mask(struct gk20a *g);
+u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g,
+					struct nvgpu_gr_intr_info *intr_info);
+
+#endif /* NVGPU_GR_INTR_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c
new file mode 100644
index 000000000..860a6264c
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/class.h>
+#include <nvgpu/nvgpu_next_class.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/nvgpu_err.h>
+
+#include <nvgpu/gr/config.h>
+#include <nvgpu/gr/gr.h>
+#include <nvgpu/gr/gr_intr.h>
+
+#include "common/gr/gr_intr_priv.h"
+#include "hal/gr/intr/gr_intr_gm20b.h"
+#include "hal/gr/intr/gr_intr_gp10b.h"
+#include "hal/gr/intr/gr_intr_gv11b.h"
+#include "gr_intr_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_gr_ga100.h>
+
+#define GR_INTR_EN_MASK	(\
+	gr_intr_en_notify__prod_f() | \
+	gr_intr_en_semaphore__prod_f() | \
+	gr_intr_en_illegal_method__prod_f() | \
+	gr_intr_en_illegal_class__prod_f() | \
+	gr_intr_en_illegal_notify__prod_f() | \
+	gr_intr_en_debug_method__prod_f() | \
+	gr_intr_en_firmware_method__prod_f() | \
+	gr_intr_en_buffer_notify__prod_f() | \
+	gr_intr_en_fecs_error__prod_f() | \
+	gr_intr_en_class_error__prod_f() | \
+	gr_intr_en_exception__prod_f() | \
+	gr_intr_en_fe_debug_intr__prod_f())
+
+u32 ga100_gr_intr_enable_mask(struct gk20a *g)
+{
+	return GR_INTR_EN_MASK;
+}
+
+u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g,
+					struct nvgpu_gr_intr_info *intr_info)
+{
+	u32 gr_intr = nvgpu_readl(g, gr_intr_r());
+
+	(void) memset(intr_info, 0, sizeof(struct nvgpu_gr_intr_info));
+
+	if ((gr_intr & gr_intr_notify_pending_f()) != 0U) {
+		intr_info->notify = gr_intr_notify_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_semaphore_pending_f()) != 0U) {
+		intr_info->semaphore = gr_intr_semaphore_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_illegal_notify_pending_f()) != 0U) {
+		intr_info->illegal_notify = gr_intr_illegal_notify_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_illegal_method_pending_f()) != 0U) {
+		intr_info->illegal_method = gr_intr_illegal_method_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_illegal_class_pending_f()) != 0U) {
+		intr_info->illegal_class = gr_intr_illegal_class_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_buffer_notify_pending_f()) != 0U) {
+		intr_info->buffer_notify = gr_intr_buffer_notify_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_fecs_error_pending_f()) != 0U) {
+		intr_info->fecs_error = gr_intr_fecs_error_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_class_error_pending_f()) != 0U) {
+		intr_info->class_error = gr_intr_class_error_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_debug_method_pending_f()) != 0U) {
+		intr_info->debug_method = gr_intr_debug_method_pending_f();
+	}
+
+	/* this one happens if someone tries to hit a non-whitelisted
+	 * register using set_falcon[4] */
+	if ((gr_intr & gr_intr_firmware_method_pending_f()) != 0U) {
+		intr_info->fw_method = gr_intr_firmware_method_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_exception_pending_f()) != 0U) {
+		intr_info->exception = gr_intr_exception_pending_f();
+	}
+
+	return gr_intr;
+}
+
+int ga100_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
+			u32 class_num, u32 offset, u32 data)
+{
+	nvgpu_log_fn(g, " ");
+
+	if (class_num == AMPERE_COMPUTE_A) {
+		switch (offset << NVGPU_GA100_SW_METHOD_SHIFT) {
+		case NVC6C0_SET_BES_CROP_DEBUG4:
+			g->ops.gr.set_bes_crop_debug4(g, data);
+			return 0;
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+		case NVC6C0_SET_SHADER_EXCEPTIONS:
+			g->ops.gr.intr.set_shader_exceptions(g, data);
+			return 0;
+#endif
+		case NVC6C0_SET_TEX_IN_DBG:
+			gv11b_gr_intr_set_tex_in_dbg(g, data);
+			return 0;
+		case NVC6C0_SET_SKEDCHECK:
+			gv11b_gr_intr_set_skedcheck(g, data);
+			return 0;
+		}
+	}
+#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS)
+	if (class_num == AMPERE_A) {
+		switch (offset << NVGPU_GA100_SW_METHOD_SHIFT) {
+		case NVC697_SET_SHADER_EXCEPTIONS:
+			g->ops.gr.intr.set_shader_exceptions(g, data);
+			return 0;
+		case NVC697_SET_CIRCULAR_BUFFER_SIZE:
+			g->ops.gr.set_circular_buffer_size(g, data);
+			return 0;
+		case NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
+			g->ops.gr.set_alpha_circular_buffer_size(g, data);
+			return 0;
+		}
+	}
+#endif
+	return -EINVAL;
+}
+
+bool ga100_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception)
+{
+	u32 gpc_reset = 0U;
+	u32 exception = nvgpu_readl(g, gr_exception_r());
+
+	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
+				"exception 0x%08x", exception);
+
+	gpc_reset = gm20b_gr_intr_check_gr_fe_exception(g, exception);
+	gpc_reset |= gm20b_gr_intr_check_gr_memfmt_exception(g, exception);
+	gpc_reset |= gm20b_gr_intr_check_gr_pd_exception(g, exception);
+	gpc_reset |= gm20b_gr_intr_check_gr_scc_exception(g, exception);
+	gpc_reset |= gm20b_gr_intr_check_gr_ds_exception(g, exception);
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		gpc_reset |=
+			gm20b_gr_intr_check_gr_ssync_exception(g, exception);
+	}
+	gpc_reset |= gm20b_gr_intr_check_gr_mme_exception(g, exception);
+	gpc_reset |= gm20b_gr_intr_check_gr_sked_exception(g, exception);
+
+	/* check if a gpc exception has occurred */
+	if ((exception & gr_exception_gpc_m()) != 0U) {
+		*is_gpc_exception = true;
+	}
+
+	return (gpc_reset != 0U)? true: false;
+}
+
+
+void ga100_gr_intr_enable_exceptions(struct gk20a *g,
+				struct nvgpu_gr_config *gr_config, bool enable)
+{
+	u32 reg_val = 0U;
+
+	if (!enable) {
+		nvgpu_writel(g, gr_exception_en_r(), reg_val);
+		nvgpu_writel(g, gr_exception1_en_r(), reg_val);
+		return;
+	}
+
+	/*
+	 * clear exceptions :
+	 * other than SM : hww_esr are reset in *enable_hww_excetpions*
+	 * SM            : cleared in *set_hww_esr_report_mask*
+	 */
+
+	/* enable exceptions */
+	reg_val = BIT32(nvgpu_gr_config_get_gpc_count(gr_config));
+	nvgpu_writel(g, gr_exception1_en_r(),
+				nvgpu_safe_sub_u32(reg_val, 1U));
+
+	reg_val = gr_exception_en_fe_enabled_f() |
+		  gr_exception_en_memfmt_enabled_f() |
+		  gr_exception_en_pd_enabled_f() |
+		  gr_exception_en_scc_enabled_f() |
+		  gr_exception_en_ds_enabled_f() |
+		  gr_exception_en_ssync_enabled_f() |
+		  gr_exception_en_mme_enabled_f() |
+		  gr_exception_en_sked_enabled_f() |
+		  gr_exception_en_gpc_enabled_f();
+
+	nvgpu_log(g, gpu_dbg_info, "gr_exception_en 0x%08x", reg_val);
+
+	nvgpu_writel(g, gr_exception_en_r(), reg_val);
+}
+
+void ga100_gr_intr_enable_gpc_exceptions(struct gk20a *g,
+					 struct nvgpu_gr_config *gr_config)
+{
+	u32 tpc_mask, tpc_mask_calc;
+
+	nvgpu_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(),
+			gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f() |
+			gr_gpcs_tpcs_tpccs_tpc_exception_en_pe_enabled_f() |
+			gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f());
+
+	tpc_mask_calc = BIT32(
+			 nvgpu_gr_config_get_max_tpc_per_gpc_count(gr_config));
+	tpc_mask =
+		gr_gpcs_gpccs_gpc_exception_en_tpc_f(
+			nvgpu_safe_sub_u32(tpc_mask_calc, 1U));
+
+	nvgpu_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(),
+		(tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_enabled_f() |
+			    gr_gpcs_gpccs_gpc_exception_en_gpccs_enabled_f() |
+			    gr_gpcs_gpccs_gpc_exception_en_gpcmmu0_enabled_f()));
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h
new file mode 100644
index 000000000..d374cc602
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_INTR_GA10B_H
+#define NVGPU_GR_INTR_GA10B_H
+
+struct gk20a;
+struct nvgpu_gr_config;
+struct nvgpu_gr_tpc_exception;
+struct nvgpu_gr_sm_ecc_status;
+enum nvgpu_gr_sm_ecc_error_types;
+struct nvgpu_gr_intr_info;
+
+/* Copy required definitions from clc797.h and clc7c0.h class files */
+#define NVC797_SET_SHADER_EXCEPTIONS		0x1528U
+#define NVC797_SET_GO_IDLE_TIMEOUT 		0x022cU
+#define NVC797_SET_CIRCULAR_BUFFER_SIZE 	0x1280U
+#define NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE 	0x02dcU
+#define NVC797_SET_CB_BASE			0x1014U
+#define NVC797_SET_BES_CROP_DEBUG4		0x10b0U
+#define NVC797_SET_TEX_IN_DBG			0x10bcU
+#define NVC797_SET_SKEDCHECK			0x10c0U
+
+#define NVC7C0_SET_SHADER_EXCEPTIONS		0x1528U
+#define NVC7C0_SET_CB_BASE			0x0220U
+#define NVC7C0_SET_BES_CROP_DEBUG4		0x022cU
+#define NVC7C0_SET_TEX_IN_DBG			0x0238U
+#define NVC7C0_SET_SKEDCHECK			0x023cU
+
+int ga10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
+			u32 class_num, u32 offset, u32 data);
+void ga10b_gr_intr_enable_interrupts(struct gk20a *g, bool enable);
+void ga10b_gr_intr_enable_gpc_exceptions(struct gk20a *g,
+					 struct nvgpu_gr_config *gr_config);
+u32 ga10b_gr_intr_get_tpc_exception(struct gk20a *g, u32 offset,
+				   struct nvgpu_gr_tpc_exception *pending_tpc);
+void ga10b_gr_intr_set_hww_esr_report_mask(struct gk20a *g);
+void ga10b_gr_intr_enable_exceptions(struct gk20a *g,
+			struct nvgpu_gr_config *gr_config, bool enable);
+bool ga10b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception);
+void ga10b_gr_intr_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc,
+		u32 gpc_exception, u32 *corrected_err, u32 *uncorrected_err);
+void ga10b_gr_intr_handle_tpc_sm_ecc_exception(struct gk20a *g, u32 gpc,
+					       u32 tpc);
+bool ga10b_gr_intr_sm_ecc_status_errors(struct gk20a *g,
+	u32 ecc_status_reg, enum nvgpu_gr_sm_ecc_error_types err_type,
+	struct nvgpu_gr_sm_ecc_status *ecc_status);
+void ga10b_gr_intr_retrigger(struct gk20a *g);
+void ga10b_gr_intr_enable_gpc_crop_hww(struct gk20a *g);
+void ga10b_gr_intr_enable_gpc_zrop_hww(struct gk20a *g);
+void ga10b_gr_intr_handle_gpc_crop_hww(struct gk20a *g, u32 gpc, u32 exception);
+void ga10b_gr_intr_handle_gpc_zrop_hww(struct gk20a *g, u32 gpc, u32 exception);
+void ga10b_gr_intr_handle_gpc_rrh_hww(struct gk20a *g, u32 gpc, u32 exception);
+u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g,
+					struct nvgpu_gr_intr_info *intr_info);
+u32 ga10b_gr_intr_enable_mask(struct gk20a *g);
+
+#endif /* NVGPU_GR_INTR_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c
new file mode 100644
index 000000000..42b5f50d4
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c
@@ -0,0 +1,1088 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/class.h>
+#include <nvgpu/nvgpu_next_class.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/nvgpu_err.h>
+
+#include <nvgpu/gr/config.h>
+#include <nvgpu/gr/gr.h>
+#include <nvgpu/gr/gr_intr.h>
+
+#include "common/gr/gr_intr_priv.h"
+#include "hal/gr/intr/gr_intr_gm20b.h"
+#include "hal/gr/intr/gr_intr_gp10b.h"
+#include "hal/gr/intr/gr_intr_gv11b.h"
+#include "gr_intr_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_gr_ga10b.h>
+
+#define GR_INTR_EN_MASK	(\
+	gr_intr_en_notify__prod_f() | \
+	gr_intr_en_semaphore__prod_f() | \
+	gr_intr_en_illegal_method__prod_f() | \
+	gr_intr_en_illegal_notify__prod_f() | \
+	gr_intr_en_debug_method__prod_f() | \
+	gr_intr_en_firmware_method__prod_f() | \
+	gr_intr_en_buffer_notify__prod_f() | \
+	gr_intr_en_fecs_error__prod_f() | \
+	gr_intr_en_class_error__prod_f() | \
+	gr_intr_en_exception__prod_f() | \
+	gr_intr_en_fe_debug_intr__prod_f())
+
+#define SM_HWW_WARP_ESR_REPORT_MASK \
+	(\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_tex_format_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_tex_layout_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_arrive_report_f() \
+	)
+
+#define SM_HWW_GLOBAL_ESR_REPORT_MASK \
+	(\
+	 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f() |\
+	 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_poison_data_report_f() \
+	)
+
+u32 ga10b_gr_intr_enable_mask(struct gk20a *g)
+{
+	return GR_INTR_EN_MASK;
+}
+
+int ga10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
+			u32 class_num, u32 offset, u32 data)
+{
+	/*
+	 * Hardware divides sw_method enum value by 2 before passing as "offset".
+	 * Left shift given offset by 2 to obtain sw_method enum value.
+	 */
+	u32 left_shift_by_2 = 2U;
+
+	nvgpu_log_fn(g, " ");
+
+	if (class_num == AMPERE_COMPUTE_B) {
+		switch (offset << left_shift_by_2) {
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+		case NVC7C0_SET_SHADER_EXCEPTIONS:
+			g->ops.gr.intr.set_shader_exceptions(g, data);
+			return 0;
+#endif
+		case NVC7C0_SET_CB_BASE:
+			/*
+			 * This method is only implemented for gm107 in resman
+			 * code. However, this method has never been defined in
+			 * nvgpu code. This case is added for debug purposes.
+			 */
+			nvgpu_err(g, "Unhandled set_cb_base method");
+			return 0;
+		case NVC7C0_SET_BES_CROP_DEBUG4:
+			g->ops.gr.set_bes_crop_debug4(g, data);
+			return 0;
+		case NVC7C0_SET_TEX_IN_DBG:
+			gv11b_gr_intr_set_tex_in_dbg(g, data);
+			return 0;
+		case NVC7C0_SET_SKEDCHECK:
+			gv11b_gr_intr_set_skedcheck(g, data);
+			return 0;
+		}
+	}
+
+#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS)
+	if (class_num == AMPERE_B) {
+		switch (offset << left_shift_by_2) {
+		case NVC797_SET_SHADER_EXCEPTIONS:
+			g->ops.gr.intr.set_shader_exceptions(g, data);
+			return 0;
+		case NVC797_SET_GO_IDLE_TIMEOUT:
+			gp10b_gr_intr_set_go_idle_timeout(g, data);
+			return 0;
+		case NVC797_SET_CIRCULAR_BUFFER_SIZE:
+			g->ops.gr.set_circular_buffer_size(g, data);
+			return 0;
+		case NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
+			g->ops.gr.set_alpha_circular_buffer_size(g, data);
+			return 0;
+		case NVC797_SET_CB_BASE:
+			/*
+			 * This method is only implemented for gm107 in resman
+			 * code. However, this method has never been defined in
+			 * nvgpu code. This case is added for debug purposes.
+			 */
+			nvgpu_err(g, "Unhandled set_cb_base method");
+			return 0;
+		case NVC797_SET_BES_CROP_DEBUG4:
+			g->ops.gr.set_bes_crop_debug4(g, data);
+			return 0;
+		case NVC797_SET_TEX_IN_DBG:
+			gv11b_gr_intr_set_tex_in_dbg(g, data);
+			return 0;
+		case NVC797_SET_SKEDCHECK:
+			gv11b_gr_intr_set_skedcheck(g, data);
+			return 0;
+		}
+	}
+#endif
+
+	return -EINVAL;
+}
+
+static u32 ga10b_gr_intr_check_gr_mme_fe1_exception(struct gk20a *g,
+							u32 exception)
+{
+	u32 mme_fe1_hww_esr;
+	u32 info, info_mthd, info_mthd2;
+	u32 mme_fe1_exception = exception & gr_exception_mme_fe1_m();
+
+	if (mme_fe1_exception == 0U) {
+		return 0U;
+	}
+
+	mme_fe1_hww_esr = nvgpu_readl(g, gr_mme_fe1_hww_esr_r());
+	info = nvgpu_readl(g, gr_mme_fe1_hww_esr_info_r());
+	info_mthd = nvgpu_readl(g, gr_mme_fe1_hww_esr_info_mthd_r());
+	info_mthd2 = nvgpu_readl(g, gr_mme_fe1_hww_esr_info_mthd2_r());
+
+	nvgpu_gr_intr_report_exception(g, 0, GPU_PGRAPH_MME_FE1_EXCEPTION,
+				       mme_fe1_hww_esr, 0U);
+	nvgpu_err(g, "mme_fe1 exception: esr 0x%08x, info 0x%08x,"
+		     "info_mthd 0x%08x, info_mthd2 0x%08x",
+		      mme_fe1_hww_esr, info, info_mthd, info_mthd2);
+
+	nvgpu_writel(g, gr_mme_fe1_hww_esr_r(),
+			gr_mme_fe1_hww_esr_reset_active_f());
+
+	return mme_fe1_exception;
+}
+
+bool ga10b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception)
+{
+	u32 gpc_reset = 0U;
+	u32 exception = nvgpu_readl(g, gr_exception_r());
+
+	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
+				"exception 0x%08x", exception);
+
+	gpc_reset = gm20b_gr_intr_check_gr_fe_exception(g, exception);
+	gpc_reset |= gm20b_gr_intr_check_gr_memfmt_exception(g, exception);
+	gpc_reset |= gm20b_gr_intr_check_gr_pd_exception(g, exception);
+	gpc_reset |= gm20b_gr_intr_check_gr_scc_exception(g, exception);
+	gpc_reset |= gm20b_gr_intr_check_gr_ds_exception(g, exception);
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		gpc_reset |= gm20b_gr_intr_check_gr_ssync_exception(g, exception);
+	}
+	gpc_reset |= gm20b_gr_intr_check_gr_mme_exception(g, exception);
+	gpc_reset |= gm20b_gr_intr_check_gr_sked_exception(g, exception);
+	gpc_reset |= ga10b_gr_intr_check_gr_mme_fe1_exception(g, exception);
+
+	/* check if a gpc exception has occurred */
+	if ((exception & gr_exception_gpc_m()) != 0U) {
+		*is_gpc_exception = true;
+	}
+
+	return (gpc_reset != 0U)? true: false;
+}
+
+void ga10b_gr_intr_set_hww_esr_report_mask(struct gk20a *g)
+{
+	u32 sm_hww_warp_esr_report_mask;
+	u32 sm_hww_global_esr_report_mask;
+
+	/*
+	 * Perform a RMW to the warp, global ESR report mask registers.
+	 * This is done in-order to retain the default values loaded from
+	 * sw_ctx_load.
+	 */
+	sm_hww_warp_esr_report_mask = nvgpu_readl(g,
+		gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r());
+	sm_hww_global_esr_report_mask = nvgpu_readl(g,
+		gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r());
+
+	/* clear hww */
+	nvgpu_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_r(), U32_MAX);
+
+	/*
+	 * setup sm warp esr report masks
+	 */
+	nvgpu_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(),
+		sm_hww_warp_esr_report_mask | SM_HWW_WARP_ESR_REPORT_MASK);
+
+	nvgpu_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(),
+		sm_hww_global_esr_report_mask | SM_HWW_GLOBAL_ESR_REPORT_MASK);
+
+	nvgpu_log_info(g,
+		"configured (global, warp)_esr_report_mask(0x%x, 0x%x)",
+		sm_hww_global_esr_report_mask | SM_HWW_GLOBAL_ESR_REPORT_MASK,
+		sm_hww_warp_esr_report_mask | SM_HWW_WARP_ESR_REPORT_MASK);
+}
+
+u32 ga10b_gr_intr_get_tpc_exception(struct gk20a *g, u32 offset,
+				    struct nvgpu_gr_tpc_exception *pending_tpc)
+{
+	u32 tpc_exception = nvgpu_readl(g, nvgpu_safe_add_u32(
+				gr_gpc0_tpc0_tpccs_tpc_exception_r(), offset));
+
+	(void) memset(pending_tpc, 0, sizeof(struct nvgpu_gr_tpc_exception));
+
+	if (gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(tpc_exception) ==
+		gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v()) {
+			pending_tpc->sm_exception = true;
+	}
+
+	if ((tpc_exception & gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m()) != 0U) {
+		pending_tpc->mpc_exception = true;
+	}
+
+	if ((tpc_exception & gr_gpc0_tpc0_tpccs_tpc_exception_pe_m()) != 0U) {
+		pending_tpc->pe_exception = true;
+	}
+
+	return tpc_exception;
+}
+
+void ga10b_gr_intr_enable_gpc_exceptions(struct gk20a *g,
+					 struct nvgpu_gr_config *gr_config)
+{
+	u32 tpc_mask, tpc_mask_calc;
+
+	nvgpu_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(),
+			gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f() |
+			gr_gpcs_tpcs_tpccs_tpc_exception_en_pe_enabled_f() |
+			gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f());
+
+	tpc_mask_calc = BIT32(
+			 nvgpu_gr_config_get_max_tpc_per_gpc_count(gr_config));
+	tpc_mask =
+		gr_gpcs_gpccs_gpc_exception_en_tpc_f(
+			nvgpu_safe_sub_u32(tpc_mask_calc, 1U));
+
+	/*
+	 * Enable exceptions from ROP subunits: zrop and crop. The rrh subunit
+	 * does not have a subunit level enable.
+	 */
+	g->ops.gr.intr.enable_gpc_zrop_hww(g);
+	g->ops.gr.intr.enable_gpc_crop_hww(g);
+
+	nvgpu_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(),
+		(tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_enabled_f() |
+			    gr_gpcs_gpccs_gpc_exception_en_gpccs_enabled_f() |
+			    gr_gpcs_gpccs_gpc_exception_en_gpcmmu0_enabled_f() |
+			    gr_gpcs_gpccs_gpc_exception_en_crop0_enabled_f() |
+			    gr_gpcs_gpccs_gpc_exception_en_zrop0_enabled_f() |
+			    gr_gpcs_gpccs_gpc_exception_en_rrh0_enabled_f() |
+			    gr_gpcs_gpccs_gpc_exception_en_crop1_enabled_f() |
+			    gr_gpcs_gpccs_gpc_exception_en_zrop1_enabled_f() |
+			    gr_gpcs_gpccs_gpc_exception_en_rrh1_enabled_f()));
+}
+
+void ga10b_gr_intr_enable_exceptions(struct gk20a *g,
+				struct nvgpu_gr_config *gr_config, bool enable)
+{
+	u32 reg_val = 0U;
+
+	if (!enable) {
+		nvgpu_writel(g, gr_exception_en_r(), reg_val);
+		nvgpu_writel(g, gr_exception1_en_r(), reg_val);
+		return;
+	}
+
+	/*
+	 * clear exceptions :
+	 * other than SM : hww_esr are reset in *enable_hww_excetpions*
+	 * SM            : cleared in *set_hww_esr_report_mask*
+	 */
+
+	/* enable exceptions */
+	reg_val = BIT32(nvgpu_gr_config_get_gpc_count(gr_config));
+	nvgpu_writel(g, gr_exception1_en_r(),
+				nvgpu_safe_sub_u32(reg_val, 1U));
+
+	reg_val = gr_exception_en_fe_enabled_f() |
+		  gr_exception_en_memfmt_enabled_f() |
+		  gr_exception_en_pd_enabled_f() |
+		  gr_exception_en_scc_enabled_f() |
+		  gr_exception_en_ds_enabled_f() |
+		  gr_exception_en_ssync_enabled_f() |
+		  gr_exception_en_mme_enabled_f() |
+		  gr_exception_en_sked_enabled_f() |
+		  gr_exception_en_mme_fe1_enabled_f() |
+		  gr_exception_en_gpc_enabled_f();
+
+	nvgpu_log(g, gpu_dbg_info, "gr_exception_en 0x%08x", reg_val);
+
+	nvgpu_writel(g, gr_exception_en_r(), reg_val);
+}
+
+static void ga10b_gr_intr_report_gpcmmu_ecc_err(struct gk20a *g,
+		u32 ecc_status, u32 gpc, u32 correct_err, u32 uncorrect_err)
+{
+	if ((ecc_status &
+	     gr_gpc0_mmu0_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m()) != 0U) {
+		nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error");
+	}
+	if ((ecc_status &
+	     gr_gpc0_mmu0_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m()) != 0U) {
+		nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_MMU, gpc,
+				GPU_MMU_L1TLB_SA_DATA_ECC_UNCORRECTED,
+				0U, uncorrect_err);
+		nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error");
+	}
+	if ((ecc_status &
+	     gr_gpc0_mmu0_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m()) != 0U) {
+		nvgpu_log(g, gpu_dbg_intr, "corrected ecc fa data error");
+	}
+	if ((ecc_status &
+	     gr_gpc0_mmu0_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m()) != 0U) {
+		nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_MMU, gpc,
+				GPU_MMU_L1TLB_FA_DATA_ECC_UNCORRECTED,
+				0U, uncorrect_err);
+		nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc fa data error");
+	}
+}
+
+void ga10b_gr_intr_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc,
+		u32 gpc_exception, u32 *corrected_err, u32 *uncorrected_err)
+{
+	u32 offset = nvgpu_gr_gpc_offset(g, gpc);
+	u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt;
+	u32 corrected_delta, uncorrected_delta;
+	u32 corrected_overflow, uncorrected_overflow;
+	u32 hww_esr;
+
+	if ((gpc_exception & gr_gpc0_gpccs_gpc_exception_gpcmmu0_m()) == 0U) {
+		return;
+	}
+
+	hww_esr = nvgpu_readl(g,
+			nvgpu_safe_add_u32(gr_gpc0_mmu0_gpcmmu_global_esr_r(),
+						offset));
+
+	if ((hww_esr & (gr_gpc0_mmu0_gpcmmu_global_esr_ecc_corrected_m() |
+		gr_gpc0_mmu0_gpcmmu_global_esr_ecc_uncorrected_m())) == 0U) {
+		return;
+	}
+
+	ecc_status = nvgpu_readl(g, nvgpu_safe_add_u32(
+			gr_gpc0_mmu0_l1tlb_ecc_status_r(), offset));
+	ecc_addr = nvgpu_readl(g, nvgpu_safe_add_u32(
+			gr_gpc0_mmu0_l1tlb_ecc_address_r(), offset));
+	corrected_cnt = nvgpu_readl(g, nvgpu_safe_add_u32(
+			gr_gpc0_mmu0_l1tlb_ecc_corrected_err_count_r(),	offset));
+	uncorrected_cnt = nvgpu_readl(g, nvgpu_safe_add_u32(
+			gr_gpc0_mmu0_l1tlb_ecc_uncorrected_err_count_r(), offset));
+	corrected_delta =
+	 gr_gpc0_mmu0_l1tlb_ecc_corrected_err_count_total_v(corrected_cnt);
+	uncorrected_delta =
+	 gr_gpc0_mmu0_l1tlb_ecc_uncorrected_err_count_total_v(uncorrected_cnt);
+	corrected_overflow = ecc_status &
+	 gr_gpc0_mmu0_l1tlb_ecc_status_corrected_err_total_counter_overflow_m();
+	uncorrected_overflow = ecc_status &
+	 gr_gpc0_mmu0_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m();
+
+	/* clear the interrupt */
+	if ((corrected_delta > 0U) || (corrected_overflow != 0U)) {
+		nvgpu_writel(g, nvgpu_safe_add_u32(
+			     gr_gpc0_mmu0_l1tlb_ecc_corrected_err_count_r(),
+			     offset), 0U);
+	}
+	if ((uncorrected_delta > 0U) || (uncorrected_overflow != 0U)) {
+		nvgpu_writel(g, nvgpu_safe_add_u32(
+			     gr_gpc0_mmu0_l1tlb_ecc_uncorrected_err_count_r(),
+			     offset), 0U);
+	}
+
+	nvgpu_writel(g, nvgpu_safe_add_u32(
+				gr_gpc0_mmu0_l1tlb_ecc_status_r(), offset),
+				gr_gpc0_mmu0_l1tlb_ecc_status_reset_task_f());
+
+	/* Handle overflow */
+	if (corrected_overflow != 0U) {
+		corrected_delta = nvgpu_safe_add_u32(corrected_delta,
+		   BIT32(gr_gpc0_mmu0_l1tlb_ecc_corrected_err_count_total_s()));
+		nvgpu_info(g, "mmu l1tlb ecc counter corrected overflow!");
+	}
+	if (uncorrected_overflow != 0U) {
+		uncorrected_delta = nvgpu_safe_add_u32(uncorrected_delta,
+		  BIT32(gr_gpc0_mmu0_l1tlb_ecc_uncorrected_err_count_total_s()));
+		nvgpu_info(g, "mmu l1tlb ecc counter uncorrected overflow!");
+	}
+
+	*corrected_err = nvgpu_safe_add_u32(*corrected_err, corrected_delta);
+	*uncorrected_err = nvgpu_safe_add_u32(*uncorrected_err, uncorrected_delta);
+
+	nvgpu_log(g, gpu_dbg_intr,
+		"mmu l1tlb gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr);
+
+	ga10b_gr_intr_report_gpcmmu_ecc_err(g, ecc_status, gpc,
+					    (u32)*corrected_err,
+					    (u32)*uncorrected_err);
+
+	nvgpu_log(g, gpu_dbg_intr,
+		"ecc error address: 0x%x", ecc_addr);
+	nvgpu_log(g, gpu_dbg_intr,
+		"ecc error count corrected: %d, uncorrected %d",
+		(u32)*corrected_err, (u32)*uncorrected_err);
+}
+
+static void ga10b_gr_intr_set_l1_tag_uncorrected_err(struct gk20a *g,
+	u32 l1_tag_ecc_status, struct nvgpu_gr_sm_ecc_status *ecc_status)
+{
+
+	if ((l1_tag_ecc_status &
+	    gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m()) != 0U) {
+		ecc_status->err_id[ecc_status->err_count] =
+				GPU_SM_L1_TAG_ECC_UNCORRECTED;
+		ecc_status->err_count =
+				nvgpu_safe_add_u32(ecc_status->err_count, 1U);
+	}
+
+	if ((l1_tag_ecc_status &
+	     gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m()) != 0U) {
+		ecc_status->err_id[ecc_status->err_count] =
+				GPU_SM_L1_TAG_MISS_FIFO_ECC_UNCORRECTED;
+		ecc_status->err_count =
+				nvgpu_safe_add_u32(ecc_status->err_count, 1U);
+	}
+
+	if ((l1_tag_ecc_status &
+	     gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m()) != 0U) {
+		ecc_status->err_id[ecc_status->err_count] =
+				GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED;
+		ecc_status->err_count =
+				nvgpu_safe_add_u32(ecc_status->err_count, 1U);
+	}
+}
+
+static void ga10b_gr_intr_set_l1_tag_corrected_err(struct gk20a *g,
+	u32 l1_tag_ecc_status, struct nvgpu_gr_sm_ecc_status *ecc_status)
+{
+
+	if ((l1_tag_ecc_status &
+	    gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m()) != 0U) {
+		ecc_status->err_id[ecc_status->err_count] =
+				GPU_SM_L1_TAG_ECC_CORRECTED;
+		ecc_status->err_count =
+				nvgpu_safe_add_u32(ecc_status->err_count, 1U);
+	}
+}
+
+static bool ga10b_gr_intr_sm_l1_tag_ecc_status_errors(struct gk20a *g,
+	u32 l1_tag_ecc_status, struct nvgpu_gr_sm_ecc_status *ecc_status)
+{
+	u32 corr_err, uncorr_err;
+	bool err_status = true;
+
+	corr_err =  l1_tag_ecc_status &
+		(gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m() |
+		 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m() |
+		 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m());
+
+	uncorr_err = l1_tag_ecc_status &
+		(gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m() |
+		 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m() |
+		 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m());
+
+	if ((corr_err == 0U) && (uncorr_err == 0U)) {
+		err_status = false;
+	}
+
+	ecc_status->err_count = 0U;
+	ecc_status->corrected_err_status = corr_err;
+	ecc_status->uncorrected_err_status = uncorr_err;
+
+	ga10b_gr_intr_set_l1_tag_corrected_err(g, l1_tag_ecc_status, ecc_status);
+	ga10b_gr_intr_set_l1_tag_uncorrected_err(g, l1_tag_ecc_status, ecc_status);
+
+	return err_status;
+}
+
+static bool ga10b_gr_intr_sm_lrf_ecc_status_errors(struct gk20a *g,
+	u32 lrf_ecc_status, struct nvgpu_gr_sm_ecc_status *ecc_status)
+{
+	u32 corr_err, uncorr_err;
+	bool err_status = true;
+
+	corr_err = lrf_ecc_status &
+		(gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m() |
+		 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m() |
+		 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m() |
+		 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m());
+
+	uncorr_err = lrf_ecc_status &
+		(gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m() |
+		 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m() |
+		 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m() |
+		 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m());
+
+	if ((corr_err == 0U) && (uncorr_err == 0U)) {
+		err_status = false;
+	}
+
+	ecc_status->err_count = 0U;
+
+	if (uncorr_err != 0U) {
+		ecc_status->err_id[ecc_status->err_count] =
+				GPU_SM_LRF_ECC_UNCORRECTED;
+		ecc_status->err_count =
+			nvgpu_safe_add_u32(ecc_status->err_count, 1U);
+	}
+
+	ecc_status->corrected_err_status = corr_err;
+	ecc_status->uncorrected_err_status = uncorr_err;
+
+	return err_status;
+}
+
+static bool ga10b_gr_intr_sm_cbu_ecc_status_errors(struct gk20a *g,
+	u32 cbu_ecc_status, struct nvgpu_gr_sm_ecc_status *ecc_status)
+{
+	u32 corr_err, uncorr_err;
+	bool err_status = true;
+
+	corr_err = cbu_ecc_status &
+	  (gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m() |
+	   gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m());
+
+	uncorr_err = cbu_ecc_status &
+	  (gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m() |
+	   gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m());
+
+	if ((corr_err == 0U) && (uncorr_err == 0U)) {
+		err_status = false;
+	}
+
+	ecc_status->err_count = 0;
+
+	if (uncorr_err != 0U) {
+		ecc_status->err_id[ecc_status->err_count] =
+				GPU_SM_CBU_ECC_UNCORRECTED;
+		ecc_status->err_count =
+			nvgpu_safe_add_u32(ecc_status->err_count, 1U);
+	}
+
+	ecc_status->corrected_err_status = corr_err;
+	ecc_status->uncorrected_err_status = uncorr_err;
+
+	return err_status;
+}
+
+static bool ga10b_gr_intr_sm_l1_data_ecc_status_errors(struct gk20a *g,
+	u32 l1_data_ecc_status, struct nvgpu_gr_sm_ecc_status *ecc_status)
+{
+	u32 corr_err, uncorr_err;
+	bool err_status = true;
+
+	corr_err = l1_data_ecc_status &
+		gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m();
+	uncorr_err = l1_data_ecc_status &
+		gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m();
+
+	if ((corr_err == 0U) && (uncorr_err == 0U)) {
+		err_status = false;
+	}
+
+	ecc_status->err_count = 0U;
+
+	if (uncorr_err != 0U) {
+		ecc_status->err_id[ecc_status->err_count] =
+				GPU_SM_L1_DATA_ECC_UNCORRECTED;
+		ecc_status->err_count =
+			nvgpu_safe_add_u32(ecc_status->err_count, 1U);
+	}
+
+	ecc_status->corrected_err_status = corr_err;
+	ecc_status->uncorrected_err_status = uncorr_err;
+
+	return err_status;
+}
+
+static bool ga10b_gr_intr_sm_rams_ecc_status_errors(struct gk20a *g,
+	u32 rams_ecc_status, struct nvgpu_gr_sm_ecc_status *ecc_status)
+{
+	u32 corr_err, uncorr_err;
+	bool err_status = true;
+
+	corr_err = rams_ecc_status &\
+		(gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_l0ic_data_m() |\
+		 gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_l0ic_predecode_m() |\
+		 gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_urf_data_m());
+	uncorr_err = rams_ecc_status &\
+		(gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_l0ic_data_m() |\
+		 gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_l0ic_predecode_m() |\
+		 gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_urf_data_m());
+
+	if ((corr_err == 0U) && (uncorr_err == 0U)) {
+		err_status = false;
+	}
+
+	ecc_status->err_count = 0U;
+
+	if (uncorr_err != 0U) {
+		ecc_status->err_id[ecc_status->err_count] =
+				GPU_SM_RAMS_ECC_UNCORRECTED;
+		ecc_status->err_count =
+			nvgpu_safe_add_u32(ecc_status->err_count, 1U);
+	}
+	if (corr_err != 0U) {
+		ecc_status->err_id[ecc_status->err_count] =
+				GPU_SM_RAMS_ECC_CORRECTED;
+		ecc_status->err_count =
+			nvgpu_safe_add_u32(ecc_status->err_count, 1U);
+	}
+
+	ecc_status->corrected_err_status = corr_err;
+	ecc_status->uncorrected_err_status = uncorr_err;
+
+	return err_status;
+}
+
+
+static bool ga10b_gr_intr_sm_icache_ecc_status_errors(struct gk20a *g,
+	u32 icache_ecc_status, struct nvgpu_gr_sm_ecc_status *ecc_status)
+{
+	u32 corr_err, uncorr_err;
+	bool err_status = true;
+
+	corr_err = icache_ecc_status &
+		gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m();
+
+	uncorr_err = icache_ecc_status &
+		gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m();
+
+	if ((corr_err == 0U) && (uncorr_err == 0U)) {
+		err_status = false;
+	}
+
+	ecc_status->err_count = 0U;
+
+	if (uncorr_err != 0U) {
+		ecc_status->err_id[ecc_status->err_count] =
+				GPU_SM_ICACHE_L1_DATA_ECC_UNCORRECTED;
+		ecc_status->err_count =
+			nvgpu_safe_add_u32(ecc_status->err_count, 1U);
+	}
+
+	ecc_status->corrected_err_status = corr_err;
+	ecc_status->uncorrected_err_status = uncorr_err;
+
+	return err_status;
+}
+
+static void ga10b_gr_intr_report_tpc_sm_rams_ecc_err(struct gk20a *g,
+		struct nvgpu_gr_sm_ecc_status *ecc_status, u32 gpc, u32 tpc)
+{
+	u32 i;
+
+	/* This check has been added to ensure that the TPC id is less than
+	 * 8-bits and hence, it can be packed as part of LSB 8-bits along with
+	 * the GPC id while reporting SM related ECC errors.
+	 */
+	tpc = tpc & U8_MAX;
+
+	for (i = 0U; i < ecc_status->err_count; i++) {
+		if (ecc_status->err_id[i] == GPU_SM_RAMS_ECC_CORRECTED) {
+			nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
+				(gpc << SHIFT_8_BITS) | tpc,
+				GPU_SM_L1_TAG_ECC_CORRECTED, 0,
+				g->ecc.gr.sm_rams_ecc_corrected_err_count[gpc][tpc].counter);
+		} else {
+			nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
+				(gpc << SHIFT_8_BITS) | tpc,
+				GPU_SM_L1_TAG_ECC_UNCORRECTED, 0,
+				g->ecc.gr.sm_rams_ecc_uncorrected_err_count[gpc][tpc].counter);
+		}
+	}
+}
+
+static void ga10b_gr_intr_handle_tpc_sm_rams_ecc_exception(struct gk20a *g,
+		u32 gpc, u32 tpc)
+{
+	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
+	u32 offset;
+	u32 rams_ecc_status;
+	u32 rams_corrected_err_count_delta = 0U;
+	u32 rams_uncorrected_err_count_delta = 0U;
+	bool is_rams_ecc_corrected_total_err_overflow = false;
+	bool is_rams_ecc_uncorrected_total_err_overflow = false;
+	struct nvgpu_gr_sm_ecc_status ecc_status;
+
+	offset = nvgpu_safe_add_u32(
+			nvgpu_safe_mult_u32(gpc_stride, gpc),
+			nvgpu_safe_mult_u32(tpc_in_gpc_stride, tpc));
+
+
+	/* Check for SM RAMS ECC errors. */
+	rams_ecc_status = nvgpu_readl(g, nvgpu_safe_add_u32(
+		gr_pri_gpc0_tpc0_sm_rams_ecc_status_r(), offset));
+
+	(void) memset(&ecc_status, 0, sizeof(struct nvgpu_gr_sm_ecc_status));
+
+	if (g->ops.gr.intr.sm_ecc_status_errors(g, rams_ecc_status,
+				SM_RAMS_ECC_ERROR, &ecc_status) == false) {
+		return;
+	}
+
+	rams_corrected_err_count_delta =
+		gr_pri_gpc0_tpc0_sm_rams_ecc_corrected_err_count_total_v(
+			nvgpu_readl(g, nvgpu_safe_add_u32(
+				gr_pri_gpc0_tpc0_sm_rams_ecc_corrected_err_count_r(),
+				offset)));
+	rams_uncorrected_err_count_delta =
+		gr_pri_gpc0_tpc0_sm_rams_ecc_uncorrected_err_count_total_v(
+			nvgpu_readl(g, nvgpu_safe_add_u32(
+				gr_pri_gpc0_tpc0_sm_rams_ecc_uncorrected_err_count_r(),
+				offset)));
+	is_rams_ecc_corrected_total_err_overflow =
+		gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_total_counter_overflow_v(rams_ecc_status) != 0U;
+	is_rams_ecc_uncorrected_total_err_overflow =
+		gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_total_counter_overflow_v(rams_ecc_status) != 0U;
+
+	if ((rams_corrected_err_count_delta > 0U) || is_rams_ecc_corrected_total_err_overflow) {
+		nvgpu_log(g, gpu_dbg_fn | gpu_dbg_intr,
+			"corrected error (SBE) detected in SM RAMS! err_mask [%08x] is_overf [%d]",
+			ecc_status.corrected_err_status, is_rams_ecc_corrected_total_err_overflow);
+
+		/* HW uses 16-bits counter */
+		if (is_rams_ecc_corrected_total_err_overflow) {
+			rams_corrected_err_count_delta =
+			   nvgpu_safe_add_u32(rams_corrected_err_count_delta,
+				BIT32(gr_pri_gpc0_tpc0_sm_rams_ecc_corrected_err_count_total_s()));
+		}
+		g->ecc.gr.sm_rams_ecc_corrected_err_count[gpc][tpc].counter =
+		   nvgpu_safe_add_u32(
+			g->ecc.gr.sm_rams_ecc_corrected_err_count[gpc][tpc].counter,
+			rams_corrected_err_count_delta);
+		nvgpu_writel(g, nvgpu_safe_add_u32(
+			gr_pri_gpc0_tpc0_sm_rams_ecc_corrected_err_count_r(), offset),
+			0U);
+	}
+
+	if ((rams_uncorrected_err_count_delta > 0U) || is_rams_ecc_uncorrected_total_err_overflow) {
+		nvgpu_log(g, gpu_dbg_fn | gpu_dbg_intr,
+			"Uncorrected error (DBE) detected in SM RAMS! err_mask [%08x] is_overf [%d]",
+			ecc_status.uncorrected_err_status, is_rams_ecc_uncorrected_total_err_overflow);
+
+		/* HW uses 16-bits counter */
+		if (is_rams_ecc_uncorrected_total_err_overflow) {
+			rams_uncorrected_err_count_delta =
+			   nvgpu_safe_add_u32(
+				rams_uncorrected_err_count_delta,
+				BIT32(gr_pri_gpc0_tpc0_sm_rams_ecc_uncorrected_err_count_total_s()));
+		}
+		g->ecc.gr.sm_rams_ecc_uncorrected_err_count[gpc][tpc].counter =
+		  nvgpu_safe_add_u32(
+			g->ecc.gr.sm_rams_ecc_uncorrected_err_count[gpc][tpc].counter,
+			rams_uncorrected_err_count_delta);
+		nvgpu_writel(g, nvgpu_safe_add_u32(
+			gr_pri_gpc0_tpc0_sm_rams_ecc_uncorrected_err_count_r(), offset),
+			0U);
+	}
+
+	ga10b_gr_intr_report_tpc_sm_rams_ecc_err(g, &ecc_status, gpc, tpc);
+	nvgpu_writel(g, nvgpu_safe_add_u32(
+			gr_pri_gpc0_tpc0_sm_rams_ecc_status_r(), offset),
+			gr_pri_gpc0_tpc0_sm_rams_ecc_status_reset_task_f());
+}
+
+bool ga10b_gr_intr_sm_ecc_status_errors(struct gk20a *g,
+	u32 ecc_status_reg, enum nvgpu_gr_sm_ecc_error_types err_type,
+	struct nvgpu_gr_sm_ecc_status *ecc_status)
+{
+	bool err_status = false;
+
+	if (err_type == SM_ICACHE_ECC_ERROR) {
+		err_status = ga10b_gr_intr_sm_icache_ecc_status_errors(g,
+						ecc_status_reg, ecc_status);
+	} else if (err_type == SM_LRF_ECC_ERROR) {
+		err_status = ga10b_gr_intr_sm_lrf_ecc_status_errors(g,
+						ecc_status_reg, ecc_status);
+	} else if (err_type == SM_L1_TAG_ERROR) {
+		err_status = ga10b_gr_intr_sm_l1_tag_ecc_status_errors(g,
+						ecc_status_reg, ecc_status);
+	} else if (err_type == SM_CBU_ECC_ERROR) {
+		err_status = ga10b_gr_intr_sm_cbu_ecc_status_errors(g,
+						ecc_status_reg, ecc_status);
+	} else if (err_type == SM_L1_DATA_ECC_ERROR) {
+		err_status = ga10b_gr_intr_sm_l1_data_ecc_status_errors(g,
+						ecc_status_reg, ecc_status);
+	} else if (err_type == SM_RAMS_ECC_ERROR) {
+		err_status = ga10b_gr_intr_sm_rams_ecc_status_errors(g,
+				ecc_status_reg, ecc_status);
+	}
+
+	return err_status;
+}
+void ga10b_gr_intr_handle_tpc_sm_ecc_exception(struct gk20a *g, u32 gpc,
+					       u32 tpc)
+{
+	gv11b_gr_intr_handle_tpc_sm_ecc_exception(g, gpc, tpc);
+	/* Check for RAMS ECC errors. */
+	ga10b_gr_intr_handle_tpc_sm_rams_ecc_exception(g, gpc, tpc);
+}
+
+void ga10b_gr_intr_enable_gpc_crop_hww(struct gk20a *g)
+{
+	nvgpu_log_fn(g, " ");
+	nvgpu_writel(g, gr_gpcs_rops_crop_hww_esr_r(),
+			gr_gpcs_rops_crop_hww_esr_reset_active_f() |
+			gr_gpcs_rops_crop_hww_esr_en_enable_f());
+}
+
+void ga10b_gr_intr_enable_gpc_zrop_hww(struct gk20a *g)
+{
+	nvgpu_log_fn(g, " ");
+	nvgpu_writel(g, gr_gpcs_rops_zrop_hww_esr_r(),
+			gr_gpcs_rops_zrop_hww_esr_reset_active_f() |
+			gr_gpcs_rops_zrop_hww_esr_en_enable_f());
+}
+
+void ga10b_gr_intr_handle_gpc_crop_hww(struct gk20a *g, u32 gpc,
+		u32 gpc_exception)
+{
+	u32 gpc_offset = 0U;
+	u32 reg_offset = 0U;
+	u32 hww_esr = 0U;
+	u32 crop_pending_masks[] = {
+		gr_gpc0_gpccs_gpc_exception_crop0_pending_f(),
+		gr_gpc0_gpccs_gpc_exception_crop1_pending_f()
+	};
+	u32 num_crop_pending_masks =
+		sizeof(crop_pending_masks)/sizeof(*crop_pending_masks);
+	u32 i = 0U;
+
+	if ((gpc_exception & (gr_gpc0_gpccs_gpc_exception_crop0_pending_f() |
+			gr_gpc0_gpccs_gpc_exception_crop1_pending_f())) == 0U) {
+		return;
+	}
+
+	gpc_offset = nvgpu_gr_gpc_offset(g, gpc);
+	for (i = 0U; i < num_crop_pending_masks; i++) {
+		if ((gpc_exception & crop_pending_masks[i]) == 0U) {
+			continue;
+		}
+		reg_offset = nvgpu_safe_add_u32(gpc_offset,
+				nvgpu_gr_rop_offset(g, i));
+		reg_offset = nvgpu_safe_add_u32(
+				gr_gpc0_rop0_crop_hww_esr_r(),
+				reg_offset);
+		hww_esr = nvgpu_readl(g, reg_offset);
+
+		nvgpu_err(g, "gpc(%u) rop(%u) crop_hww_esr(0x%08x)", gpc, i,
+				hww_esr);
+		nvgpu_writel(g, reg_offset,
+			gr_gpc0_rop0_crop_hww_esr_reset_active_f() |
+			gr_gpc0_rop0_crop_hww_esr_en_enable_f());
+	}
+}
+
+void ga10b_gr_intr_handle_gpc_zrop_hww(struct gk20a *g, u32 gpc,
+		u32 gpc_exception)
+{
+	u32 gpc_offset = 0U;
+	u32 reg_offset = 0U;
+	u32 hww_esr = 0U;
+	u32 zrop_pending_masks[] = {
+		gr_gpc0_gpccs_gpc_exception_zrop0_pending_f(),
+		gr_gpc0_gpccs_gpc_exception_zrop1_pending_f()
+	};
+	u32 num_zrop_pending_masks =
+		sizeof(zrop_pending_masks)/sizeof(*zrop_pending_masks);
+	u32 i = 0U;
+
+	if ((gpc_exception & (gr_gpc0_gpccs_gpc_exception_zrop0_pending_f() |
+			gr_gpc0_gpccs_gpc_exception_zrop1_pending_f())) == 0U) {
+		return;
+	}
+
+	gpc_offset = nvgpu_gr_gpc_offset(g, gpc);
+	for (i = 0U; i < num_zrop_pending_masks; i++) {
+		if ((gpc_exception & zrop_pending_masks[i]) == 0U) {
+			continue;
+		}
+		reg_offset = nvgpu_safe_add_u32(gpc_offset,
+				nvgpu_gr_rop_offset(g, i));
+		reg_offset = nvgpu_safe_add_u32(
+				gr_gpc0_rop0_zrop_hww_esr_r(),
+				reg_offset);
+		hww_esr = nvgpu_readl(g, reg_offset);
+
+		nvgpu_err(g,
+			"gpc(%u) rop(%u) zrop_hww_esr(0x%08x)", gpc, i,
+			hww_esr);
+
+		nvgpu_writel(g, reg_offset,
+			gr_gpc0_rop0_zrop_hww_esr_reset_active_f() |
+			gr_gpc0_rop0_zrop_hww_esr_en_enable_f());
+	}
+
+}
+
+void ga10b_gr_intr_handle_gpc_rrh_hww(struct gk20a *g, u32 gpc,
+		u32 gpc_exception)
+{
+	u32 gpc_offset = 0U;
+	u32 reg_offset = 0U;
+	u32 status = 0U;
+	u32 rrh_pending_masks[] = {
+		gr_gpc0_gpccs_gpc_exception_rrh0_pending_f(),
+		gr_gpc0_gpccs_gpc_exception_rrh1_pending_f()
+	};
+	u32 num_rrh_pending_masks =
+		sizeof(rrh_pending_masks)/sizeof(*rrh_pending_masks);
+	u32 i = 0U;
+
+	if ((gpc_exception & (gr_gpc0_gpccs_gpc_exception_rrh0_pending_f() |
+			gr_gpc0_gpccs_gpc_exception_rrh1_pending_f())) == 0U) {
+		return;
+	}
+
+
+	gpc_offset = nvgpu_gr_gpc_offset(g, gpc);
+	for (i = 0U; i < num_rrh_pending_masks; i++) {
+		if ((gpc_exception & rrh_pending_masks[i]) == 0U) {
+			continue;
+		}
+		reg_offset = nvgpu_safe_add_u32(gpc_offset,
+				nvgpu_gr_rop_offset(g, i));
+		reg_offset = nvgpu_safe_add_u32(
+				gr_gpc0_rop0_rrh_status_r(),
+				reg_offset);
+		status = nvgpu_readl(g, reg_offset);
+
+		nvgpu_err(g, "gpc(%u) rop(%u) rrh exception status(0x%08x)",
+				gpc, i, status);
+	}
+}
+
+void ga10b_gr_intr_enable_interrupts(struct gk20a *g, bool enable)
+{
+	u32 intr_notify_ctrl;
+
+	/*
+	 * The init value for the notify vector is retained and only
+	 * the cpu, gsp enable fields are updated here.
+	 */
+	intr_notify_ctrl = nvgpu_readl(g, gr_intr_notify_ctrl_r());
+
+	if (enable) {
+		nvgpu_log(g, gpu_dbg_intr, "gr intr notify vector(%d)",
+				gr_intr_notify_ctrl_vector_f(intr_notify_ctrl));
+		/* Mask intr */
+		nvgpu_writel(g, gr_intr_en_r(), 0U);
+		/* Clear interrupt */
+		nvgpu_writel(g, gr_intr_r(), U32_MAX);
+		/* Enable notifying interrupt to cpu */
+		intr_notify_ctrl |= gr_intr_notify_ctrl_cpu_enable_f();
+		/* Disable notifying interrupt to gsp */
+		intr_notify_ctrl &= ~gr_intr_notify_ctrl_gsp_enable_f();
+		nvgpu_writel(g, gr_intr_notify_ctrl_r(), intr_notify_ctrl);
+		/* Enable gr interrupts */
+		nvgpu_writel(g, gr_intr_en_r(), g->ops.gr.intr.enable_mask(g));
+	} else {
+		/* Mask intr */
+		nvgpu_writel(g, gr_intr_en_r(), 0U);
+		/* Disable notifying interrupt to cpu */
+		intr_notify_ctrl &= ~gr_intr_notify_ctrl_cpu_enable_f();
+		/* Disable notifying interrupt to gsp */
+		intr_notify_ctrl &= ~gr_intr_notify_ctrl_gsp_enable_f();
+		nvgpu_writel(g, gr_intr_notify_ctrl_r(), intr_notify_ctrl);
+		/* Clear intr */
+		nvgpu_writel(g, gr_intr_r(), U32_MAX);
+	}
+}
+
+void ga10b_gr_intr_retrigger(struct gk20a *g)
+{
+	nvgpu_writel(g, gr_intr_retrigger_r(),
+			gr_intr_retrigger_trigger_true_f());
+}
+
+u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g,
+					struct nvgpu_gr_intr_info *intr_info)
+{
+	u32 gr_intr = nvgpu_readl(g, gr_intr_r());
+
+	(void) memset(intr_info, 0, sizeof(struct nvgpu_gr_intr_info));
+
+	if ((gr_intr & gr_intr_notify_pending_f()) != 0U) {
+		intr_info->notify = gr_intr_notify_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_semaphore_pending_f()) != 0U) {
+		intr_info->semaphore = gr_intr_semaphore_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_illegal_notify_pending_f()) != 0U) {
+		intr_info->illegal_notify = gr_intr_illegal_notify_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_illegal_method_pending_f()) != 0U) {
+		intr_info->illegal_method = gr_intr_illegal_method_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_buffer_notify_pending_f()) != 0U) {
+		intr_info->buffer_notify = gr_intr_buffer_notify_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_fecs_error_pending_f()) != 0U) {
+		intr_info->fecs_error = gr_intr_fecs_error_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_class_error_pending_f()) != 0U) {
+		intr_info->class_error = gr_intr_class_error_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_debug_method_pending_f()) != 0U) {
+		intr_info->debug_method = gr_intr_debug_method_pending_f();
+	}
+
+	/* this one happens if someone tries to hit a non-whitelisted
+	 * register using set_falcon[4] */
+	if ((gr_intr & gr_intr_firmware_method_pending_f()) != 0U) {
+		intr_info->fw_method = gr_intr_firmware_method_pending_f();
+	}
+
+	if ((gr_intr & gr_intr_exception_pending_f()) != 0U) {
+		intr_info->exception = gr_intr_exception_pending_f();
+	}
+
+	return gr_intr;
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.c b/drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.c
new file mode 100644
index 000000000..b070f2643
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/static_analysis.h>
+#include <nvgpu/gr/zbc.h>
+
+#include "zbc_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_gr_ga10b.h>
+
+#define data_index_0	0U
+#define data_index_1	1U
+#define data_index_2	2U
+#define data_index_3	3U
+
+void ga10b_gr_zbc_init_table_indices(struct gk20a *g,
+			struct nvgpu_gr_zbc_table_indices *zbc_indices)
+{
+	/* Color indices */
+	zbc_indices->min_color_index =
+		gr_pri_gpcs_rops_crop_zbc_index_address_min_v();
+	zbc_indices->max_color_index =
+		gr_pri_gpcs_rops_crop_zbc_index_address_max_v();
+
+	/* Depth indices */
+	zbc_indices->min_depth_index = NVGPU_GR_ZBC_STARTOF_TABLE;
+	zbc_indices->max_depth_index = gr_gpcs_swdx_dss_zbc_z__size_1_v();
+
+	/* Stencil indices */
+	zbc_indices->min_stencil_index = NVGPU_GR_ZBC_STARTOF_TABLE;
+	zbc_indices->max_stencil_index = gr_gpcs_swdx_dss_zbc_s__size_1_v();
+}
+
+void ga10b_gr_zbc_add_color(struct gk20a *g,
+			   struct nvgpu_gr_zbc_entry *color_val, u32 index)
+{
+	nvgpu_log(g, gpu_dbg_zbc, "adding color at index %u", index);
+	nvgpu_log(g, gpu_dbg_zbc,
+		"color_clear_val[%u-%u]: 0x%08x 0x%08x 0x%08x 0x%08x",
+		data_index_0, data_index_3,
+		nvgpu_gr_zbc_get_entry_color_l2(color_val, data_index_0),
+		nvgpu_gr_zbc_get_entry_color_l2(color_val, data_index_1),
+		nvgpu_gr_zbc_get_entry_color_l2(color_val, data_index_2),
+		nvgpu_gr_zbc_get_entry_color_l2(color_val, data_index_3));
+
+	nvgpu_writel(g, gr_pri_gpcs_rops_crop_zbc_index_r(),
+		gr_pri_gpcs_rops_crop_zbc_index_address_f(index));
+
+	nvgpu_writel(g, gr_pri_gpcs_rops_crop_zbc_color_clear_value_0_r(),
+		gr_pri_gpcs_rops_crop_zbc_color_clear_value_0_bits_f(
+			nvgpu_gr_zbc_get_entry_color_l2(
+				color_val, data_index_0)));
+	nvgpu_writel(g, gr_pri_gpcs_rops_crop_zbc_color_clear_value_1_r(),
+		gr_pri_gpcs_rops_crop_zbc_color_clear_value_1_bits_f(
+			nvgpu_gr_zbc_get_entry_color_l2(
+				color_val, data_index_1)));
+	nvgpu_writel(g, gr_pri_gpcs_rops_crop_zbc_color_clear_value_2_r(),
+		gr_pri_gpcs_rops_crop_zbc_color_clear_value_2_bits_f(
+			nvgpu_gr_zbc_get_entry_color_l2(
+				color_val, data_index_2)));
+	nvgpu_writel(g, gr_pri_gpcs_rops_crop_zbc_color_clear_value_3_r(),
+		gr_pri_gpcs_rops_crop_zbc_color_clear_value_3_bits_f(
+			nvgpu_gr_zbc_get_entry_color_l2(
+				color_val, data_index_3)));
+}
diff --git a/drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.h b/drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.h
new file mode 100644
index 000000000..34eec3c5f
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef ZBC_GA10B_H
+#define ZBC_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_gr_zbc_table_indices;
+
+void ga10b_gr_zbc_init_table_indices(struct gk20a *g,
+			struct nvgpu_gr_zbc_table_indices *zbc_indices);
+void ga10b_gr_zbc_add_color(struct gk20a *g,
+			struct nvgpu_gr_zbc_entry *color_val, u32 index);
+#endif /* ZBC_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga100.c b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga100.c
new file mode 100644
index 000000000..0a5ff1d7e
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga100.c
@@ -0,0 +1,1209 @@
+/*
+ * GA100 GR MANAGER
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include "grmgr_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_smcarb_ga100.h>
+
+#define GA100_GRMGR_PSMCARB_ALLOWED_UGPU(gpu_instance_id, gpcgrp_id) \
+	((gpu_instance_id == 0U) || ((gpu_instance_id == 1U) && (gpcgrp_id == 0U)) || \
+	((gpu_instance_id == 2U) && (gpcgrp_id == 1U)) || ((gpu_instance_id == 3U) && (gpcgrp_id == 0U)) || \
+	((gpu_instance_id == 4U) && (gpcgrp_id == 0U)) || ((gpu_instance_id == 5U) && (gpcgrp_id == 1U)) || \
+	((gpu_instance_id == 6U) && (gpcgrp_id == 1U)) || ((gpu_instance_id == 7U) && (gpcgrp_id == 0U)) || \
+	((gpu_instance_id == 8U) && (gpcgrp_id == 0U)) || ((gpu_instance_id == 9U) && (gpcgrp_id == 0U)) || \
+	((gpu_instance_id == 10U) && (gpcgrp_id == 0U)) || ((gpu_instance_id == 11U) && (gpcgrp_id == 1U)) || \
+	((gpu_instance_id == 12U) && (gpcgrp_id == 1U)) || ((gpu_instance_id == 13U) && (gpcgrp_id == 1U)) || \
+	((gpu_instance_id == 14U) && (gpcgrp_id == 1U)))
+
+#define GA100_GRMGR_PSMCARB_SYS_PIPE_ALLOWED_UGPU(gr_syspipe_id, gpcgrp_id) \
+	(((gr_syspipe_id == 0U) && (gpcgrp_id == 0U)) || ((gr_syspipe_id == 1U) && (gpcgrp_id == 0U)) || \
+	((gr_syspipe_id == 2U) && (gpcgrp_id == 0U)) || ((gr_syspipe_id == 3U) && (gpcgrp_id == 0U)) || \
+	((gr_syspipe_id == 4U) && (gpcgrp_id == 1U)) || ((gr_syspipe_id == 5U) && (gpcgrp_id == 1U)) || \
+	((gr_syspipe_id == 6U) && (gpcgrp_id == 1U)) || ((gr_syspipe_id == 7U) && (gpcgrp_id == 1U)))
+
+/* Static mig config list for 8 syspipes(OxFFU) + 8 GPCs + 8 Aysnc LCEs + 4:4 gpc group config */
+static const struct nvgpu_mig_gpu_instance_config ga100_gpu_instance_config_8_syspipes = {
+	.usable_gr_syspipe_count	= 8U,
+	.usable_gr_syspipe_mask		= 0xFFU,
+	.num_config_supported		= 10U,
+	.gpcgrp_gpc_count		= { 4U, 4U },
+	.gpc_count			= 8U,
+	.gpu_instance_config = {
+		{.config_name = "2 GPU instances each with 4 GPCs",
+		 .num_gpu_instances = 2U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 1U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 4U},
+			{.gpu_instance_id 		= 2U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 4U}}},
+		{.config_name = "4 GPU instances each with 2 GPCs",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 4U,
+			 .gr_syspipe_id			= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 6U,
+			 .gr_syspipe_id			= 6U,
+			 .num_gpc			= 2U}}},
+		{.config_name = "8 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 8U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 1 GPU instance with 4 GPCs + 4 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 5U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 1U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 4U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 4 GPU instances each with 1 GPC + 1 GPU instance with 4 GPCs",
+		 .num_gpu_instances = 5U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 2U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 4U}}},
+		{.config_name = "6 GPU instances - 2 GPU instances each with 2 GPCs + 4 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 6U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 4U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "6 GPU instances -  4 GPU instances each with 1 GPC + 2 GPU instances with 2 GPCs",
+		 .num_gpu_instances = 6U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 6U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 2U}}},
+		{.config_name = "5 GPU instances - 2 GPU instances each with 2 GPCs + 1 GPC instance with 2 GPCs + 2 GPU instances each with 1 GPC",
+		.num_gpu_instances = 5U,
+		.gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 4U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 1 GPC instance with 2 GPCs + 2 GPU instances each with 1 GPC + 2 GPU instances each with 2 GPCs",
+		.num_gpu_instances = 5U,
+		.gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 6U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 2U}}},
+		{.config_name = "1 GPU instance with 8 GPCs",
+		 .num_gpu_instances = 1U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 0U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 8U}}}}
+};
+
+/* Static mig config list for 7 syspipes(OxFDU) + 8 GPCs + 8 Aysnc LCEs + 3:4 gpc group config */
+static const struct nvgpu_mig_gpu_instance_config ga100_gpu_instance_config_7_syspipes = {
+	.usable_gr_syspipe_count	= 7U,
+	.usable_gr_syspipe_mask		= 0xFDU,
+	.num_config_supported		= 10U,
+	.gpcgrp_gpc_count		= { 4U, 4U },
+	.gpc_count			= 8U,
+	.gpu_instance_config = {
+		{.config_name = "2 GPU instances each with 4 GPCs",
+		 .num_gpu_instances = 2U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 1U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 4U},
+			{.gpu_instance_id 		= 2U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 4U}}},
+		{.config_name = "4 GPU instances each with 2 GPCs",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 4U,
+			 .gr_syspipe_id			= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 6U,
+			 .gr_syspipe_id			= 6U,
+			 .num_gpc			= 2U}}},
+		{.config_name = "7 GPU instances - 1 GPU instance with 2 GPCs + 6 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 7U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 1 GPU instance with 4 GPCs + 4 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 5U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 1U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 4U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "4 GPU instances - 1 GPU instance with 2 GPCs + 2 GPU instances each with 1 GPC + 1 GPU instance with 4 GPCs",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 2U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 4U}}},
+		{.config_name = "6 GPU instances - 2 GPU instances each with 2 GPCs + 4 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 6U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 4U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances -  1 GPU instance with 2 GPCs + 2 GPU instances each with 1 GPC + 2 GPU instances with 2 GPCs",
+		 .num_gpu_instances = 5U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 6U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 2U}}},
+		{.config_name = "5 GPU instances - 2 GPU instances each with 2 GPCs + 1 GPC instance with 2 GPCs + 2 GPU instances with 1 GPC",
+		.num_gpu_instances = 5U,
+		.gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 4U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 1 GPC instance with 2 GPCs + 2 GPU instances each with 1 GPC + 2 GPU instances each with 2 GPCs",
+		.num_gpu_instances = 5U,
+		.gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 6U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 2U}}},
+		{.config_name = "1 GPU instance with 8 GPCs",
+		 .num_gpu_instances = 1U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 0U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 8U}}}}
+};
+
+/* Static mig config list for 8 syspipes(OxFFU) + 7 GPCs + 8 Aysnc LCEs + 4:3 gpc group config */
+static const struct nvgpu_mig_gpu_instance_config ga100_gpu_instance_config_8_syspipes_7_gpcs_4_3_gpcgrp = {
+	.usable_gr_syspipe_count	= 8U,
+	.usable_gr_syspipe_mask		= 0xFFU,
+	.num_config_supported		= 10U,
+	.gpcgrp_gpc_count		= { 4U, 3U },
+	.gpc_count			= 7U,
+	.gpu_instance_config = {
+		{.config_name = "2 GPU instances - 1 GPU instance with 4 GPCs + 1 GPU instance with 3 GPCs",
+		 .num_gpu_instances = 2U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 1U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 4U},
+			{.gpu_instance_id 		= 2U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 3U}}},
+		{.config_name = "4 GPU instances - 3 GPU instances each with 2 GPCs + 1 GPU instance with 1 GPC",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 4U,
+			 .gr_syspipe_id			= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id			= 6U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "7 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 7U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "4 GPU instances - 1 GPU instance with 4 GPCs + 3 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 1U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 4U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 2 GPU instances with 2 GPCs + 3 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 5U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id		= 4U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "6 GPU instances - 1 GPU instance with 2 GPCs + 5 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 6U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 1 GPU instance with 2 GPCs + 2 GPU instances each with 1 GPC + 1 GPU instance with 2 GPCs + 1 GPU instance with 1 GPC",
+		 .num_gpu_instances = 5U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 2 GPU instances each with 1 GPC + 2 GPC instances each with 2 GPCs + + 1 GPC instance with 1 GPC",
+		.num_gpu_instances = 5U,
+		.gpu_instance_static_config = {
+			{.gpu_instance_id		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 4U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 4 GPU instances each with 1 GPC + 1 GPC instance with 3 GPCs",
+		.num_gpu_instances = 5U,
+		.gpu_instance_static_config = {
+			{.gpu_instance_id		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 2U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 3U}}},
+		{.config_name = "1 GPU instance with 7 GPCs",
+		 .num_gpu_instances = 1U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 0U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 7U}}}}
+};
+
+/* Static mig config list for 8 syspipes(OxFFU) + 7 GPCs + 8 Aysnc LCEs + 3:4 gpc group config */
+static const struct nvgpu_mig_gpu_instance_config ga100_gpu_instance_config_8_syspipes_7_gpcs_3_4_gpcgrp = {
+	.usable_gr_syspipe_count	= 8U,
+	.usable_gr_syspipe_mask		= 0xFFU,
+	.num_config_supported		= 10U,
+	.gpcgrp_gpc_count		= { 3U, 4U },
+	.gpc_count			= 7U,
+	.gpu_instance_config = {
+		{.config_name = "2 GPU instances - 1 GPU instance with 3 GPCs + 1 GPU instance with 4 GPCs",
+		 .num_gpu_instances = 2U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 1U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 3U},
+			{.gpu_instance_id 		= 2U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 4U}}},
+		{.config_name = "4 GPU instances - 1 GPU instance with 2 GPCs + 1 GPU instance with 1 GPC + 2 GPU instances with 2 GPCs",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id			= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 6U,
+			 .gr_syspipe_id			= 6U,
+			 .num_gpc			= 2U}}},
+		{.config_name = "7 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 7U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+ 			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "4 GPU instances - 3 GPU instances each with 1 GPC + 1 GPU instance with 4 GPCs",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 2U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 4U}}},
+		{.config_name = "6 GPU instances - 1 GPU instance with 2 GPCs + 1 GPU instance with 1 GPC + 4 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 6U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "6 GPU instances - 1 GPU instances with 2 GPCs + 5 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 6U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 1 GPU instance with 2 GPCs + 1 GPU instance with 1 GPC + 1 GPU instance with 2 GPCs + 2 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 5U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 14U,
+			 .gr_syspipe_id 		= 7U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 3 GPU instances each with 1 GPC + 2 GPC instances with 2 GPCs",
+		.num_gpu_instances = 5U,
+		.gpu_instance_static_config = {
+			{.gpu_instance_id		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 6U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 2U}}},
+		{.config_name = "4 GPU instances - 3 GPU instances each with 1 GPC + 1 GPC instance with 4 GPCs",
+		.num_gpu_instances = 4U,
+		.gpu_instance_static_config = {
+			{.gpu_instance_id		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 2U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 4U}}},
+		{.config_name = "1 GPU instance with 7 GPCs",
+		 .num_gpu_instances = 1U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 0U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 7U}}}}
+};
+
+/* Static mig config list for 8 syspipes(OxFFU) + 6 GPCs + 8 Aysnc LCEs + 3:3 gpc group config */
+static const struct nvgpu_mig_gpu_instance_config ga100_gpu_instance_config_8_syspipes_6_gpcs_3_3_gpcgrp = {
+	.usable_gr_syspipe_count	= 8U,
+	.usable_gr_syspipe_mask		= 0xFFU,
+	.num_config_supported		= 7U,
+	.gpcgrp_gpc_count		= { 3U, 3U },
+	.gpc_count			= 6U,
+	.gpu_instance_config = {
+		{.config_name = "2 GPU instances each with 3 GPCs",
+		 .num_gpu_instances = 2U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 1U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 3U},
+			{.gpu_instance_id 		= 2U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 3U}}},
+		{.config_name = "3 GPU instances - 1 GPU instance with 3 GPCs + 1 GPU instance with 2 GPCs + 1 GPU instance with 1 GPC",
+		 .num_gpu_instances = 3U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 1U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 3U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U}}},
+			{.config_name = "6 GPU instances each with 1 GPC",
+			 .num_gpu_instances = 6U,
+			 .gpu_instance_static_config = {
+			{.gpu_instance_id		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "4 GPU instances - 1 GPU instance with 3 GPCs + 3 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 1U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 3U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "4 GPU instances - 1 GPU instance with 2 GPCs + 1 GPU instance with 1 GPC + 1 GPU instance with 2 GPCs + 1 GPU instance with 1 GPC",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id			= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id			= 6U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "5 GPU instances - 1 GPU instance with 2 GPCs + 1 GPU instance with 1 GPC + 3 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 5U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 13U,
+			 .gr_syspipe_id 		= 6U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "1 GPU instance with 6 GPCs",
+		 .num_gpu_instances = 1U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 0U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 6U}}}}
+};
+
+/* Static mig config list for 8 syspipes(OxFFU) + 6 GPCs + 8 Aysnc LCEs + 4:2 gpc group config */
+static const struct nvgpu_mig_gpu_instance_config ga100_gpu_instance_config_8_syspipes_6_gpcs_4_2_gpcgrp = {
+	.usable_gr_syspipe_count	= 8U,
+	.usable_gr_syspipe_mask		= 0xFFU,
+	.num_config_supported		= 7U,
+	.gpcgrp_gpc_count		= { 4U, 2U },
+	.gpc_count			= 6U,
+	.gpu_instance_config = {
+		{.config_name = "3 GPU instances each with 2 GPCs",
+		 .num_gpu_instances = 3U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 4U,
+			 .gr_syspipe_id			= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 2U}}},
+		{.config_name = "4 GPU instances - 2 GPU instances each with 2 GPCs + 2 GPU instances each with 1 GPC ",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 4U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U}}},
+			{.config_name = "6 GPU instances each with 1 GPC",
+			 .num_gpu_instances = 6U,
+			 .gpu_instance_static_config = {
+			{.gpu_instance_id		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "4 GPU instances - 2 GPU instances each with 1 GPC + 2 GPU instances each with 2 GPCs",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 7U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 8U,
+			 .gr_syspipe_id 		= 1U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 4U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 2U}}},
+		{.config_name = "4 GPU instances - 1 GPU instance with 2 GPCs + 2 GPU instances each with 1 GPC + 1 GPU instance with 2 GPCs ",
+		 .num_gpu_instances = 4U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id			= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 10U,
+			 .gr_syspipe_id			= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 5U,
+			 .gr_syspipe_id			= 4U,
+			 .num_gpc			= 2U}}},
+		{.config_name = "5 GPU instances - 1 GPU instance with 2 GPCs + 4 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 5U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 3U,
+			 .gr_syspipe_id 		= 0U,
+			 .num_gpc			= 2U},
+			{.gpu_instance_id 		= 9U,
+			 .gr_syspipe_id 		= 2U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 10U,
+			 .gr_syspipe_id 		= 3U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 11U,
+			 .gr_syspipe_id 		= 4U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 12U,
+			 .gr_syspipe_id 		= 5U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "1 GPU instance with 6 GPCs",
+		 .num_gpu_instances = 1U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 0U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 6U}}}}
+};
+
+static int ga100_grmgr_get_first_available_gr_syspipe_id(struct gk20a *g,
+		u32 gpu_instance_id, u32 ugpu_id, u32 *gr_syspipe_id)
+{
+	u32 usable_gr_syspipe_count = g->mig.usable_gr_syspipe_count;
+	u32 index;
+
+	if (gr_syspipe_id == NULL) {
+		nvgpu_err(g, "gr_syspipe_id NULL");
+		return -EINVAL;
+	}
+	for (index = 0U; index < usable_gr_syspipe_count; index++) {
+		u32 local_gr_syspipe_id =
+			g->mig.usable_gr_syspipe_instance_id[index];
+		if (GA100_GRMGR_PSMCARB_SYS_PIPE_ALLOWED_UGPU(local_gr_syspipe_id, ugpu_id)) {
+			*gr_syspipe_id = local_gr_syspipe_id;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+const struct nvgpu_mig_gpu_instance_config *ga100_grmgr_get_mig_config_ptr(
+		struct gk20a *g) {
+	static struct nvgpu_mig_gpu_instance_config ga100_gpu_instance_default_config;
+	struct nvgpu_gpu_instance_config *gpu_instance_config;
+	u32 gpc_count_per_gpu_instance = 0U;
+	u32 num_config = 0U;
+	int err;
+
+	if ((g->mig.usable_gr_syspipe_count ==
+				ga100_gpu_instance_config_8_syspipes_6_gpcs_3_3_gpcgrp.usable_gr_syspipe_count) &&
+			(g->mig.usable_gr_syspipe_mask ==
+				ga100_gpu_instance_config_8_syspipes_6_gpcs_3_3_gpcgrp.usable_gr_syspipe_mask) &&
+			(g->mig.gpc_count ==
+				ga100_gpu_instance_config_8_syspipes_6_gpcs_3_3_gpcgrp.gpc_count) &&
+			(g->mig.gpcgrp_gpc_count[0] ==
+				ga100_gpu_instance_config_8_syspipes_6_gpcs_3_3_gpcgrp.gpcgrp_gpc_count[0]) &&
+			(g->mig.gpcgrp_gpc_count[1] ==
+				ga100_gpu_instance_config_8_syspipes_6_gpcs_3_3_gpcgrp.gpcgrp_gpc_count[1])) {
+		nvgpu_log(g, gpu_dbg_mig,
+			"Static mig config list for 8 syspipes(0xFFU) + 6 GPCs + 8 Aysnc LCEs "
+			"+ 3:3 gpc group config ");
+		return &ga100_gpu_instance_config_8_syspipes_6_gpcs_3_3_gpcgrp;
+	} else if ((g->mig.usable_gr_syspipe_count ==
+				ga100_gpu_instance_config_8_syspipes_6_gpcs_4_2_gpcgrp.usable_gr_syspipe_count) &&
+			(g->mig.usable_gr_syspipe_mask ==
+				ga100_gpu_instance_config_8_syspipes_6_gpcs_4_2_gpcgrp.usable_gr_syspipe_mask) &&
+			(g->mig.gpc_count ==
+				ga100_gpu_instance_config_8_syspipes_6_gpcs_4_2_gpcgrp.gpc_count) &&
+			(g->mig.gpcgrp_gpc_count[0] ==
+				ga100_gpu_instance_config_8_syspipes_6_gpcs_4_2_gpcgrp.gpcgrp_gpc_count[0]) &&
+			(g->mig.gpcgrp_gpc_count[1] ==
+				ga100_gpu_instance_config_8_syspipes_6_gpcs_4_2_gpcgrp.gpcgrp_gpc_count[1])) {
+		nvgpu_log(g, gpu_dbg_mig,
+			"Static mig config list for 8 syspipes(0xFFU) + 6 GPCs + 8 Aysnc LCEs "
+			"+ 4:2 gpc group config ");
+		return &ga100_gpu_instance_config_8_syspipes_6_gpcs_4_2_gpcgrp;
+	} else if ((g->mig.usable_gr_syspipe_count ==
+				ga100_gpu_instance_config_8_syspipes.usable_gr_syspipe_count) &&
+			(g->mig.usable_gr_syspipe_mask ==
+				ga100_gpu_instance_config_8_syspipes.usable_gr_syspipe_mask) &&
+			(g->mig.gpc_count ==
+				ga100_gpu_instance_config_8_syspipes.gpc_count) &&
+			(g->mig.gpcgrp_gpc_count[0] ==
+				ga100_gpu_instance_config_8_syspipes.gpcgrp_gpc_count[0]) &&
+			(g->mig.gpcgrp_gpc_count[1] ==
+				ga100_gpu_instance_config_8_syspipes.gpcgrp_gpc_count[1])) {
+		nvgpu_log(g, gpu_dbg_mig,
+			"Static mig config list for 8 syspipes(0xFFU) + 8 GPCs + 8 Aysnc LCEs "
+				"+ 4:4 gpc group config ");
+		return &ga100_gpu_instance_config_8_syspipes;
+	} else if ((g->mig.usable_gr_syspipe_count ==
+				ga100_gpu_instance_config_7_syspipes.usable_gr_syspipe_count) &&
+			(g->mig.usable_gr_syspipe_mask ==
+				ga100_gpu_instance_config_7_syspipes.usable_gr_syspipe_mask) &&
+			(g->mig.gpc_count ==
+				ga100_gpu_instance_config_7_syspipes.gpc_count) &&
+			(g->mig.gpcgrp_gpc_count[0] ==
+				ga100_gpu_instance_config_7_syspipes.gpcgrp_gpc_count[0]) &&
+			(g->mig.gpcgrp_gpc_count[1] ==
+				ga100_gpu_instance_config_7_syspipes.gpcgrp_gpc_count[1])) {
+		nvgpu_log(g, gpu_dbg_mig,
+			"Static mig config list for 7 syspipes(0xFDU) + 8 GPCs + 8 Aysnc LCEs "
+				"+ 4:4 gpc group config ");
+		return &ga100_gpu_instance_config_7_syspipes;
+	} else if ((g->mig.usable_gr_syspipe_count ==
+				ga100_gpu_instance_config_8_syspipes_7_gpcs_4_3_gpcgrp.usable_gr_syspipe_count) &&
+			(g->mig.usable_gr_syspipe_mask ==
+				ga100_gpu_instance_config_8_syspipes_7_gpcs_4_3_gpcgrp.usable_gr_syspipe_mask) &&
+			(g->mig.gpc_count ==
+				ga100_gpu_instance_config_8_syspipes_7_gpcs_4_3_gpcgrp.gpc_count) &&
+			(g->mig.gpcgrp_gpc_count[0] ==
+				ga100_gpu_instance_config_8_syspipes_7_gpcs_4_3_gpcgrp.gpcgrp_gpc_count[0]) &&
+			(g->mig.gpcgrp_gpc_count[1] ==
+				ga100_gpu_instance_config_8_syspipes_7_gpcs_4_3_gpcgrp.gpcgrp_gpc_count[1])) {
+		nvgpu_log(g, gpu_dbg_mig,
+			"Static mig config list for 8 syspipes(0xFFU) + 7 GPCs + 8 Aysnc LCEs "
+				"+ 4:3 gpc group config ");
+		return &ga100_gpu_instance_config_8_syspipes_7_gpcs_4_3_gpcgrp;
+	} else if ((g->mig.usable_gr_syspipe_count ==
+				ga100_gpu_instance_config_8_syspipes_7_gpcs_3_4_gpcgrp.usable_gr_syspipe_count) &&
+			(g->mig.usable_gr_syspipe_mask ==
+				ga100_gpu_instance_config_8_syspipes_7_gpcs_3_4_gpcgrp.usable_gr_syspipe_mask) &&
+			(g->mig.gpc_count ==
+				ga100_gpu_instance_config_8_syspipes_7_gpcs_3_4_gpcgrp.gpc_count) &&
+			(g->mig.gpcgrp_gpc_count[0] ==
+				ga100_gpu_instance_config_8_syspipes_7_gpcs_3_4_gpcgrp.gpcgrp_gpc_count[0]) &&
+			(g->mig.gpcgrp_gpc_count[1] ==
+				ga100_gpu_instance_config_8_syspipes_7_gpcs_3_4_gpcgrp.gpcgrp_gpc_count[1])) {
+		nvgpu_log(g, gpu_dbg_mig,
+			"Static mig config list for 8 syspipes(0xFFU) + 7 GPCs + 8 Aysnc LCEs "
+				"+ 3:4 gpc group config ");
+		return &ga100_gpu_instance_config_8_syspipes_7_gpcs_3_4_gpcgrp;
+	}
+
+	/* Fall back to default config */
+	ga100_gpu_instance_default_config.usable_gr_syspipe_count =
+		g->mig.usable_gr_syspipe_count;
+	ga100_gpu_instance_default_config.usable_gr_syspipe_mask =
+		g->mig.usable_gr_syspipe_mask;
+	ga100_gpu_instance_default_config.gpcgrp_gpc_count[0] =
+		g->mig.gpcgrp_gpc_count[0];
+	ga100_gpu_instance_default_config.gpcgrp_gpc_count[1] =
+		g->mig.gpcgrp_gpc_count[1];
+	ga100_gpu_instance_default_config.gpc_count = g->mig.gpc_count;
+
+	gpc_count_per_gpu_instance = (g->mig.gpc_count / 2);
+
+	if ((g->mig.usable_gr_syspipe_count >= 0x2U) &&
+			(g->mig.gpcgrp_gpc_count[0] >= gpc_count_per_gpu_instance) &&
+			(g->mig.gpcgrp_gpc_count[1] >= gpc_count_per_gpu_instance)) {
+		u32 index;
+		u32 start_id_of_half_partition = 0x1;
+		gpu_instance_config =
+			&ga100_gpu_instance_default_config.gpu_instance_config[num_config];
+		snprintf(gpu_instance_config->config_name,
+			NVGPU_MIG_MAX_CONFIG_NAME_SIZE,
+			"2 GPU instances each with %u GPCs", gpc_count_per_gpu_instance);
+		gpu_instance_config->num_gpu_instances = 2U;
+
+		for (index = 0U; index < 2U; index++) {
+			struct nvgpu_gpu_instance_static_config
+				*gpu_instance_static_config =
+					&gpu_instance_config->gpu_instance_static_config[index];
+			gpu_instance_static_config->gpu_instance_id =
+				nvgpu_safe_add_u32(start_id_of_half_partition, index);
+
+			err = ga100_grmgr_get_first_available_gr_syspipe_id(g,
+					nvgpu_safe_add_u32(start_id_of_half_partition, index),
+					index,
+					&gpu_instance_static_config->gr_syspipe_id);
+			if (err != 0) {
+				nvgpu_err(g, "ga100_grmgr_get_first_available_gr_syspipe_id-failed "
+					"index[%u] gpu_instance_id[%u] ",
+					index,
+					gpu_instance_static_config->gpu_instance_id);
+				return NULL;
+			}
+			gpu_instance_static_config->num_gpc = gpc_count_per_gpu_instance;
+
+			nvgpu_log(g, gpu_dbg_mig,
+				"Fall back to default HALF partition index[%u] config_index[%u] "
+					"gpu_instance_id[%u] gr_syspipe_id[%u] num_gpc[%u]",
+					index,
+					num_config,
+					gpu_instance_static_config->gpu_instance_id,
+					gpu_instance_static_config->gr_syspipe_id,
+					gpu_instance_static_config->num_gpc);
+		}
+		num_config++;
+	}
+
+	gpu_instance_config =
+		&ga100_gpu_instance_default_config.gpu_instance_config[num_config];
+
+	snprintf(gpu_instance_config->config_name,
+		NVGPU_MIG_MAX_CONFIG_NAME_SIZE,
+		"1 GPU instance with %u GPCs", g->mig.gpc_count);
+	gpu_instance_config->num_gpu_instances = 1U;
+	gpu_instance_config->gpu_instance_static_config[0].gpu_instance_id = 0U;
+	gpu_instance_config->gpu_instance_static_config[0].gr_syspipe_id = 0U;
+	gpu_instance_config->gpu_instance_static_config[0].num_gpc =
+		g->mig.gpc_count;
+
+	++num_config;
+	ga100_gpu_instance_default_config.num_config_supported = num_config;
+
+	nvgpu_err(g,
+		"mig gpu instance config is not found for usable_gr_syspipe_count[%u] "
+			"usable_gr_syspipe_mask[%x] gpc[%u] "
+			"fall back to %u default config mode",
+		g->mig.usable_gr_syspipe_count,
+		g->mig.usable_gr_syspipe_mask,
+		g->mig.gpc_count,
+		num_config);
+	return ((const struct nvgpu_mig_gpu_instance_config *)
+		&ga100_gpu_instance_default_config);
+}
+
+u32 ga100_grmgr_get_max_sys_pipes(struct gk20a *g)
+{
+	return smcarb_max_partitionable_sys_pipes_v();
+}
+
+u32 ga100_grmgr_get_allowed_swizzid_size(struct gk20a *g)
+{
+	return smcarb_allowed_swizzid__size1_v();
+}
+
+int ga100_grmgr_get_gpc_instance_gpcgrp_id(struct gk20a *g,
+		u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id)
+{
+	u32 local_gpcgrp_id;
+	bool supported;
+
+	if ((gr_syspipe_id >= g->ops.grmgr.get_max_sys_pipes(g)) ||
+			(gpu_instance_id >= smcarb_allowed_swizzid__size1_v()) ||
+			(gpcgrp_id == NULL)) {
+		nvgpu_err(g,
+			"[Invalid param] gr_syspipe_id[%u %u] gpu_instance_id[%u %u] "
+				"or gpcgrp_id == NULL ",
+				gr_syspipe_id, g->ops.grmgr.get_max_sys_pipes(g),
+				gpu_instance_id, smcarb_allowed_swizzid__size1_v());
+		return -EINVAL;
+	}
+
+	for (local_gpcgrp_id = 0U; local_gpcgrp_id < 2U; local_gpcgrp_id++) {
+		supported = GA100_GRMGR_PSMCARB_ALLOWED_UGPU(
+			gpu_instance_id, local_gpcgrp_id);
+		supported &= GA100_GRMGR_PSMCARB_SYS_PIPE_ALLOWED_UGPU(
+			gr_syspipe_id, local_gpcgrp_id);
+		if (supported) {
+			*gpcgrp_id = local_gpcgrp_id;
+			nvgpu_log(g, gpu_dbg_mig,
+					"Found [%u] gpcgrp id for gpu_instance_id[%u] "
+						"gr_syspipe_id[%u] ",
+					*gpcgrp_id,
+					gpu_instance_id,
+					gr_syspipe_id);
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
diff --git a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga100.h b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga100.h
new file mode 100644
index 000000000..41b5dfbae
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga100.h
@@ -0,0 +1,37 @@
+/*
+ * GA100 GR MANAGER
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GRMGR_GA100_H
+#define NVGPU_GRMGR_GA100_H
+
+struct gk20a;
+
+const struct nvgpu_mig_gpu_instance_config *ga100_grmgr_get_mig_config_ptr(
+		struct gk20a *g);
+u32 ga100_grmgr_get_max_sys_pipes(struct gk20a *g);
+u32 ga100_grmgr_get_allowed_swizzid_size(struct gk20a *g);
+int ga100_grmgr_get_gpc_instance_gpcgrp_id(struct gk20a *g,
+		u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id);
+
+#endif /* NVGPU_GRMGR_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
new file mode 100644
index 000000000..5c78018c1
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
@@ -0,0 +1,1008 @@
+/*
+ * GA10B GR MANAGER
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/grmgr.h>
+
+#include "grmgr_ga10b.h"
+#include <nvgpu/hw/ga10b/hw_smcarb_ga10b.h>
+
+#ifdef CONFIG_NVGPU_MIG
+#include <nvgpu/enabled.h>
+#include <nvgpu/string.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/device.h>
+
+#define GA10B_GRMGR_PSMCARB_ALLOWED_UGPU(gpu_instance_id, gpcgrp_id) \
+	(((gpu_instance_id) == 0U))
+
+/* Static mig config list for 2 syspipes(0x3U) + 2 GPCs + 2 Aysnc LCEs + 2:0 gpc group config */
+static const struct nvgpu_mig_gpu_instance_config ga10b_gpu_instance_config = {
+	.usable_gr_syspipe_count	= 2U,
+	.usable_gr_syspipe_mask		= 0x3U,
+	.num_config_supported		= 2U,
+	.gpcgrp_gpc_count		= { 2U, 0U },
+	.gpc_count			= 2U,
+	.gpu_instance_config = {
+		{.config_name = "2 GPU instances each with 1 GPC",
+		 .num_gpu_instances = 2U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 0U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 1U},
+			{.gpu_instance_id 		= 0U,
+			 .gr_syspipe_id			= 1U,
+			 .num_gpc			= 1U}}},
+		{.config_name = "1 GPU instance with 2 GPCs",
+		 .num_gpu_instances = 1U,
+		 .gpu_instance_static_config = {
+			{.gpu_instance_id 		= 0U,
+			 .gr_syspipe_id			= 0U,
+			 .num_gpc			= 2U}}}}
+};
+
+const struct nvgpu_mig_gpu_instance_config *ga10b_grmgr_get_mig_config_ptr(
+		struct gk20a *g) {
+	static struct nvgpu_mig_gpu_instance_config ga10b_gpu_instance_default_config;
+	struct nvgpu_gpu_instance_config *gpu_instance_config =
+		&ga10b_gpu_instance_default_config.gpu_instance_config[0];
+
+	if ((g->mig.usable_gr_syspipe_count ==
+				ga10b_gpu_instance_config.usable_gr_syspipe_count) &&
+			(g->mig.usable_gr_syspipe_mask ==
+				ga10b_gpu_instance_config.usable_gr_syspipe_mask) &&
+			(g->mig.gpc_count ==
+				ga10b_gpu_instance_config.gpc_count) &&
+			(g->mig.gpcgrp_gpc_count[0] ==
+				ga10b_gpu_instance_config.gpcgrp_gpc_count[0]) &&
+			(g->mig.gpcgrp_gpc_count[1] ==
+				ga10b_gpu_instance_config.gpcgrp_gpc_count[1])) {
+		nvgpu_log(g, gpu_dbg_mig,
+			"Static mig config list for 2 syspipes + 2 GPCs + 2 Aysnc LCEs "
+				"+ 2:0 gpc group config ");
+		return &ga10b_gpu_instance_config;
+	}
+
+	/* Fall back to default config */
+	ga10b_gpu_instance_default_config.usable_gr_syspipe_count =
+		g->mig.usable_gr_syspipe_count;
+	ga10b_gpu_instance_default_config.usable_gr_syspipe_mask =
+		g->mig.usable_gr_syspipe_mask;
+	ga10b_gpu_instance_default_config.num_config_supported = 1U;
+	ga10b_gpu_instance_default_config.gpcgrp_gpc_count[0] =
+		g->mig.gpcgrp_gpc_count[0];
+	ga10b_gpu_instance_default_config.gpcgrp_gpc_count[1] =
+		g->mig.gpcgrp_gpc_count[1];
+	ga10b_gpu_instance_default_config.gpc_count = g->mig.gpc_count;
+	snprintf(gpu_instance_config->config_name,
+		NVGPU_MIG_MAX_CONFIG_NAME_SIZE,
+		"1 GPU instance with %u GPCs", g->mig.gpc_count);
+	gpu_instance_config->num_gpu_instances = 1U;
+	gpu_instance_config->gpu_instance_static_config[0].gpu_instance_id = 0U;
+	gpu_instance_config->gpu_instance_static_config[0].gr_syspipe_id = 0U;
+	gpu_instance_config->gpu_instance_static_config[0].num_gpc =
+		g->mig.gpc_count;
+
+	nvgpu_err(g,
+		"mig gpu instance config is not found for usable_gr_syspipe_count[%u %u] "
+			"usable_gr_syspipe_mask[%x %x] gpc[%u %u] "
+			"fall back to 1 GPU instance with %u GPCs",
+		g->mig.usable_gr_syspipe_count,
+		ga10b_gpu_instance_config.usable_gr_syspipe_count,
+		g->mig.usable_gr_syspipe_mask,
+		ga10b_gpu_instance_config.usable_gr_syspipe_mask,
+		g->mig.gpc_count,
+		ga10b_gpu_instance_config.gpc_count,
+		g->mig.gpc_count);
+	return ((const struct nvgpu_mig_gpu_instance_config *)
+		&ga10b_gpu_instance_default_config);
+}
+
+void ga10b_grmgr_get_gpcgrp_count(struct gk20a *g)
+{
+	u32 gpcgrp_gpc_count[2] = {0U, 0U};
+	u32 logical_gpc_id;
+	struct nvgpu_gpc *gpcs = g->mig.gpu_instance[0].gr_syspipe.gpcs;
+	u32 reg_val = nvgpu_readl(g, smcarb_ugpu_gpc_count_r());
+	g->mig.gpcgrp_gpc_count[0] = smcarb_ugpu_gpc_count_ugpu0_v(reg_val);
+	g->mig.gpcgrp_gpc_count[1] = smcarb_ugpu_gpc_count_ugpu1_v(reg_val);
+
+	for (logical_gpc_id = 0U; logical_gpc_id < g->mig.gpc_count;
+			logical_gpc_id++) {
+		if (gpcs[logical_gpc_id].gpcgrp_id == 0U) {
+			++gpcgrp_gpc_count[0];
+		} else if (gpcs[logical_gpc_id].gpcgrp_id == 1U) {
+			++gpcgrp_gpc_count[1];
+		} else {
+			nvgpu_err(g, "invalid gpcgrp_id[%d]",
+				gpcs[logical_gpc_id].gpcgrp_id);
+			nvgpu_assert(gpcs[logical_gpc_id].gpcgrp_id <= 1U);
+		}
+	}
+
+	if ((gpcgrp_gpc_count[0] != g->mig.gpcgrp_gpc_count[0]) ||
+			(gpcgrp_gpc_count[1] != g->mig.gpcgrp_gpc_count[1])) {
+		nvgpu_log(g, gpu_dbg_mig,
+			"expected gpcgrp0_gpc_count[%u] actual gpcgrp0_gpc_count[%u] "
+				"expected gpcgrp1_gpc_count[%u] actual gpcgrp1_gpc_count[%u] "
+				"g->mig.gpc_count[%u]",
+			g->mig.gpcgrp_gpc_count[0], gpcgrp_gpc_count[0],
+			g->mig.gpcgrp_gpc_count[1], gpcgrp_gpc_count[1],
+			g->mig.gpc_count);
+	}
+
+	g->mig.gpcgrp_gpc_count[0] = gpcgrp_gpc_count[0];
+	g->mig.gpcgrp_gpc_count[1] = gpcgrp_gpc_count[1];
+}
+
+static bool ga10b_grmgr_is_syspipe_lce(struct gk20a *g,
+				      const struct nvgpu_device *gr_dev,
+				      const struct nvgpu_device *lce_dev)
+{
+	u32 gr_fb_thread_id;
+	u32 lce_fb_thread_id;
+
+	gr_fb_thread_id = g->ops.runlist.get_esched_fb_thread_id(g,
+		gr_dev->next.rl_pri_base);
+
+	lce_fb_thread_id = g->ops.runlist.get_esched_fb_thread_id(g,
+		lce_dev->next.rl_pri_base);
+
+	nvgpu_log(g, gpu_dbg_mig,
+		"gr_engine_id[%u] lce_engine_id[%u] "
+			"gr_fb_thread_id[%u] lce_fb_thread_id[%u] ",
+		gr_dev->engine_id, lce_dev->engine_id,
+		gr_fb_thread_id, lce_fb_thread_id);
+
+	return (gr_fb_thread_id == lce_fb_thread_id);
+}
+
+static u32 ga10b_grmgr_get_local_gr_syspipe_index(struct gk20a *g,
+		u32 gr_syspipe_id)
+{
+	u32 usable_gr_syspipe_mask = g->mig.usable_gr_syspipe_mask;
+	u32 local_gr_syspipe_index = 0U;
+	u32 gr_syspipe_mask = (usable_gr_syspipe_mask &
+		nvgpu_safe_sub_u32(BIT32(gr_syspipe_id), 1U));
+
+	while (gr_syspipe_mask != 0U) {
+		u32 bit_position = nvgpu_safe_sub_u32(
+			nvgpu_ffs(gr_syspipe_mask), 1UL);
+		++local_gr_syspipe_index;
+		gr_syspipe_mask ^= BIT32(bit_position);
+	}
+
+	nvgpu_log(g, gpu_dbg_mig,
+		"usable_gr_syspipe_mask[%x] gr_syspipe_id[%u] "
+			"local_gr_syspipe_index[%u] ",
+		usable_gr_syspipe_mask, gr_syspipe_id,
+		local_gr_syspipe_index);
+
+	return local_gr_syspipe_index;
+}
+
+static u32 ga10b_grmgr_get_gr_syspipe_id_from_local_gr_syspipe_index(
+		struct gk20a *g,
+		u32 local_gr_syspipe_index)
+{
+	u32 usable_gr_syspipe_mask = g->mig.usable_gr_syspipe_mask;
+	u32 temp_gr_syspipe_index = 0U;
+	u32 gr_syspipe_id = 0U;
+	u32 max_allowed_syspipe_index = nvgpu_safe_add_u32(
+		local_gr_syspipe_index, 1U);
+
+	nvgpu_assert(max_allowed_syspipe_index <= g->mig.usable_gr_syspipe_count);
+
+	while (temp_gr_syspipe_index < max_allowed_syspipe_index) {
+		gr_syspipe_id = nvgpu_safe_sub_u32(
+			nvgpu_ffs(usable_gr_syspipe_mask), 1UL);
+		++temp_gr_syspipe_index;
+		usable_gr_syspipe_mask ^= BIT32(gr_syspipe_id);
+	}
+
+	nvgpu_log(g, gpu_dbg_mig,
+		"usable_gr_syspipe_mask[%x] local_gr_syspipe_index[%u] "
+			"num_gr[%u] gr_syspipe_id[%u]",
+		g->mig.usable_gr_syspipe_mask, local_gr_syspipe_index,
+		g->mig.usable_gr_syspipe_count, gr_syspipe_id);
+
+	return gr_syspipe_id;
+}
+
+static u32 ga10b_grmgr_get_num_gr_syspipe_enabled(struct gk20a *g,
+		u32 start_gr_syspipe_id,
+		u32 num_gpc)
+{
+	u32 usable_gr_syspipe_mask = g->mig.usable_gr_syspipe_mask;
+	u32 expected_gr_syspipe_mask = ((nvgpu_safe_sub_u32(BIT32(num_gpc), 1U)) <<
+		start_gr_syspipe_id);
+	u32 gr_syspipe_enabled_mask = (usable_gr_syspipe_mask &
+		expected_gr_syspipe_mask);
+	u32 gr_syspipe_enabled_count = 0U;
+
+	while (gr_syspipe_enabled_mask != 0U) {
+		u32 bit_pos = nvgpu_safe_sub_u32(
+					nvgpu_ffs(gr_syspipe_enabled_mask), 1UL);
+		gr_syspipe_enabled_mask ^= BIT32(bit_pos);
+		++gr_syspipe_enabled_count;
+	}
+
+	nvgpu_log(g, gpu_dbg_mig,
+		"start_gr_syspipe_id[%u] num_gpc[%u] "
+			"usable_gr_syspipe_mask[%x] expected_gr_syspipe_mask[%x] "
+			"gr_syspipe_enabled_count[%u] ",
+		start_gr_syspipe_id, num_gpc, usable_gr_syspipe_mask,
+		expected_gr_syspipe_mask, gr_syspipe_enabled_count);
+
+	return gr_syspipe_enabled_count;
+}
+
+static int ga10b_grmgr_get_gpu_instance(struct gk20a *g,
+		u32 config_id,
+		struct nvgpu_gpu_instance gpu_instance[],
+		struct nvgpu_gpc gpcs[],
+		u32 *num_gpu_instances)
+{
+	int err = 0;
+	u32 num_gr;
+	const struct nvgpu_device *lces[NVGPU_MIG_MAX_ENGINES] = { };
+	u32 num_lce;
+	struct nvgpu_gr_syspipe *gr_syspipe;
+	u32 index;
+	u32 physical_ce_id;
+	u32 logical_gpc_id;
+	bool is_memory_partition_supported;
+	u32 temp_num_gpu_instances;
+	u32 lce_mask;
+	u32 gpc_mask;
+	u32 temp_lce_mask;
+	u32 temp_gpc_mask;
+	u32 temp_lce_cnt;
+	u32 temp_gpc_cnt;
+	u32 local_gr_syspipe_index;
+	u32 gr_syspipe_enabled_count = 0U;
+	u32 veid_count_per_gpc;
+	u32 veid_start_offset = 0U;
+	u32 num_gpc = g->mig.gpc_count;
+	u32 gpu_instance_gpcgrp_id[NVGPU_MIG_MAX_GPU_INSTANCES];
+	const struct nvgpu_gpu_instance_static_config *gpu_instance_static_config;
+	u32 *gr_instance_id_per_swizzid;
+	const struct nvgpu_mig_gpu_instance_config *mig_gpu_instance_config =
+		g->ops.grmgr.get_mig_config_ptr(g);
+	u32 allowed_swizzid_size = g->ops.grmgr.get_allowed_swizzid_size(g);
+	u32 max_subctx_count = g->ops.gr.init.get_max_subctx_count();
+	u32 max_fbps_count = g->mig.max_fbps_count;
+	u32 physical_fbp_en_mask = g->mig.gpu_instance[0].fbp_en_mask;
+	u32 *physical_fbp_rop_l2_en_mask = g->mig.gpu_instance[0].fbp_rop_l2_en_mask;
+
+	if ((mig_gpu_instance_config == NULL) || (num_gpc > NVGPU_MIG_MAX_GPCS)) {
+		nvgpu_err(g,"mig_gpu_instance_config NULL "
+			"or (num_gpc > NVGPU_MIG_MAX_GPCS)[%u %u] ",
+			num_gpc, NVGPU_MIG_MAX_GPCS);
+		return -EINVAL;
+	}
+
+	temp_num_gpu_instances = mig_gpu_instance_config->gpu_instance_config[config_id].num_gpu_instances;
+
+	if ((config_id >= mig_gpu_instance_config->num_config_supported) ||
+		(gpu_instance == NULL) || (num_gpu_instances == NULL) ||
+		(temp_num_gpu_instances > g->ops.grmgr.get_max_sys_pipes(g))) {
+		nvgpu_err(g,
+			"[Invalid param] conf_id[%u %u] num_gpu_inst[%u %u] ",
+			config_id, mig_gpu_instance_config->num_config_supported,
+			temp_num_gpu_instances, g->ops.grmgr.get_max_sys_pipes(g));
+		return -EINVAL;
+	}
+
+	gpu_instance_static_config =
+		mig_gpu_instance_config->gpu_instance_config[config_id].gpu_instance_static_config;
+	nvgpu_log(g, gpu_dbg_mig,
+		"temp_num_gpu_instances[%u] config_name[%s] ",
+		temp_num_gpu_instances,
+		mig_gpu_instance_config->gpu_instance_config[config_id].config_name);
+
+	/* TODO : Enable SMC memory partition support. */
+	is_memory_partition_supported = false; /*(allowed_swizzid_size > 1U); */
+
+	num_lce = nvgpu_device_get_async_copies(g, lces, NVGPU_MIG_MAX_ENGINES);
+	nvgpu_assert(num_lce > 0U);
+
+	num_gr = g->mig.usable_gr_syspipe_count;
+	if (num_gr < temp_num_gpu_instances) {
+		nvgpu_err(g, "(num_gr < temp_num_gpu_instances)[%u %u]",
+			num_gr, temp_num_gpu_instances);
+		return -EINVAL;
+	}
+
+	lce_mask = nvgpu_safe_sub_u32(BIT32(num_lce), 1U);
+	gpc_mask = nvgpu_safe_sub_u32(BIT32(num_gpc), 1U);
+
+	gr_instance_id_per_swizzid = (u32 *)nvgpu_kzalloc(g,
+		nvgpu_safe_mult_u32(sizeof(u32), allowed_swizzid_size));
+	if (gr_instance_id_per_swizzid == NULL) {
+		nvgpu_err(g, "(gr_instance_id_per_swizzid- kzalloc failed");
+		return -ENOMEM;
+	}
+
+	nvgpu_log(g, gpu_dbg_mig, "num_gr[%u] num_lce[%u] ", num_gr, num_lce);
+
+	nvgpu_assert(max_subctx_count > 0U);
+
+	veid_count_per_gpc = (max_subctx_count / num_gpc);
+
+	nvgpu_log(g, gpu_dbg_mig, "veid_count_per_gpc[%u] num_gpc[%u] ",
+		veid_count_per_gpc, num_gpc);
+
+	for (index = 0U; index < temp_num_gpu_instances; index++) {
+		u32 gr_syspipe_id =
+			gpu_instance_static_config[index].gr_syspipe_id;
+
+		local_gr_syspipe_index =
+			ga10b_grmgr_get_local_gr_syspipe_index(g, gr_syspipe_id);
+		if (local_gr_syspipe_index >= num_gr) {
+			nvgpu_err(g,
+				"GR index config mismatch, "
+				"num_gr[%d] actual_gr_index[%u] ",
+				num_gr, local_gr_syspipe_index);
+			err = -EINVAL;
+			goto exit;
+		}
+
+		if ((g->mig.usable_gr_syspipe_instance_id[local_gr_syspipe_index] !=
+				gr_syspipe_id)) {
+			nvgpu_err(g,
+				"GR SYSPIPE ID mismatch expected[%u] actual[%u] "
+				"or (gr_engine_info == NULL) ",
+				gr_syspipe_id,
+				g->mig.usable_gr_syspipe_instance_id[local_gr_syspipe_index]);
+			err = -EINVAL;
+			goto exit;
+		}
+
+		gr_syspipe = &gpu_instance[index].gr_syspipe;
+
+		if (g->ops.grmgr.get_gpc_instance_gpcgrp_id(g,
+				gpu_instance_static_config[index].gpu_instance_id,
+				gpu_instance_static_config[index].gr_syspipe_id,
+				&gpu_instance_gpcgrp_id[index]) != 0) {
+			nvgpu_err(g,
+				"g->ops.grmgr.get_gpc_instance_gpcgrp_id -failed");
+			err = -EINVAL;
+			goto exit;
+		}
+
+		temp_gpc_cnt = 0U;
+		temp_gpc_mask = gpc_mask;
+		gr_syspipe->num_gpc = 0;
+		while (temp_gpc_mask && (temp_gpc_cnt <
+				(gpu_instance_static_config[index].num_gpc))) {
+
+			logical_gpc_id = nvgpu_safe_sub_u32(
+					nvgpu_ffs(temp_gpc_mask), 1UL);
+
+			if ((gpcs[logical_gpc_id].gpcgrp_id ==
+					gpu_instance_gpcgrp_id[index]) ||
+					(temp_num_gpu_instances == 1U)) {
+				gr_syspipe->gpcs[temp_gpc_cnt].logical_id =
+					gpcs[logical_gpc_id].logical_id;
+				gr_syspipe->gpcs[temp_gpc_cnt].physical_id =
+					gpcs[logical_gpc_id].physical_id;
+				gr_syspipe->gpcs[temp_gpc_cnt].gpcgrp_id =
+					gpcs[logical_gpc_id].gpcgrp_id;
+
+				gpc_mask ^= BIT32(logical_gpc_id);
+
+				nvgpu_log(g, gpu_dbg_mig,
+					"gpu_instance_id[%u] "
+						"gr_instance_id[%u] gr_syspipe_id[%u] "
+						"gpc_local_id[%u] gpc_logical_id[%u] "
+						"gpc_physical_id[%u]  gpc_grpid[%u] "
+						"free_gpc_mask[%x] gr_syspipe_id[%u]",
+					gpu_instance_static_config[index].gpu_instance_id,
+					index,
+					gpu_instance_static_config[index].gr_syspipe_id,
+					temp_gpc_cnt,
+					gr_syspipe->gpcs[temp_gpc_cnt].logical_id,
+					gr_syspipe->gpcs[temp_gpc_cnt].physical_id,
+					gr_syspipe->gpcs[temp_gpc_cnt].gpcgrp_id,
+					gpc_mask,
+					gpu_instance_static_config[index].gr_syspipe_id);
+
+				++temp_gpc_cnt;
+				++gr_syspipe->num_gpc;
+			}
+			temp_gpc_mask ^= BIT32(logical_gpc_id);
+		}
+
+		if (gr_syspipe->num_gpc !=
+				gpu_instance_static_config[index].num_gpc) {
+			nvgpu_err(g,
+				"GPC config mismatch, [%d] gpu_instance_id[%u] "
+					"gr_syspipe_id[%u] available[%u] expected[%u] ",
+				index,
+				gpu_instance_static_config[index].gpu_instance_id,
+				gpu_instance_static_config[index].gr_syspipe_id,
+				gr_syspipe->num_gpc,
+				gpu_instance_static_config[index].num_gpc);
+			err = -EINVAL;
+			goto exit;
+		}
+
+		gpu_instance[index].gpu_instance_id =
+			gpu_instance_static_config[index].gpu_instance_id;
+		gr_syspipe->gr_instance_id = gr_instance_id_per_swizzid[
+			gpu_instance[index].gpu_instance_id]++;
+		gr_syspipe->gr_syspipe_id =
+			gpu_instance_static_config[index].gr_syspipe_id;
+		gr_syspipe->gpc_mask = nvgpu_safe_sub_u32(
+			BIT32(gr_syspipe->num_gpc), 1U);
+		gr_syspipe->gr_dev = nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS,
+						      gr_syspipe->gr_syspipe_id);
+		nvgpu_assert(gr_syspipe->gr_dev != NULL);
+
+		gr_syspipe->max_veid_count_per_tsg = nvgpu_safe_mult_u32(
+			veid_count_per_gpc, gr_syspipe->num_gpc);
+
+		/* Add extra VEIDs in 1st gpu instance */
+		if (index == 0U) {
+			gr_syspipe->max_veid_count_per_tsg =
+				nvgpu_safe_add_u32(gr_syspipe->max_veid_count_per_tsg,
+					(max_subctx_count % num_gpc));
+		}
+
+		gr_syspipe->veid_start_offset = veid_start_offset;
+		veid_start_offset = nvgpu_safe_add_u32(
+			veid_start_offset,
+			gr_syspipe->max_veid_count_per_tsg);
+
+		gpu_instance[index].is_memory_partition_supported =
+			is_memory_partition_supported;
+		gpu_instance[index].gpu_instance_type = NVGPU_MIG_TYPE_MIG;
+
+		if (g->mig.is_nongr_engine_sharable ||
+				(temp_num_gpu_instances == 1U)) {
+			gpu_instance[index].num_lce = num_lce;
+			nvgpu_memcpy((u8 *)gpu_instance[index].lce_devs,
+				     (u8 *)lces,
+				     nvgpu_safe_mult_u32(sizeof(*lces), num_lce));
+		} else {
+			temp_lce_cnt = 0U;
+			temp_lce_mask = lce_mask;
+			gr_syspipe_enabled_count =
+				ga10b_grmgr_get_num_gr_syspipe_enabled(g,
+					gr_syspipe->gr_syspipe_id, gr_syspipe->num_gpc);
+			while (temp_lce_mask &&
+					(temp_lce_cnt < gr_syspipe_enabled_count)) {
+				u32 gr_syspipe_id =
+					ga10b_grmgr_get_gr_syspipe_id_from_local_gr_syspipe_index(g,
+						nvgpu_safe_add_u32(local_gr_syspipe_index,
+							temp_lce_cnt));
+				physical_ce_id = nvgpu_safe_sub_u32(
+					nvgpu_ffs(temp_lce_mask), 1UL);
+				if (ga10b_grmgr_is_syspipe_lce(g,
+						nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS,
+							gr_syspipe_id),
+						lces[physical_ce_id])) {
+					gpu_instance[index].lce_devs[temp_lce_cnt] =
+						lces[physical_ce_id];
+					++temp_lce_cnt;
+					lce_mask ^= BIT32(physical_ce_id);
+					nvgpu_log(g, gpu_dbg_mig,
+						"[%d] gpu_instance_id[%u] "
+							"gr_instance_id[%u] gr_syspipe_id[%u] "
+							"gr_syspipe_id[%u] "
+							"gr_engine_id [%u] lce_engine_id[%u] "
+							"gr_syspipe_enabled_count[%u] ",
+						index,
+						gpu_instance[index].gpu_instance_id,
+						gr_syspipe->gr_instance_id,
+						gr_syspipe->gr_syspipe_id,
+						gr_syspipe_id,
+						nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS,
+								 gr_syspipe_id)->engine_id,
+						lces[physical_ce_id]->engine_id,
+						gr_syspipe_enabled_count);
+				}
+				temp_lce_mask ^= BIT32(physical_ce_id);
+			}
+			gpu_instance[index].num_lce = temp_lce_cnt;
+
+			if (index == nvgpu_safe_sub_u32(temp_num_gpu_instances, 1U)) {
+				u32 gpu_instance_id = 0U;
+				while ((lce_mask != 0U) &&
+						(temp_lce_cnt < NVGPU_MIG_MAX_ENGINES) &&
+						(gpu_instance_id < temp_num_gpu_instances)) {
+					struct nvgpu_gr_syspipe *local_gr_syspipe =
+						&gpu_instance[gpu_instance_id].gr_syspipe;
+					physical_ce_id = nvgpu_safe_sub_u32(
+						nvgpu_ffs(lce_mask), 1UL);
+					temp_lce_cnt = gpu_instance[gpu_instance_id].num_lce;
+					gpu_instance[gpu_instance_id].lce_devs[temp_lce_cnt] =
+						lces[physical_ce_id];
+					lce_mask ^= BIT32(physical_ce_id);
+					++temp_lce_cnt;
+					gpu_instance[gpu_instance_id].num_lce = temp_lce_cnt;
+					nvgpu_log(g, gpu_dbg_mig,
+						"Added Extra LCEs to %u GPU instance "
+							"gpu_instance_id[%u] "
+							"gr_instance_id[%u] gr_syspipe_id[%u] "
+							"gr_engine_id [%u] lce_engine_id[%u] "
+							"temp_lce_cnt[%u] ",
+						gpu_instance_id,
+						gpu_instance[gpu_instance_id].gpu_instance_id,
+						local_gr_syspipe->gr_instance_id,
+						local_gr_syspipe->gr_syspipe_id,
+						local_gr_syspipe->gr_dev->engine_id,
+						lces[physical_ce_id]->engine_id,
+						temp_lce_cnt);
+					++gpu_instance_id;
+					gpu_instance_id %= temp_num_gpu_instances;
+				}
+			}
+		}
+
+		gpu_instance[index].fbp_rop_l2_en_mask =
+			nvgpu_kzalloc(g,
+				nvgpu_safe_mult_u64(max_fbps_count, sizeof(u32)));
+		if (gpu_instance[index].fbp_rop_l2_en_mask == NULL) {
+			nvgpu_err(g,
+				"gpu_instance[%d].fbp_rop_l2_en_mask aloc failed",
+				index);
+			err = -ENOMEM;
+			goto exit;
+		}
+
+		if (gpu_instance[index].is_memory_partition_supported == false) {
+			u32 physical_fb_id, logical_fb_id;
+			u32 *logical_fbp_rop_l2_en_mask =
+				gpu_instance[index].fbp_rop_l2_en_mask;
+
+			gpu_instance[index].num_fbp = g->mig.gpu_instance[0].num_fbp;
+			gpu_instance[index].fbp_en_mask =
+				nvgpu_safe_sub_u32(BIT32(gpu_instance[index].num_fbp), 1U);
+
+			/* Convert physical to logical FBP mask order */
+			for (logical_fb_id = 0U, physical_fb_id = 0U;
+					((logical_fb_id < gpu_instance[index].num_fbp) &&
+						(physical_fb_id < max_fbps_count));
+					++physical_fb_id) {
+				if (physical_fbp_en_mask & BIT32(physical_fb_id)) {
+					logical_fbp_rop_l2_en_mask[logical_fb_id] =
+						physical_fbp_rop_l2_en_mask[physical_fb_id];
+					++logical_fb_id;
+				}
+			}
+
+			nvgpu_assert(logical_fb_id == gpu_instance[index].num_fbp);
+
+		} else {
+			/* SMC Memory partition is not yet supported */
+			nvgpu_assert(
+				gpu_instance[index].is_memory_partition_supported == false);
+		}
+
+		nvgpu_log(g, gpu_dbg_mig,
+			"[%d] gpu_instance_id[%u] gr_instance_id[%u] "
+				"gr_syspipe_id[%u] num_gpc[%u] gr_engine_id[%u] "
+				"max_veid_count_per_tsg[%u] veid_start_offset[%u] "
+				"veid_end_offset[%u] "
+				"is_memory_partition_support[%d] num_lce[%u] "
+				"gr_syspipe_enabled_count[%u] "
+				"max_fbps_count[%u] num_fbp[%u] fbp_en_mask [0x%x] ",
+			index, gpu_instance[index].gpu_instance_id,
+			gr_syspipe->gr_instance_id,
+			gr_syspipe->gr_syspipe_id,
+			gr_syspipe->num_gpc,
+			gr_syspipe->gr_dev->engine_id,
+			gr_syspipe->max_veid_count_per_tsg,
+			gr_syspipe->veid_start_offset,
+			nvgpu_safe_sub_u32(
+				nvgpu_safe_add_u32(gr_syspipe->veid_start_offset,
+					gr_syspipe->max_veid_count_per_tsg), 1U),
+			gpu_instance[index].is_memory_partition_supported,
+			gpu_instance[index].num_lce,
+			gr_syspipe_enabled_count,
+			max_fbps_count,
+			gpu_instance[index].num_fbp,
+			gpu_instance[index].fbp_en_mask);
+	}
+
+	*num_gpu_instances = temp_num_gpu_instances;
+
+exit:
+	nvgpu_kfree(g, gr_instance_id_per_swizzid);
+	return err;
+}
+
+static void ga10b_grmgr_set_smc_state(struct gk20a *g, bool enable)
+{
+	u32 smc_state = 0U;
+
+	smc_state = nvgpu_readl(g, smcarb_sys_pipe_info_r());
+
+	if (smcarb_sys_pipe_info_mode_v(smc_state) != enable) {
+		smc_state &= ~smcarb_sys_pipe_info_mode_m();
+		if (enable) {
+			smc_state |= smcarb_sys_pipe_info_mode_f(
+				smcarb_sys_pipe_info_mode_smc_v());
+		} else {
+			smc_state |= smcarb_sys_pipe_info_mode_f(
+				smcarb_sys_pipe_info_mode_legacy_v());
+		}
+		nvgpu_writel(g, smcarb_sys_pipe_info_r(), smc_state);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_MIG, enable);
+		nvgpu_log(g, gpu_dbg_mig, "MIG boot reg_val[%x] enable[%d]",
+			smc_state, enable);
+	}
+}
+
+static int ga10b_grmgr_config_gpc_smc_map(struct gk20a *g, bool enable)
+{
+	u32 physical_gpc_id;
+	u32 local_gpc_id;
+	u32 logical_gpc_id = 0U;
+	u32 gpu_instance_id;
+	u32 gr_sys_pipe_id;
+	u32 ugpu_id;
+	u32 reg_val;
+	struct nvgpu_gr_syspipe *gr_syspipe;
+
+	for (gpu_instance_id = 0; gpu_instance_id < g->mig.num_gpu_instances;
+			++gpu_instance_id) {
+
+		if (!nvgpu_grmgr_is_mig_type_gpu_instance(
+				&g->mig.gpu_instance[gpu_instance_id])) {
+			nvgpu_log(g, gpu_dbg_mig, "skip physical instance[%u]",
+				gpu_instance_id);
+			/* Skip physical device gpu instance when MIG is enabled */
+			continue;
+		}
+
+		gr_syspipe = &g->mig.gpu_instance[gpu_instance_id].gr_syspipe;
+		gr_sys_pipe_id = gr_syspipe->gr_syspipe_id;
+		local_gpc_id = 0;
+
+		while (local_gpc_id < gr_syspipe->num_gpc) {
+			ugpu_id = gr_syspipe->gpcs[local_gpc_id].gpcgrp_id;
+			physical_gpc_id = gr_syspipe->gpcs[local_gpc_id].physical_id;
+			logical_gpc_id = gr_syspipe->gpcs[local_gpc_id].logical_id;
+
+			reg_val = nvgpu_readl(g,
+				smcarb_smc_partition_gpc_map_r(logical_gpc_id));
+
+			if (enable == false) {
+				reg_val = set_field(reg_val,
+					smcarb_smc_partition_gpc_map_valid_m(),
+					smcarb_smc_partition_gpc_map_valid_f(
+						smcarb_smc_partition_gpc_map_valid_false_v()));
+			}
+			else if (enable && (physical_gpc_id ==
+					smcarb_smc_partition_gpc_map_physical_gpc_id_v(reg_val)) &&
+					(ugpu_id == smcarb_smc_partition_gpc_map_ugpu_id_v(reg_val))) {
+				reg_val = set_field(reg_val,
+					smcarb_smc_partition_gpc_map_sys_pipe_local_gpc_id_m(),
+					smcarb_smc_partition_gpc_map_sys_pipe_local_gpc_id_f(
+						local_gpc_id));
+				reg_val = set_field(reg_val,
+					smcarb_smc_partition_gpc_map_sys_pipe_id_m(),
+					smcarb_smc_partition_gpc_map_sys_pipe_id_f(
+						gr_sys_pipe_id));
+				reg_val = set_field(reg_val,
+					smcarb_smc_partition_gpc_map_valid_m(),
+					smcarb_smc_partition_gpc_map_valid_f(
+						smcarb_smc_partition_gpc_map_valid_true_v()));
+			} else {
+				nvgpu_err(g, "wrong mig config found [%u %u %u %u %u]",
+					logical_gpc_id,
+					physical_gpc_id,
+					smcarb_smc_partition_gpc_map_physical_gpc_id_v(reg_val),
+					ugpu_id,
+					smcarb_smc_partition_gpc_map_ugpu_id_v(reg_val));
+				return -EINVAL;
+			}
+
+			nvgpu_writel(g, smcarb_smc_partition_gpc_map_r(logical_gpc_id), reg_val);
+			nvgpu_log(g, gpu_dbg_mig,
+				"[%d] gpu_instance_id[%u] gr_instance_id[%u] "
+					"gr_syspipe_id[%u] logical_gpc_id[%u] physical_gpc_id[%u] "
+					" local_gpc_id[%u] gpcgrp_id[%u] reg_val[%x] enable[%d] ",
+				gpu_instance_id, g->mig.gpu_instance[gpu_instance_id].gpu_instance_id,
+				gr_syspipe->gr_instance_id,
+				gr_sys_pipe_id, logical_gpc_id, physical_gpc_id,
+				local_gpc_id, ugpu_id, reg_val, enable);
+			++local_gpc_id;
+		}
+	}
+
+	if (g->ops.priv_ring.config_gpc_rs_map(g, enable) != 0) {
+		nvgpu_err(g, "g->ops.priv_ring.config_gpc_rs_map-failed");
+		return -EINVAL;
+	}
+
+	if (g->ops.fb.set_smc_eng_config(g, enable) != 0) {
+		nvgpu_err(g, "g->ops.fb.set_smc_eng_config-failed");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int ga10b_grmgr_init_gr_manager(struct gk20a *g)
+{
+	struct nvgpu_gr_syspipe *gr_syspipe;
+	int err;
+	u32 index;
+	u32 num_gpu_instances;
+	const struct nvgpu_device *gr_dev = NULL;
+	u32 max_veid_count_per_tsg = g->ops.gr.init.get_max_subctx_count();
+
+	/* Init physical device gpu instance */
+	err = nvgpu_init_gr_manager(g);
+	if (err != 0) {
+		nvgpu_err(g, "nvgpu_init_gr_manager-failed[%d]", err);
+		return err;
+	}
+
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG) ||
+			(g->mig.gpc_count < 2U)) {
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_MIG, false);
+		/* Fall back to non MIG gr manager init */
+		nvgpu_log(g, gpu_dbg_mig,
+			"legacy mode boot[non MIG]");
+		return 0;
+	}
+
+	g->mig.is_nongr_engine_sharable = false;
+	if (max_veid_count_per_tsg < 64U) {
+		nvgpu_err(g,
+			"re-generate mig gpu instance config based on floorsweep config veid[%u]",
+			max_veid_count_per_tsg);
+		return -EINVAL;
+	}
+
+	err = ga10b_grmgr_get_gpu_instance(g, g->mig.current_gpu_instance_config_id,
+			&g->mig.gpu_instance[1],
+			g->mig.gpu_instance[0].gr_syspipe.gpcs,
+			&num_gpu_instances);
+	if (err != 0) {
+		nvgpu_err(g, "ga10b_grmgr_get_gpu_instance-failed[%d]", err);
+		return err;
+	}
+
+	g->mig.num_gpu_instances = nvgpu_safe_add_u32(num_gpu_instances, 1U);
+
+	g->mig.max_gr_sys_pipes_supported = g->ops.grmgr.get_max_sys_pipes(g);
+
+	g->mig.gr_syspipe_en_mask = 0;
+	g->mig.num_gr_sys_pipes_enabled = 0U;
+
+	for (index = 0U; index  < g->mig.num_gpu_instances; index++) {
+		if (!nvgpu_grmgr_is_mig_type_gpu_instance(
+				&g->mig.gpu_instance[index])) {
+			/* Skip physical device gpu instance when MIG is enabled */
+			nvgpu_log(g, gpu_dbg_mig, "skip physical instance[%u]", index);
+			continue;
+		}
+		gr_syspipe = &g->mig.gpu_instance[index].gr_syspipe;
+		g->mig.gr_syspipe_en_mask |= BIT(gr_syspipe->gr_syspipe_id);
+
+		gr_dev = nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS,
+			gr_syspipe->gr_syspipe_id);
+
+		/*
+		 * HW recommended to put GR engine into reset before programming
+		 * config_gpc_rs_map (ga10b_grmgr_config_gpc_smc_map()).
+		 */
+		err = g->ops.mc.enable_dev(g, gr_dev, false);
+		if (err != 0) {
+			nvgpu_err(g, "GR engine reset failed gr_syspipe_id[%u %u]",
+				gr_syspipe->gr_syspipe_id, gr_dev->inst_id);
+			return err;
+		}
+
+		++g->mig.num_gr_sys_pipes_enabled;
+	}
+
+	g->mig.current_gr_syspipe_id = NVGPU_MIG_INVALID_GR_SYSPIPE_ID;
+	nvgpu_mutex_init(&g->mig.gr_syspipe_lock);
+
+	err = ga10b_grmgr_config_gpc_smc_map(g, true);
+	if (err != 0) {
+		nvgpu_err(g, "ga10b_grmgr_config_gpc_smc_map-failed[%d]", err);
+		return err;
+	}
+
+	err = g->ops.fb.config_veid_smc_map(g, true);
+	if (err != 0) {
+		return err;
+	}
+
+	err = g->ops.fb.set_remote_swizid(g, true);
+	if (err != 0) {
+		nvgpu_err(g, "g->ops.fb.set_remote_swizid-failed[%d]", err);
+		return err;
+	}
+
+	ga10b_grmgr_set_smc_state(g, true);
+
+	nvgpu_log(g, gpu_dbg_mig,
+		"MIG boot success num_gpu_instances[%u] "
+			"num_gr_sys_pipes_enabled[%u] gr_syspipe_en_mask[%x]",
+		g->mig.num_gpu_instances,
+		g->mig.num_gr_sys_pipes_enabled,
+		g->mig.gr_syspipe_en_mask);
+
+	return err;
+}
+
+u32 ga10b_grmgr_get_max_sys_pipes(struct gk20a *g)
+{
+	return smcarb_max_partitionable_sys_pipes_v();
+}
+
+u32 ga10b_grmgr_get_allowed_swizzid_size(struct gk20a *g)
+{
+	return smcarb_allowed_swizzid__size1_v();
+}
+
+int ga10b_grmgr_get_gpc_instance_gpcgrp_id(struct gk20a *g,
+		u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id)
+{
+	u32 local_gpcgrp_id;
+	bool supported;
+
+	if ((gr_syspipe_id >= g->ops.grmgr.get_max_sys_pipes(g)) ||
+		(gpu_instance_id >= smcarb_allowed_swizzid__size1_v()) ||
+		(gpcgrp_id == NULL)) {
+		nvgpu_err(g,
+			"[Invalid_param] gr_syspipe_id[%u %u] gpu_instance_id[%u %u] "
+				"or gpcgrp_id == NULL ",
+				gr_syspipe_id, g->ops.grmgr.get_max_sys_pipes(g),
+				gpu_instance_id, smcarb_allowed_swizzid__size1_v());
+		return -EINVAL;
+	}
+
+	for (local_gpcgrp_id = 0U; local_gpcgrp_id < 2U; local_gpcgrp_id++) {
+		supported = GA10B_GRMGR_PSMCARB_ALLOWED_UGPU(
+			gpu_instance_id, local_gpcgrp_id);
+		if (supported) {
+			*gpcgrp_id = local_gpcgrp_id;
+			nvgpu_log(g, gpu_dbg_mig,
+					"Found [%u] gpcgrp id for gpu_instance_id[%u] "
+						"gr_syspipe_id[%u] ",
+					*gpcgrp_id,
+					gpu_instance_id,
+					gr_syspipe_id);
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+int ga10b_grmgr_remove_gr_manager(struct gk20a *g)
+{
+	int err;
+	u32 index;
+
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		/* Fall back to non MIG gr manager remove ops - noop */
+		return 0;
+	}
+
+	ga10b_grmgr_set_smc_state(g, false);
+	err = ga10b_grmgr_config_gpc_smc_map(g, false);
+	err |= g->ops.fb.config_veid_smc_map(g, false);
+	err |= g->ops.fb.set_remote_swizid(g, false);
+
+	/* Free only MIG instance fbp_rop_l2_en_mask */
+	for (index = 1U; index  < g->mig.num_gpu_instances; index++) {
+		if (g->mig.gpu_instance[index].fbp_rop_l2_en_mask !=
+				NULL) {
+			nvgpu_kfree(g,
+				g->mig.gpu_instance[index].fbp_rop_l2_en_mask);
+			g->mig.gpu_instance[index].fbp_rop_l2_en_mask = NULL;
+			g->mig.gpu_instance[index].num_fbp = 0U;
+			g->mig.gpu_instance[index].fbp_en_mask = 0U;
+		}
+	}
+	nvgpu_mutex_destroy(&g->mig.gr_syspipe_lock);
+
+	(void)memset(&g->mig, 0, sizeof(struct nvgpu_mig));
+
+	nvgpu_log(g, gpu_dbg_mig, "success");
+
+	return err;
+}
+
+int ga10b_grmgr_get_mig_gpu_instance_config(struct gk20a *g,
+		const char **config_name,
+		u32 *num_config_supported) {
+
+	u32 config_id;
+	const struct nvgpu_mig_gpu_instance_config *mig_gpu_instance_config =
+		g->ops.grmgr.get_mig_config_ptr(g);
+
+	if (num_config_supported == NULL) {
+		return -EINVAL;
+	}
+
+	*num_config_supported = mig_gpu_instance_config->num_config_supported;
+
+	if (config_name != NULL) {
+		for (config_id = 0U; config_id < *num_config_supported;
+			config_id++) {
+				config_name[config_id] =
+					mig_gpu_instance_config->gpu_instance_config[config_id].config_name;
+		}
+	}
+	return 0;
+}
+
+#endif
+
+void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g)
+{
+	u32 reg_val;
+
+	/* set prod value for smc arb timestamp ctrl disable tick */
+	reg_val = nvgpu_readl(g, smcarb_timestamp_ctrl_r());
+	reg_val = set_field(reg_val,
+			smcarb_timestamp_ctrl_disable_tick_m(),
+                        smcarb_timestamp_ctrl_disable_tick__prod_f());
+	nvgpu_writel(g, smcarb_timestamp_ctrl_r(), reg_val);
+
+}
+
+int ga10b_grmgr_discover_gpc_ids(struct gk20a *g,
+		u32 num_gpc, struct nvgpu_gpc *gpcs)
+{
+	u32 logical_gpc_id;
+	u32 reg_val;
+
+	if (gpcs == NULL) {
+		nvgpu_err(g, "no valid gpcs ptr");
+		return -EINVAL;
+	}
+
+	for (logical_gpc_id = 0U; logical_gpc_id < num_gpc; logical_gpc_id++) {
+		reg_val = nvgpu_readl(g,
+			smcarb_smc_partition_gpc_map_r(logical_gpc_id));
+		gpcs[logical_gpc_id].logical_id = logical_gpc_id;
+		gpcs[logical_gpc_id].physical_id =
+			smcarb_smc_partition_gpc_map_physical_gpc_id_v(reg_val);
+		gpcs[logical_gpc_id].gpcgrp_id =
+			smcarb_smc_partition_gpc_map_ugpu_id_v(reg_val);
+		nvgpu_log(g, gpu_dbg_mig,
+			"index[%u] gpc_logical_id[%u] "
+				"gpc_physical_id[%u]  gpc_grpid[%u] ",
+			logical_gpc_id,
+			gpcs[logical_gpc_id].logical_id,
+			gpcs[logical_gpc_id].physical_id,
+			gpcs[logical_gpc_id].gpcgrp_id);
+	}
+	return 0;
+}
diff --git a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h
new file mode 100644
index 000000000..cf66591f3
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h
@@ -0,0 +1,49 @@
+/*
+ * GA10B GR MANAGER
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GRMGR_GA10B_H
+#define NVGPU_GRMGR_GA10B_H
+
+struct gk20a;
+
+#ifdef CONFIG_NVGPU_MIG
+const struct nvgpu_mig_gpu_instance_config *ga10b_grmgr_get_mig_config_ptr(
+		struct gk20a *g);
+u32 ga10b_grmgr_get_allowed_swizzid_size(struct gk20a *g);
+int ga10b_grmgr_init_gr_manager(struct gk20a *g);
+u32 ga10b_grmgr_get_max_sys_pipes(struct gk20a *g);
+int ga10b_grmgr_get_gpc_instance_gpcgrp_id(struct gk20a *g,
+		u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id);
+int ga10b_grmgr_remove_gr_manager(struct gk20a *g);
+int ga10b_grmgr_get_mig_gpu_instance_config(struct gk20a *g,
+		const char **config_name,
+		u32 *num_config_supported);
+void ga10b_grmgr_get_gpcgrp_count(struct gk20a *g);
+#endif
+
+void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g);
+int ga10b_grmgr_discover_gpc_ids(struct gk20a *g,
+		u32 num_gpc, struct nvgpu_gpc *gpcs);
+
+#endif /* NVGPU_GRMGR_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c
new file mode 100644
index 000000000..99bd0792f
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/falcon.h>
+#include <nvgpu/mm.h>
+#include <nvgpu/io.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/bug.h>
+
+#include "gsp_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_pgsp_ga10b.h>
+
+u32 ga10b_gsp_falcon2_base_addr(void)
+{
+	return pgsp_falcon2_gsp_base_r();
+}
+
+u32 ga10b_gsp_falcon_base_addr(void)
+{
+	return pgsp_falcon_irqsset_r();
+}
diff --git a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h
new file mode 100644
index 000000000..f61da19b1
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GSP_GA10B_H
+#define GSP_GA10B_H
+
+u32 ga10b_gsp_falcon_base_addr(void);
+u32 ga10b_gsp_falcon2_base_addr(void);
+
+#endif /* GSP_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
new file mode 100644
index 000000000..13e1185ad
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
@@ -0,0 +1,1958 @@
+/*
+ * GA100 Tegra HAL interface
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/errata.h>
+#include <nvgpu/acr.h>
+#include <nvgpu/ce.h>
+#include <nvgpu/ce_app.h>
+#include <nvgpu/pmu.h>
+#ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/pmu_pstate.h>
+#endif
+#include <nvgpu/fbp.h>
+#include <nvgpu/therm.h>
+#include <nvgpu/clk_arb.h>
+#include <nvgpu/fuse.h>
+#include <nvgpu/pbdma.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/preempt.h>
+#include <nvgpu/gmmu.h>
+#include <nvgpu/regops.h>
+#include <nvgpu/gr/gr_falcon.h>
+#include <nvgpu/gr/gr.h>
+#include <nvgpu/gr/fs_state.h>
+
+#include <nvgpu/ptimer.h>
+#include <nvgpu/error_notifier.h>
+#include <nvgpu/class.h>
+#include <nvgpu/debugger.h>
+#include <nvgpu/pm_reservation.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/fifo/userd.h>
+#include <nvgpu/perfbuf.h>
+#include <nvgpu/cyclestats_snapshot.h>
+#include <nvgpu/regops.h>
+#ifdef CONFIG_NVGPU_GRAPHICS
+#include <nvgpu/gr/zbc.h>
+#endif
+#include <nvgpu/gr/setup.h>
+#include <nvgpu/gr/fecs_trace.h>
+#include <nvgpu/pmu/clk/clk.h>
+#include <nvgpu/pmu/perf.h>
+#include <nvgpu/gr/gr_falcon.h>
+#include <nvgpu/gr/gr.h>
+#include <nvgpu/gr/gr_intr.h>
+#include <nvgpu/pmu/pmu_perfmon.h>
+#include <nvgpu/nvgpu_init.h>
+#include <nvgpu/sbr.h>
+#include <nvgpu/nvhost.h>
+#include <nvgpu/clk_mon.h>
+#include <nvgpu/profiler.h>
+
+#include "hal/mm/mm_gm20b.h"
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
+#include "hal/mm/mm_tu104.h"
+#include "hal/mm/cache/flush_gk20a.h"
+#include "hal/mm/cache/flush_gv11b.h"
+#include "hal/mm/gmmu/gmmu_gm20b.h"
+#include "hal/mm/gmmu/gmmu_gp10b.h"
+#include "hal/mm/gmmu/gmmu_gv11b.h"
+#include "hal/mm/gmmu/gmmu_ga10b.h"
+#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
+#include "hal/mm/mmu_fault/mmu_fault_ga10b.h"
+#include "hal/mc/mc_gm20b.h"
+#include "hal/mc/mc_gp10b.h"
+#include "hal/mc/mc_gv11b.h"
+#include "hal/mc/mc_gv100.h"
+#include "hal/mc/mc_tu104.h"
+#include "hal/mc/mc_ga10b.h"
+#include "hal/mc/mc_intr_ga10b.h"
+#include "hal/bus/bus_gk20a.h"
+#include "hal/bus/bus_gp10b.h"
+#include "hal/bus/bus_gm20b.h"
+#include "hal/bus/bus_gv100.h"
+#include "hal/bus/bus_gv11b.h"
+#include "hal/bus/bus_tu104.h"
+#include "hal/bus/bus_ga10b.h"
+#include "hal/bus/bus_ga100.h"
+#include "hal/ce/ce_gp10b.h"
+#include "hal/ce/ce_gv11b.h"
+#include "hal/ce/ce_tu104.h"
+#include "hal/class/class_ga100.h"
+#include "hal/priv_ring/priv_ring_gm20b.h"
+#include "hal/priv_ring/priv_ring_gp10b.h"
+#include "hal/priv_ring/priv_ring_ga10b.h"
+#include "hal/priv_ring/priv_ring_ga100.h"
+#include "hal/power_features/cg/ga100_gating_reglist.h"
+#include "hal/cbc/cbc_gm20b.h"
+#include "hal/cbc/cbc_tu104.h"
+#include "hal/cbc/cbc_ga100.h"
+#include "hal/therm/therm_gm20b.h"
+#include "hal/therm/therm_tu104.h"
+#include "hal/therm/therm_gv11b.h"
+#include "hal/therm/therm_ga10b.h"
+#include "hal/ltc/ltc_gm20b.h"
+#include "hal/ltc/ltc_gp10b.h"
+#include "hal/ltc/ltc_gv11b.h"
+#include "hal/ltc/ltc_tu104.h"
+#include "hal/ltc/ltc_ga10b.h"
+#include "hal/ltc/intr/ltc_intr_gv11b.h"
+#include "hal/ltc/intr/ltc_intr_ga10b.h"
+#include "hal/fb/fb_gm20b.h"
+#include "hal/fb/fb_gp10b.h"
+#include "hal/fb/fb_gp106.h"
+#include "hal/fb/fb_gv11b.h"
+#include "hal/fb/fb_gv100.h"
+#include "hal/fb/fb_ga10b.h"
+#include "hal/fb/fb_tu104.h"
+#include "hal/fb/fb_ga100.h"
+#include "hal/fb/fb_mmu_fault_gv11b.h"
+#include "hal/fb/fb_mmu_fault_tu104.h"
+#include "hal/fb/ecc/fb_ecc_ga10b.h"
+#include "hal/fb/ecc/fb_ecc_gv11b.h"
+#include "hal/fb/intr/fb_intr_ecc_gv11b.h"
+#include "hal/fb/intr/fb_intr_ecc_ga10b.h"
+#include "hal/fb/intr/fb_intr_tu104.h"
+#include "hal/fb/intr/fb_intr_ga10b.h"
+#include "hal/fb/intr/fb_intr_ecc_gv11b.h"
+#include "hal/func/func_ga10b.h"
+#include "hal/fuse/fuse_gm20b.h"
+#include "hal/fuse/fuse_gp10b.h"
+#include "hal/fuse/fuse_ga10b.h"
+#include "hal/fuse/fuse_ga100.h"
+#include "hal/fuse/fuse_gp106.h"
+#include "hal/ptimer/ptimer_gk20a.h"
+#include "hal/ptimer/ptimer_gp10b.h"
+#include "hal/ptimer/ptimer_gv11b.h"
+#include "hal/ptimer/ptimer_ga10b.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
+#include "hal/regops/regops_ga100.h"
+#include "hal/regops/allowlist_ga100.h"
+#endif
+#ifdef CONFIG_NVGPU_RECOVERY
+#include "hal/rc/rc_gv11b.h"
+#endif
+#include "hal/fifo/fifo_gk20a.h"
+#include "hal/fifo/fifo_gv11b.h"
+#include "hal/fifo/fifo_ga10b.h"
+#include "hal/fifo/pbdma_gm20b.h"
+#include "hal/fifo/pbdma_gp10b.h"
+#include "hal/fifo/pbdma_gv11b.h"
+#include "hal/fifo/pbdma_ga10b.h"
+#include "hal/fifo/pbdma_ga100.h"
+#include "hal/fifo/preempt_gv11b.h"
+#include "hal/fifo/preempt_ga10b.h"
+#include "hal/fifo/engine_status_gv100.h"
+#include "hal/fifo/engine_status_ga10b.h"
+#include "hal/fifo/pbdma_status_gm20b.h"
+#include "hal/fifo/pbdma_status_ga10b.h"
+#include "hal/fifo/engines_gp10b.h"
+#include "hal/fifo/engines_gv11b.h"
+#include "hal/fifo/ramfc_gp10b.h"
+#include "hal/fifo/ramfc_gv11b.h"
+#include "hal/fifo/ramfc_ga10b.h"
+#include "hal/fifo/ramin_gk20a.h"
+#include "hal/fifo/ramin_gm20b.h"
+#include "hal/fifo/ramin_gv11b.h"
+#include "hal/fifo/ramin_ga10b.h"
+#include "hal/fifo/runlist_ram_gk20a.h"
+#include "hal/fifo/runlist_ram_gv11b.h"
+#include "hal/fifo/runlist_fifo_gk20a.h"
+#include "hal/fifo/runlist_fifo_gv11b.h"
+#include "hal/fifo/runlist_fifo_ga10b.h"
+#include "hal/fifo/runlist_fifo_ga100.h"
+#include "hal/fifo/runlist_ga10b.h"
+#include "hal/fifo/tsg_ga10b.h"
+#include "hal/fifo/tsg_gv11b.h"
+#include "hal/fifo/userd_gk20a.h"
+#include "hal/fifo/userd_gv11b.h"
+#include "hal/fifo/userd_ga10b.h"
+#include "hal/fifo/usermode_gv11b.h"
+#include "hal/fifo/usermode_tu104.h"
+#include "hal/fifo/usermode_ga10b.h"
+#include "hal/fifo/fifo_intr_gk20a.h"
+#include "hal/fifo/fifo_intr_gv11b.h"
+#include "hal/fifo/fifo_intr_ga10b.h"
+#include "hal/fifo/ctxsw_timeout_gv11b.h"
+#include "hal/fifo/ctxsw_timeout_ga10b.h"
+#include "hal/gr/ecc/ecc_gv11b.h"
+#include "hal/gr/ecc/ecc_ga10b.h"
+#ifdef CONFIG_NVGPU_FECS_TRACE
+#include "hal/gr/fecs_trace/fecs_trace_gm20b.h"
+#include "hal/gr/fecs_trace/fecs_trace_gv11b.h"
+#endif
+#include "hal/gr/falcon/gr_falcon_gm20b.h"
+#include "hal/gr/falcon/gr_falcon_gp10b.h"
+#include "hal/gr/falcon/gr_falcon_gv11b.h"
+#include "hal/gr/falcon/gr_falcon_tu104.h"
+#include "hal/gr/falcon/gr_falcon_ga10b.h"
+#include "hal/gr/falcon/gr_falcon_ga100.h"
+#include "hal/gr/config/gr_config_gm20b.h"
+#include "hal/gr/config/gr_config_gv100.h"
+#ifdef CONFIG_NVGPU_GRAPHICS
+#include "hal/gr/zbc/zbc_gm20b.h"
+#include "hal/gr/zbc/zbc_gp10b.h"
+#include "hal/gr/zbc/zbc_gv11b.h"
+#include "hal/gr/zcull/zcull_gm20b.h"
+#include "hal/gr/zcull/zcull_gv11b.h"
+#endif
+#include "hal/gr/init/gr_init_gm20b.h"
+#include "hal/gr/init/gr_init_gp10b.h"
+#include "hal/gr/init/gr_init_gv11b.h"
+#include "hal/gr/init/gr_init_tu104.h"
+#include "hal/gr/init/gr_init_ga10b.h"
+#include "hal/gr/init/gr_init_ga100.h"
+#include "hal/gr/intr/gr_intr_gm20b.h"
+#include "hal/gr/intr/gr_intr_gp10b.h"
+#include "hal/gr/intr/gr_intr_gv11b.h"
+#include "hal/gr/intr/gr_intr_tu104.h"
+#include "hal/gr/intr/gr_intr_ga10b.h"
+#include "hal/gr/intr/gr_intr_ga100.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
+#include "hal/gr/hwpm_map/hwpm_map_gv100.h"
+#endif
+#include "hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_ga100.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
+#include "hal/gr/gr/gr_gk20a.h"
+#include "hal/gr/gr/gr_gm20b.h"
+#include "hal/gr/gr/gr_gp10b.h"
+#include "hal/gr/gr/gr_gv100.h"
+#include "hal/gr/gr/gr_gv11b.h"
+#include "hal/gr/gr/gr_tu104.h"
+#include "hal/gr/gr/gr_ga10b.h"
+#include "hal/gr/gr/gr_ga100.h"
+#endif
+#include "hal/pmu/pmu_gk20a.h"
+#ifdef CONFIG_NVGPU_LS_PMU
+#include "hal/pmu/pmu_gm20b.h"
+#endif
+#include "hal/pmu/pmu_gp10b.h"
+#include "hal/pmu/pmu_gv11b.h"
+#include "hal/pmu/pmu_tu104.h"
+#include "hal/pmu/pmu_ga10b.h"
+#include "hal/pmu/pmu_ga100.h"
+#include "hal/falcon/falcon_gk20a.h"
+#include "hal/falcon/falcon_ga10b.h"
+#include "hal/nvdec/nvdec_ga100.h"
+#include "hal/gsp/gsp_tu104.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
+#include "hal/perf/perf_gv11b.h"
+#endif
+#ifdef CONFIG_NVGPU_DGPU
+#include "hal/sec2/sec2_tu104.h"
+#endif
+#include "hal/sync/syncpt_cmdbuf_gv11b.h"
+#include "hal/sync/sema_cmdbuf_gv11b.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
+#include "hal/perf/perf_ga10b.h"
+#include "hal/perf/perf_ga100.h"
+#endif
+#include "hal/netlist/netlist_ga100.h"
+#include "hal/top/top_gm20b.h"
+#include "hal/top/top_gp10b.h"
+#include "hal/top/top_gv100.h"
+#include "hal/top/top_gv11b.h"
+#include "hal/top/top_ga10b.h"
+#include "hal/bios/bios_tu104.h"
+#include "hal/pramin/pramin_init.h"
+#include "hal/xve/xve_gp106.h"
+#include "hal/xve/xve_tu104.h"
+
+#include "hal/fifo/channel_gk20a.h"
+#include "hal/fifo/channel_gm20b.h"
+#include "hal/fifo/channel_gv11b.h"
+#include "hal/fifo/channel_ga10b.h"
+#include "hal/fifo/channel_ga100.h"
+
+#ifdef CONFIG_NVGPU_CLK_ARB
+#include "common/clk_arb/clk_arb_gv100.h"
+#endif
+
+#include "hal/clk/clk_tu104.h"
+#include "hal/clk/clk_mon_tu104.h"
+#include "hal/clk/clk_ga100.h"
+#include "hal/fbpa/fbpa_tu104.h"
+#include "hal_ga100.h"
+#include "hal_ga100_litter.h"
+
+#include <nvgpu/hw/tu104/hw_pwr_tu104.h>
+
+#include "hal/grmgr/grmgr_ga10b.h"
+
+#ifdef CONFIG_NVGPU_MIG
+#include "hal/grmgr/grmgr_ga100.h"
+#else
+#include <nvgpu/grmgr.h>
+#endif
+
+static int ga100_init_gpu_characteristics(struct gk20a *g)
+{
+	int err;
+
+	err = nvgpu_init_gpu_characteristics(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init GPU characteristics");
+		return err;
+	}
+
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
+#ifdef CONFIG_NVGPU_GRAPHICS
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
+#endif
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true);
+	if (nvgpu_has_syncpoints(g)) {
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
+	}
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_DEVICE_EVENTS, true);
+
+	return 0;
+}
+
+static const struct gops_acr ga100_ops_acr = {
+	.acr_init = nvgpu_acr_init,
+	.acr_construct_execute = nvgpu_acr_construct_execute,
+};
+
+static const struct gops_sbr ga100_ops_sbr = {
+	.sbr_pub_load_and_execute = nvgpu_sbr_pub_load_and_execute,
+};
+
+static const struct gops_func ga100_ops_func = {
+	.get_full_phys_offset = ga10b_func_get_full_phys_offset,
+};
+
+static const struct gops_bios ga100_ops_bios = {
+#ifdef CONFIG_NVGPU_DGPU
+	.bios_sw_init = nvgpu_bios_sw_init,
+	.bios_sw_deinit = nvgpu_bios_sw_deinit,
+	.wait_for_bios_init_done = nvgpu_bios_wait_for_init_done,
+#endif /* CONFIG_NVGPU_DGPU */
+	.get_aon_secure_scratch_reg = tu104_get_aon_secure_scratch_reg,
+};
+
+static const struct gops_ecc ga100_ops_ecc = {
+	.ecc_init_support = nvgpu_ecc_init_support,
+	.ecc_finalize_support = nvgpu_ecc_finalize_support,
+	.ecc_remove_support = nvgpu_ecc_remove_support,
+};
+
+static const struct gops_ltc_intr ga100_ops_ltc_intr = {
+	.configure = ga10b_ltc_intr_configure,
+	.isr = ga10b_ltc_intr_isr,
+	.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
+};
+
+static const struct gops_ltc ga100_ops_ltc = {
+	.ecc_init = gv11b_lts_ecc_init,
+	.init_ltc_support = nvgpu_init_ltc_support,
+	.ltc_remove_support = nvgpu_ltc_remove_support,
+	.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
+	.init_fs_state = ga10b_ltc_init_fs_state,
+	.ltc_lts_set_mgmt_setup = ga10b_ltc_lts_set_mgmt_setup,
+	.flush = gm20b_flush_ltc,
+	.set_enabled = gp10b_ltc_set_enabled,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
+	.set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
+	.set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
+	.is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
+	.is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
+	.split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
+	.split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
+	.pri_is_lts_tstg_addr = tu104_ltc_pri_is_lts_tstg_addr,
+	.pri_shared_addr = ga10b_ltc_pri_shared_addr,
+	.set_l2_max_ways_evict_last = ga10b_set_l2_max_ways_evict_last,
+	.get_l2_max_ways_evict_last = ga10b_get_l2_max_ways_evict_last,
+	.set_l2_sector_promotion = tu104_set_l2_sector_promotion,
+#endif /* CONFIG_NVGPU_DEBUGGER */
+};
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+static const struct gops_cbc ga100_ops_cbc = {
+	.cbc_init_support = nvgpu_cbc_init_support,
+	.cbc_remove_support = nvgpu_cbc_remove_support,
+	.init = tu104_cbc_init,
+	.get_base_divisor = tu104_cbc_get_base_divisor,
+	.alloc_comptags = ga100_cbc_alloc_comptags,
+	.ctrl = tu104_cbc_ctrl,
+	.fix_config = NULL,
+};
+#endif
+
+static const struct gops_ce ga100_ops_ce = {
+	.ce_init_support = nvgpu_ce_init_support,
+#ifdef CONFIG_NVGPU_DGPU
+	.ce_app_init_support = nvgpu_ce_app_init_support,
+	.ce_app_suspend = nvgpu_ce_app_suspend,
+	.ce_app_destroy = nvgpu_ce_app_destroy,
+#endif
+	.set_pce2lce_mapping = NULL,
+	.isr_stall = gv11b_ce_stall_isr,
+	.isr_nonstall = NULL,
+	.get_num_pce = gv11b_ce_get_num_pce,
+	.mthd_buffer_fault_in_bar2_fault = gv11b_ce_mthd_buffer_fault_in_bar2_fault,
+	.init_prod_values = gv11b_ce_init_prod_values,
+};
+
+static const struct gops_gr_ecc ga100_ops_gr_ecc = {
+	.detect = ga10b_ecc_detect_enabled_units,
+	.gpc_tpc_ecc_init = ga10b_gr_gpc_tpc_ecc_init,
+	.fecs_ecc_init = gv11b_gr_fecs_ecc_init,
+#ifdef CONFIG_NVGPU_INJECT_HWERR
+	.get_mmu_err_desc = ga10b_gr_ecc_get_mmu_err_desc,
+	.get_gcc_err_desc = gv11b_gr_intr_get_gcc_err_desc,
+	.get_sm_err_desc = gv11b_gr_intr_get_sm_err_desc,
+	.get_gpccs_err_desc = gv11b_gr_intr_get_gpccs_err_desc,
+	.get_fecs_err_desc = gv11b_gr_intr_get_fecs_err_desc,
+#endif /* CONFIG_NVGPU_INJECT_HWERR */
+};
+
+static const struct gops_gr_ctxsw_prog ga100_ops_gr_ctxsw_prog = {
+	.hw_get_fecs_header_size = ga100_ctxsw_prog_hw_get_fecs_header_size,
+	.get_patch_count = gm20b_ctxsw_prog_get_patch_count,
+	.set_patch_count = gm20b_ctxsw_prog_set_patch_count,
+	.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
+	.init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data,
+	.set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
+	.set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode,
+	.set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr,
+	.disable_verif_features = gm20b_ctxsw_prog_disable_verif_features,
+	.set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr,
+	.set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr,
+	.set_zcull = gm20b_ctxsw_prog_set_zcull,
+	.set_zcull_mode_no_ctxsw = gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw,
+	.is_zcull_mode_separate_buffer = gm20b_ctxsw_prog_is_zcull_mode_separate_buffer,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+#ifdef CONFIG_NVGPU_GFXP
+	.set_graphics_preemption_mode_gfxp = gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp,
+	.set_full_preemption_ptr = gv11b_ctxsw_prog_set_full_preemption_ptr,
+	.set_full_preemption_ptr_veid0 = gv11b_ctxsw_prog_set_full_preemption_ptr_veid0,
+#endif /* CONFIG_NVGPU_GFXP */
+#ifdef CONFIG_NVGPU_CILP
+	.set_compute_preemption_mode_cilp = gp10b_ctxsw_prog_set_compute_preemption_mode_cilp,
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.hw_get_gpccs_header_size = ga100_ctxsw_prog_hw_get_gpccs_header_size,
+	.hw_get_extended_buffer_segments_size_in_bytes = gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes,
+	.hw_extended_marker_size_in_bytes = gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes,
+	.hw_get_perf_counter_control_register_stride = gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride,
+	.get_main_image_ctx_id = gm20b_ctxsw_prog_get_main_image_ctx_id,
+	.set_pm_ptr = gv11b_ctxsw_prog_set_pm_ptr,
+	.set_pm_mode = gm20b_ctxsw_prog_set_pm_mode,
+	.set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode,
+	.hw_get_pm_mode_no_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw,
+	.hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw,
+	.hw_get_pm_mode_stream_out_ctxsw = gv11b_ctxsw_prog_hw_get_pm_mode_stream_out_ctxsw,
+	.set_cde_enabled = NULL,
+	.set_pc_sampling = NULL,
+	.check_main_image_header_magic = ga100_ctxsw_prog_check_main_image_header_magic,
+	.check_local_header_magic = ga100_ctxsw_prog_check_local_header_magic,
+	.get_num_gpcs = gm20b_ctxsw_prog_get_num_gpcs,
+	.get_num_tpcs = gm20b_ctxsw_prog_get_num_tpcs,
+	.get_extended_buffer_size_offset = gm20b_ctxsw_prog_get_extended_buffer_size_offset,
+	.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
+	.get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
+	.set_pmu_options_boost_clock_frequencies = NULL,
+	.hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride,
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#ifdef CONFIG_DEBUG_FS
+	.dump_ctxsw_stats = ga100_ctxsw_prog_dump_ctxsw_stats,
+#endif
+#ifdef CONFIG_NVGPU_FECS_TRACE
+	.hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,
+	.hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag,
+	.hw_record_ts_timestamp = gm20b_ctxsw_prog_hw_record_ts_timestamp,
+	.hw_get_ts_record_size_in_bytes = gm20b_ctxsw_prog_hw_get_ts_record_size_in_bytes,
+	.is_ts_valid_record = gm20b_ctxsw_prog_is_ts_valid_record,
+	.get_ts_buffer_aperture_mask = NULL,
+	.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
+	.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
+#endif
+};
+
+static const struct gops_gr_config ga100_ops_gr_config = {
+	.get_gpc_mask = gm20b_gr_config_get_gpc_mask,
+	.get_gpc_tpc_mask = gm20b_gr_config_get_gpc_tpc_mask,
+	.get_tpc_count_in_gpc = gm20b_gr_config_get_tpc_count_in_gpc,
+	.get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask,
+	.get_pd_dist_skip_table_size = gm20b_gr_config_get_pd_dist_skip_table_size,
+	.init_sm_id_table = gv100_gr_config_init_sm_id_table,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.get_zcull_count_in_gpc = gm20b_gr_config_get_zcull_count_in_gpc,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+};
+
+#ifdef CONFIG_NVGPU_FECS_TRACE
+static const struct gops_gr_fecs_trace ga100_ops_gr_fecs_trace = {
+	.alloc_user_buffer = nvgpu_gr_fecs_trace_ring_alloc,
+	.free_user_buffer = nvgpu_gr_fecs_trace_ring_free,
+	.get_mmap_user_buffer_info = nvgpu_gr_fecs_trace_get_mmap_buffer_info,
+	.init = nvgpu_gr_fecs_trace_init,
+	.deinit = nvgpu_gr_fecs_trace_deinit,
+	.enable = nvgpu_gr_fecs_trace_enable,
+	.disable = nvgpu_gr_fecs_trace_disable,
+	.is_enabled = nvgpu_gr_fecs_trace_is_enabled,
+	.reset = nvgpu_gr_fecs_trace_reset,
+	.flush = NULL,
+	.poll = nvgpu_gr_fecs_trace_poll,
+	.bind_channel = nvgpu_gr_fecs_trace_bind_channel,
+	.unbind_channel = nvgpu_gr_fecs_trace_unbind_channel,
+	.max_entries = nvgpu_gr_fecs_trace_max_entries,
+	.get_buffer_full_mailbox_val = gv11b_fecs_trace_get_buffer_full_mailbox_val,
+	.get_read_index = gm20b_fecs_trace_get_read_index,
+	.get_write_index = gm20b_fecs_trace_get_write_index,
+	.set_read_index = gm20b_fecs_trace_set_read_index,
+};
+#endif
+
+static const struct gops_gr_setup ga100_ops_gr_setup = {
+	.alloc_obj_ctx = nvgpu_gr_setup_alloc_obj_ctx,
+	.free_gr_ctx = nvgpu_gr_setup_free_gr_ctx,
+	.free_subctx = nvgpu_gr_setup_free_subctx,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+	.set_preemption_mode = nvgpu_gr_setup_set_preemption_mode,
+};
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+static const struct gops_gr_zbc ga100_ops_gr_zbc = {
+	.add_color = gp10b_gr_zbc_add_color,
+	.add_depth = gp10b_gr_zbc_add_depth,
+	.set_table = nvgpu_gr_zbc_set_table,
+	.query_table = nvgpu_gr_zbc_query_table,
+	.add_stencil = gv11b_gr_zbc_add_stencil,
+	.get_gpcs_swdx_dss_zbc_c_format_reg = gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg,
+	.get_gpcs_swdx_dss_zbc_z_format_reg = gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg,
+	.init_table_indices = gv11b_gr_zbc_init_table_indices,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+static const struct gops_gr_zcull ga100_ops_gr_zcull = {
+	.init_zcull_hw = gm20b_gr_init_zcull_hw,
+	.get_zcull_info = gm20b_gr_get_zcull_info,
+	.program_zcull_mapping = gv11b_gr_program_zcull_mapping,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_gr_hwpm_map ga100_ops_gr_hwpm_map = {
+	.align_regs_perf_pma = gv100_gr_hwpm_map_align_regs_perf_pma,
+	.get_active_fbpa_mask = gv100_gr_hwpm_map_get_active_fbpa_mask,
+};
+#endif
+
+static const struct gops_gr_init ga100_ops_gr_init = {
+	.get_no_of_sm = nvgpu_gr_get_no_of_sm,
+	.get_nonpes_aware_tpc = gv11b_gr_init_get_nonpes_aware_tpc,
+	.wait_initialized = nvgpu_gr_wait_initialized,
+	.ecc_scrub_reg = NULL,
+	.lg_coalesce = NULL,
+	.su_coalesce = NULL,
+	.pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,
+	.gpc_mmu = ga10b_gr_init_gpc_mmu,
+	.reset_gpcs = ga10b_gr_init_reset_gpcs,
+	.fifo_access = gm20b_gr_init_fifo_access,
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
+	.get_access_map = gv11b_gr_init_get_access_map,
+#endif
+	.get_sm_id_size = gp10b_gr_init_get_sm_id_size,
+	.sm_id_config_early = nvgpu_gr_init_sm_id_early_config,
+	.sm_id_config = gv11b_gr_init_sm_id_config,
+	.sm_id_numbering = ga10b_gr_init_sm_id_numbering,
+	.tpc_mask = gv11b_gr_init_tpc_mask,
+	.fs_state = ga10b_gr_init_fs_state,
+	.pd_tpc_per_gpc = gm20b_gr_init_pd_tpc_per_gpc,
+	.pd_skip_table_gpc = gm20b_gr_init_pd_skip_table_gpc,
+	.cwd_gpcs_tpcs_num = gm20b_gr_init_cwd_gpcs_tpcs_num,
+	.wait_empty = ga10b_gr_init_wait_empty,
+	.wait_idle = ga10b_gr_init_wait_idle,
+	.wait_fe_idle = gm20b_gr_init_wait_fe_idle,
+#ifdef CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION
+	.restore_stats_counter_bundle_data = gv11b_gr_init_restore_stats_counter_bundle_data,
+#endif
+	.fe_pwr_mode_force_on = gm20b_gr_init_fe_pwr_mode_force_on,
+	.override_context_reset = ga100_gr_init_override_context_reset,
+	.fe_go_idle_timeout = ga10b_gr_init_fe_go_idle_timeout,
+	.auto_go_idle = ga10b_gr_init_auto_go_idle,
+	.load_method_init = gm20b_gr_init_load_method_init,
+	.commit_global_timeslice = ga10b_gr_init_commit_global_timeslice,
+	.get_bundle_cb_default_size = tu104_gr_init_get_bundle_cb_default_size,
+	.get_min_gpm_fifo_depth = ga100_gr_init_get_min_gpm_fifo_depth,
+	.get_bundle_cb_token_limit = ga100_gr_init_get_bundle_cb_token_limit,
+	.get_attrib_cb_default_size = ga100_gr_init_get_attrib_cb_default_size,
+	.get_alpha_cb_default_size = tu104_gr_init_get_alpha_cb_default_size,
+	.get_attrib_cb_size = gv11b_gr_init_get_attrib_cb_size,
+	.get_alpha_cb_size = gv11b_gr_init_get_alpha_cb_size,
+	.get_global_attr_cb_size = gv11b_gr_init_get_global_attr_cb_size,
+	.get_global_ctx_cb_buffer_size = gm20b_gr_init_get_global_ctx_cb_buffer_size,
+	.get_global_ctx_pagepool_buffer_size = gm20b_gr_init_get_global_ctx_pagepool_buffer_size,
+	.commit_global_bundle_cb = ga100_gr_init_commit_global_bundle_cb,
+	.pagepool_default_size = gp10b_gr_init_pagepool_default_size,
+	.commit_global_pagepool = gp10b_gr_init_commit_global_pagepool,
+	.commit_global_attrib_cb = gv11b_gr_init_commit_global_attrib_cb,
+	.commit_global_cb_manager = gp10b_gr_init_commit_global_cb_manager,
+#ifdef CONFIG_NVGPU_SM_DIVERSITY
+	.commit_sm_id_programming = gv11b_gr_init_commit_sm_id_programming,
+#endif
+	.pipe_mode_override = gm20b_gr_init_pipe_mode_override,
+#ifdef CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION
+	.load_sw_bundle_init = gv11b_gr_init_load_sw_bundle_init,
+#else
+	.load_sw_bundle_init = gm20b_gr_init_load_sw_bundle_init,
+#endif
+	.load_sw_veid_bundle = gv11b_gr_init_load_sw_veid_bundle,
+	.load_sw_bundle64 = tu104_gr_init_load_sw_bundle64,
+	.get_max_subctx_count = gv11b_gr_init_get_max_subctx_count,
+	.get_patch_slots = gv11b_gr_init_get_patch_slots,
+	.detect_sm_arch = gv11b_gr_init_detect_sm_arch,
+	.get_supported__preemption_modes = gp10b_gr_init_get_supported_preemption_modes,
+	.get_default_preemption_modes = gp10b_gr_init_get_default_preemption_modes,
+	.is_allowed_sw_bundle = gm20b_gr_init_is_allowed_sw_bundle,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.rop_mapping = gv11b_gr_init_rop_mapping,
+	.get_rtv_cb_size = tu104_gr_init_get_rtv_cb_size,
+	.commit_rtv_cb = tu104_gr_init_commit_rtv_cb,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+#ifdef CONFIG_NVGPU_GFXP
+	.preemption_state = gv11b_gr_init_preemption_state,
+	.get_ctx_attrib_cb_size = gp10b_gr_init_get_ctx_attrib_cb_size,
+	.commit_cbes_reserve = gv11b_gr_init_commit_cbes_reserve,
+	.commit_gfxp_rtv_cb = tu104_gr_init_commit_gfxp_rtv_cb,
+	.get_gfxp_rtv_cb_size = tu104_gr_init_get_gfxp_rtv_cb_size,
+	.get_attrib_cb_gfxp_default_size = ga100_gr_init_get_attrib_cb_gfxp_default_size,
+	.get_attrib_cb_gfxp_size = ga100_gr_init_get_attrib_cb_gfxp_size,
+	.gfxp_wfi_timeout = gv11b_gr_init_commit_gfxp_wfi_timeout,
+	.get_ctx_spill_size = ga100_gr_init_get_ctx_spill_size,
+	.get_ctx_pagepool_size = gp10b_gr_init_get_ctx_pagepool_size,
+	.get_ctx_betacb_size = ga100_gr_init_get_ctx_betacb_size,
+	.commit_ctxsw_spill = gv11b_gr_init_commit_ctxsw_spill,
+#endif /* CONFIG_NVGPU_GFXP */
+};
+
+static const struct gops_gr_intr ga100_ops_gr_intr = {
+	.handle_fecs_error = gv11b_gr_intr_handle_fecs_error,
+	.handle_sw_method = ga100_gr_intr_handle_sw_method,
+	.handle_class_error = gp10b_gr_intr_handle_class_error,
+	.clear_pending_interrupts = gm20b_gr_intr_clear_pending_interrupts,
+	.read_pending_interrupts = ga100_gr_intr_read_pending_interrupts,
+	.handle_exceptions = ga100_gr_intr_handle_exceptions,
+	.read_gpc_tpc_exception = gm20b_gr_intr_read_gpc_tpc_exception,
+	.read_gpc_exception = gm20b_gr_intr_read_gpc_exception,
+	.read_exception1 = gm20b_gr_intr_read_exception1,
+	.trapped_method_info = gm20b_gr_intr_get_trapped_method_info,
+	.handle_semaphore_pending = nvgpu_gr_intr_handle_semaphore_pending,
+	.handle_notify_pending = nvgpu_gr_intr_handle_notify_pending,
+	.handle_gcc_exception = gv11b_gr_intr_handle_gcc_exception,
+	.handle_gpc_gpcmmu_exception = ga10b_gr_intr_handle_gpc_gpcmmu_exception,
+	.handle_gpc_prop_exception = gv11b_gr_intr_handle_gpc_prop_exception,
+	.handle_gpc_zcull_exception = gv11b_gr_intr_handle_gpc_zcull_exception,
+	.handle_gpc_setup_exception = gv11b_gr_intr_handle_gpc_setup_exception,
+	.handle_gpc_pes_exception = gv11b_gr_intr_handle_gpc_pes_exception,
+	.handle_gpc_gpccs_exception = gv11b_gr_intr_handle_gpc_gpccs_exception,
+	.get_tpc_exception = ga10b_gr_intr_get_tpc_exception,
+	.handle_tpc_mpc_exception = gv11b_gr_intr_handle_tpc_mpc_exception,
+	.handle_tpc_pe_exception = gv11b_gr_intr_handle_tpc_pe_exception,
+	.enable_hww_exceptions = gv11b_gr_intr_enable_hww_exceptions,
+	.enable_mask = ga100_gr_intr_enable_mask,
+	.enable_interrupts = ga10b_gr_intr_enable_interrupts,
+	.enable_gpc_exceptions = ga100_gr_intr_enable_gpc_exceptions,
+	.enable_exceptions = ga100_gr_intr_enable_exceptions,
+	.nonstall_isr = NULL,
+	.handle_sm_exception = nvgpu_gr_intr_handle_sm_exception,
+	.stall_isr = nvgpu_gr_intr_stall_isr,
+	.retrigger = ga10b_gr_intr_retrigger,
+	.flush_channel_tlb = nvgpu_gr_intr_flush_channel_tlb,
+	.set_hww_esr_report_mask = ga10b_gr_intr_set_hww_esr_report_mask,
+	.handle_tpc_sm_ecc_exception = ga10b_gr_intr_handle_tpc_sm_ecc_exception,
+	.get_esr_sm_sel = gv11b_gr_intr_get_esr_sm_sel,
+	.clear_sm_hww = gv11b_gr_intr_clear_sm_hww,
+	.handle_ssync_hww = gv11b_gr_intr_handle_ssync_hww,
+	.log_mme_exception = tu104_gr_intr_log_mme_exception,
+	.record_sm_error_state = gv11b_gr_intr_record_sm_error_state,
+	.get_sm_hww_warp_esr = gv11b_gr_intr_get_sm_hww_warp_esr,
+	.get_sm_hww_warp_esr_pc = gv11b_gr_intr_get_sm_hww_warp_esr_pc,
+	.get_sm_hww_global_esr = gv11b_gr_intr_get_sm_hww_global_esr,
+	.get_sm_no_lock_down_hww_global_esr_mask = gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
+	.get_ctxsw_checksum_mismatch_mailbox_val = gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val,
+	.sm_ecc_status_errors = ga10b_gr_intr_sm_ecc_status_errors,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+	.handle_tex_exception = NULL,
+	.set_shader_exceptions = gv11b_gr_intr_set_shader_exceptions,
+	.tpc_exception_sm_enable = gm20b_gr_intr_tpc_exception_sm_enable,
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.tpc_exception_sm_disable = gm20b_gr_intr_tpc_exception_sm_disable,
+	.tpc_enabled_exceptions = gm20b_gr_intr_tpc_enabled_exceptions,
+#endif
+};
+
+static const struct gops_gr_falcon ga100_ops_gr_falcon = {
+	.handle_fecs_ecc_error = gv11b_gr_falcon_handle_fecs_ecc_error,
+	.read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_fecs_ctxsw_mailbox,
+	.fecs_host_clear_intr = gm20b_gr_falcon_fecs_host_clear_intr,
+	.fecs_host_intr_status = gm20b_gr_falcon_fecs_host_intr_status,
+	.fecs_base_addr = gm20b_gr_falcon_fecs_base_addr,
+	.gpccs_base_addr = gm20b_gr_falcon_gpccs_base_addr,
+	.set_current_ctx_invalid = gm20b_gr_falcon_set_current_ctx_invalid,
+	.dump_stats = ga10b_gr_falcon_dump_stats,
+	.fecs_ctxsw_mailbox_size = ga10b_gr_falcon_get_fecs_ctxsw_mailbox_size,
+	.fecs_ctxsw_clear_mailbox = ga10b_gr_falcon_fecs_ctxsw_clear_mailbox,
+	.get_fecs_ctx_state_store_major_rev_id = gm20b_gr_falcon_get_fecs_ctx_state_store_major_rev_id,
+	.start_gpccs = gm20b_gr_falcon_start_gpccs,
+	.start_fecs = gm20b_gr_falcon_start_fecs,
+	.get_gpccs_start_reg_offset = gm20b_gr_falcon_get_gpccs_start_reg_offset,
+	.bind_instblk = NULL,
+	.wait_mem_scrubbing = gm20b_gr_falcon_wait_mem_scrubbing,
+	.wait_ctxsw_ready = gm20b_gr_falcon_wait_ctxsw_ready,
+	.ctrl_ctxsw = ga100_gr_falcon_ctrl_ctxsw,
+	.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
+	.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
+	.get_fecs_current_ctx_data = gm20b_gr_falcon_get_fecs_current_ctx_data,
+	.init_ctx_state = gp10b_gr_falcon_init_ctx_state,
+	.fecs_host_int_enable = gv11b_gr_falcon_fecs_host_int_enable,
+	.read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_fecs_ctxsw_status0,
+	.read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_fecs_ctxsw_status1,
+	.load_ctxsw_ucode = nvgpu_gr_falcon_load_secure_ctxsw_ucode,
+#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
+	.load_ctxsw_ucode_header = gm20b_gr_falcon_load_ctxsw_ucode_header,
+	.load_ctxsw_ucode_boot = gm20b_gr_falcon_load_ctxsw_ucode_boot,
+	.load_gpccs_dmem = gm20b_gr_falcon_load_gpccs_dmem,
+	.gpccs_dmemc_write = ga10b_gr_falcon_gpccs_dmemc_write,
+	.load_fecs_dmem = gm20b_gr_falcon_load_fecs_dmem,
+	.fecs_dmemc_write = ga10b_gr_falcon_fecs_dmemc_write,
+	.load_gpccs_imem = gm20b_gr_falcon_load_gpccs_imem,
+	.gpccs_imemc_write = ga10b_gr_falcon_gpccs_imemc_write,
+	.load_fecs_imem = gm20b_gr_falcon_load_fecs_imem,
+	.fecs_imemc_write = ga10b_gr_falcon_fecs_imemc_write,
+	.start_ucode = gm20b_gr_falcon_start_ucode,
+#endif
+#ifdef CONFIG_NVGPU_SIM
+	.configure_fmodel = gm20b_gr_falcon_configure_fmodel,
+#endif
+};
+
+static const struct gops_gr ga100_ops_gr = {
+	.gr_init_support = nvgpu_gr_init_support,
+	.gr_suspend = nvgpu_gr_suspend,
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.get_gr_status = gr_gm20b_get_gr_status,
+	.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size,
+	.set_circular_buffer_size = gr_ga100_set_circular_buffer_size,
+	.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
+	.get_sm_dsm_perf_ctrl_regs = gr_tu104_get_sm_dsm_perf_ctrl_regs,
+#ifdef CONFIG_NVGPU_TEGRA_FUSE
+	.set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask,
+#endif
+	.dump_gr_regs = gr_ga100_dump_gr_status_regs,
+	.update_pc_sampling = NULL,
+	.init_sm_dsm_reg_info = gr_tu104_init_sm_dsm_reg_info,
+	.init_cyclestats = gr_gm20b_init_cyclestats,
+	.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode,
+	.bpt_reg_info = gv11b_gr_bpt_reg_info,
+	.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
+	.update_smpc_global_mode = tu104_gr_update_smpc_global_mode,
+	.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
+	.disable_cau = tu104_gr_disable_cau,
+	.disable_smpc = tu104_gr_disable_smpc,
+	.get_hwpm_cau_init_data = ga10b_gr_get_hwpm_cau_init_data,
+	.init_cau = tu104_gr_init_cau,
+	.clear_sm_error_state = gv11b_gr_clear_sm_error_state,
+	.suspend_contexts = gr_gp10b_suspend_contexts,
+	.resume_contexts = gr_gk20a_resume_contexts,
+	.trigger_suspend = NULL,
+	.wait_for_pause = NULL,
+	.resume_from_pause = NULL,
+	.clear_sm_errors = gr_gk20a_clear_sm_errors,
+	.is_tsg_ctx_resident = gk20a_is_tsg_ctx_resident,
+	.sm_debugger_attached = gv11b_gr_sm_debugger_attached,
+	.suspend_single_sm = gv11b_gr_suspend_single_sm,
+	.suspend_all_sms = gv11b_gr_suspend_all_sms,
+	.resume_single_sm = gv11b_gr_resume_single_sm,
+	.resume_all_sms = gv11b_gr_resume_all_sms,
+	.lock_down_sm = gv11b_gr_lock_down_sm,
+	.wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down,
+	.init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf,
+	.get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs,
+#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
+	.set_boosted_ctx = gr_gp10b_set_boosted_ctx,
+#endif
+	.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
+	.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
+	.set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
+	.is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
+	.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
+	.get_egpc_base = gv11b_gr_get_egpc_base,
+	.get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
+	.is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
+	.decode_egpc_addr = gv11b_gr_decode_egpc_addr,
+	.decode_priv_addr = gr_ga10b_decode_priv_addr,
+	.create_priv_addr_table = gr_ga10b_create_priv_addr_table,
+	.split_fbpa_broadcast_addr = gr_gv100_split_fbpa_broadcast_addr,
+	.get_offset_in_gpccs_segment = gr_tu104_get_offset_in_gpccs_segment,
+	.process_context_buffer_priv_segment =
+		gr_ga100_process_context_buffer_priv_segment,
+	.set_debug_mode = gm20b_gr_set_debug_mode,
+	.set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode,
+	.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
+	.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
+	.get_pm_ctx_buffer_offsets = gr_gk20a_get_pm_ctx_buffer_offsets,
+	.find_priv_offset_in_buffer =
+		gr_gk20a_find_priv_offset_in_buffer,
+	.check_warp_esr_error = ga10b_gr_check_warp_esr_error,
+#endif /* CONFIG_NVGPU_DEBUGGER */
+};
+
+static const struct gops_class ga100_ops_gpu_class = {
+	.is_valid = ga100_class_is_valid,
+	.is_valid_compute = ga100_class_is_valid_compute,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.is_valid_gfx = ga100_class_is_valid_gfx,
+#endif
+};
+
+static const struct gops_fb_ecc ga100_ops_fb_ecc = {
+	.init = ga10b_fb_ecc_init,
+	.free = ga10b_fb_ecc_free,
+	.l2tlb_error_mask = ga10b_fb_ecc_l2tlb_error_mask,
+};
+
+static const struct gops_fb_intr ga100_ops_fb_intr = {
+	.enable = ga10b_fb_intr_enable,
+	.disable = ga10b_fb_intr_disable,
+	.isr = ga10b_fb_intr_isr,
+	.is_mmu_fault_pending = NULL,
+	.handle_ecc = gv11b_fb_intr_handle_ecc,
+	.handle_ecc_l2tlb = ga10b_fb_intr_handle_ecc_l2tlb,
+	.handle_ecc_hubtlb = ga10b_fb_intr_handle_ecc_hubtlb,
+	.handle_ecc_fillunit = ga10b_fb_intr_handle_ecc_fillunit,
+};
+
+static const struct gops_fb ga100_ops_fb = {
+	.fbpa_ecc_init = tu104_fbpa_ecc_init,
+	.fbpa_ecc_free = tu104_fbpa_ecc_free,
+	.init_hw = ga10b_fb_init_hw,
+	.init_fs_state = ga100_fb_init_fs_state,
+	.set_mmu_page_size = NULL,
+	.mmu_ctrl = gm20b_fb_mmu_ctrl,
+	.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
+	.mmu_debug_wr = gm20b_fb_mmu_debug_wr,
+	.mmu_debug_rd = gm20b_fb_mmu_debug_rd,
+#ifdef CONFIG_NVGPU_COMPRESSION
+	.is_comptagline_mode_enabled = ga100_fb_is_comptagline_mode_enabled,
+	.cbc_configure = tu104_fb_cbc_configure,
+	.set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line,
+	.compression_page_size = ga100_fb_compression_page_size,
+	.compressible_page_size = gp10b_fb_compressible_page_size,
+	.compression_align_mask = gm20b_fb_compression_align_mask,
+#endif
+	.vpr_info_fetch = ga10b_fb_vpr_info_fetch,
+	.dump_vpr_info = ga10b_fb_dump_vpr_info,
+	.dump_wpr_info = ga10b_fb_dump_wpr_info,
+	.read_wpr_info = ga10b_fb_read_wpr_info,
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
+	.set_debug_mode = gm20b_fb_set_debug_mode,
+	.set_mmu_debug_mode = gv100_fb_set_mmu_debug_mode,
+#endif
+	.tlb_invalidate = fb_tu104_tlb_invalidate,
+#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
+	.handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault,
+	.mmu_invalidate_replay = tu104_fb_mmu_invalidate_replay,
+#endif
+	.mem_unlock = NULL,
+	.init_fbpa = tu104_fbpa_init,
+	.handle_fbpa_intr = tu104_fbpa_handle_intr,
+	.write_mmu_fault_buffer_lo_hi = tu104_fb_write_mmu_fault_buffer_lo_hi,
+	.write_mmu_fault_buffer_get = tu104_fb_write_mmu_fault_buffer_get,
+	.write_mmu_fault_buffer_size = tu104_fb_write_mmu_fault_buffer_size,
+	.write_mmu_fault_status = tu104_fb_write_mmu_fault_status,
+	.read_mmu_fault_buffer_get = tu104_fb_read_mmu_fault_buffer_get,
+	.read_mmu_fault_buffer_put = tu104_fb_read_mmu_fault_buffer_put,
+	.read_mmu_fault_buffer_size = tu104_fb_read_mmu_fault_buffer_size,
+	.read_mmu_fault_addr_lo_hi = tu104_fb_read_mmu_fault_addr_lo_hi,
+	.read_mmu_fault_inst_lo_hi = tu104_fb_read_mmu_fault_inst_lo_hi,
+	.read_mmu_fault_info = tu104_fb_read_mmu_fault_info,
+	.read_mmu_fault_status = tu104_fb_read_mmu_fault_status,
+	.is_fault_buf_enabled = gv11b_fb_is_fault_buf_enabled,
+	.fault_buf_set_state_hw = gv11b_fb_fault_buf_set_state_hw,
+	.fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw,
+	.get_num_active_ltcs = ga10b_fb_get_num_active_ltcs,
+#ifdef CONFIG_NVGPU_DGPU
+	.get_vidmem_size = tu104_fb_get_vidmem_size,
+#endif
+#ifdef CONFIG_NVGPU_MIG
+	.config_veid_smc_map = ga10b_fb_config_veid_smc_map,
+	.set_smc_eng_config = ga10b_fb_set_smc_eng_config,
+	.set_remote_swizid = ga10b_fb_set_remote_swizid,
+#endif
+};
+
+static const struct gops_nvdec ga100_ops_nvdec = {
+	.falcon_base_addr = ga100_nvdec_falcon_base_addr,
+};
+
+static const struct gops_cg ga100_ops_cg = {
+	.slcg_bus_load_gating_prod = ga100_slcg_bus_load_gating_prod,
+	.slcg_ce2_load_gating_prod = ga100_slcg_ce2_load_gating_prod,
+	.slcg_chiplet_load_gating_prod = ga100_slcg_chiplet_load_gating_prod,
+	.slcg_fb_load_gating_prod = ga100_slcg_fb_load_gating_prod,
+	.slcg_fifo_load_gating_prod = NULL,
+	.slcg_runlist_load_gating_prod = ga100_slcg_runlist_load_gating_prod,
+	.slcg_gr_load_gating_prod = ga100_slcg_gr_load_gating_prod,
+	.slcg_ltc_load_gating_prod = ga100_slcg_ltc_load_gating_prod,
+	.slcg_perf_load_gating_prod = ga100_slcg_perf_load_gating_prod,
+	.slcg_priring_load_gating_prod = ga100_slcg_priring_load_gating_prod,
+	.slcg_pmu_load_gating_prod = ga100_slcg_pmu_load_gating_prod,
+	.slcg_therm_load_gating_prod = ga100_slcg_therm_load_gating_prod,
+	.slcg_xbar_load_gating_prod = ga100_slcg_xbar_load_gating_prod,
+	.slcg_hshub_load_gating_prod = ga100_slcg_hshub_load_gating_prod,
+	.slcg_timer_load_gating_prod = ga100_slcg_timer_load_gating_prod,
+	.blcg_bus_load_gating_prod = ga100_blcg_bus_load_gating_prod,
+	.blcg_ce_load_gating_prod = ga100_blcg_ce_load_gating_prod,
+	.blcg_fb_load_gating_prod = ga100_blcg_fb_load_gating_prod,
+	.blcg_fifo_load_gating_prod = NULL,
+	.blcg_runlist_load_gating_prod = ga100_blcg_runlist_load_gating_prod,
+	.blcg_gr_load_gating_prod = ga100_blcg_gr_load_gating_prod,
+	.blcg_ltc_load_gating_prod = ga100_blcg_ltc_load_gating_prod,
+	.blcg_pmu_load_gating_prod = ga100_blcg_pmu_load_gating_prod,
+	.blcg_xbar_load_gating_prod = ga100_blcg_xbar_load_gating_prod,
+	.blcg_hshub_load_gating_prod = ga100_blcg_hshub_load_gating_prod,
+	.elcg_ce_load_gating_prod = ga100_elcg_ce_load_gating_prod,
+};
+
+static const struct gops_fifo ga100_ops_fifo = {
+	.fifo_init_support = nvgpu_fifo_init_support,
+	.fifo_suspend = nvgpu_fifo_suspend,
+	.init_fifo_setup_hw = ga10b_init_fifo_setup_hw,
+	.preempt_channel = gv11b_fifo_preempt_channel,
+	.preempt_tsg = nvgpu_fifo_preempt_tsg,
+	.preempt_trigger = ga10b_fifo_preempt_trigger,
+	.preempt_poll_pbdma = gv11b_fifo_preempt_poll_pbdma,
+	.is_preempt_pending = gv11b_fifo_is_preempt_pending,
+	.reset_enable_hw = ga10b_init_fifo_reset_enable_hw,
+#ifdef CONFIG_NVGPU_RECOVERY
+	.recover = gv11b_fifo_recover,
+#endif
+	.intr_set_recover_mask = ga10b_fifo_intr_set_recover_mask,
+	.intr_unset_recover_mask = ga10b_fifo_intr_unset_recover_mask,
+	.setup_sw = nvgpu_fifo_setup_sw,
+	.cleanup_sw = nvgpu_fifo_cleanup_sw,
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.set_sm_exception_type_mask = nvgpu_tsg_set_sm_exception_type_mask,
+#endif
+	.intr_top_enable = ga10b_fifo_intr_top_enable,
+	.intr_0_enable = ga10b_fifo_intr_0_enable,
+	.intr_1_enable = ga10b_fifo_intr_1_enable,
+	.intr_0_isr = ga10b_fifo_intr_0_isr,
+	.intr_1_isr = NULL,
+	.runlist_intr_retrigger = ga10b_fifo_runlist_intr_retrigger,
+	.handle_sched_error = NULL,
+	.ctxsw_timeout_enable = ga10b_fifo_ctxsw_timeout_enable,
+	.handle_ctxsw_timeout = NULL,
+	.trigger_mmu_fault = NULL,
+	.get_mmu_fault_info = NULL,
+	.get_mmu_fault_desc = NULL,
+	.get_mmu_fault_client_desc = NULL,
+	.get_mmu_fault_gpc_desc = NULL,
+	.get_runlist_timeslice = NULL,
+	.get_pb_timeslice = NULL,
+	.mmu_fault_id_to_pbdma_id = ga10b_fifo_mmu_fault_id_to_pbdma_id,
+};
+
+static const struct gops_engine ga100_ops_engine = {
+	.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
+	.init_ce_info = gp10b_engine_init_ce_info,
+};
+
+static const struct gops_pbdma ga100_ops_pbdma = {
+	.setup_sw = nvgpu_pbdma_setup_sw,
+	.cleanup_sw = nvgpu_pbdma_cleanup_sw,
+	.setup_hw = NULL,
+	.intr_enable = ga10b_pbdma_intr_enable,
+	.acquire_val = gm20b_pbdma_acquire_val,
+	.get_signature = gp10b_pbdma_get_signature,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+	.syncpt_debug_dump = NULL,
+	.dump_status = ga10b_pbdma_dump_status,
+#endif
+	.handle_intr_0 = ga10b_pbdma_handle_intr_0,
+	.handle_intr_1 = ga10b_pbdma_handle_intr_1,
+	.handle_intr = ga10b_pbdma_handle_intr,
+	.set_clear_intr_offsets = ga100_pbdma_set_clear_intr_offsets,
+	.read_data = ga100_pbdma_read_data,
+	.reset_header = ga10b_pbdma_reset_header,
+	.device_fatal_0_intr_descs = ga10b_pbdma_device_fatal_0_intr_descs,
+	.channel_fatal_0_intr_descs = ga10b_pbdma_channel_fatal_0_intr_descs,
+	.restartable_0_intr_descs = gm20b_pbdma_restartable_0_intr_descs,
+	.format_gpfifo_entry = gm20b_pbdma_format_gpfifo_entry,
+	.get_gp_base = gm20b_pbdma_get_gp_base,
+	.get_gp_base_hi = gm20b_pbdma_get_gp_base_hi,
+	.get_fc_formats = NULL,
+	.get_fc_pb_header = gv11b_pbdma_get_fc_pb_header,
+	.get_fc_subdevice = gm20b_pbdma_get_fc_subdevice,
+	.get_fc_target = ga100_pbdma_get_fc_target,
+	.get_ctrl_hce_priv_mode_yes = gm20b_pbdma_get_ctrl_hce_priv_mode_yes,
+	.get_userd_aperture_mask = NULL,
+	.get_userd_addr = NULL,
+	.get_userd_hi_addr = NULL,
+	.get_fc_runlist_timeslice = NULL,
+	.get_config_auth_level_privileged = gp10b_pbdma_get_config_auth_level_privileged,
+	.set_channel_info_veid = gv11b_pbdma_set_channel_info_veid,
+	.set_channel_info_chid = ga10b_pbdma_set_channel_info_chid,
+	.set_intr_notify = ga10b_pbdma_set_intr_notify,
+	.pbdma_force_ce_split = ga100_pbdma_force_ce_split,
+	.config_userd_writeback_enable = gv11b_pbdma_config_userd_writeback_enable,
+	.get_mmu_fault_id = ga10b_pbdma_get_mmu_fault_id,
+	.get_num_of_pbdmas = ga100_pbdma_get_num_of_pbdmas,
+};
+
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+static const struct gops_sync_syncpt ga100_ops_sync_syncpt = {
+	.alloc_buf = gv11b_syncpt_alloc_buf,
+	.free_buf = gv11b_syncpt_free_buf,
+#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
+	.add_wait_cmd = gv11b_syncpt_add_wait_cmd,
+	.get_wait_cmd_size = gv11b_syncpt_get_wait_cmd_size,
+	.add_incr_cmd = gv11b_syncpt_add_incr_cmd,
+	.get_incr_cmd_size = gv11b_syncpt_get_incr_cmd_size,
+	.get_incr_per_release = gv11b_syncpt_get_incr_per_release,
+#endif
+	.get_sync_ro_map = gv11b_syncpt_get_sync_ro_map,
+};
+#endif
+
+#if defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT) && \
+	defined(CONFIG_NVGPU_SW_SEMAPHORE)
+static const struct gops_sync_sema ga100_ops_sync_sema = {
+	.add_wait_cmd = gv11b_sema_add_wait_cmd,
+	.get_wait_cmd_size = gv11b_sema_get_wait_cmd_size,
+	.add_incr_cmd = gv11b_sema_add_incr_cmd,
+	.get_incr_cmd_size = gv11b_sema_get_incr_cmd_size,
+};
+#endif
+
+static const struct gops_sync ga100_ops_sync = {
+};
+
+static const struct gops_engine_status ga100_ops_engine_status = {
+	.read_engine_status_info = ga10b_read_engine_status_info,
+	/* TODO update this hal for ga100 */
+	.dump_engine_status = gv100_dump_engine_status,
+};
+
+static const struct gops_pbdma_status ga100_ops_pbdma_status = {
+	.read_pbdma_status_info = ga10b_read_pbdma_status_info,
+};
+
+static const struct gops_ramfc ga100_ops_ramfc = {
+	.setup = ga10b_ramfc_setup,
+	.capture_ram_dump = ga10b_ramfc_capture_ram_dump,
+	.commit_userd = NULL,
+	.get_syncpt = NULL,
+	.set_syncpt = NULL,
+};
+
+static const struct gops_ramin ga100_ops_ramin = {
+	.set_gr_ptr = gv11b_ramin_set_gr_ptr,
+	.set_big_page_size = gm20b_ramin_set_big_page_size,
+	.init_pdb = ga10b_ramin_init_pdb,
+	.init_subctx_pdb = gv11b_ramin_init_subctx_pdb,
+	.set_adr_limit = NULL,
+	.base_shift = gk20a_ramin_base_shift,
+	.alloc_size = gk20a_ramin_alloc_size,
+	.set_eng_method_buffer = gv11b_ramin_set_eng_method_buffer,
+};
+
+static const struct gops_runlist ga100_ops_runlist = {
+#ifdef NVGPU_CHANNEL_TSG_SCHEDULING
+	.reschedule = gv11b_runlist_reschedule,
+	.reschedule_preempt_next_locked = ga10b_fifo_reschedule_preempt_next,
+#endif
+	.update = nvgpu_runlist_update,
+	.reload = nvgpu_runlist_reload,
+	.count_max = ga100_runlist_count_max,
+	.entry_size = gv11b_runlist_entry_size,
+	.length_max = ga10b_runlist_length_max,
+	.get_tsg_entry = gv11b_runlist_get_tsg_entry,
+	.get_ch_entry = gv11b_runlist_get_ch_entry,
+	.hw_submit = ga100_runlist_hw_submit,
+	.wait_pending = ga10b_runlist_wait_pending,
+	.write_state = ga10b_runlist_write_state,
+	.get_runlist_id = ga10b_runlist_get_runlist_id,
+	.get_engine_id_from_rleng_id = ga10b_runlist_get_engine_id_from_rleng_id,
+	.get_chram_bar0_offset = ga10b_runlist_get_chram_bar0_offset,
+	.get_pbdma_info = ga10b_runlist_get_pbdma_info,
+	.get_engine_intr_id = ga10b_runlist_get_engine_intr_id,
+	.init_enginfo = nvgpu_next_runlist_init_enginfo,
+	.get_tsg_max_timeslice = gv11b_runlist_max_timeslice,
+	.get_esched_fb_thread_id = ga10b_runlist_get_esched_fb_thread_id,
+};
+
+static const struct gops_userd ga100_ops_userd = {
+#ifdef CONFIG_NVGPU_USERD
+	.setup_sw = nvgpu_userd_setup_sw,
+	.cleanup_sw = nvgpu_userd_cleanup_sw,
+	.init_mem = ga10b_userd_init_mem,
+#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
+	.gp_get = gv11b_userd_gp_get,
+	.gp_put = gv11b_userd_gp_put,
+	.pb_get = gv11b_userd_pb_get,
+#endif
+#endif /* CONFIG_NVGPU_USERD */
+	.entry_size = gk20a_userd_entry_size,
+};
+
+static const struct gops_channel ga100_ops_channel = {
+	.alloc_inst = nvgpu_channel_alloc_inst,
+	.free_inst = nvgpu_channel_free_inst,
+	.bind = ga10b_channel_bind,
+	.unbind = ga10b_channel_unbind,
+	.clear = ga10b_channel_unbind,
+	.enable = ga10b_channel_enable,
+	.disable = ga10b_channel_disable,
+	.count = ga100_channel_count,
+	.read_state = ga10b_channel_read_state,
+	.force_ctx_reload = ga10b_channel_force_ctx_reload,
+	.abort_clean_up = nvgpu_channel_abort_clean_up,
+	.suspend_all_serviceable_ch = nvgpu_channel_suspend_all_serviceable_ch,
+	.resume_all_serviceable_ch = nvgpu_channel_resume_all_serviceable_ch,
+	.set_error_notifier = nvgpu_set_err_notifier_if_empty,
+	.reset_faulted = ga10b_channel_reset_faulted,
+};
+
+static const struct gops_tsg ga100_ops_tsg = {
+	.enable = gv11b_tsg_enable,
+	.disable = nvgpu_tsg_disable,
+	.init_eng_method_buffers = gv11b_tsg_init_eng_method_buffers,
+	.deinit_eng_method_buffers = gv11b_tsg_deinit_eng_method_buffers,
+	.bind_channel = NULL,
+	.bind_channel_eng_method_buffers = gv11b_tsg_bind_channel_eng_method_buffers,
+	.unbind_channel = NULL,
+	.unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_check_hw_state,
+	.unbind_channel_check_hw_next = ga10b_tsg_unbind_channel_check_hw_next,
+	.unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_check_ctx_reload,
+	.unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted,
+#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
+	.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
+#endif
+#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL
+	.force_reset = nvgpu_tsg_force_reset_ch,
+	.post_event_id = nvgpu_tsg_post_event_id,
+#endif
+#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
+	.set_timeslice = nvgpu_tsg_set_timeslice,
+	.set_long_timeslice = nvgpu_tsg_set_long_timeslice,
+#endif
+	.default_timeslice_us = nvgpu_tsg_default_timeslice_us,
+};
+
+static const struct gops_usermode ga100_ops_usermode = {
+	.setup_hw = ga10b_usermode_setup_hw,
+	.base = tu104_usermode_base,
+	.bus_base = tu104_usermode_bus_base,
+	.ring_doorbell = tu104_usermode_ring_doorbell,
+	.doorbell_token = tu104_usermode_doorbell_token,
+};
+
+static const struct gops_netlist ga100_ops_netlist = {
+	.get_netlist_name = ga100_netlist_get_name,
+	.is_fw_defined = ga100_netlist_is_firmware_defined,
+};
+
+static const struct gops_mm_mmu_fault ga100_ops_mm_mmu_fault = {
+	.setup_sw = gv11b_mm_mmu_fault_setup_sw,
+	.setup_hw = gv11b_mm_mmu_fault_setup_hw,
+	.info_mem_destroy = gv11b_mm_mmu_fault_info_mem_destroy,
+	.disable_hw = gv11b_mm_mmu_fault_disable_hw,
+	.parse_mmu_fault_info = ga10b_mm_mmu_fault_parse_mmu_fault_info,
+};
+
+static const struct gops_mm_cache ga100_ops_mm_cache = {
+	.fb_flush = gk20a_mm_fb_flush,
+	.l2_invalidate = gk20a_mm_l2_invalidate,
+	.l2_flush = gv11b_mm_l2_flush,
+#ifdef CONFIG_NVGPU_COMPRESSION
+	.cbc_clean = gk20a_mm_cbc_clean,
+#endif
+};
+
+static const struct gops_mm_gmmu ga100_ops_mm_gmmu = {
+	.get_mmu_levels = ga10b_mm_get_mmu_levels,
+	.get_max_page_table_levels = ga10b_get_max_page_table_levels,
+	.map = nvgpu_gmmu_map_locked,
+	.unmap = nvgpu_gmmu_unmap_locked,
+	.get_big_page_sizes = gm20b_mm_get_big_page_sizes,
+	.get_default_big_page_size = nvgpu_gmmu_default_big_page_size,
+	/* iommu bit is not applicable for dgpu */
+	.get_iommu_bit = NULL,
+	.gpu_phys_addr = gv11b_gpu_phys_addr,
+};
+
+static const struct gops_mm ga100_ops_mm = {
+	.init_mm_support = nvgpu_init_mm_support,
+	.pd_cache_init = nvgpu_pd_cache_init,
+	.mm_suspend = nvgpu_mm_suspend,
+	.vm_bind_channel = nvgpu_vm_bind_channel,
+	.setup_hw = nvgpu_mm_setup_hw,
+	.is_bar1_supported = gv11b_mm_is_bar1_supported,
+	.init_inst_block = gv11b_mm_init_inst_block,
+	.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
+	.init_bar2_vm = gp10b_mm_init_bar2_vm,
+	.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
+	.get_flush_retries = tu104_mm_get_flush_retries,
+	.get_default_va_sizes = gp10b_mm_get_default_va_sizes,
+	.bar1_map_userd = NULL,
+};
+
+static const struct gops_therm ga100_ops_therm = {
+	.therm_max_fpdiv_factor = ga10b_therm_max_fpdiv_factor,
+	.init_therm_support = nvgpu_init_therm_support,
+	/* PROD values match with H/W INIT values */
+	.init_elcg_mode = gv11b_therm_init_elcg_mode,
+#ifdef CONFIG_NVGPU_NON_FUSA
+	.init_blcg_mode = gm20b_therm_init_blcg_mode,
+#endif
+	.elcg_init_idle_filters = NULL,
+#ifdef CONFIG_NVGPU_LS_PMU
+	.get_internal_sensor_limits = tu104_get_internal_sensor_limits,
+#endif
+};
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_pmu ga100_ops_pmu = {
+	.ecc_init = gv11b_pmu_ecc_init,
+	.ecc_free = gv11b_pmu_ecc_free,
+	/* Init */
+	.pmu_early_init = nvgpu_pmu_early_init,
+	.pmu_rtos_init = nvgpu_pmu_rtos_init,
+	.pmu_pstate_sw_setup = nvgpu_pmu_pstate_sw_setup,
+	.pmu_pstate_pmu_setup = nvgpu_pmu_pstate_pmu_setup,
+	.pmu_destroy = nvgpu_pmu_destroy,
+	.falcon_base_addr = tu104_pmu_falcon_base_addr,
+	.pmu_queue_tail = gk20a_pmu_queue_tail,
+	.pmu_get_queue_head = tu104_pmu_queue_head_r,
+	.pmu_mutex_release = gk20a_pmu_mutex_release,
+	.pmu_is_interrupted = gk20a_pmu_is_interrupted,
+	.pmu_isr = gk20a_pmu_isr,
+	.pmu_init_perfmon_counter = ga10b_pmu_init_perfmon_counter,
+	.pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config,
+	.pmu_read_idle_counter = ga10b_pmu_read_idle_counter,
+	.pmu_reset_idle_counter = ga10b_pmu_reset_idle_counter,
+	.pmu_read_idle_intr_status = gk20a_pmu_read_idle_intr_status,
+	.pmu_clear_idle_intr_status = gk20a_pmu_clear_idle_intr_status,
+	.pmu_dump_elpg_stats = ga10b_pmu_dump_elpg_stats,
+	.pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats,
+	.pmu_enable_irq = gv11b_pmu_enable_irq,
+	.is_pmu_supported = ga100_is_pmu_supported,
+	.pmu_mutex_owner = gk20a_pmu_mutex_owner,
+	.pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
+	.pmu_msgq_tail = gk20a_pmu_msgq_tail,
+	.pmu_get_queue_head_size = tu104_pmu_queue_head__size_1_v,
+	.pmu_reset = nvgpu_pmu_reset,
+	.pmu_queue_head = gk20a_pmu_queue_head,
+	.pmu_get_queue_tail_size = tu104_pmu_queue_tail__size_1_v,
+	.reset_engine = gv11b_pmu_engine_reset,
+	.write_dmatrfbase = gp10b_write_dmatrfbase,
+	.pmu_mutex_size = tu104_pmu_mutex__size_1_v,
+	.is_engine_in_reset = gv11b_pmu_is_engine_in_reset,
+	.pmu_get_queue_tail = tu104_pmu_queue_tail_r,
+	.get_irqdest = gk20a_pmu_get_irqdest,
+	.handle_ext_irq = NULL,
+	.is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en,
+	.setup_apertures = tu104_pmu_setup_apertures,
+	.secured_pmu_start = gm20b_secured_pmu_start,
+	.pmu_clear_bar0_host_err_status = gm20b_clear_pmu_bar0_host_err_status,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_clk ga100_ops_clk = {
+#ifdef CONFIG_NVGPU_CLK_ARB
+	.init_clk_support = tu104_init_clk_support,
+	.get_crystal_clk_hz = tu104_crystal_clk_hz,
+	.get_rate_cntr = tu104_get_rate_cntr,
+	.measure_freq = tu104_clk_measure_freq,
+	.suspend_clk_support = tu104_suspend_clk_support,
+	.clk_domain_get_f_points = tu104_clk_domain_get_f_points,
+	.get_maxrate = tu104_clk_maxrate,
+	.get_change_seq_time = tu104_get_change_seq_time,
+	.get_cntr_xbarclk_source = ga100_clk_get_cntr_xbarclk_source,
+	.get_cntr_sysclk_source = ga100_clk_get_cntr_sysclk_source,
+#endif
+	.change_host_clk_source = tu104_change_host_clk_source,
+	.perf_pmu_vfe_load = nvgpu_pmu_perf_load,
+	.clk_mon_init_domains = nvgpu_pmu_clk_mon_init_domains,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_clk_mon ga100_ops_clk_mon = {
+	.clk_mon_alloc_memory = nvgpu_clk_mon_alloc_memory,
+	.clk_mon_check_master_fault_status = tu104_clk_mon_check_master_fault_status,
+	.clk_mon_check_status = tu104_clk_mon_check_status,
+	.clk_mon_check_clk_good = tu104_clk_mon_check_clk_good,
+	.clk_mon_check_pll_lock = tu104_clk_mon_check_pll_lock,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_CLK_ARB
+static const struct gops_clk_arb ga100_ops_clk_arb = {
+	.clk_arb_init_arbiter = nvgpu_clk_arb_init_arbiter,
+	.check_clk_arb_support = gv100_check_clk_arb_support,
+	.get_arbiter_clk_domains = gv100_get_arbiter_clk_domains,
+	.get_arbiter_f_points = gv100_get_arbiter_f_points,
+	.get_arbiter_clk_range = gv100_get_arbiter_clk_range,
+	.get_arbiter_clk_default = gv100_get_arbiter_clk_default,
+	.get_current_pstate = nvgpu_clk_arb_get_current_pstate,
+	.arbiter_clk_init = gv100_init_clk_arbiter,
+	.clk_arb_run_arbiter_cb = gv100_clk_arb_run_arbiter_cb,
+	.clk_arb_cleanup = gv100_clk_arb_cleanup,
+	.stop_clk_arb_threads = gv100_stop_clk_arb_threads,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_regops ga100_ops_regops = {
+	.exec_regops = exec_regops_gk20a,
+	.get_global_whitelist_ranges = ga100_get_global_whitelist_ranges,
+	.get_global_whitelist_ranges_count = ga100_get_global_whitelist_ranges_count,
+	.get_context_whitelist_ranges = ga100_get_context_whitelist_ranges,
+	.get_context_whitelist_ranges_count = ga100_get_context_whitelist_ranges_count,
+	.get_runcontrol_whitelist = ga100_get_runcontrol_whitelist,
+	.get_runcontrol_whitelist_count = ga100_get_runcontrol_whitelist_count,
+	.get_hwpm_router_register_stride = ga100_get_hwpm_router_register_stride,
+	.get_hwpm_perfmon_register_stride = ga100_get_hwpm_perfmon_register_stride,
+	.get_hwpm_pma_channel_register_stride = ga100_get_hwpm_pma_channel_register_stride,
+	.get_hwpm_pma_trigger_register_stride = ga100_get_hwpm_pma_trigger_register_stride,
+	.get_smpc_register_stride = ga100_get_smpc_register_stride,
+	.get_cau_register_stride = ga100_get_cau_register_stride,
+	.get_hwpm_perfmon_register_offset_allowlist =
+	    ga100_get_hwpm_perfmon_register_offset_allowlist,
+	.get_hwpm_router_register_offset_allowlist =
+	    ga100_get_hwpm_router_register_offset_allowlist,
+	.get_hwpm_pma_channel_register_offset_allowlist =
+	    ga100_get_hwpm_pma_channel_register_offset_allowlist,
+	.get_hwpm_pma_trigger_register_offset_allowlist =
+	    ga100_get_hwpm_pma_trigger_register_offset_allowlist,
+	.get_smpc_register_offset_allowlist = ga100_get_smpc_register_offset_allowlist,
+	.get_cau_register_offset_allowlist = ga100_get_cau_register_offset_allowlist,
+	.get_hwpm_perfmon_register_ranges = ga100_get_hwpm_perfmon_register_ranges,
+	.get_hwpm_router_register_ranges = ga100_get_hwpm_router_register_ranges,
+	.get_hwpm_pma_channel_register_ranges = ga100_get_hwpm_pma_channel_register_ranges,
+	.get_hwpm_pma_trigger_register_ranges = ga100_get_hwpm_pma_trigger_register_ranges,
+	.get_smpc_register_ranges = ga100_get_smpc_register_ranges,
+	.get_cau_register_ranges = ga100_get_cau_register_ranges,
+	.get_hwpm_perfmux_register_ranges = ga100_get_hwpm_perfmux_register_ranges,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_mc ga100_ops_mc = {
+	.get_chip_details = gm20b_get_chip_details,
+	.intr_mask = ga10b_intr_mask_top,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+	.intr_enable = NULL,
+#endif
+	.intr_nonstall_unit_config = ga10b_intr_host2soc_0_unit_config,
+	.intr_nonstall = ga10b_intr_host2soc_0,
+	.intr_nonstall_pause = ga10b_intr_host2soc_0_pause,
+	.intr_nonstall_resume = ga10b_intr_host2soc_0_resume,
+	.isr_nonstall = ga10b_intr_isr_host2soc_0,
+	.intr_stall_unit_config = ga10b_intr_stall_unit_config,
+	.intr_stall = ga10b_intr_stall,
+	.intr_stall_pause = ga10b_intr_stall_pause,
+	.intr_stall_resume = ga10b_intr_stall_resume,
+	.isr_stall = ga10b_intr_isr_stall,
+	.is_intr1_pending = NULL,
+	.enable_units = ga10b_mc_enable_units,
+	.enable_dev = ga10b_mc_enable_dev,
+	.enable_devtype = ga10b_mc_enable_devtype,
+#ifdef CONFIG_NVGPU_NON_FUSA
+	.log_pending_intrs = ga10b_intr_log_pending_intrs,
+#endif
+	.is_intr_hub_pending = NULL,
+	.is_stall_and_eng_intr_pending = ga10b_intr_is_stall_and_eng_intr_pending,
+#ifdef CONFIG_NVGPU_LS_PMU
+	.is_enabled = gm20b_mc_is_enabled,
+#endif
+	.fb_reset = NULL,
+	.ltc_isr = mc_tu104_ltc_isr,
+	.is_mmu_fault_pending = ga10b_intr_is_mmu_fault_pending,
+	.intr_get_unit_info = ga10b_mc_intr_get_unit_info,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_debug ga100_ops_debug = {
+	.show_dump = gk20a_debug_show_dump,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_debugger ga100_ops_debugger = {
+	.post_events = nvgpu_dbg_gpu_post_events,
+	.dbg_set_powergate = nvgpu_dbg_set_powergate,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_perf ga100_ops_perf = {
+	.enable_membuf = ga10b_perf_enable_membuf,
+	.disable_membuf = ga10b_perf_disable_membuf,
+	.bind_mem_bytes_buffer_addr = ga10b_perf_bind_mem_bytes_buffer_addr,
+	.init_inst_block = ga10b_perf_init_inst_block,
+	.deinit_inst_block = ga10b_perf_deinit_inst_block,
+	.membuf_reset_streaming = ga10b_perf_membuf_reset_streaming,
+	.get_membuf_pending_bytes = ga10b_perf_get_membuf_pending_bytes,
+	.set_membuf_handled_bytes = ga10b_perf_set_membuf_handled_bytes,
+	.get_membuf_overflow_status = ga10b_perf_get_membuf_overflow_status,
+	.get_pmmsys_per_chiplet_offset = ga100_perf_get_pmmsys_per_chiplet_offset,
+	.get_pmmgpc_per_chiplet_offset = ga100_perf_get_pmmgpc_per_chiplet_offset,
+	.get_pmmfbp_per_chiplet_offset = ga100_perf_get_pmmfbp_per_chiplet_offset,
+	.update_get_put = ga10b_perf_update_get_put,
+	.get_hwpm_sys_perfmon_regs = ga100_perf_get_hwpm_sys_perfmon_regs,
+	.get_hwpm_gpc_perfmon_regs = ga100_perf_get_hwpm_gpc_perfmon_regs,
+	.get_hwpm_fbp_perfmon_regs = ga100_perf_get_hwpm_fbp_perfmon_regs,
+	.set_pmm_register = gv11b_perf_set_pmm_register,
+	.get_num_hwpm_perfmon = ga100_perf_get_num_hwpm_perfmon,
+	.init_hwpm_pmm_register = ga10b_perf_init_hwpm_pmm_register,
+	.reset_hwpm_pmm_registers = gv11b_perf_reset_hwpm_pmm_registers,
+	.pma_stream_enable = ga10b_perf_pma_stream_enable,
+	.disable_all_perfmons = ga10b_perf_disable_all_perfmons,
+	.wait_for_idle_pmm_routers = gv11b_perf_wait_for_idle_pmm_routers,
+	.wait_for_idle_pma = ga10b_perf_wait_for_idle_pma,
+	.enable_hs_streaming = ga10b_perf_enable_hs_streaming,
+	.reset_hs_streaming_credits = ga10b_perf_reset_hs_streaming_credits,
+	.enable_pmasys_legacy_mode = ga10b_perf_enable_pmasys_legacy_mode,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_perfbuf ga100_ops_perfbuf = {
+	.perfbuf_enable = nvgpu_perfbuf_enable_locked,
+	.perfbuf_disable = nvgpu_perfbuf_disable_locked,
+	.init_inst_block = nvgpu_perfbuf_init_inst_block,
+	.deinit_inst_block = nvgpu_perfbuf_deinit_inst_block,
+	.update_get_put = nvgpu_perfbuf_update_get_put,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_PROFILER
+static const struct gops_pm_reservation ga100_ops_pm_reservation = {
+	.acquire = nvgpu_pm_reservation_acquire,
+	.release = nvgpu_pm_reservation_release,
+	.release_all_per_vmid = nvgpu_pm_reservation_release_all_per_vmid,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_PROFILER
+static const struct gops_profiler ga100_ops_profiler = {
+	.bind_hwpm = nvgpu_profiler_bind_hwpm,
+	.unbind_hwpm = nvgpu_profiler_unbind_hwpm,
+	.bind_hwpm_streamout = nvgpu_profiler_bind_hwpm_streamout,
+	.unbind_hwpm_streamout = nvgpu_profiler_unbind_hwpm_streamout,
+	.bind_smpc = nvgpu_profiler_bind_smpc,
+	.unbind_smpc = nvgpu_profiler_unbind_smpc,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_bus ga100_ops_bus = {
+	.init_hw = ga10b_bus_init_hw,
+	.isr = ga10b_bus_isr,
+	.bar1_bind = gm20b_bus_bar1_bind,
+	.bar2_bind = gp10b_bus_bar2_bind,
+	.configure_debug_bus = NULL,
+#ifdef CONFIG_NVGPU_DGPU
+	.set_bar0_window = gk20a_bus_set_bar0_window,
+	.read_sw_scratch = ga100_bus_read_sw_scratch,
+	.write_sw_scratch = ga100_bus_write_sw_scratch,
+#endif
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_ptimer ga100_ops_ptimer = {
+	.isr = gk20a_ptimer_isr,
+	.read_ptimer = gk20a_read_ptimer,
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
+	.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.config_gr_tick_freq = gp10b_ptimer_config_gr_tick_freq,
+#endif
+#ifdef CONFIG_NVGPU_PROFILER
+	.get_timer_reg_offsets = gv11b_ptimer_get_timer_reg_offsets,
+#endif
+};
+#endif
+
+#if defined(CONFIG_NVGPU_CYCLESTATS)
+static const struct gops_css ga100_ops_css = {
+	.enable_snapshot = nvgpu_css_enable_snapshot,
+	.disable_snapshot = nvgpu_css_disable_snapshot,
+	.check_data_available = nvgpu_css_check_data_available,
+	.set_handled_snapshots = nvgpu_css_set_handled_snapshots,
+	.allocate_perfmon_ids = nvgpu_css_allocate_perfmon_ids,
+	.release_perfmon_ids = nvgpu_css_release_perfmon_ids,
+	.get_overflow_status = nvgpu_css_get_overflow_status,
+	.get_pending_snapshots = nvgpu_css_get_pending_snapshots,
+	.get_max_buffer_size = nvgpu_css_get_max_buffer_size,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_xve ga100_ops_xve = {
+	.get_speed = xve_get_speed_gp106,
+	.xve_readl = xve_xve_readl_gp106,
+	.xve_writel = xve_xve_writel_gp106,
+	.disable_aspm = xve_disable_aspm_gp106,
+	.reset_gpu = xve_reset_gpu_gp106,
+#if defined(CONFIG_PCI_MSI)
+	.rearm_msi = xve_rearm_msi_gp106,
+#endif
+	.enable_shadow_rom = NULL,
+	.disable_shadow_rom = NULL,
+	.devinit_deferred_settings = tu104_devinit_deferred_settings,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_falcon ga100_ops_falcon = {
+	.falcon_sw_init = nvgpu_falcon_sw_init,
+	.falcon_sw_free = nvgpu_falcon_sw_free,
+	.reset = gk20a_falcon_reset,
+	.is_falcon_cpu_halted = gk20a_is_falcon_cpu_halted,
+	.is_falcon_idle = gk20a_is_falcon_idle,
+	.is_falcon_scrubbing_done = gk20a_is_falcon_scrubbing_done,
+	.get_mem_size = gk20a_falcon_get_mem_size,
+	.get_ports_count = gk20a_falcon_get_ports_count,
+	.copy_to_dmem = gk20a_falcon_copy_to_dmem,
+	.copy_to_imem = gk20a_falcon_copy_to_imem,
+	.dmemc_blk_mask = ga10b_falcon_dmemc_blk_mask,
+	.imemc_blk_field = ga10b_falcon_imemc_blk_field,
+	.bootstrap = gk20a_falcon_bootstrap,
+	.mailbox_read = gk20a_falcon_mailbox_read,
+	.mailbox_write = gk20a_falcon_mailbox_write,
+	.set_irq = gk20a_falcon_set_irq,
+#ifdef CONFIG_NVGPU_FALCON_DEBUG
+	.dump_falcon_stats = gk20a_falcon_dump_stats,
+#endif
+	.clear_halt_interrupt_status = gk20a_falcon_clear_halt_interrupt_status,
+#ifdef CONFIG_NVGPU_FALCON_NON_FUSA
+	.copy_from_dmem = gk20a_falcon_copy_from_dmem,
+	.copy_from_imem = gk20a_falcon_copy_from_imem,
+	.get_falcon_ctls = gk20a_falcon_get_ctls,
+#endif
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_fbp ga100_ops_fbp = {
+	.fbp_init_support = nvgpu_fbp_init_support,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_priv_ring ga100_ops_priv_ring = {
+	.enable_priv_ring = gm20b_priv_ring_enable,
+	.isr = gp10b_priv_ring_isr,
+	.isr_handle_0 = ga10b_priv_ring_isr_handle_0,
+	.isr_handle_1 = ga10b_priv_ring_isr_handle_1,
+	.decode_error_code = ga10b_priv_ring_decode_error_code,
+	.set_ppriv_timeout_settings = NULL,
+	.enum_ltc = ga10b_priv_ring_enum_ltc,
+	.get_gpc_count = gm20b_priv_ring_get_gpc_count,
+	.get_fbp_count = gm20b_priv_ring_get_fbp_count,
+#ifdef CONFIG_NVGPU_MIG
+	.config_gr_remap_window = ga10b_priv_ring_config_gr_remap_window,
+	.config_gpc_rs_map = ga100_priv_ring_config_gpc_rs_map,
+#endif
+#ifdef CONFIG_NVGPU_PROFILER
+	.read_pri_fence = ga10b_priv_ring_read_pri_fence,
+#endif
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_fuse ga100_ops_fuse = {
+	.is_opt_ecc_enable = ga10b_fuse_is_opt_ecc_enable,
+	.is_opt_feature_override_disable = ga10b_fuse_is_opt_feature_override_disable,
+	.fuse_status_opt_fbio = ga10b_fuse_status_opt_fbio,
+	.fuse_status_opt_fbp = ga10b_fuse_status_opt_fbp,
+	.fuse_status_opt_rop_l2_fbp = ga100_fuse_status_opt_rop_l2_fbp,
+	.fuse_status_opt_gpc = ga10b_fuse_status_opt_gpc,
+	.fuse_status_opt_tpc_gpc = ga10b_fuse_status_opt_tpc_gpc,
+	.fuse_ctrl_opt_tpc_gpc = ga10b_fuse_ctrl_opt_tpc_gpc,
+	.fuse_opt_sec_debug_en = NULL,
+	.fuse_opt_priv_sec_en = ga10b_fuse_opt_priv_sec_en,
+	.fuse_opt_sm_ttu_en = ga10b_fuse_opt_sm_ttu_en,
+	.read_vin_cal_fuse_rev = NULL,
+	.read_vin_cal_slope_intercept_fuse = NULL,
+	.read_vin_cal_gain_offset_fuse = NULL,
+	.read_per_device_identifier = ga100_fuse_read_per_device_identifier,
+	.read_ucode_version = ga100_read_ucode_version,
+};
+#endif
+
+#if defined(CONFIG_NVGPU_NVLINK)
+static const struct gops_nvlink ga100_ops_nvlink = {
+	.init = NULL,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DGPU
+static const struct gops_sec2 ga100_ops_sec2 = {
+	.init_sec2_setup_sw = nvgpu_init_sec2_setup_sw,
+	.init_sec2_support = nvgpu_init_sec2_support,
+	.sec2_destroy = nvgpu_sec2_destroy,
+	.secured_sec2_start = tu104_start_sec2_secure,
+	.enable_irq = tu104_sec2_enable_irq,
+	.is_interrupted = tu104_sec2_is_interrupted,
+	.get_intr = tu104_sec2_get_intr,
+	.msg_intr_received = tu104_sec2_msg_intr_received,
+	.set_msg_intr = tu104_sec2_set_msg_intr,
+	.clr_intr = tu104_sec2_clr_intr,
+	.process_intr = tu104_sec2_process_intr,
+	.msgq_tail = tu104_sec2_msgq_tail,
+	.falcon_base_addr = tu104_sec2_falcon_base_addr,
+	.sec2_reset = tu104_sec2_reset,
+	.sec2_copy_to_emem = tu104_sec2_flcn_copy_to_emem,
+	.sec2_copy_from_emem = tu104_sec2_flcn_copy_from_emem,
+	.sec2_queue_head = tu104_sec2_queue_head,
+	.sec2_queue_tail = tu104_sec2_queue_tail,
+	.flcn_setup_boot_config = tu104_sec2_flcn_setup_boot_config,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_gsp ga100_ops_gsp = {
+	.falcon_base_addr = tu104_gsp_falcon_base_addr,
+	.falcon_setup_boot_config = tu104_gsp_flcn_setup_boot_config,
+	.gsp_reset = tu104_gsp_reset,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_top ga100_ops_top = {
+	.device_info_parse_enum = NULL,
+	.device_info_parse_data = NULL,
+	.parse_next_device = ga10b_top_parse_next_dev,
+	.get_max_gpc_count = gm20b_top_get_max_gpc_count,
+	.get_max_tpc_per_gpc_count = gm20b_top_get_max_tpc_per_gpc_count,
+	.get_max_fbps_count = gm20b_top_get_max_fbps_count,
+	.get_max_fbpas_count = gv100_top_get_max_fbpas_count,
+	.get_max_ltc_per_fbp = gm20b_top_get_max_ltc_per_fbp,
+	.get_max_lts_per_ltc = gm20b_top_get_max_lts_per_ltc,
+	.get_num_ltcs = gm20b_top_get_num_ltcs,
+	.get_num_lce = gv11b_top_get_num_lce,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_grmgr ga100_ops_grmgr = {
+#ifdef CONFIG_NVGPU_MIG
+	.init_gr_manager = ga10b_grmgr_init_gr_manager,
+	.remove_gr_manager = ga10b_grmgr_remove_gr_manager,
+	.get_max_sys_pipes = ga100_grmgr_get_max_sys_pipes,
+	.get_mig_config_ptr = ga100_grmgr_get_mig_config_ptr,
+	.get_allowed_swizzid_size = ga100_grmgr_get_allowed_swizzid_size,
+	.get_gpc_instance_gpcgrp_id = ga100_grmgr_get_gpc_instance_gpcgrp_id,
+	.get_mig_gpu_instance_config = ga10b_grmgr_get_mig_gpu_instance_config,
+	.get_gpcgrp_count = ga10b_grmgr_get_gpcgrp_count,
+#else
+	.init_gr_manager = nvgpu_init_gr_manager,
+#endif
+	.load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod,
+	.discover_gpc_ids = ga10b_grmgr_discover_gpc_ids,
+};
+#endif
+
+int ga100_init_hal(struct gk20a *g)
+{
+	struct gpu_ops *gops = &g->ops;
+
+	gops->acr = ga100_ops_acr;
+	gops->sbr = ga100_ops_sbr;
+	gops->func = ga100_ops_func;
+	gops->bios = ga100_ops_bios;
+	gops->ecc = ga100_ops_ecc;
+	gops->ltc = ga100_ops_ltc;
+	gops->ltc.intr = ga100_ops_ltc_intr;
+#ifdef CONFIG_NVGPU_COMPRESSION
+	gops->cbc = ga100_ops_cbc;
+#endif
+	gops->ce = ga100_ops_ce;
+	gops->gr = ga100_ops_gr;
+	gops->gr.ecc = ga100_ops_gr_ecc;
+	gops->gr.ctxsw_prog = ga100_ops_gr_ctxsw_prog;
+	gops->gr.config = ga100_ops_gr_config;
+#ifdef CONFIG_NVGPU_FECS_TRACE
+	gops->gr.fecs_trace = ga100_ops_gr_fecs_trace;
+#endif /* CONFIG_NVGPU_FECS_TRACE */
+	gops->gr.setup = ga100_ops_gr_setup;
+#ifdef CONFIG_NVGPU_GRAPHICS
+	gops->gr.zbc = ga100_ops_gr_zbc;
+	gops->gr.zcull = ga100_ops_gr_zcull;
+#endif /* CONFIG_NVGPU_GRAPHICS */
+#ifdef CONFIG_NVGPU_DEBUGGER
+	gops->gr.hwpm_map = ga100_ops_gr_hwpm_map;
+#endif
+	gops->gr.init = ga100_ops_gr_init;
+	gops->gr.intr = ga100_ops_gr_intr;
+	gops->gr.falcon = ga100_ops_gr_falcon;
+	gops->gpu_class = ga100_ops_gpu_class;
+	gops->fb = ga100_ops_fb;
+	gops->fb.ecc = ga100_ops_fb_ecc;
+	gops->fb.intr = ga100_ops_fb_intr;
+	gops->nvdec = ga100_ops_nvdec;
+	gops->cg = ga100_ops_cg;
+	gops->fifo = ga100_ops_fifo;
+	gops->engine = ga100_ops_engine;
+	gops->pbdma = ga100_ops_pbdma;
+	gops->sync = ga100_ops_sync;
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+	gops->sync.syncpt = ga100_ops_sync_syncpt;
+#endif /* CONFIG_TEGRA_GK20A_NVHOST */
+#if defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT) && \
+	defined(CONFIG_NVGPU_SW_SEMAPHORE)
+	gops->sync.sema = ga100_ops_sync_sema;
+#endif
+	gops->engine_status = ga100_ops_engine_status;
+	gops->pbdma_status = ga100_ops_pbdma_status;
+	gops->ramfc = ga100_ops_ramfc;
+	gops->ramin = ga100_ops_ramin;
+	gops->runlist = ga100_ops_runlist;
+	gops->userd = ga100_ops_userd;
+	gops->channel = ga100_ops_channel;
+	gops->tsg = ga100_ops_tsg;
+	gops->usermode = ga100_ops_usermode;
+	gops->netlist = ga100_ops_netlist;
+	gops->mm = ga100_ops_mm;
+	gops->mm.mmu_fault = ga100_ops_mm_mmu_fault;
+	gops->mm.cache = ga100_ops_mm_cache;
+	gops->mm.gmmu = ga100_ops_mm_gmmu;
+	gops->therm = ga100_ops_therm;
+#ifdef CONFIG_NVGPU_LS_PMU
+	gops->pmu = ga100_ops_pmu;
+#endif
+	gops->clk = ga100_ops_clk;
+	gops->clk_mon = ga100_ops_clk_mon;
+#ifdef CONFIG_NVGPU_CLK_ARB
+	gops->clk_arb = ga100_ops_clk_arb;
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	gops->regops = ga100_ops_regops;
+#endif
+	gops->mc = ga100_ops_mc;
+	gops->debug = ga100_ops_debug;
+#ifdef CONFIG_NVGPU_DEBUGGER
+	gops->debugger = ga100_ops_debugger;
+	gops->perf = ga100_ops_perf;
+	gops->perfbuf = ga100_ops_perfbuf;
+#endif
+#ifdef CONFIG_NVGPU_PROFILER
+	gops->pm_reservation = ga100_ops_pm_reservation;
+	gops->profiler = ga100_ops_profiler;
+#endif
+	gops->bus = ga100_ops_bus;
+	gops->ptimer = ga100_ops_ptimer;
+#if defined(CONFIG_NVGPU_CYCLESTATS)
+	gops->css = ga100_ops_css;
+#endif
+	gops->xve = ga100_ops_xve;
+	gops->falcon = ga100_ops_falcon;
+	gops->fbp = ga100_ops_fbp;
+	gops->priv_ring = ga100_ops_priv_ring;
+	gops->fuse = ga100_ops_fuse;
+#if defined(CONFIG_NVGPU_NVLINK)
+	gops->nvlink = ga100_ops_nvlink;
+#endif
+#ifdef CONFIG_NVGPU_DGPU
+	gops->sec2 = ga100_ops_sec2;
+#endif
+	gops->gsp = ga100_ops_gsp;
+	gops->top = ga100_ops_top;
+	gops->grmgr = ga100_ops_grmgr;
+	gops->chip_init_gpu_characteristics = ga100_init_gpu_characteristics;
+	gops->get_litter_value = ga100_get_litter_value;
+	gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;
+
+	nvgpu_set_errata(g, NVGPU_ERRATA_200601972, true);
+	nvgpu_set_errata(g, NVGPU_ERRATA_200391931, true);
+	nvgpu_set_errata(g, NVGPU_ERRATA_SYNCPT_INVALID_ID_0, true);
+
+	if (gops->fuse.fuse_opt_sm_ttu_en(g) != 0U) {
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_SM_TTU, true);
+	}
+
+	nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
+	nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, true);
+#ifdef CONFIG_NVGPU_FECS_TRACE
+	nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
+	nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true);
+#endif
+
+#ifdef CONFIG_NVGPU_PROFILER
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PROFILER_V2_DEVICE, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PROFILER_V2_CONTEXT, false);
+#endif
+
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_RTOS, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_RTOS_FBQ, true);
+#ifdef CONFIG_NVGPU_GRAPHICS
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true);
+#endif
+#ifdef CONFIG_NVGPU_GFXP
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true);
+#endif
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_VM, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_GSP_VM, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_SUPER_SURFACE, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_DGPU_THERMAL_ALERT, false);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_DGPU_PCIE_SCRIPT_EXECUTE, true);
+	nvgpu_set_enabled(g, NVGPU_FMON_SUPPORT_ENABLE, false);
+#ifdef CONFIG_NVGPU_PROFILER
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SMPC_GLOBAL_MODE, true);
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	nvgpu_set_enabled(g, NVGPU_L2_MAX_WAYS_EVICT_LAST_ENABLED, true);
+#endif
+	/*
+	 * Tu104 has multiple async-LCE (3), GRCE (2) and PCE (4).
+	 * The allocation used for the HW structures is deterministic.
+	 * LCE/PCE is likely to follow the same resource allocation in primary
+	 * and redundant execution mode if we use the same LCE/PCE pairs for
+	 * both execution modes. All available LCEs and GRCEs should be mapped
+	 * to unique PCEs.
+	 *
+	 * The recommendation is to swap the GRCEs with each other during
+	 * redundant execution. The async-LCEs have their own PCEs,
+	 * so the suggestion is to use a different async-LCE during redundant
+	 * execution. This will allow us to claim very high coverage for
+	 * permanent fault.
+	 */
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_COPY_ENGINE_DIVERSITY, true);
+
+#ifdef CONFIG_NVGPU_SM_DIVERSITY
+	/*
+	 * To achieve permanent fault coverage, the CTAs launched by each kernel
+	 * in the mission and redundant contexts must execute on different
+	 * hardware resources. This feature proposes modifications in the
+	 * software to modify the virtual SM id to TPC mapping across the
+	 * mission and redundant contexts.
+	 *
+	 * The virtual SM identifier to TPC mapping is done by the nvgpu
+	 * when setting up the golden context. Once the table with this mapping
+	 * is initialized, it is used by all subsequent contexts that are
+	 * created. The proposal is for setting up the virtual SM identifier
+	 * to TPC mapping on a per-context basis and initializing this
+	 * virtual SM identifier to TPC mapping differently for the mission and
+	 * redundant contexts.
+	 *
+	 * The recommendation for the redundant setting is to offset the
+	 * assignment by 1 (TPC). This will ensure both GPC and TPC diversity.
+	 * The SM and Quadrant diversity will happen naturally.
+	 *
+	 * For kernels with few CTAs, the diversity is guaranteed to be 100%.
+	 * In case of completely random CTA allocation, e.g. large number of
+	 * CTAs in the waiting queue, the diversity is 1 - 1/#SM,
+	 * or 97.9% for TU104.
+	 */
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SM_DIVERSITY, true);
+	g->max_sm_diversity_config_count =
+		NVGPU_MAX_SM_DIVERSITY_CONFIG_COUNT;
+#else
+	g->max_sm_diversity_config_count =
+		NVGPU_DEFAULT_SM_DIVERSITY_CONFIG_COUNT;
+#endif
+	/* for now */
+	gops->clk.support_pmgr_domain = false;
+	gops->clk.support_lpwr_pg = false;
+	gops->clk.support_vf_point = true;
+	gops->clk.lut_num_entries = CTRL_CLK_LUT_NUM_ENTRIES_GV10x;
+#ifdef CONFIG_NVGPU_LS_PMU
+	gops->clk.perf_pmu_vfe_load = nvgpu_pmu_perf_load;
+#endif
+#ifdef CONFIG_NVGPU_DGPU
+	nvgpu_pramin_ops_init(g);
+#endif
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_COMPRESSION, true);
+
+	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_COMPRESSION)) {
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_POST_L2_COMPRESSION, false);
+	} else {
+		gops->cbc.init = NULL;
+		gops->cbc.ctrl = NULL;
+		gops->cbc.alloc_comptags = NULL;
+	}
+#endif
+
+	/* dGpu VDK support */
+#ifdef CONFIG_NVGPU_SIM
+	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)){
+#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
+		gops->gr.falcon.load_ctxsw_ucode =
+			nvgpu_gr_falcon_load_ctxsw_ucode;
+#endif
+
+		nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP,
+									false);
+		/* Disable fb mem_unlock */
+		gops->fb.mem_unlock = NULL;
+
+		/* Disable clock support */
+#ifdef CONFIG_NVGPU_CLK_ARB
+		gops->clk_arb.get_arbiter_clk_domains = NULL;
+#endif
+	} else
+#endif
+	{
+		nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
+	}
+
+	g->name = "ga100";
+
+	return 0;
+}
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.h b/drivers/gpu/nvgpu/hal/init/hal_ga100.h
new file mode 100644
index 000000000..f1ab7eeab
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.h
@@ -0,0 +1,32 @@
+/*
+ * GA100 Tegra HAL interface
+ *
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_HAL_GA100_H
+#define NVGPU_HAL_GA100_H
+
+struct gk20a;
+
+int ga100_init_hal(struct gk20a *g);
+
+#endif /* NVGPU_HAL_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100_litter.c b/drivers/gpu/nvgpu/hal/init/hal_ga100_litter.c
new file mode 100644
index 000000000..1a95d6138
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100_litter.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/class.h>
+#include <nvgpu/nvgpu_next_class.h>
+
+#include <nvgpu/hw/ga100/hw_proj_ga100.h>
+
+#include "hal_ga100_litter.h"
+
+u32 ga100_get_litter_value(struct gk20a *g, int value)
+{
+	u32 ret = 0;
+
+	switch (value) {
+	case GPU_LIT_NUM_GPCS:
+		ret = proj_scal_litter_num_gpcs_v();
+		break;
+	case GPU_LIT_NUM_PES_PER_GPC:
+		ret = proj_scal_litter_num_pes_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_ZCULL_BANKS:
+		ret = proj_scal_litter_num_zcull_banks_v();
+		break;
+	case GPU_LIT_NUM_TPC_PER_GPC:
+		ret = proj_scal_litter_num_tpc_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_SM_PER_TPC:
+		ret = proj_scal_litter_num_sm_per_tpc_v();
+		break;
+	case GPU_LIT_NUM_FBPS:
+		ret = proj_scal_litter_num_fbps_v();
+		break;
+	case GPU_LIT_GPC_BASE:
+		ret = proj_gpc_base_v();
+		break;
+	case GPU_LIT_GPC_STRIDE:
+		ret = proj_gpc_stride_v();
+		break;
+	case GPU_LIT_GPC_SHARED_BASE:
+		ret = proj_gpc_shared_base_v();
+		break;
+	case GPU_LIT_GPC_ADDR_WIDTH:
+		ret = proj_gpc_addr_width_v();
+		break;
+	case GPU_LIT_TPC_ADDR_WIDTH:
+		ret = proj_tpc_addr_width_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_BASE:
+		ret = proj_tpc_in_gpc_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_STRIDE:
+		ret = proj_tpc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
+		ret = proj_tpc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_BASE:
+		ret = proj_ppc_in_gpc_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_STRIDE:
+		ret = proj_ppc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
+		ret = proj_ppc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_ROP_BASE:
+		ret = proj_rop_base_v();
+		break;
+	case GPU_LIT_ROP_STRIDE:
+		ret = proj_rop_stride_v();
+		break;
+	case GPU_LIT_ROP_SHARED_BASE:
+		ret = proj_rop_shared_base_v();
+		break;
+	case GPU_LIT_HOST_NUM_ENGINES:
+		ret = proj_host_num_engines_v();
+		break;
+	case GPU_LIT_HOST_NUM_PBDMA:
+		ret = proj_host_num_pbdma_v();
+		break;
+	case GPU_LIT_LTC_STRIDE:
+		ret = proj_ltc_stride_v();
+		break;
+	case GPU_LIT_LTS_STRIDE:
+		ret = proj_lts_stride_v();
+		break;
+	case GPU_LIT_NUM_FBPAS:
+		ret = proj_scal_litter_num_fbpas_v();
+		break;
+	case GPU_LIT_FBPA_SHARED_BASE:
+		ret = proj_fbpa_shared_base_v();
+		break;
+	case GPU_LIT_FBPA_BASE:
+		ret = proj_fbpa_base_v();
+		break;
+	case GPU_LIT_FBPA_STRIDE:
+		ret = proj_fbpa_stride_v();
+		break;
+	case GPU_LIT_SM_PRI_STRIDE:
+		ret = proj_sm_stride_v();
+		break;
+	case GPU_LIT_SMPC_PRI_BASE:
+		ret = proj_smpc_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_SHARED_BASE:
+		ret = proj_smpc_shared_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_UNIQUE_BASE:
+		ret = proj_smpc_unique_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_STRIDE:
+		ret = proj_smpc_stride_v();
+		break;
+	case GPU_LIT_SM_UNIQUE_BASE:
+		ret = proj_sm_unique_base_v();
+		break;
+	case GPU_LIT_SM_SHARED_BASE:
+		ret = proj_sm_shared_base_v();
+		break;
+	case GPU_LIT_NUM_LTC_LTS_SETS:
+		ret = proj_scal_litter_num_ltc_lts_sets_v();
+		break;
+	case GPU_LIT_NUM_LTC_LTS_WAYS:
+		ret = proj_scal_litter_num_ltc_lts_ways_v();
+		break;
+#ifdef CONFIG_NVGPU_GRAPHICS
+	case GPU_LIT_TWOD_CLASS:
+		ret = FERMI_TWOD_A;
+		break;
+	case GPU_LIT_THREED_CLASS:
+		break;
+#endif
+	case GPU_LIT_COMPUTE_CLASS:
+		ret = AMPERE_COMPUTE_A;
+		break;
+	case GPU_LIT_GPFIFO_CLASS:
+		ret = AMPERE_CHANNEL_GPFIFO_A;
+		break;
+	case GPU_LIT_I2M_CLASS:
+		ret = KEPLER_INLINE_TO_MEMORY_B;
+		break;
+	case GPU_LIT_DMA_COPY_CLASS:
+		ret = AMPERE_DMA_COPY_A;
+		break;
+	case GPU_LIT_GPC_PRIV_STRIDE:
+		ret = proj_gpc_priv_stride_v();
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START:
+		ret = 2;
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START:
+		ret = 8;
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT:
+		ret = 6;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START:
+		ret = 2;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT:
+		ret = 8;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START:
+		ret = 10;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT:
+		ret = 2;
+		break;
+	case GPU_LIT_MAX_RUNLISTS_SUPPORTED:
+		ret = 24U;
+		break;
+	default:
+		nvgpu_err(g, "Missing definition %d", value);
+		BUG();
+		break;
+	}
+
+	return ret;
+}
+
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100_litter.h b/drivers/gpu/nvgpu/hal/init/hal_ga100_litter.h
new file mode 100644
index 000000000..c90e0b53e
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100_litter.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_HAL_GA100_LITTER_H
+#define NVGPU_HAL_GA100_LITTER_H
+
+u32 ga100_get_litter_value(struct gk20a *g, int value);
+
+#endif /* NVGPU_HAL_GA100_LITTER_H */
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
new file mode 100644
index 000000000..2fcdcd26b
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -0,0 +1,1880 @@
+/*
+ * GA10B Tegra HAL interface
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/errata.h>
+#include <nvgpu/acr.h>
+#include <nvgpu/ce.h>
+#include <nvgpu/ce_app.h>
+#include <nvgpu/pmu.h>
+#ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/pmu_pstate.h>
+#endif
+#include <nvgpu/fbp.h>
+#include <nvgpu/therm.h>
+#include <nvgpu/clk_arb.h>
+#include <nvgpu/fuse.h>
+#include <nvgpu/pbdma.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/preempt.h>
+#include <nvgpu/regops.h>
+#include <nvgpu/gr/gr_falcon.h>
+#include <nvgpu/gr/gr.h>
+#include <nvgpu/gr/fs_state.h>
+#include <nvgpu/nvhost.h>
+#ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/pmu_perfmon.h>
+#endif
+#include <nvgpu/profiler.h>
+
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
+#include "hal/mm/cache/flush_gk20a.h"
+#include "hal/mm/cache/flush_gv11b.h"
+#include "hal/mm/gmmu/gmmu_gm20b.h"
+#include "hal/mm/gmmu/gmmu_gp10b.h"
+#include "hal/mm/gmmu/gmmu_gv11b.h"
+#include "hal/mm/gmmu/gmmu_ga10b.h"
+#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
+#include "hal/mm/mmu_fault/mmu_fault_ga10b.h"
+#include "hal/mc/mc_gm20b.h"
+#include "hal/mc/mc_gp10b.h"
+#include "hal/mc/mc_gv11b.h"
+#include "hal/mc/mc_tu104.h"
+#include "hal/mc/mc_ga10b.h"
+#include "hal/mc/mc_intr_ga10b.h"
+#include "hal/bus/bus_gk20a.h"
+#include "hal/bus/bus_gp10b.h"
+#include "hal/bus/bus_gm20b.h"
+#include "hal/bus/bus_gv11b.h"
+#include "hal/bus/bus_ga10b.h"
+#include "hal/ce/ce_gv11b.h"
+#include "hal/class/class_gv11b.h"
+#include "hal/class/class_ga10b.h"
+#include "hal/priv_ring/priv_ring_gm20b.h"
+#include "hal/priv_ring/priv_ring_gp10b.h"
+#include "hal/priv_ring/priv_ring_ga10b.h"
+#include "hal/gr/config/gr_config_gv100.h"
+#include "hal/power_features/cg/ga10b_gating_reglist.h"
+#ifdef CONFIG_NVGPU_COMPRESSION
+#include "hal/cbc/cbc_gp10b.h"
+#include "hal/cbc/cbc_gv11b.h"
+#include "hal/cbc/cbc_tu104.h"
+#include "hal/cbc/cbc_ga10b.h"
+#endif
+#include "hal/ce/ce_gp10b.h"
+#include "hal/ce/ce_ga10b.h"
+#include "hal/therm/therm_gm20b.h"
+#include "hal/therm/therm_gv11b.h"
+#include "hal/therm/therm_ga10b.h"
+#include "hal/ltc/ltc_gm20b.h"
+#include "hal/ltc/ltc_gp10b.h"
+#include "hal/ltc/ltc_gv11b.h"
+#include "hal/ltc/ltc_tu104.h"
+#include "hal/ltc/ltc_ga10b.h"
+#include "hal/ltc/intr/ltc_intr_gv11b.h"
+#include "hal/ltc/intr/ltc_intr_ga10b.h"
+#include "hal/fb/fb_gm20b.h"
+#include "hal/fb/fb_gp10b.h"
+#include "hal/fb/fb_gv11b.h"
+#include "hal/fb/fb_tu104.h"
+#include "hal/fb/fb_ga10b.h"
+#include "hal/fb/fb_mmu_fault_gv11b.h"
+#include "hal/fb/ecc/fb_ecc_ga10b.h"
+#include "hal/fb/ecc/fb_ecc_gv11b.h"
+#include "hal/fb/intr/fb_intr_gv11b.h"
+#include "hal/fb/intr/fb_intr_ga10b.h"
+#include "hal/fb/intr/fb_intr_ecc_gv11b.h"
+#include "hal/fb/intr/fb_intr_ecc_ga10b.h"
+#include "hal/fb/vab/vab_ga10b.h"
+#include "hal/func/func_ga10b.h"
+#include "hal/fuse/fuse_gm20b.h"
+#include "hal/fuse/fuse_gp10b.h"
+#include "hal/fuse/fuse_ga10b.h"
+#include "hal/ptimer/ptimer_gk20a.h"
+#include "hal/ptimer/ptimer_gp10b.h"
+#include "hal/ptimer/ptimer_gv11b.h"
+#include "hal/ptimer/ptimer_ga10b.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
+#include "hal/regops/regops_ga10b.h"
+#include "hal/regops/allowlist_ga10b.h"
+#endif
+#ifdef CONFIG_NVGPU_RECOVERY
+#include "hal/rc/rc_gv11b.h"
+#endif
+#include "hal/fifo/fifo_gk20a.h"
+#include "hal/fifo/fifo_gv11b.h"
+#include "hal/fifo/fifo_ga10b.h"
+#include "hal/fifo/pbdma_gm20b.h"
+#include "hal/fifo/pbdma_gp10b.h"
+#include "hal/fifo/pbdma_gv11b.h"
+#include "hal/fifo/pbdma_ga10b.h"
+#include "hal/fifo/preempt_gv11b.h"
+#include "hal/fifo/preempt_ga10b.h"
+#include "hal/fifo/engine_status_gv100.h"
+#include "hal/fifo/engine_status_ga10b.h"
+#include "hal/fifo/pbdma_status_gm20b.h"
+#include "hal/fifo/pbdma_status_ga10b.h"
+#include "hal/fifo/engines_gp10b.h"
+#include "hal/fifo/engines_gv11b.h"
+#include "hal/fifo/ramfc_gp10b.h"
+#include "hal/fifo/ramfc_gv11b.h"
+#include "hal/fifo/ramfc_ga10b.h"
+#include "hal/fifo/ramin_gk20a.h"
+#include "hal/fifo/ramin_gm20b.h"
+#include "hal/fifo/ramin_gv11b.h"
+#include "hal/fifo/ramin_ga10b.h"
+#include "hal/fifo/runlist_ram_gk20a.h"
+#include "hal/fifo/runlist_ram_gv11b.h"
+#include "hal/fifo/runlist_fifo_gk20a.h"
+#include "hal/fifo/runlist_fifo_gv11b.h"
+#include "hal/fifo/runlist_fifo_ga10b.h"
+#include "hal/fifo/runlist_ga10b.h"
+#include "hal/fifo/tsg_ga10b.h"
+#include "hal/fifo/tsg_gv11b.h"
+#include "hal/fifo/userd_gk20a.h"
+#include "hal/fifo/userd_gv11b.h"
+#include "hal/fifo/userd_ga10b.h"
+#include "hal/fifo/usermode_gv11b.h"
+#include "hal/fifo/usermode_tu104.h"
+#include "hal/fifo/usermode_ga10b.h"
+#include "hal/fifo/fifo_intr_gk20a.h"
+#include "hal/fifo/fifo_intr_gv11b.h"
+#include "hal/fifo/fifo_intr_ga10b.h"
+#include "hal/fifo/ctxsw_timeout_gv11b.h"
+#include "hal/fifo/ctxsw_timeout_ga10b.h"
+#include "hal/gr/ecc/ecc_gv11b.h"
+#include "hal/gr/ecc/ecc_ga10b.h"
+#ifdef CONFIG_NVGPU_FECS_TRACE
+#include "hal/gr/fecs_trace/fecs_trace_gm20b.h"
+#include "hal/gr/fecs_trace/fecs_trace_gv11b.h"
+#endif
+#include "hal/gr/falcon/gr_falcon_gm20b.h"
+#include "hal/gr/falcon/gr_falcon_gp10b.h"
+#include "hal/gr/falcon/gr_falcon_gv11b.h"
+#include "hal/gr/falcon/gr_falcon_tu104.h"
+#include "hal/gr/falcon/gr_falcon_ga10b.h"
+#include "hal/gr/config/gr_config_gm20b.h"
+#ifdef CONFIG_NVGPU_GRAPHICS
+#include "hal/gr/zbc/zbc_gp10b.h"
+#include "hal/gr/zbc/zbc_gv11b.h"
+#include "hal/gr/zbc/zbc_ga10b.h"
+#include "hal/gr/zcull/zcull_gm20b.h"
+#include "hal/gr/zcull/zcull_gv11b.h"
+#endif
+#include "hal/gr/init/gr_init_gm20b.h"
+#include "hal/gr/init/gr_init_gp10b.h"
+#include "hal/gr/init/gr_init_gv11b.h"
+#include "hal/gr/init/gr_init_tu104.h"
+#include "hal/gr/init/gr_init_ga10b.h"
+#include "hal/gr/intr/gr_intr_gm20b.h"
+#include "hal/gr/intr/gr_intr_gp10b.h"
+#include "hal/gr/intr/gr_intr_gv11b.h"
+#include "hal/gr/intr/gr_intr_ga10b.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
+#include "hal/gr/hwpm_map/hwpm_map_gv100.h"
+#endif
+#include "hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
+#include "hal/gr/gr/gr_gk20a.h"
+#include "hal/gr/gr/gr_gm20b.h"
+#include "hal/gr/gr/gr_gp10b.h"
+#include "hal/gr/gr/gr_gv100.h"
+#include "hal/gr/gr/gr_gv11b.h"
+#include "hal/gr/gr/gr_tu104.h"
+#include "hal/gr/gr/gr_ga10b.h"
+#include "hal/gr/gr/gr_ga100.h"
+#endif
+#include "hal/pmu/pmu_gk20a.h"
+#ifdef CONFIG_NVGPU_LS_PMU
+#include "hal/pmu/pmu_gm20b.h"
+#endif
+#include "hal/pmu/pmu_gv11b.h"
+#include "hal/pmu/pmu_ga10b.h"
+#include "hal/gsp/gsp_ga10b.h"
+#include "hal/sync/syncpt_cmdbuf_gv11b.h"
+#include "hal/sync/sema_cmdbuf_gv11b.h"
+#include "hal/falcon/falcon_gk20a.h"
+#include "hal/falcon/falcon_ga10b.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
+#include "hal/perf/perf_gv11b.h"
+#include "hal/perf/perf_ga10b.h"
+#endif
+#include "hal/netlist/netlist_ga10b.h"
+#include "hal/top/top_gm20b.h"
+#include "hal/top/top_gp10b.h"
+#include "hal/top/top_gv11b.h"
+#include "hal/top/top_ga10b.h"
+
+#ifdef CONFIG_NVGPU_LS_PMU
+#include "common/pmu/pg/pg_sw_gm20b.h"
+#include "common/pmu/pg/pg_sw_gp106.h"
+#include "common/pmu/pg/pg_sw_gv11b.h"
+#endif
+
+#ifdef CONFIG_NVGPU_CLK_ARB
+#include "common/clk_arb/clk_arb_gp10b.h"
+#endif
+
+#include "hal/fifo/channel_gk20a.h"
+#include "hal/fifo/channel_gm20b.h"
+#include "hal/fifo/channel_gv11b.h"
+#include "hal/fifo/channel_ga10b.h"
+
+#ifdef CONFIG_NVGPU_TPC_POWERGATE
+#include "hal/tpc/tpc_gv11b.h"
+#endif
+
+#include "hal_ga10b.h"
+#include "hal_ga10b_litter.h"
+
+#include <nvgpu/ptimer.h>
+#include <nvgpu/error_notifier.h>
+#include <nvgpu/debugger.h>
+#include <nvgpu/pm_reservation.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/fifo/userd.h>
+#include <nvgpu/perfbuf.h>
+#include <nvgpu/cyclestats_snapshot.h>
+#include <nvgpu/gr/zbc.h>
+#include <nvgpu/gr/setup.h>
+#include <nvgpu/gr/fecs_trace.h>
+#include <nvgpu/gr/gr_intr.h>
+#include <nvgpu/nvgpu_init.h>
+#ifdef CONFIG_NVGPU_SIM
+#include <nvgpu/sim.h>
+#endif
+
+#include "hal/grmgr/grmgr_ga10b.h"
+
+#ifndef CONFIG_NVGPU_MIG
+#include <nvgpu/grmgr.h>
+#endif
+
+static int ga10b_init_gpu_characteristics(struct gk20a *g)
+{
+	int err;
+
+	err = nvgpu_init_gpu_characteristics(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init GPU characteristics");
+		return err;
+	}
+
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
+#ifdef CONFIG_NVGPU_GRAPHICS
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
+#endif
+#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true);
+#endif
+	if (nvgpu_has_syncpoints(g)) {
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
+	}
+
+	return 0;
+}
+
+static const struct gops_acr ga10b_ops_acr = {
+	.acr_init = nvgpu_acr_init,
+	.acr_construct_execute = nvgpu_acr_construct_execute,
+};
+
+static const struct gops_func ga10b_ops_func = {
+	.get_full_phys_offset = ga10b_func_get_full_phys_offset,
+};
+
+#ifdef CONFIG_NVGPU_DGPU
+static const struct gops_bios ga10b_ops_bios = {
+	.bios_sw_init = nvgpu_bios_sw_init,
+};
+#endif
+
+static const struct gops_ecc ga10b_ops_ecc = {
+	.ecc_init_support = nvgpu_ecc_init_support,
+	.ecc_finalize_support = nvgpu_ecc_finalize_support,
+	.ecc_remove_support = nvgpu_ecc_remove_support,
+};
+
+static const struct gops_ltc_intr ga10b_ops_ltc_intr = {
+	.configure = ga10b_ltc_intr_configure,
+	.isr = ga10b_ltc_intr_isr,
+	.isr_extra = ga10b_ltc_intr_handle_lts_intr3_extra,
+	.ltc_intr3_configure_extra = ga10b_ltc_intr3_configure_extra,
+	.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
+};
+
+static const struct gops_ltc ga10b_ops_ltc = {
+	.ecc_init = gv11b_lts_ecc_init,
+	.init_ltc_support = nvgpu_init_ltc_support,
+	.ltc_remove_support = nvgpu_ltc_remove_support,
+	.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
+	.init_fs_state = ga10b_ltc_init_fs_state,
+	.ltc_lts_set_mgmt_setup = ga10b_ltc_lts_set_mgmt_setup,
+	.flush = gm20b_flush_ltc,
+	.set_enabled = gp10b_ltc_set_enabled,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.set_zbc_s_entry = ga10b_ltc_set_zbc_stencil_entry,
+	.set_zbc_color_entry = ga10b_ltc_set_zbc_color_entry,
+	.set_zbc_depth_entry = ga10b_ltc_set_zbc_depth_entry,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
+	.is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
+	.is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
+	.split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
+	.split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
+	.pri_is_lts_tstg_addr = tu104_ltc_pri_is_lts_tstg_addr,
+	.pri_shared_addr = ga10b_ltc_pri_shared_addr,
+	.set_l2_max_ways_evict_last = ga10b_set_l2_max_ways_evict_last,
+	.get_l2_max_ways_evict_last = ga10b_get_l2_max_ways_evict_last,
+	.set_l2_sector_promotion = tu104_set_l2_sector_promotion,
+#endif /* CONFIG_NVGPU_DEBUGGER */
+};
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+static const struct gops_cbc ga10b_ops_cbc = {
+	.cbc_init_support = nvgpu_cbc_init_support,
+	.cbc_remove_support = nvgpu_cbc_remove_support,
+	.init = ga10b_cbc_init,
+	.get_base_divisor = tu104_cbc_get_base_divisor,
+	.alloc_comptags = ga10b_cbc_alloc_comptags,
+	.ctrl = tu104_cbc_ctrl,
+};
+#endif
+
+static const struct gops_ce ga10b_ops_ce = {
+	.ce_init_support = nvgpu_ce_init_support,
+#ifdef CONFIG_NVGPU_DGPU
+	.ce_app_init_support = nvgpu_ce_app_init_support,
+	.ce_app_suspend = nvgpu_ce_app_suspend,
+	.ce_app_destroy = nvgpu_ce_app_destroy,
+#endif
+	.init_hw = ga10b_ce_init_hw,
+	.intr_enable = ga10b_ce_intr_enable,
+	.isr_stall = ga10b_ce_stall_isr,
+	.intr_retrigger = ga10b_ce_intr_retrigger,
+	.isr_nonstall = NULL,
+	.get_num_pce = gv11b_ce_get_num_pce,
+	.mthd_buffer_fault_in_bar2_fault = gv11b_ce_mthd_buffer_fault_in_bar2_fault,
+	.init_prod_values = gv11b_ce_init_prod_values,
+};
+
+static const struct gops_gr_ecc ga10b_ops_gr_ecc = {
+	.detect = ga10b_ecc_detect_enabled_units,
+	.gpc_tpc_ecc_init = ga10b_gr_gpc_tpc_ecc_init,
+	.fecs_ecc_init = gv11b_gr_fecs_ecc_init,
+#ifdef CONFIG_NVGPU_INJECT_HWERR
+	.get_mmu_err_desc = ga10b_gr_ecc_get_mmu_err_desc,
+	.get_gcc_err_desc = gv11b_gr_intr_get_gcc_err_desc,
+	.get_sm_err_desc = gv11b_gr_intr_get_sm_err_desc,
+	.get_gpccs_err_desc = gv11b_gr_intr_get_gpccs_err_desc,
+	.get_fecs_err_desc = gv11b_gr_intr_get_fecs_err_desc,
+#endif /* CONFIG_NVGPU_INJECT_HWERR */
+};
+
+static const struct gops_gr_ctxsw_prog ga10b_ops_gr_ctxsw_prog = {
+	.hw_get_fecs_header_size = ga10b_ctxsw_prog_hw_get_fecs_header_size,
+	.get_patch_count = gm20b_ctxsw_prog_get_patch_count,
+	.set_patch_count = gm20b_ctxsw_prog_set_patch_count,
+	.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
+	.init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data,
+	.set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
+	.set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode,
+	.set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr,
+	.disable_verif_features = gm20b_ctxsw_prog_disable_verif_features,
+	.set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr,
+	.set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr,
+	.set_zcull = gm20b_ctxsw_prog_set_zcull,
+	.set_zcull_mode_no_ctxsw = gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw,
+	.is_zcull_mode_separate_buffer = gm20b_ctxsw_prog_is_zcull_mode_separate_buffer,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+#ifdef CONFIG_NVGPU_GFXP
+	.set_graphics_preemption_mode_gfxp = gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp,
+	.set_full_preemption_ptr = gv11b_ctxsw_prog_set_full_preemption_ptr,
+	.set_full_preemption_ptr_veid0 = gv11b_ctxsw_prog_set_full_preemption_ptr_veid0,
+#endif /* CONFIG_NVGPU_GFXP */
+#ifdef CONFIG_NVGPU_CILP
+	.set_compute_preemption_mode_cilp = gp10b_ctxsw_prog_set_compute_preemption_mode_cilp,
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.hw_get_gpccs_header_size = ga10b_ctxsw_prog_hw_get_gpccs_header_size,
+	.hw_get_extended_buffer_segments_size_in_bytes = gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes,
+	.hw_extended_marker_size_in_bytes = gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes,
+	.hw_get_perf_counter_control_register_stride = gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride,
+	.get_main_image_ctx_id = gm20b_ctxsw_prog_get_main_image_ctx_id,
+	.set_pm_ptr = gv11b_ctxsw_prog_set_pm_ptr,
+	.set_pm_mode = gm20b_ctxsw_prog_set_pm_mode,
+	.set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode,
+	.hw_get_pm_mode_no_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw,
+	.hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw,
+	.hw_get_pm_mode_stream_out_ctxsw = gv11b_ctxsw_prog_hw_get_pm_mode_stream_out_ctxsw,
+	.set_cde_enabled = NULL,
+	.set_pc_sampling = NULL,
+	.check_main_image_header_magic = ga10b_ctxsw_prog_check_main_image_header_magic,
+	.check_local_header_magic = ga10b_ctxsw_prog_check_local_header_magic,
+	.get_num_gpcs = gm20b_ctxsw_prog_get_num_gpcs,
+	.get_num_tpcs = gm20b_ctxsw_prog_get_num_tpcs,
+	.get_extended_buffer_size_offset = gm20b_ctxsw_prog_get_extended_buffer_size_offset,
+	.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
+	.get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
+	.set_pmu_options_boost_clock_frequencies = NULL,
+	.hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride,
+	.hw_get_main_header_size = ga10b_ctxsw_prog_hw_get_main_header_size,
+	.hw_get_gpccs_header_stride = ga10b_ctxsw_prog_hw_get_gpccs_header_stride,
+	.get_compute_sysreglist_offset = ga10b_ctxsw_prog_get_compute_sysreglist_offset,
+	.get_gfx_sysreglist_offset = ga10b_ctxsw_prog_get_gfx_sysreglist_offset,
+	.get_ltsreglist_offset = ga10b_ctxsw_prog_get_ltsreglist_offset,
+	.get_compute_gpcreglist_offset = ga10b_ctxsw_prog_get_compute_gpcreglist_offset,
+	.get_gfx_gpcreglist_offset = ga10b_ctxsw_prog_get_gfx_gpcreglist_offset,
+	.get_compute_tpcreglist_offset = ga10b_ctxsw_prog_get_compute_tpcreglist_offset,
+	.get_gfx_tpcreglist_offset = ga10b_ctxsw_prog_get_gfx_tpcreglist_offset,
+	.get_compute_ppcreglist_offset = ga10b_ctxsw_prog_get_compute_ppcreglist_offset,
+	.get_gfx_ppcreglist_offset = ga10b_ctxsw_prog_get_gfx_ppcreglist_offset,
+	.get_compute_etpcreglist_offset = ga10b_ctxsw_prog_get_compute_etpcreglist_offset,
+	.get_gfx_etpcreglist_offset = ga10b_ctxsw_prog_get_gfx_etpcreglist_offset,
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#ifdef CONFIG_DEBUG_FS
+	.dump_ctxsw_stats = ga10b_ctxsw_prog_dump_ctxsw_stats,
+#endif
+#ifdef CONFIG_NVGPU_FECS_TRACE
+	.hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,
+	.hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag,
+	.hw_record_ts_timestamp = gm20b_ctxsw_prog_hw_record_ts_timestamp,
+	.hw_get_ts_record_size_in_bytes = gm20b_ctxsw_prog_hw_get_ts_record_size_in_bytes,
+	.is_ts_valid_record = gm20b_ctxsw_prog_is_ts_valid_record,
+	.get_ts_buffer_aperture_mask = NULL,
+	.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
+	.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
+#endif
+};
+
+static const struct gops_gr_config ga10b_ops_gr_config = {
+	.get_gpc_mask = gm20b_gr_config_get_gpc_mask,
+	.get_gpc_tpc_mask = gm20b_gr_config_get_gpc_tpc_mask,
+	.get_tpc_count_in_gpc = gm20b_gr_config_get_tpc_count_in_gpc,
+	.get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask,
+	.get_pd_dist_skip_table_size = gm20b_gr_config_get_pd_dist_skip_table_size,
+	.init_sm_id_table = gv100_gr_config_init_sm_id_table,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.get_zcull_count_in_gpc = gm20b_gr_config_get_zcull_count_in_gpc,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+};
+
+#ifdef CONFIG_NVGPU_FECS_TRACE
+static const struct gops_gr_fecs_trace ga10b_ops_gr_fecs_trace = {
+	.alloc_user_buffer = nvgpu_gr_fecs_trace_ring_alloc,
+	.free_user_buffer = nvgpu_gr_fecs_trace_ring_free,
+	.get_mmap_user_buffer_info = nvgpu_gr_fecs_trace_get_mmap_buffer_info,
+	.init = nvgpu_gr_fecs_trace_init,
+	.deinit = nvgpu_gr_fecs_trace_deinit,
+	.enable = nvgpu_gr_fecs_trace_enable,
+	.disable = nvgpu_gr_fecs_trace_disable,
+	.is_enabled = nvgpu_gr_fecs_trace_is_enabled,
+	.reset = nvgpu_gr_fecs_trace_reset,
+	.flush = NULL,
+	.poll = nvgpu_gr_fecs_trace_poll,
+	.bind_channel = nvgpu_gr_fecs_trace_bind_channel,
+	.unbind_channel = nvgpu_gr_fecs_trace_unbind_channel,
+	.max_entries = nvgpu_gr_fecs_trace_max_entries,
+	.get_buffer_full_mailbox_val = gv11b_fecs_trace_get_buffer_full_mailbox_val,
+	.get_read_index = gm20b_fecs_trace_get_read_index,
+	.get_write_index = gm20b_fecs_trace_get_write_index,
+	.set_read_index = gm20b_fecs_trace_set_read_index,
+};
+#endif
+
+static const struct gops_gr_setup ga10b_ops_gr_setup = {
+	.alloc_obj_ctx = nvgpu_gr_setup_alloc_obj_ctx,
+	.free_gr_ctx = nvgpu_gr_setup_free_gr_ctx,
+	.free_subctx = nvgpu_gr_setup_free_subctx,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+	.set_preemption_mode = nvgpu_gr_setup_set_preemption_mode,
+};
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+static const struct gops_gr_zbc ga10b_ops_gr_zbc = {
+	.add_color = ga10b_gr_zbc_add_color,
+	.add_depth = gp10b_gr_zbc_add_depth,
+	.set_table = nvgpu_gr_zbc_set_table,
+	.query_table = nvgpu_gr_zbc_query_table,
+	.add_stencil = gv11b_gr_zbc_add_stencil,
+	.get_gpcs_swdx_dss_zbc_c_format_reg = gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg,
+	.get_gpcs_swdx_dss_zbc_z_format_reg = gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg,
+	.init_table_indices = ga10b_gr_zbc_init_table_indices,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+static const struct gops_gr_zcull ga10b_ops_gr_zcull = {
+	.init_zcull_hw = gm20b_gr_init_zcull_hw,
+	.get_zcull_info = gm20b_gr_get_zcull_info,
+	.program_zcull_mapping = gv11b_gr_program_zcull_mapping,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_gr_hwpm_map ga10b_ops_gr_hwpm_map = {
+	.align_regs_perf_pma = gv100_gr_hwpm_map_align_regs_perf_pma,
+};
+#endif
+
+static const struct gops_gr_init ga10b_ops_gr_init = {
+	.get_no_of_sm = nvgpu_gr_get_no_of_sm,
+	.get_nonpes_aware_tpc = gv11b_gr_init_get_nonpes_aware_tpc,
+	.wait_initialized = nvgpu_gr_wait_initialized,
+	/* Since ecc scrubbing is moved to ctxsw ucode, setting HAL to NULL */
+	.ecc_scrub_reg = NULL,
+	.lg_coalesce = NULL,
+	.su_coalesce = NULL,
+	.pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,
+	.gpc_mmu = ga10b_gr_init_gpc_mmu,
+	.eng_config = ga10b_gr_init_eng_config,
+	.reset_gpcs = ga10b_gr_init_reset_gpcs,
+	.fifo_access = gm20b_gr_init_fifo_access,
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
+	.get_access_map = ga10b_gr_init_get_access_map,
+#endif
+	.get_sm_id_size = gp10b_gr_init_get_sm_id_size,
+	.sm_id_config_early = nvgpu_gr_init_sm_id_early_config,
+	.sm_id_config = gv11b_gr_init_sm_id_config,
+	.sm_id_numbering = ga10b_gr_init_sm_id_numbering,
+	.tpc_mask = gv11b_gr_init_tpc_mask,
+	.fs_state = ga10b_gr_init_fs_state,
+	.pd_tpc_per_gpc = gm20b_gr_init_pd_tpc_per_gpc,
+	.pd_skip_table_gpc = gm20b_gr_init_pd_skip_table_gpc,
+	.cwd_gpcs_tpcs_num = gm20b_gr_init_cwd_gpcs_tpcs_num,
+	.wait_empty = ga10b_gr_init_wait_empty,
+	.wait_idle = ga10b_gr_init_wait_idle,
+	.wait_fe_idle = gm20b_gr_init_wait_fe_idle,
+#ifdef CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION
+	.restore_stats_counter_bundle_data = gv11b_gr_init_restore_stats_counter_bundle_data,
+#endif
+	.fe_pwr_mode_force_on = gm20b_gr_init_fe_pwr_mode_force_on,
+	.override_context_reset = ga10b_gr_init_override_context_reset,
+	.fe_go_idle_timeout = ga10b_gr_init_fe_go_idle_timeout,
+	.auto_go_idle = ga10b_gr_init_auto_go_idle,
+	.load_method_init = gm20b_gr_init_load_method_init,
+	.commit_global_timeslice = ga10b_gr_init_commit_global_timeslice,
+	.get_bundle_cb_default_size = gv11b_gr_init_get_bundle_cb_default_size,
+	.get_min_gpm_fifo_depth = ga10b_gr_init_get_min_gpm_fifo_depth,
+	.get_bundle_cb_token_limit = ga10b_gr_init_get_bundle_cb_token_limit,
+	.get_attrib_cb_default_size = ga10b_gr_init_get_attrib_cb_default_size,
+	.get_alpha_cb_default_size = gv11b_gr_init_get_alpha_cb_default_size,
+	.get_attrib_cb_size = gv11b_gr_init_get_attrib_cb_size,
+	.get_alpha_cb_size = gv11b_gr_init_get_alpha_cb_size,
+	.get_global_attr_cb_size = gv11b_gr_init_get_global_attr_cb_size,
+	.get_global_ctx_cb_buffer_size = gm20b_gr_init_get_global_ctx_cb_buffer_size,
+	.get_global_ctx_pagepool_buffer_size = gm20b_gr_init_get_global_ctx_pagepool_buffer_size,
+	.commit_global_bundle_cb = ga10b_gr_init_commit_global_bundle_cb,
+	.pagepool_default_size = gp10b_gr_init_pagepool_default_size,
+	.commit_global_pagepool = gp10b_gr_init_commit_global_pagepool,
+	.commit_global_attrib_cb = gv11b_gr_init_commit_global_attrib_cb,
+	.commit_global_cb_manager = gp10b_gr_init_commit_global_cb_manager,
+	.pipe_mode_override = gm20b_gr_init_pipe_mode_override,
+#ifdef CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION
+	.load_sw_bundle_init = gv11b_gr_init_load_sw_bundle_init,
+#else
+	.load_sw_bundle_init = gm20b_gr_init_load_sw_bundle_init,
+#endif
+	.load_sw_veid_bundle = gv11b_gr_init_load_sw_veid_bundle,
+	.load_sw_bundle64 = tu104_gr_init_load_sw_bundle64,
+	.get_max_subctx_count = gv11b_gr_init_get_max_subctx_count,
+	.get_patch_slots = gv11b_gr_init_get_patch_slots,
+	.detect_sm_arch = gv11b_gr_init_detect_sm_arch,
+	.get_supported__preemption_modes = gp10b_gr_init_get_supported_preemption_modes,
+	.get_default_preemption_modes = gp10b_gr_init_get_default_preemption_modes,
+	.is_allowed_sw_bundle = gm20b_gr_init_is_allowed_sw_bundle,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.rop_mapping = gv11b_gr_init_rop_mapping,
+	.get_rtv_cb_size = tu104_gr_init_get_rtv_cb_size,
+	.commit_rtv_cb = tu104_gr_init_commit_rtv_cb,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+#ifdef CONFIG_NVGPU_GFXP
+	.preemption_state = gv11b_gr_init_preemption_state,
+	.get_ctx_attrib_cb_size = gp10b_gr_init_get_ctx_attrib_cb_size,
+	.commit_cbes_reserve = gv11b_gr_init_commit_cbes_reserve,
+	.commit_gfxp_rtv_cb = tu104_gr_init_commit_gfxp_rtv_cb,
+	.get_gfxp_rtv_cb_size = tu104_gr_init_get_gfxp_rtv_cb_size,
+	.get_attrib_cb_gfxp_default_size = ga10b_gr_init_get_attrib_cb_gfxp_default_size,
+	.get_attrib_cb_gfxp_size = ga10b_gr_init_get_attrib_cb_gfxp_size,
+	.gfxp_wfi_timeout = gv11b_gr_init_commit_gfxp_wfi_timeout,
+	.get_ctx_spill_size = ga10b_gr_init_get_ctx_spill_size,
+	.get_ctx_pagepool_size = gp10b_gr_init_get_ctx_pagepool_size,
+	.get_ctx_betacb_size = ga10b_gr_init_get_ctx_betacb_size,
+	.commit_ctxsw_spill = gv11b_gr_init_commit_ctxsw_spill,
+#endif /* CONFIG_NVGPU_GFXP */
+};
+
+static const struct gops_gr_intr ga10b_ops_gr_intr = {
+	.handle_fecs_error = gv11b_gr_intr_handle_fecs_error,
+	.handle_sw_method = ga10b_gr_intr_handle_sw_method,
+	.handle_class_error = gp10b_gr_intr_handle_class_error,
+	.clear_pending_interrupts = gm20b_gr_intr_clear_pending_interrupts,
+	.read_pending_interrupts = ga10b_gr_intr_read_pending_interrupts,
+	.handle_exceptions = ga10b_gr_intr_handle_exceptions,
+	.read_gpc_tpc_exception = gm20b_gr_intr_read_gpc_tpc_exception,
+	.read_gpc_exception = gm20b_gr_intr_read_gpc_exception,
+	.read_exception1 = gm20b_gr_intr_read_exception1,
+	.trapped_method_info = gm20b_gr_intr_get_trapped_method_info,
+	.handle_semaphore_pending = nvgpu_gr_intr_handle_semaphore_pending,
+	.handle_notify_pending = nvgpu_gr_intr_handle_notify_pending,
+	.handle_gcc_exception = gv11b_gr_intr_handle_gcc_exception,
+	.handle_gpc_gpcmmu_exception = ga10b_gr_intr_handle_gpc_gpcmmu_exception,
+	.handle_gpc_prop_exception = gv11b_gr_intr_handle_gpc_prop_exception,
+	.handle_gpc_zcull_exception = gv11b_gr_intr_handle_gpc_zcull_exception,
+	.handle_gpc_setup_exception = gv11b_gr_intr_handle_gpc_setup_exception,
+	.handle_gpc_pes_exception = gv11b_gr_intr_handle_gpc_pes_exception,
+	.handle_gpc_gpccs_exception = gv11b_gr_intr_handle_gpc_gpccs_exception,
+	.handle_gpc_zrop_hww = ga10b_gr_intr_handle_gpc_zrop_hww,
+	.handle_gpc_crop_hww = ga10b_gr_intr_handle_gpc_crop_hww,
+	.handle_gpc_rrh_hww = ga10b_gr_intr_handle_gpc_rrh_hww,
+	.get_tpc_exception = ga10b_gr_intr_get_tpc_exception,
+	.handle_tpc_mpc_exception = gv11b_gr_intr_handle_tpc_mpc_exception,
+	.handle_tpc_pe_exception = gv11b_gr_intr_handle_tpc_pe_exception,
+	.enable_hww_exceptions = gv11b_gr_intr_enable_hww_exceptions,
+	.enable_mask = ga10b_gr_intr_enable_mask,
+	.enable_interrupts = ga10b_gr_intr_enable_interrupts,
+	.enable_gpc_exceptions = ga10b_gr_intr_enable_gpc_exceptions,
+	.enable_gpc_crop_hww = ga10b_gr_intr_enable_gpc_crop_hww,
+	.enable_gpc_zrop_hww = ga10b_gr_intr_enable_gpc_zrop_hww,
+	.enable_exceptions = ga10b_gr_intr_enable_exceptions,
+	.nonstall_isr = NULL,
+	.handle_sm_exception = nvgpu_gr_intr_handle_sm_exception,
+	.stall_isr = nvgpu_gr_intr_stall_isr,
+	.retrigger = ga10b_gr_intr_retrigger,
+	.flush_channel_tlb = nvgpu_gr_intr_flush_channel_tlb,
+	.set_hww_esr_report_mask = ga10b_gr_intr_set_hww_esr_report_mask,
+	.handle_tpc_sm_ecc_exception = ga10b_gr_intr_handle_tpc_sm_ecc_exception,
+	.get_esr_sm_sel = gv11b_gr_intr_get_esr_sm_sel,
+	.clear_sm_hww = gv11b_gr_intr_clear_sm_hww,
+	.handle_ssync_hww = gv11b_gr_intr_handle_ssync_hww,
+	.record_sm_error_state = gv11b_gr_intr_record_sm_error_state,
+	.get_sm_hww_warp_esr = gv11b_gr_intr_get_sm_hww_warp_esr,
+	.get_sm_hww_warp_esr_pc = gv11b_gr_intr_get_sm_hww_warp_esr_pc,
+	.get_sm_hww_global_esr = gv11b_gr_intr_get_sm_hww_global_esr,
+	.get_sm_no_lock_down_hww_global_esr_mask = gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
+	.get_ctxsw_checksum_mismatch_mailbox_val = gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val,
+	.sm_ecc_status_errors = ga10b_gr_intr_sm_ecc_status_errors,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+	.handle_tex_exception = NULL,
+	.set_shader_exceptions = gv11b_gr_intr_set_shader_exceptions,
+	.tpc_exception_sm_enable = gm20b_gr_intr_tpc_exception_sm_enable,
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.tpc_exception_sm_disable = gm20b_gr_intr_tpc_exception_sm_disable,
+	.tpc_enabled_exceptions = gm20b_gr_intr_tpc_enabled_exceptions,
+#endif
+};
+
+static const struct gops_gr_falcon ga10b_ops_gr_falcon = {
+	.handle_fecs_ecc_error = gv11b_gr_falcon_handle_fecs_ecc_error,
+	.read_fecs_ctxsw_mailbox = gm20b_gr_falcon_read_fecs_ctxsw_mailbox,
+	.fecs_host_clear_intr = gm20b_gr_falcon_fecs_host_clear_intr,
+	.fecs_host_intr_status = gm20b_gr_falcon_fecs_host_intr_status,
+	.fecs_base_addr = gm20b_gr_falcon_fecs_base_addr,
+	.gpccs_base_addr = gm20b_gr_falcon_gpccs_base_addr,
+	.set_current_ctx_invalid = gm20b_gr_falcon_set_current_ctx_invalid,
+	.dump_stats = ga10b_gr_falcon_dump_stats,
+	.fecs_ctxsw_mailbox_size = ga10b_gr_falcon_get_fecs_ctxsw_mailbox_size,
+	.fecs_ctxsw_clear_mailbox = ga10b_gr_falcon_fecs_ctxsw_clear_mailbox,
+	.get_fecs_ctx_state_store_major_rev_id = gm20b_gr_falcon_get_fecs_ctx_state_store_major_rev_id,
+	.start_gpccs = gm20b_gr_falcon_start_gpccs,
+	.start_fecs = gm20b_gr_falcon_start_fecs,
+	.get_gpccs_start_reg_offset = gm20b_gr_falcon_get_gpccs_start_reg_offset,
+	.bind_instblk = NULL,
+	.wait_mem_scrubbing = gm20b_gr_falcon_wait_mem_scrubbing,
+	.wait_ctxsw_ready = gm20b_gr_falcon_wait_ctxsw_ready,
+	.ctrl_ctxsw = tu104_gr_falcon_ctrl_ctxsw,
+	.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
+	.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
+	.get_fecs_current_ctx_data = gm20b_gr_falcon_get_fecs_current_ctx_data,
+	.init_ctx_state = gp10b_gr_falcon_init_ctx_state,
+	.fecs_host_int_enable = gv11b_gr_falcon_fecs_host_int_enable,
+	.read_fecs_ctxsw_status0 = gm20b_gr_falcon_read_fecs_ctxsw_status0,
+	.read_fecs_ctxsw_status1 = gm20b_gr_falcon_read_fecs_ctxsw_status1,
+#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
+	.load_ctxsw_ucode_header = gm20b_gr_falcon_load_ctxsw_ucode_header,
+	.load_ctxsw_ucode_boot = gm20b_gr_falcon_load_ctxsw_ucode_boot,
+	.load_gpccs_dmem = gm20b_gr_falcon_load_gpccs_dmem,
+	.gpccs_dmemc_write = ga10b_gr_falcon_gpccs_dmemc_write,
+	.load_fecs_dmem = gm20b_gr_falcon_load_fecs_dmem,
+	.fecs_dmemc_write = ga10b_gr_falcon_fecs_dmemc_write,
+	.load_gpccs_imem = gm20b_gr_falcon_load_gpccs_imem,
+	.gpccs_imemc_write = ga10b_gr_falcon_gpccs_imemc_write,
+	.load_fecs_imem = gm20b_gr_falcon_load_fecs_imem,
+	.fecs_imemc_write = ga10b_gr_falcon_fecs_imemc_write,
+	.start_ucode = gm20b_gr_falcon_start_ucode,
+	.load_ctxsw_ucode = nvgpu_gr_falcon_load_ctxsw_ucode,
+#endif
+#ifdef CONFIG_NVGPU_SIM
+	.configure_fmodel = gm20b_gr_falcon_configure_fmodel,
+#endif
+};
+
+static const struct gops_gr ga10b_ops_gr = {
+	.gr_init_support = nvgpu_gr_init_support,
+	.gr_suspend = nvgpu_gr_suspend,
+	.vab_init = ga10b_gr_vab_init,
+	.vab_release = ga10b_gr_vab_release,
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.get_gr_status = gr_gm20b_get_gr_status,
+	.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size,
+	.set_circular_buffer_size = gr_ga10b_set_circular_buffer_size,
+	.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
+	.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
+#ifdef CONFIG_NVGPU_TEGRA_FUSE
+	.set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask,
+#endif
+	.dump_gr_regs = gr_ga10b_dump_gr_status_regs,
+	.update_pc_sampling = NULL,
+	.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
+	.init_cyclestats = gr_gm20b_init_cyclestats,
+	.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode,
+	.bpt_reg_info = gv11b_gr_bpt_reg_info,
+	.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
+	.update_smpc_global_mode = tu104_gr_update_smpc_global_mode,
+	.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
+	.disable_cau = tu104_gr_disable_cau,
+	.disable_smpc = tu104_gr_disable_smpc,
+	.get_hwpm_cau_init_data = ga10b_gr_get_hwpm_cau_init_data,
+	.init_cau = tu104_gr_init_cau,
+	.clear_sm_error_state = gv11b_gr_clear_sm_error_state,
+	.suspend_contexts = gr_gp10b_suspend_contexts,
+	.resume_contexts = gr_gk20a_resume_contexts,
+	.trigger_suspend = NULL,
+	.wait_for_pause = NULL,
+	.resume_from_pause = NULL,
+	.clear_sm_errors = gr_gk20a_clear_sm_errors,
+	.is_tsg_ctx_resident = gk20a_is_tsg_ctx_resident,
+	.sm_debugger_attached = gv11b_gr_sm_debugger_attached,
+	.suspend_single_sm = gv11b_gr_suspend_single_sm,
+	.suspend_all_sms = gv11b_gr_suspend_all_sms,
+	.resume_single_sm = gv11b_gr_resume_single_sm,
+	.resume_all_sms = gv11b_gr_resume_all_sms,
+	.lock_down_sm = gv11b_gr_lock_down_sm,
+	.wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down,
+	.init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf,
+	.get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs,
+#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
+	.set_boosted_ctx = NULL,
+#endif
+	.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
+	.set_bes_crop_debug3 = NULL,
+	.set_bes_crop_debug4 = ga10b_gr_set_gpcs_rops_crop_debug4,
+	.is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
+	.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
+	.get_egpc_base = gv11b_gr_get_egpc_base,
+	.get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
+	.is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
+	.decode_egpc_addr = gv11b_gr_decode_egpc_addr,
+	.decode_priv_addr = gr_ga10b_decode_priv_addr,
+	.create_priv_addr_table = gr_ga10b_create_priv_addr_table,
+	.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
+	.get_offset_in_gpccs_segment = NULL,
+	.process_context_buffer_priv_segment =
+		gr_ga10b_process_context_buffer_priv_segment,
+	.set_debug_mode = gm20b_gr_set_debug_mode,
+	.set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode,
+	.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
+	.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
+	.get_pm_ctx_buffer_offsets = gr_gk20a_get_pm_ctx_buffer_offsets,
+	.find_priv_offset_in_buffer =
+		gr_ga10b_find_priv_offset_in_buffer,
+	.check_warp_esr_error = ga10b_gr_check_warp_esr_error,
+#endif /* CONFIG_NVGPU_DEBUGGER */
+};
+
+static const struct gops_class ga10b_ops_gpu_class = {
+	.is_valid = ga10b_class_is_valid,
+	.is_valid_compute = ga10b_class_is_valid_compute,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.is_valid_gfx = ga10b_class_is_valid_gfx,
+#endif
+};
+
+static const struct gops_fb_ecc ga10b_ops_fb_ecc = {
+	.init = ga10b_fb_ecc_init,
+	.free = ga10b_fb_ecc_free,
+	.l2tlb_error_mask = ga10b_fb_ecc_l2tlb_error_mask,
+};
+
+static const struct gops_fb_intr ga10b_ops_fb_intr = {
+	.enable = ga10b_fb_intr_enable,
+	.disable = ga10b_fb_intr_disable,
+	.isr = ga10b_fb_intr_isr,
+	.is_mmu_fault_pending = NULL,
+	.handle_ecc = gv11b_fb_intr_handle_ecc,
+	.handle_ecc_l2tlb = ga10b_fb_intr_handle_ecc_l2tlb,
+	.handle_ecc_hubtlb = ga10b_fb_intr_handle_ecc_hubtlb,
+	.handle_ecc_fillunit = ga10b_fb_intr_handle_ecc_fillunit,
+};
+
+static const struct gops_fb_vab ga10b_ops_fb_vab = {
+	.init = ga10b_fb_vab_init,
+	.reserve = ga10b_fb_vab_reserve,
+	.dump_and_clear = ga10b_fb_vab_dump_and_clear,
+	.release = ga10b_fb_vab_release,
+	.teardown = ga10b_fb_vab_teardown,
+};
+
+static const struct gops_fb ga10b_ops_fb = {
+#ifdef CONFIG_NVGPU_INJECT_HWERR
+	.get_hubmmu_err_desc = gv11b_fb_intr_get_hubmmu_err_desc,
+#endif /* CONFIG_NVGPU_INJECT_HWERR */
+	.init_hw = ga10b_fb_init_hw,
+	.init_fs_state = ga10b_fb_init_fs_state,
+	.set_mmu_page_size = NULL,
+	.mmu_ctrl = gm20b_fb_mmu_ctrl,
+	.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
+	.mmu_debug_wr = gm20b_fb_mmu_debug_wr,
+	.mmu_debug_rd = gm20b_fb_mmu_debug_rd,
+#ifdef CONFIG_NVGPU_COMPRESSION
+	.cbc_configure = ga10b_fb_cbc_configure,
+	.set_use_full_comp_tag_line = NULL,
+	.compression_page_size = gp10b_fb_compression_page_size,
+	.compressible_page_size = gp10b_fb_compressible_page_size,
+	.compression_align_mask = gm20b_fb_compression_align_mask,
+#endif
+	.vpr_info_fetch = ga10b_fb_vpr_info_fetch,
+	.dump_vpr_info = ga10b_fb_dump_vpr_info,
+	.dump_wpr_info = ga10b_fb_dump_wpr_info,
+	.read_wpr_info = ga10b_fb_read_wpr_info,
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
+	.set_debug_mode = gm20b_fb_set_debug_mode,
+	.set_mmu_debug_mode = gm20b_fb_set_mmu_debug_mode,
+#endif
+	.tlb_invalidate = gm20b_fb_tlb_invalidate,
+#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
+	.handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault,
+	.mmu_invalidate_replay = gv11b_fb_mmu_invalidate_replay,
+#endif
+#ifdef CONFIG_NVGPU_DGPU
+	.mem_unlock = NULL,
+#endif
+	.write_mmu_fault_buffer_lo_hi = gv11b_fb_write_mmu_fault_buffer_lo_hi,
+	.write_mmu_fault_buffer_get = fb_gv11b_write_mmu_fault_buffer_get,
+	.write_mmu_fault_buffer_size = gv11b_fb_write_mmu_fault_buffer_size,
+	.write_mmu_fault_status = gv11b_fb_write_mmu_fault_status,
+	.read_mmu_fault_buffer_get = gv11b_fb_read_mmu_fault_buffer_get,
+	.read_mmu_fault_buffer_put = gv11b_fb_read_mmu_fault_buffer_put,
+	.read_mmu_fault_buffer_size = gv11b_fb_read_mmu_fault_buffer_size,
+	.read_mmu_fault_addr_lo_hi = gv11b_fb_read_mmu_fault_addr_lo_hi,
+	.read_mmu_fault_inst_lo_hi = gv11b_fb_read_mmu_fault_inst_lo_hi,
+	.read_mmu_fault_info = gv11b_fb_read_mmu_fault_info,
+	.read_mmu_fault_status = gv11b_fb_read_mmu_fault_status,
+	.is_fault_buf_enabled = gv11b_fb_is_fault_buf_enabled,
+	.fault_buf_set_state_hw = gv11b_fb_fault_buf_set_state_hw,
+	.fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw,
+	.get_num_active_ltcs = ga10b_fb_get_num_active_ltcs,
+#ifdef CONFIG_NVGPU_MIG
+	.config_veid_smc_map = ga10b_fb_config_veid_smc_map,
+	.set_smc_eng_config = ga10b_fb_set_smc_eng_config,
+	.set_remote_swizid = ga10b_fb_set_remote_swizid,
+#endif
+	.set_atomic_mode = ga10b_fb_set_atomic_mode,
+};
+
+static const struct gops_cg ga10b_ops_cg = {
+	.slcg_bus_load_gating_prod = ga10b_slcg_bus_load_gating_prod,
+	.slcg_ce2_load_gating_prod = ga10b_slcg_ce2_load_gating_prod,
+	.slcg_chiplet_load_gating_prod = ga10b_slcg_chiplet_load_gating_prod,
+	.slcg_fb_load_gating_prod = ga10b_slcg_fb_load_gating_prod,
+	.slcg_fifo_load_gating_prod = NULL,
+	.slcg_runlist_load_gating_prod = ga10b_slcg_runlist_load_gating_prod,
+	.slcg_gr_load_gating_prod = ga10b_slcg_gr_load_gating_prod,
+	.slcg_ltc_load_gating_prod = ga10b_slcg_ltc_load_gating_prod,
+	.slcg_perf_load_gating_prod = ga10b_slcg_perf_load_gating_prod,
+	.slcg_priring_load_gating_prod = ga10b_slcg_priring_load_gating_prod,
+	.slcg_rs_ctrl_fbp_load_gating_prod =
+				ga10b_slcg_rs_ctrl_fbp_load_gating_prod,
+	.slcg_rs_ctrl_gpc_load_gating_prod =
+				ga10b_slcg_rs_ctrl_gpc_load_gating_prod,
+	.slcg_rs_ctrl_sys_load_gating_prod =
+				ga10b_slcg_rs_ctrl_sys_load_gating_prod,
+	.slcg_rs_fbp_load_gating_prod = ga10b_slcg_rs_fbp_load_gating_prod,
+	.slcg_rs_gpc_load_gating_prod = ga10b_slcg_rs_gpc_load_gating_prod,
+	.slcg_rs_sys_load_gating_prod = ga10b_slcg_rs_sys_load_gating_prod,
+	.slcg_pmu_load_gating_prod = ga10b_slcg_pmu_load_gating_prod,
+	.slcg_therm_load_gating_prod = ga10b_slcg_therm_load_gating_prod,
+	.slcg_xbar_load_gating_prod = ga10b_slcg_xbar_load_gating_prod,
+	.slcg_hshub_load_gating_prod = ga10b_slcg_hshub_load_gating_prod,
+	.slcg_timer_load_gating_prod = ga10b_slcg_timer_load_gating_prod,
+	.blcg_bus_load_gating_prod = ga10b_blcg_bus_load_gating_prod,
+	.blcg_ce_load_gating_prod = ga10b_blcg_ce_load_gating_prod,
+	.blcg_fb_load_gating_prod = ga10b_blcg_fb_load_gating_prod,
+	.blcg_fifo_load_gating_prod = NULL,
+	.blcg_runlist_load_gating_prod = ga10b_blcg_runlist_load_gating_prod,
+	.blcg_gr_load_gating_prod = ga10b_blcg_gr_load_gating_prod,
+	.blcg_ltc_load_gating_prod = ga10b_blcg_ltc_load_gating_prod,
+	.blcg_pmu_load_gating_prod = ga10b_blcg_pmu_load_gating_prod,
+	.blcg_xbar_load_gating_prod = ga10b_blcg_xbar_load_gating_prod,
+	.blcg_hshub_load_gating_prod = ga10b_blcg_hshub_load_gating_prod,
+	.elcg_ce_load_gating_prod = ga10b_elcg_ce_load_gating_prod,
+};
+
+static const struct gops_fifo ga10b_ops_fifo = {
+	.fifo_init_support = nvgpu_fifo_init_support,
+	.fifo_suspend = nvgpu_fifo_suspend,
+	.init_fifo_setup_hw = ga10b_init_fifo_setup_hw,
+	.preempt_channel = gv11b_fifo_preempt_channel,
+	.preempt_tsg = nvgpu_fifo_preempt_tsg,
+	.preempt_trigger = ga10b_fifo_preempt_trigger,
+	.preempt_poll_pbdma = gv11b_fifo_preempt_poll_pbdma,
+	.is_preempt_pending = gv11b_fifo_is_preempt_pending,
+	.reset_enable_hw = ga10b_init_fifo_reset_enable_hw,
+#ifdef CONFIG_NVGPU_RECOVERY
+	.recover = gv11b_fifo_recover,
+#endif
+	.intr_set_recover_mask = ga10b_fifo_intr_set_recover_mask,
+	.intr_unset_recover_mask = ga10b_fifo_intr_unset_recover_mask,
+	.setup_sw = nvgpu_fifo_setup_sw,
+	.cleanup_sw = nvgpu_fifo_cleanup_sw,
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.set_sm_exception_type_mask = nvgpu_tsg_set_sm_exception_type_mask,
+#endif
+	.intr_top_enable = ga10b_fifo_intr_top_enable,
+	.intr_0_enable = ga10b_fifo_intr_0_enable,
+	.intr_1_enable = ga10b_fifo_intr_1_enable,
+	.intr_0_isr = ga10b_fifo_intr_0_isr,
+	.intr_1_isr = NULL,
+	.runlist_intr_retrigger = ga10b_fifo_runlist_intr_retrigger,
+	.handle_sched_error = NULL,
+	.ctxsw_timeout_enable = ga10b_fifo_ctxsw_timeout_enable,
+	.handle_ctxsw_timeout = NULL,
+	.trigger_mmu_fault = NULL,
+	.get_mmu_fault_info = NULL,
+	.get_mmu_fault_desc = NULL,
+	.get_mmu_fault_client_desc = NULL,
+	.get_mmu_fault_gpc_desc = NULL,
+	.get_runlist_timeslice = NULL,
+	.get_pb_timeslice = NULL,
+	.mmu_fault_id_to_pbdma_id = ga10b_fifo_mmu_fault_id_to_pbdma_id,
+};
+
+static const struct gops_engine ga10b_ops_engine = {
+	.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
+	.init_ce_info = gp10b_engine_init_ce_info,
+};
+
+static const struct gops_pbdma ga10b_ops_pbdma = {
+	.setup_sw = nvgpu_pbdma_setup_sw,
+	.cleanup_sw = nvgpu_pbdma_cleanup_sw,
+	.setup_hw = NULL,
+	.intr_enable = ga10b_pbdma_intr_enable,
+	.acquire_val = gm20b_pbdma_acquire_val,
+	.get_signature = gp10b_pbdma_get_signature,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+	.syncpt_debug_dump = NULL,
+	.dump_status = ga10b_pbdma_dump_status,
+#endif
+	.handle_intr_0 = ga10b_pbdma_handle_intr_0,
+	.handle_intr_1 = ga10b_pbdma_handle_intr_1,
+	.handle_intr = ga10b_pbdma_handle_intr,
+	.set_clear_intr_offsets = ga10b_pbdma_set_clear_intr_offsets,
+	.read_data = ga10b_pbdma_read_data,
+	.reset_header = ga10b_pbdma_reset_header,
+	.device_fatal_0_intr_descs = ga10b_pbdma_device_fatal_0_intr_descs,
+	.channel_fatal_0_intr_descs = ga10b_pbdma_channel_fatal_0_intr_descs,
+	.restartable_0_intr_descs = gm20b_pbdma_restartable_0_intr_descs,
+	.format_gpfifo_entry = gm20b_pbdma_format_gpfifo_entry,
+	.get_gp_base = gm20b_pbdma_get_gp_base,
+	.get_gp_base_hi = gm20b_pbdma_get_gp_base_hi,
+	.get_fc_formats = NULL,
+	.get_fc_pb_header = gv11b_pbdma_get_fc_pb_header,
+	.get_fc_subdevice = gm20b_pbdma_get_fc_subdevice,
+	.get_fc_target = ga10b_pbdma_get_fc_target,
+	.get_ctrl_hce_priv_mode_yes = gm20b_pbdma_get_ctrl_hce_priv_mode_yes,
+	.get_userd_aperture_mask = NULL,
+	.get_userd_addr = NULL,
+	.get_userd_hi_addr = NULL,
+	.get_fc_runlist_timeslice = NULL,
+	.get_config_auth_level_privileged = gp10b_pbdma_get_config_auth_level_privileged,
+	.set_channel_info_veid = gv11b_pbdma_set_channel_info_veid,
+	.set_channel_info_chid = ga10b_pbdma_set_channel_info_chid,
+	.set_intr_notify = ga10b_pbdma_set_intr_notify,
+	.config_userd_writeback_enable = gv11b_pbdma_config_userd_writeback_enable,
+	.get_mmu_fault_id = ga10b_pbdma_get_mmu_fault_id,
+	.get_num_of_pbdmas = ga10b_pbdma_get_num_of_pbdmas,
+};
+
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+static const struct gops_sync_syncpt ga10b_ops_sync_syncpt = {
+	.alloc_buf = gv11b_syncpt_alloc_buf,
+	.free_buf = gv11b_syncpt_free_buf,
+#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
+	.add_wait_cmd = gv11b_syncpt_add_wait_cmd,
+	.get_wait_cmd_size = gv11b_syncpt_get_wait_cmd_size,
+	.add_incr_cmd = gv11b_syncpt_add_incr_cmd,
+	.get_incr_cmd_size = gv11b_syncpt_get_incr_cmd_size,
+	.get_incr_per_release = gv11b_syncpt_get_incr_per_release,
+#endif
+	.get_sync_ro_map = gv11b_syncpt_get_sync_ro_map,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_SW_SEMAPHORE
+static const struct gops_sync_sema ga10b_ops_sync_sema = {
+	.add_wait_cmd = gv11b_sema_add_wait_cmd,
+	.get_wait_cmd_size = gv11b_sema_get_wait_cmd_size,
+	.add_incr_cmd = gv11b_sema_add_incr_cmd,
+	.get_incr_cmd_size = gv11b_sema_get_incr_cmd_size,
+};
+#endif
+
+static const struct gops_sync ga10b_ops_sync = {
+};
+
+static const struct gops_engine_status ga10b_ops_engine_status = {
+	.read_engine_status_info = ga10b_read_engine_status_info,
+	/* TODO update this hal for ga10b */
+	.dump_engine_status = gv100_dump_engine_status,
+};
+
+static const struct gops_pbdma_status ga10b_ops_pbdma_status = {
+	.read_pbdma_status_info = ga10b_read_pbdma_status_info,
+};
+
+static const struct gops_ramfc ga10b_ops_ramfc = {
+	.setup = ga10b_ramfc_setup,
+	.capture_ram_dump = ga10b_ramfc_capture_ram_dump,
+	.commit_userd = NULL,
+	.get_syncpt = NULL,
+	.set_syncpt = NULL,
+};
+
+static const struct gops_ramin ga10b_ops_ramin = {
+	.set_gr_ptr = gv11b_ramin_set_gr_ptr,
+	.set_big_page_size = gm20b_ramin_set_big_page_size,
+	.init_pdb = ga10b_ramin_init_pdb,
+	.init_subctx_pdb = gv11b_ramin_init_subctx_pdb,
+	.set_adr_limit = NULL,
+	.base_shift = gk20a_ramin_base_shift,
+	.alloc_size = gk20a_ramin_alloc_size,
+	.set_eng_method_buffer = gv11b_ramin_set_eng_method_buffer,
+};
+
+static const struct gops_runlist ga10b_ops_runlist = {
+#ifdef NVGPU_CHANNEL_TSG_SCHEDULING
+	.reschedule = gv11b_runlist_reschedule,
+	.reschedule_preempt_next_locked = ga10b_fifo_reschedule_preempt_next,
+#endif
+	.update = nvgpu_runlist_update,
+	.reload = nvgpu_runlist_reload,
+	.count_max = ga10b_runlist_count_max,
+	.entry_size = gv11b_runlist_entry_size,
+	.length_max = ga10b_runlist_length_max,
+	.get_tsg_entry = gv11b_runlist_get_tsg_entry,
+	.get_ch_entry = gv11b_runlist_get_ch_entry,
+	.hw_submit = ga10b_runlist_hw_submit,
+	.wait_pending = ga10b_runlist_wait_pending,
+	.write_state = ga10b_runlist_write_state,
+	.get_runlist_id = ga10b_runlist_get_runlist_id,
+	.get_engine_id_from_rleng_id = ga10b_runlist_get_engine_id_from_rleng_id,
+	.get_chram_bar0_offset = ga10b_runlist_get_chram_bar0_offset,
+	.get_pbdma_info = ga10b_runlist_get_pbdma_info,
+	.get_engine_intr_id = ga10b_runlist_get_engine_intr_id,
+	.init_enginfo = nvgpu_next_runlist_init_enginfo,
+	.get_tsg_max_timeslice = gv11b_runlist_max_timeslice,
+	.get_esched_fb_thread_id = ga10b_runlist_get_esched_fb_thread_id,
+};
+
+static const struct gops_userd ga10b_ops_userd = {
+#ifdef CONFIG_NVGPU_USERD
+	.setup_sw = nvgpu_userd_setup_sw,
+	.cleanup_sw = nvgpu_userd_cleanup_sw,
+	.init_mem = ga10b_userd_init_mem,
+#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
+	.gp_get = gv11b_userd_gp_get,
+	.gp_put = gv11b_userd_gp_put,
+	.pb_get = gv11b_userd_pb_get,
+#endif
+#endif /* CONFIG_NVGPU_USERD */
+	.entry_size = gk20a_userd_entry_size,
+};
+
+static const struct gops_channel ga10b_ops_channel = {
+	.alloc_inst = nvgpu_channel_alloc_inst,
+	.free_inst = nvgpu_channel_free_inst,
+	.bind = ga10b_channel_bind,
+	.unbind = ga10b_channel_unbind,
+	.clear = ga10b_channel_unbind,
+	.enable = ga10b_channel_enable,
+	.disable = ga10b_channel_disable,
+	.count = ga10b_channel_count,
+	.read_state = ga10b_channel_read_state,
+	.force_ctx_reload = ga10b_channel_force_ctx_reload,
+	.abort_clean_up = nvgpu_channel_abort_clean_up,
+	.suspend_all_serviceable_ch = nvgpu_channel_suspend_all_serviceable_ch,
+	.resume_all_serviceable_ch = nvgpu_channel_resume_all_serviceable_ch,
+	.set_error_notifier = nvgpu_set_err_notifier_if_empty,
+	.reset_faulted = ga10b_channel_reset_faulted,
+};
+
+static const struct gops_tsg ga10b_ops_tsg = {
+	.enable = gv11b_tsg_enable,
+	.disable = nvgpu_tsg_disable,
+	.init_eng_method_buffers = gv11b_tsg_init_eng_method_buffers,
+	.deinit_eng_method_buffers = gv11b_tsg_deinit_eng_method_buffers,
+	.bind_channel = NULL,
+	.bind_channel_eng_method_buffers = gv11b_tsg_bind_channel_eng_method_buffers,
+	.unbind_channel = NULL,
+	.unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_check_hw_state,
+	.unbind_channel_check_hw_next = ga10b_tsg_unbind_channel_check_hw_next,
+	.unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_check_ctx_reload,
+	.unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted,
+#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
+	.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
+#endif
+#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL
+	.force_reset = nvgpu_tsg_force_reset_ch,
+	.post_event_id = nvgpu_tsg_post_event_id,
+#endif
+#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
+	.set_timeslice = nvgpu_tsg_set_timeslice,
+	.set_long_timeslice = nvgpu_tsg_set_long_timeslice,
+#endif
+	.default_timeslice_us = nvgpu_tsg_default_timeslice_us,
+};
+
+static const struct gops_usermode ga10b_ops_usermode = {
+	.setup_hw = ga10b_usermode_setup_hw,
+	.base = tu104_usermode_base,
+	.bus_base = tu104_usermode_bus_base,
+	.ring_doorbell = tu104_usermode_ring_doorbell,
+	.doorbell_token = tu104_usermode_doorbell_token,
+};
+
+static const struct gops_netlist ga10b_ops_netlist = {
+	.get_netlist_name = ga10b_netlist_get_name,
+	.is_fw_defined = ga10b_netlist_is_firmware_defined,
+};
+
+static const struct gops_mm_mmu_fault ga10b_ops_mm_mmu_fault = {
+	.setup_sw = gv11b_mm_mmu_fault_setup_sw,
+	.setup_hw = gv11b_mm_mmu_fault_setup_hw,
+	.info_mem_destroy = gv11b_mm_mmu_fault_info_mem_destroy,
+	.disable_hw = gv11b_mm_mmu_fault_disable_hw,
+	.parse_mmu_fault_info = ga10b_mm_mmu_fault_parse_mmu_fault_info,
+};
+
+static const struct gops_mm_cache ga10b_ops_mm_cache = {
+	.fb_flush = gk20a_mm_fb_flush,
+	.l2_invalidate = gk20a_mm_l2_invalidate,
+	.l2_flush = gv11b_mm_l2_flush,
+#ifdef CONFIG_NVGPU_COMPRESSION
+	.cbc_clean = gk20a_mm_cbc_clean,
+#endif
+};
+
+static const struct gops_mm_gmmu ga10b_ops_mm_gmmu = {
+	.get_mmu_levels = ga10b_mm_get_mmu_levels,
+	.get_max_page_table_levels = ga10b_get_max_page_table_levels,
+	.map = nvgpu_gmmu_map_locked,
+	.unmap = nvgpu_gmmu_unmap_locked,
+	.get_big_page_sizes = gm20b_mm_get_big_page_sizes,
+	.get_default_big_page_size = nvgpu_gmmu_default_big_page_size,
+	.get_iommu_bit = ga10b_mm_get_iommu_bit,
+	.gpu_phys_addr = gv11b_gpu_phys_addr,
+};
+
+static const struct gops_mm ga10b_ops_mm = {
+	.init_mm_support = nvgpu_init_mm_support,
+	.pd_cache_init = nvgpu_pd_cache_init,
+	.mm_suspend = nvgpu_mm_suspend,
+	.vm_bind_channel = nvgpu_vm_bind_channel,
+	.setup_hw = nvgpu_mm_setup_hw,
+	.is_bar1_supported = gv11b_mm_is_bar1_supported,
+	.init_inst_block = gv11b_mm_init_inst_block,
+	.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
+	.init_bar2_vm = gp10b_mm_init_bar2_vm,
+	.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
+	.get_default_va_sizes = gp10b_mm_get_default_va_sizes,
+	.bar1_map_userd = NULL,
+};
+
+static const struct gops_therm ga10b_ops_therm = {
+	.therm_max_fpdiv_factor = ga10b_therm_max_fpdiv_factor,
+	.init_therm_support = nvgpu_init_therm_support,
+	.init_therm_setup_hw = gv11b_init_therm_setup_hw,
+	.init_elcg_mode = gv11b_therm_init_elcg_mode,
+#ifdef CONFIG_NVGPU_NON_FUSA
+	.init_blcg_mode = gm20b_therm_init_blcg_mode,
+#endif
+	.elcg_init_idle_filters = ga10b_elcg_init_idle_filters,
+};
+
+static const struct gops_gsp ga10b_ops_gsp = {
+	.falcon_base_addr = ga10b_gsp_falcon_base_addr,
+	.falcon2_base_addr = ga10b_gsp_falcon2_base_addr,
+};
+
+static const struct gops_pmu ga10b_ops_pmu = {
+	.ecc_init = gv11b_pmu_ecc_init,
+	.ecc_free = gv11b_pmu_ecc_free,
+#ifdef CONFIG_NVGPU_INJECT_HWERR
+	.get_pmu_err_desc = gv11b_pmu_intr_get_err_desc,
+#endif /* CONFIG_NVGPU_INJECT_HWERR */
+	/*
+		 * Basic init ops are must, as PMU engine used by ACR to
+		 * load & bootstrap GR LS falcons without LS PMU, remaining
+		 * ops can be assigned/ignored as per build flag request
+		 */
+	/* Basic init ops */
+	.pmu_early_init = nvgpu_pmu_early_init,
+	.is_pmu_supported = ga10b_is_pmu_supported,
+	.falcon_base_addr = gv11b_pmu_falcon_base_addr,
+	.falcon2_base_addr = ga10b_pmu_falcon2_base_addr,
+	.pmu_reset = nvgpu_pmu_reset,
+	.reset_engine = gv11b_pmu_engine_reset,
+	.is_engine_in_reset = gv11b_pmu_is_engine_in_reset,
+	.is_debug_mode_enabled = ga10b_pmu_is_debug_mode_en,
+	/* aperture set up is moved to acr */
+	.setup_apertures = NULL,
+	.secured_pmu_start = gv11b_secured_pmu_start,
+	.write_dmatrfbase = gv11b_write_dmatrfbase,
+	.flcn_setup_boot_config = gv11b_pmu_flcn_setup_boot_config,
+	.pmu_clear_bar0_host_err_status = gv11b_clear_pmu_bar0_host_err_status,
+	.bar0_error_status = gv11b_pmu_bar0_error_status,
+	.validate_mem_integrity = gv11b_pmu_validate_mem_integrity,
+	.pmu_enable_irq = gv11b_pmu_enable_irq,
+	.get_irqdest = gv11b_pmu_get_irqdest,
+	.get_irqmask = ga10b_pmu_get_irqmask,
+	.pmu_isr = gk20a_pmu_isr,
+	.handle_ext_irq = gv11b_pmu_handle_ext_irq,
+#ifdef CONFIG_NVGPU_LS_PMU
+	.get_inst_block_config = ga10b_pmu_get_inst_block_config,
+	/* Init */
+	.pmu_rtos_init = nvgpu_pmu_rtos_init,
+	.pmu_pstate_sw_setup = nvgpu_pmu_pstate_sw_setup,
+	.pmu_pstate_pmu_setup = nvgpu_pmu_pstate_pmu_setup,
+	.pmu_destroy = nvgpu_pmu_destroy,
+	/* ISR */
+	.pmu_is_interrupted = gk20a_pmu_is_interrupted,
+	/* queue */
+	.pmu_get_queue_head = gv11b_pmu_queue_head_r,
+	.pmu_get_queue_head_size = gv11b_pmu_queue_head__size_1_v,
+	.pmu_get_queue_tail = gv11b_pmu_queue_tail_r,
+	.pmu_get_queue_tail_size = gv11b_pmu_queue_tail__size_1_v,
+	.pmu_queue_head = gk20a_pmu_queue_head,
+	.pmu_queue_tail = gk20a_pmu_queue_tail,
+	.pmu_msgq_tail = gk20a_pmu_msgq_tail,
+	/* mutex */
+	.pmu_mutex_size = gv11b_pmu_mutex__size_1_v,
+	.pmu_mutex_owner = gk20a_pmu_mutex_owner,
+	.pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
+	.pmu_mutex_release = gk20a_pmu_mutex_release,
+	/* power-gating */
+	.pmu_setup_elpg = gv11b_pmu_setup_elpg,
+	.pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config,
+	.pmu_dump_elpg_stats = ga10b_pmu_dump_elpg_stats,
+	/* perfmon */
+	.pmu_init_perfmon_counter = ga10b_pmu_init_perfmon_counter,
+	.pmu_read_idle_counter = ga10b_pmu_read_idle_counter,
+	.pmu_reset_idle_counter = ga10b_pmu_reset_idle_counter,
+	.pmu_read_idle_intr_status = gk20a_pmu_read_idle_intr_status,
+	.pmu_clear_idle_intr_status = gk20a_pmu_clear_idle_intr_status,
+	/* debug */
+	.dump_secure_fuses = pmu_dump_security_fuses_gm20b,
+	.pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats,
+	/* PMU ucode */
+	.pmu_ns_bootstrap = ga10b_pmu_ns_bootstrap,
+#endif
+};
+
+#ifdef CONFIG_NVGPU_CLK_ARB
+static const struct gops_clk_arb ga10b_ops_clk_arb = {
+	.clk_arb_init_arbiter = nvgpu_clk_arb_init_arbiter,
+	.check_clk_arb_support = gp10b_check_clk_arb_support,
+	.get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
+	.get_arbiter_f_points = gp10b_get_arbiter_f_points,
+	.get_arbiter_clk_range = gp10b_get_arbiter_clk_range,
+	.get_arbiter_clk_default = gp10b_get_arbiter_clk_default,
+	.arbiter_clk_init = gp10b_init_clk_arbiter,
+	.clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
+	.clk_arb_cleanup = gp10b_clk_arb_cleanup,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_regops ga10b_ops_regops = {
+	.exec_regops = exec_regops_gk20a,
+	.get_global_whitelist_ranges = ga10b_get_global_whitelist_ranges,
+	.get_global_whitelist_ranges_count = ga10b_get_global_whitelist_ranges_count,
+	.get_context_whitelist_ranges = ga10b_get_context_whitelist_ranges,
+	.get_context_whitelist_ranges_count = ga10b_get_context_whitelist_ranges_count,
+	.get_runcontrol_whitelist = ga10b_get_runcontrol_whitelist,
+	.get_runcontrol_whitelist_count = ga10b_get_runcontrol_whitelist_count,
+	.get_hwpm_router_register_stride = ga10b_get_hwpm_router_register_stride,
+	.get_hwpm_perfmon_register_stride = ga10b_get_hwpm_perfmon_register_stride,
+	.get_hwpm_pma_channel_register_stride = ga10b_get_hwpm_pma_channel_register_stride,
+	.get_hwpm_pma_trigger_register_stride = ga10b_get_hwpm_pma_trigger_register_stride,
+	.get_smpc_register_stride = ga10b_get_smpc_register_stride,
+	.get_cau_register_stride = ga10b_get_cau_register_stride,
+	.get_hwpm_perfmon_register_offset_allowlist =
+		ga10b_get_hwpm_perfmon_register_offset_allowlist,
+	.get_hwpm_router_register_offset_allowlist =
+		ga10b_get_hwpm_router_register_offset_allowlist,
+	.get_hwpm_pma_channel_register_offset_allowlist =
+		ga10b_get_hwpm_pma_channel_register_offset_allowlist,
+	.get_hwpm_pma_trigger_register_offset_allowlist =
+		ga10b_get_hwpm_pma_trigger_register_offset_allowlist,
+	.get_smpc_register_offset_allowlist = ga10b_get_smpc_register_offset_allowlist,
+	.get_cau_register_offset_allowlist = ga10b_get_cau_register_offset_allowlist,
+	.get_hwpm_perfmon_register_ranges = ga10b_get_hwpm_perfmon_register_ranges,
+	.get_hwpm_router_register_ranges = ga10b_get_hwpm_router_register_ranges,
+	.get_hwpm_pma_channel_register_ranges = ga10b_get_hwpm_pma_channel_register_ranges,
+	.get_hwpm_pma_trigger_register_ranges = ga10b_get_hwpm_pma_trigger_register_ranges,
+	.get_smpc_register_ranges = ga10b_get_smpc_register_ranges,
+	.get_cau_register_ranges = ga10b_get_cau_register_ranges,
+	.get_hwpm_perfmux_register_ranges = ga10b_get_hwpm_perfmux_register_ranges,
+};
+#endif
+
+static const struct gops_mc ga10b_ops_mc = {
+	.get_chip_details = gm20b_get_chip_details,
+	.intr_mask = ga10b_intr_mask_top,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+	.intr_enable = NULL,
+#endif
+	.intr_nonstall_unit_config = ga10b_intr_host2soc_0_unit_config,
+	.intr_nonstall = ga10b_intr_host2soc_0,
+	.intr_nonstall_pause = ga10b_intr_host2soc_0_pause,
+	.intr_nonstall_resume = ga10b_intr_host2soc_0_resume,
+	.isr_nonstall = ga10b_intr_isr_host2soc_0,
+	.intr_stall_unit_config = ga10b_intr_stall_unit_config,
+	.intr_stall = ga10b_intr_stall,
+	.intr_stall_pause = ga10b_intr_stall_pause,
+	.intr_stall_resume = ga10b_intr_stall_resume,
+	.isr_stall = ga10b_intr_isr_stall,
+	.is_intr1_pending = NULL,
+	.enable_units = ga10b_mc_enable_units,
+	.enable_dev = ga10b_mc_enable_dev,
+	.enable_devtype = ga10b_mc_enable_devtype,
+#ifdef CONFIG_NVGPU_NON_FUSA
+	.elpg_enable = ga10b_mc_elpg_enable,
+	.log_pending_intrs = ga10b_intr_log_pending_intrs,
+#endif
+	.is_intr_hub_pending = NULL,
+	.is_stall_and_eng_intr_pending = ga10b_intr_is_stall_and_eng_intr_pending,
+#ifdef CONFIG_NVGPU_LS_PMU
+	.is_enabled = gm20b_mc_is_enabled,
+#endif
+	.fb_reset = NULL,
+	.ltc_isr = mc_tu104_ltc_isr,
+	.is_mmu_fault_pending = ga10b_intr_is_mmu_fault_pending,
+	.intr_get_unit_info = ga10b_mc_intr_get_unit_info,
+};
+
+static const struct gops_debug ga10b_ops_debug = {
+	.show_dump = gk20a_debug_show_dump,
+};
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_debugger ga10b_ops_debugger = {
+	.post_events = nvgpu_dbg_gpu_post_events,
+	.dbg_set_powergate = nvgpu_dbg_set_powergate,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_perf ga10b_ops_perf = {
+	.enable_membuf = ga10b_perf_enable_membuf,
+	.disable_membuf = ga10b_perf_disable_membuf,
+	.bind_mem_bytes_buffer_addr = ga10b_perf_bind_mem_bytes_buffer_addr,
+	.init_inst_block = ga10b_perf_init_inst_block,
+	.deinit_inst_block = ga10b_perf_deinit_inst_block,
+	.membuf_reset_streaming = ga10b_perf_membuf_reset_streaming,
+	.get_membuf_pending_bytes = ga10b_perf_get_membuf_pending_bytes,
+	.set_membuf_handled_bytes = ga10b_perf_set_membuf_handled_bytes,
+	.get_membuf_overflow_status = ga10b_perf_get_membuf_overflow_status,
+	.get_pmmsys_per_chiplet_offset = ga10b_perf_get_pmmsys_per_chiplet_offset,
+	.get_pmmgpc_per_chiplet_offset = ga10b_perf_get_pmmgpc_per_chiplet_offset,
+	.get_pmmfbp_per_chiplet_offset = ga10b_perf_get_pmmfbp_per_chiplet_offset,
+	.update_get_put = ga10b_perf_update_get_put,
+	.get_hwpm_sys_perfmon_regs = ga10b_perf_get_hwpm_sys_perfmon_regs,
+	.get_hwpm_gpc_perfmon_regs = ga10b_perf_get_hwpm_gpc_perfmon_regs,
+	.get_hwpm_fbp_perfmon_regs = ga10b_perf_get_hwpm_fbp_perfmon_regs,
+	.set_pmm_register = gv11b_perf_set_pmm_register,
+	.get_num_hwpm_perfmon = ga10b_perf_get_num_hwpm_perfmon,
+	.init_hwpm_pmm_register = ga10b_perf_init_hwpm_pmm_register,
+	.reset_hwpm_pmm_registers = gv11b_perf_reset_hwpm_pmm_registers,
+	.pma_stream_enable = ga10b_perf_pma_stream_enable,
+	.disable_all_perfmons = ga10b_perf_disable_all_perfmons,
+	.wait_for_idle_pmm_routers = gv11b_perf_wait_for_idle_pmm_routers,
+	.wait_for_idle_pma = ga10b_perf_wait_for_idle_pma,
+	.enable_hs_streaming = ga10b_perf_enable_hs_streaming,
+	.reset_hs_streaming_credits = ga10b_perf_reset_hs_streaming_credits,
+	.enable_pmasys_legacy_mode = ga10b_perf_enable_pmasys_legacy_mode,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_perfbuf ga10b_ops_perfbuf = {
+	.perfbuf_enable = nvgpu_perfbuf_enable_locked,
+	.perfbuf_disable = nvgpu_perfbuf_disable_locked,
+	.init_inst_block = nvgpu_perfbuf_init_inst_block,
+	.deinit_inst_block = nvgpu_perfbuf_deinit_inst_block,
+	.update_get_put = nvgpu_perfbuf_update_get_put,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_PROFILER
+static const struct gops_pm_reservation ga10b_ops_pm_reservation = {
+	.acquire = nvgpu_pm_reservation_acquire,
+	.release = nvgpu_pm_reservation_release,
+	.release_all_per_vmid = nvgpu_pm_reservation_release_all_per_vmid,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_PROFILER
+static const struct gops_profiler ga10b_ops_profiler = {
+	.bind_hwpm = nvgpu_profiler_bind_hwpm,
+	.unbind_hwpm = nvgpu_profiler_unbind_hwpm,
+	.bind_hwpm_streamout = nvgpu_profiler_bind_hwpm_streamout,
+	.unbind_hwpm_streamout = nvgpu_profiler_unbind_hwpm_streamout,
+	.bind_smpc = nvgpu_profiler_bind_smpc,
+	.unbind_smpc = nvgpu_profiler_unbind_smpc,
+};
+#endif
+
+static const struct gops_bus ga10b_ops_bus = {
+	.init_hw = ga10b_bus_init_hw,
+	.isr = ga10b_bus_isr,
+	.bar1_bind = gm20b_bus_bar1_bind,
+	.bar2_bind = gp10b_bus_bar2_bind,
+	.configure_debug_bus = NULL,
+#ifdef CONFIG_NVGPU_DGPU
+	.set_bar0_window = gk20a_bus_set_bar0_window,
+#endif
+};
+
+static const struct gops_ptimer ga10b_ops_ptimer = {
+	.isr = ga10b_ptimer_isr,
+	.read_ptimer = gk20a_read_ptimer,
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
+	.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.config_gr_tick_freq = gp10b_ptimer_config_gr_tick_freq,
+#endif
+#ifdef CONFIG_NVGPU_PROFILER
+	.get_timer_reg_offsets = gv11b_ptimer_get_timer_reg_offsets,
+#endif
+
+};
+
+#if defined(CONFIG_NVGPU_CYCLESTATS)
+static const struct gops_css ga10b_ops_css = {
+	.enable_snapshot = nvgpu_css_enable_snapshot,
+	.disable_snapshot = nvgpu_css_disable_snapshot,
+	.check_data_available = nvgpu_css_check_data_available,
+	.set_handled_snapshots = nvgpu_css_set_handled_snapshots,
+	.allocate_perfmon_ids = nvgpu_css_allocate_perfmon_ids,
+	.release_perfmon_ids = nvgpu_css_release_perfmon_ids,
+	.get_overflow_status = nvgpu_css_get_overflow_status,
+	.get_pending_snapshots = nvgpu_css_get_pending_snapshots,
+	.get_max_buffer_size = nvgpu_css_get_max_buffer_size,
+};
+#endif
+
+static const struct gops_falcon ga10b_ops_falcon = {
+	.falcon_sw_init = nvgpu_falcon_sw_init,
+	.falcon_sw_free = nvgpu_falcon_sw_free,
+	.reset = gk20a_falcon_reset,
+	.is_falcon_cpu_halted = ga10b_falcon_is_cpu_halted,
+	.is_falcon_idle = ga10b_is_falcon_idle,
+	.is_falcon_scrubbing_done = ga10b_is_falcon_scrubbing_done,
+	.get_mem_size = gk20a_falcon_get_mem_size,
+	.get_ports_count = gk20a_falcon_get_ports_count,
+	.copy_to_dmem = gk20a_falcon_copy_to_dmem,
+	.copy_to_imem = gk20a_falcon_copy_to_imem,
+	.dmemc_blk_mask = ga10b_falcon_dmemc_blk_mask,
+	.imemc_blk_field = ga10b_falcon_imemc_blk_field,
+	.bootstrap = ga10b_falcon_bootstrap,
+	.dump_brom_stats = ga10b_falcon_dump_brom_stats,
+	.get_brom_retcode = ga10b_falcon_get_brom_retcode,
+	.is_priv_lockdown = ga10b_falcon_is_priv_lockdown,
+	.check_brom_passed = ga10b_falcon_check_brom_passed,
+	.set_bcr = ga10b_falcon_set_bcr,
+	.brom_config = ga10b_falcon_brom_config,
+	.mailbox_read = gk20a_falcon_mailbox_read,
+	.mailbox_write = gk20a_falcon_mailbox_write,
+	.set_irq = gk20a_falcon_set_irq,
+#ifdef CONFIG_NVGPU_FALCON_DEBUG
+	.dump_falcon_stats = ga10b_falcon_dump_stats,
+#endif
+#ifdef CONFIG_NVGPU_FALCON_NON_FUSA
+	.clear_halt_interrupt_status = gk20a_falcon_clear_halt_interrupt_status,
+	.copy_from_dmem = gk20a_falcon_copy_from_dmem,
+	.copy_from_imem = gk20a_falcon_copy_from_imem,
+	.get_falcon_ctls = gk20a_falcon_get_ctls,
+#endif
+};
+
+static const struct gops_fbp ga10b_ops_fbp = {
+	.fbp_init_support = nvgpu_fbp_init_support,
+};
+
+static const struct gops_priv_ring ga10b_ops_priv_ring = {
+	.enable_priv_ring = gm20b_priv_ring_enable,
+	.isr = gp10b_priv_ring_isr,
+	.isr_handle_0 = ga10b_priv_ring_isr_handle_0,
+	.isr_handle_1 = ga10b_priv_ring_isr_handle_1,
+	.decode_error_code = ga10b_priv_ring_decode_error_code,
+	.set_ppriv_timeout_settings = NULL,
+	.enum_ltc = ga10b_priv_ring_enum_ltc,
+	.get_gpc_count = gm20b_priv_ring_get_gpc_count,
+	.get_fbp_count = gm20b_priv_ring_get_fbp_count,
+#ifdef CONFIG_NVGPU_MIG
+	.config_gr_remap_window = ga10b_priv_ring_config_gr_remap_window,
+	.config_gpc_rs_map = ga10b_priv_ring_config_gpc_rs_map,
+#endif
+#ifdef CONFIG_NVGPU_PROFILER
+	.read_pri_fence = ga10b_priv_ring_read_pri_fence,
+#endif
+};
+
+static const struct gops_fuse ga10b_ops_fuse = {
+	.check_priv_security = ga10b_fuse_check_priv_security,
+	.is_opt_ecc_enable = ga10b_fuse_is_opt_ecc_enable,
+	.is_opt_feature_override_disable = ga10b_fuse_is_opt_feature_override_disable,
+	.fuse_status_opt_fbio = ga10b_fuse_status_opt_fbio,
+	.fuse_status_opt_fbp = ga10b_fuse_status_opt_fbp,
+	/* Update hal for ROP in GPC - NVGPU-4668 */
+	.fuse_status_opt_rop_l2_fbp = ga10b_fuse_status_opt_rop_gpc,
+	.fuse_status_opt_tpc_gpc = ga10b_fuse_status_opt_tpc_gpc,
+	.fuse_ctrl_opt_tpc_gpc = ga10b_fuse_ctrl_opt_tpc_gpc,
+	.fuse_opt_sec_debug_en = ga10b_fuse_opt_sec_debug_en,
+	.fuse_opt_priv_sec_en = ga10b_fuse_opt_priv_sec_en,
+	.fuse_opt_sm_ttu_en = ga10b_fuse_opt_sm_ttu_en,
+	.opt_sec_source_isolation_en =
+			ga10b_fuse_opt_secure_source_isolation_en,
+	.read_vin_cal_fuse_rev = NULL,
+	.read_vin_cal_slope_intercept_fuse = NULL,
+	.read_vin_cal_gain_offset_fuse = NULL,
+	.read_gcplex_config_fuse = ga10b_fuse_read_gcplex_config_fuse,
+	.fuse_status_opt_gpc = ga10b_fuse_status_opt_gpc,
+	.write_feature_override_ecc = ga10b_fuse_write_feature_override_ecc,
+	.write_feature_override_ecc_1 = ga10b_fuse_write_feature_override_ecc_1,
+	.read_feature_override_ecc = ga10b_fuse_read_feature_override_ecc,
+	.read_per_device_identifier = ga10b_fuse_read_per_device_identifier,
+	.fetch_falcon_fuse_settings = ga10b_fetch_falcon_fuse_settings,
+};
+
+static const struct gops_top ga10b_ops_top = {
+	.device_info_parse_enum = NULL,
+	.device_info_parse_data = NULL,
+	.parse_next_device = ga10b_top_parse_next_dev,
+	.get_max_gpc_count = gm20b_top_get_max_gpc_count,
+	.get_max_tpc_per_gpc_count = gm20b_top_get_max_tpc_per_gpc_count,
+	.get_max_fbps_count = gm20b_top_get_max_fbps_count,
+	.get_max_ltc_per_fbp = gm20b_top_get_max_ltc_per_fbp,
+	.get_max_lts_per_ltc = gm20b_top_get_max_lts_per_ltc,
+	.get_num_ltcs = gm20b_top_get_num_ltcs,
+	.get_num_lce = gv11b_top_get_num_lce,
+};
+
+#ifdef CONFIG_NVGPU_TPC_POWERGATE
+static const struct gops_tpc ga10b_ops_tpc = {
+	.init_tpc_powergate = gv11b_tpc_powergate,
+	.tpc_gr_pg = gv11b_gr_pg_tpc,
+};
+#endif
+
+static const struct gops_grmgr ga10b_ops_grmgr = {
+#ifdef CONFIG_NVGPU_MIG
+	.init_gr_manager = ga10b_grmgr_init_gr_manager,
+	.remove_gr_manager = ga10b_grmgr_remove_gr_manager,
+	.get_max_sys_pipes = ga10b_grmgr_get_max_sys_pipes,
+	.get_mig_config_ptr = ga10b_grmgr_get_mig_config_ptr,
+	.get_allowed_swizzid_size = ga10b_grmgr_get_allowed_swizzid_size,
+	.get_gpc_instance_gpcgrp_id = ga10b_grmgr_get_gpc_instance_gpcgrp_id,
+	.get_mig_gpu_instance_config = ga10b_grmgr_get_mig_gpu_instance_config,
+	.get_gpcgrp_count = ga10b_grmgr_get_gpcgrp_count,
+#else
+	.init_gr_manager = nvgpu_init_gr_manager,
+#endif
+	.load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod,
+	.discover_gpc_ids = ga10b_grmgr_discover_gpc_ids,
+};
+
+int ga10b_init_hal(struct gk20a *g)
+{
+	struct gpu_ops *gops = &g->ops;
+
+	gops->acr = ga10b_ops_acr;
+	gops->func = ga10b_ops_func;
+#ifdef CONFIG_NVGPU_DGPU
+	gops->bios = ga10b_ops_bios;
+#endif /* CONFIG_NVGPU_DGPU */
+	gops->ecc = ga10b_ops_ecc;
+	gops->ltc = ga10b_ops_ltc;
+	gops->ltc.intr = ga10b_ops_ltc_intr;
+#ifdef CONFIG_NVGPU_COMPRESSION
+	gops->cbc = ga10b_ops_cbc;
+#endif
+	gops->ce = ga10b_ops_ce;
+	gops->gr = ga10b_ops_gr;
+	gops->gr.ecc = ga10b_ops_gr_ecc;
+	gops->gr.ctxsw_prog = ga10b_ops_gr_ctxsw_prog;
+	gops->gr.config = ga10b_ops_gr_config;
+#ifdef CONFIG_NVGPU_FECS_TRACE
+	gops->gr.fecs_trace = ga10b_ops_gr_fecs_trace;
+#endif /* CONFIG_NVGPU_FECS_TRACE */
+	gops->gr.setup = ga10b_ops_gr_setup;
+#ifdef CONFIG_NVGPU_GRAPHICS
+	gops->gr.zbc = ga10b_ops_gr_zbc;
+	gops->gr.zcull = ga10b_ops_gr_zcull;
+#endif /* CONFIG_NVGPU_GRAPHICS */
+#ifdef CONFIG_NVGPU_DEBUGGER
+	gops->gr.hwpm_map = ga10b_ops_gr_hwpm_map;
+#endif
+	gops->gr.init = ga10b_ops_gr_init;
+	gops->gr.intr = ga10b_ops_gr_intr;
+	gops->gr.falcon = ga10b_ops_gr_falcon;
+	gops->gpu_class = ga10b_ops_gpu_class;
+	gops->fb = ga10b_ops_fb;
+	gops->fb.ecc = ga10b_ops_fb_ecc;
+	gops->fb.intr = ga10b_ops_fb_intr;
+	gops->fb.vab = ga10b_ops_fb_vab;
+	gops->cg = ga10b_ops_cg;
+	gops->fifo = ga10b_ops_fifo;
+	gops->engine = ga10b_ops_engine;
+	gops->pbdma = ga10b_ops_pbdma;
+	gops->sync = ga10b_ops_sync;
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+	gops->sync.syncpt = ga10b_ops_sync_syncpt;
+#endif /* CONFIG_TEGRA_GK20A_NVHOST */
+#ifdef CONFIG_NVGPU_SW_SEMAPHORE
+	gops->sync.sema = ga10b_ops_sync_sema;
+#endif
+	gops->engine_status = ga10b_ops_engine_status;
+	gops->pbdma_status = ga10b_ops_pbdma_status;
+	gops->ramfc = ga10b_ops_ramfc;
+	gops->ramin = ga10b_ops_ramin;
+	gops->runlist = ga10b_ops_runlist;
+	gops->userd = ga10b_ops_userd;
+	gops->channel = ga10b_ops_channel;
+	gops->tsg = ga10b_ops_tsg;
+	gops->usermode = ga10b_ops_usermode;
+	gops->netlist = ga10b_ops_netlist;
+	gops->mm = ga10b_ops_mm;
+	gops->mm.mmu_fault = ga10b_ops_mm_mmu_fault;
+	gops->mm.cache = ga10b_ops_mm_cache;
+	gops->mm.gmmu = ga10b_ops_mm_gmmu;
+	gops->therm = ga10b_ops_therm;
+	gops->pmu = ga10b_ops_pmu;
+#ifdef CONFIG_NVGPU_CLK_ARB
+	gops->clk_arb = ga10b_ops_clk_arb;
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	gops->regops = ga10b_ops_regops;
+#endif
+	gops->mc = ga10b_ops_mc;
+	gops->debug = ga10b_ops_debug;
+#ifdef CONFIG_NVGPU_DEBUGGER
+	gops->debugger = ga10b_ops_debugger;
+	gops->perf = ga10b_ops_perf;
+	gops->perfbuf = ga10b_ops_perfbuf;
+#endif
+#ifdef CONFIG_NVGPU_PROFILER
+	gops->pm_reservation = ga10b_ops_pm_reservation;
+	gops->profiler = ga10b_ops_profiler;
+#endif
+	gops->bus = ga10b_ops_bus;
+	gops->ptimer = ga10b_ops_ptimer;
+#if defined(CONFIG_NVGPU_CYCLESTATS)
+	gops->css = ga10b_ops_css;
+#endif
+	gops->falcon = ga10b_ops_falcon;
+	gops->gsp = ga10b_ops_gsp;
+	gops->fbp = ga10b_ops_fbp;
+	gops->priv_ring = ga10b_ops_priv_ring;
+	gops->fuse = ga10b_ops_fuse;
+	gops->top = ga10b_ops_top;
+#ifdef CONFIG_NVGPU_TPC_POWERGATE
+	gops->tpc = ga10b_ops_tpc;
+#endif
+	gops->grmgr = ga10b_ops_grmgr;
+	gops->chip_init_gpu_characteristics = ga10b_init_gpu_characteristics;
+	gops->get_litter_value = ga10b_get_litter_value;
+	gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;
+
+	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)){
+		nvgpu_set_errata(g, NVGPU_ERRATA_2969956, true);
+	}
+	nvgpu_set_errata(g, NVGPU_ERRATA_200601972, true);
+	nvgpu_set_errata(g, NVGPU_ERRATA_200391931, true);
+	nvgpu_set_errata(g, NVGPU_ERRATA_200677649, true);
+	nvgpu_set_errata(g, NVGPU_ERRATA_3154076, true);
+	nvgpu_set_errata(g, NVGPU_ERRATA_3288192, true);
+	nvgpu_set_errata(g, NVGPU_ERRATA_SYNCPT_INVALID_ID_0, true);
+
+	nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
+
+	if ((gops->fuse.fuse_opt_sm_ttu_en(g) != 0U) ||
+		nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_SM_TTU, true);
+	}
+
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_ROP_IN_GPC, true);
+
+	/* Read fuses to check if gpu needs to boot in secure/non-secure mode */
+	if (gops->fuse.check_priv_security(g) != 0) {
+		/* Do not boot gpu */
+		return -EINVAL;
+	}
+
+	/* priv security dependent ops */
+	if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
+		gops->gr.falcon.load_ctxsw_ucode =
+			nvgpu_gr_falcon_load_secure_ctxsw_ucode;
+	} else {
+#ifdef CONFIG_NVGPU_LS_PMU
+		/* non-secure boot */
+		gops->pmu.setup_apertures =
+			gm20b_pmu_ns_setup_apertures;
+#endif
+	}
+
+#ifdef CONFIG_NVGPU_FECS_TRACE
+	nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
+	nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true);
+#endif
+
+#ifdef CONFIG_NVGPU_PROFILER
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PROFILER_V2_DEVICE, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PROFILER_V2_CONTEXT, false);
+#endif
+
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);
+#ifdef CONFIG_NVGPU_GRAPHICS
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true);
+#endif
+#ifdef CONFIG_NVGPU_GFXP
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true);
+#endif
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true);
+#ifdef CONFIG_NVGPU_PROFILER
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_VAB_ENABLED, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SMPC_GLOBAL_MODE, true);
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	nvgpu_set_enabled(g, NVGPU_L2_MAX_WAYS_EVICT_LAST_ENABLED, true);
+#endif
+
+	if (g->ops.pmu.is_pmu_supported(g)) {
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_RTOS_FBQ, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_SUPER_SURFACE, true);
+	}
+
+	/*
+	 * ga10b bypasses the IOMMU since it uses a special nvlink path to
+	 * memory.
+	 */
+	nvgpu_set_enabled(g, NVGPU_MM_BYPASSES_IOMMU, true);
+
+	/*
+	 * ecc scrub init can get called before
+	 * ga10b_init_gpu_characteristics call.
+	 */
+	g->ops.gr.ecc.detect(g);
+
+#ifndef CONFIG_NVGPU_BUILD_CONFIGURATION_IS_SAFETY
+	/*
+	 * To achieve permanent fault coverage, the CTAs launched by each kernel
+	 * in the mission and redundant contexts must execute on different
+	 * hardware resources. This feature proposes modifications in the
+	 * software to modify the virtual SM id to TPC mapping across the
+	 * mission and redundant contexts.
+	 *
+	 * The virtual SM identifier to TPC mapping is done by the nvgpu
+	 * when setting up the golden context. Once the table with this mapping
+	 * is initialized, it is used by all subsequent contexts that are
+	 * created. The proposal is for setting up the virtual SM identifier
+	 * to TPC mapping on a per-context basis and initializing this
+	 * virtual SM identifier to TPC mapping differently for the mission and
+	 * redundant contexts.
+	 *
+	 * The recommendation for the redundant setting is to offset the
+	 * assignment by 1 (TPC). This will ensure both GPC and TPC diversity.
+	 * The SM and Quadrant diversity will happen naturally.
+	 *
+	 * For kernels with few CTAs, the diversity is guaranteed to be 100%.
+	 * In case of completely random CTA allocation, e.g. large number of
+	 * CTAs in the waiting queue, the diversity is 1 - 1/#SM,
+	 * or 87.5% for GV11B.
+	 */
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SM_DIVERSITY, true);
+	g->max_sm_diversity_config_count =
+		NVGPU_MAX_SM_DIVERSITY_CONFIG_COUNT;
+#else
+	g->max_sm_diversity_config_count =
+		NVGPU_DEFAULT_SM_DIVERSITY_CONFIG_COUNT;
+#endif
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_COMPRESSION, true);
+
+	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_COMPRESSION)) {
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_POST_L2_COMPRESSION, true);
+	} else {
+		gops->cbc.init = NULL;
+		gops->cbc.ctrl = NULL;
+		gops->cbc.alloc_comptags = NULL;
+	}
+#endif
+
+#ifdef CONFIG_NVGPU_SIM
+	/* SIM specific overrides */
+	nvgpu_next_init_sim_support(g);
+	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)){
+		/* Disable fb mem_unlock */
+		gops->fb.mem_unlock = NULL;
+
+		/* Disable clock support */
+#ifdef CONFIG_NVGPU_CLK_ARB
+		gops->clk_arb.get_arbiter_clk_domains = NULL;
+#endif
+	}
+
+#endif
+	g->name = "ga10b";
+
+	return 0;
+}
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.h b/drivers/gpu/nvgpu/hal/init/hal_ga10b.h
new file mode 100644
index 000000000..7ccaa0ea6
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.h
@@ -0,0 +1,32 @@
+/*
+ * GA10B Tegra HAL interface
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_HAL_GA10B_H
+#define NVGPU_HAL_GA10B_H
+
+struct gk20a;
+
+int ga10b_init_hal(struct gk20a *gops);
+
+#endif /* NVGPU_HAL_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.c
new file mode 100644
index 000000000..d24bc7c79
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/class.h>
+#include <nvgpu/nvgpu_next_class.h>
+#include <nvgpu/nvgpu_next_litter.h>
+
+#include <nvgpu/hw/ga10b/hw_proj_ga10b.h>
+
+#include "hal_ga10b_litter.h"
+
+u32 ga10b_get_litter_value(struct gk20a *g, int value)
+{
+	u32 ret = 0;
+
+	switch (value) {
+	case GPU_LIT_NUM_GPCS:
+		ret = proj_scal_litter_num_gpcs_v();
+		break;
+	case GPU_LIT_NUM_PES_PER_GPC:
+		ret = proj_scal_litter_num_pes_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_ZCULL_BANKS:
+		ret = proj_scal_litter_num_zcull_banks_v();
+		break;
+	case GPU_LIT_NUM_TPC_PER_GPC:
+		ret = proj_scal_litter_num_tpc_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_SM_PER_TPC:
+		ret = proj_scal_litter_num_sm_per_tpc_v();
+		break;
+	case GPU_LIT_NUM_FBPS:
+		ret = proj_scal_litter_num_fbps_v();
+		break;
+	case GPU_LIT_GPC_BASE:
+		ret = proj_gpc_base_v();
+		break;
+	case GPU_LIT_GPC_STRIDE:
+		ret = proj_gpc_stride_v();
+		break;
+	case GPU_LIT_GPC_SHARED_BASE:
+		ret = proj_gpc_shared_base_v();
+		break;
+	case GPU_LIT_GPC_ADDR_WIDTH:
+		ret = proj_gpc_addr_width_v();
+		break;
+	case GPU_LIT_TPC_ADDR_WIDTH:
+		ret = proj_tpc_addr_width_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_BASE:
+		ret = proj_tpc_in_gpc_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_STRIDE:
+		ret = proj_tpc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
+		ret = proj_tpc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_BASE:
+		ret = proj_ppc_in_gpc_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
+		ret = proj_ppc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_STRIDE:
+		ret = proj_ppc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_ROP_BASE:
+		ret = proj_rop_base_v();
+		break;
+	case GPU_LIT_ROP_STRIDE:
+		ret = proj_rop_stride_v();
+		break;
+	case GPU_LIT_ROP_SHARED_BASE:
+		ret = proj_rop_shared_base_v();
+		break;
+	case GPU_LIT_HOST_NUM_ENGINES:
+		ret = proj_host_num_engines_v();
+		break;
+	case GPU_LIT_HOST_NUM_PBDMA:
+		ret = proj_host_num_pbdma_v();
+		break;
+	case GPU_LIT_LTC_STRIDE:
+		ret = proj_ltc_stride_v();
+		break;
+	case GPU_LIT_LTS_STRIDE:
+		ret = proj_lts_stride_v();
+		break;
+	case GPU_LIT_SM_PRI_STRIDE:
+		ret = proj_sm_stride_v();
+		break;
+	case GPU_LIT_SMPC_PRI_BASE:
+		ret = proj_smpc_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_SHARED_BASE:
+		ret = proj_smpc_shared_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_UNIQUE_BASE:
+		ret = proj_smpc_unique_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_STRIDE:
+		ret = proj_smpc_stride_v();
+		break;
+	case GPU_LIT_SM_UNIQUE_BASE:
+		ret = proj_sm_unique_base_v();
+		break;
+	case GPU_LIT_SM_SHARED_BASE:
+		ret = proj_sm_shared_base_v();
+		break;
+	case GPU_LIT_NUM_FBPAS:
+		ret = proj_scal_litter_num_fbpas_v();
+		break;
+	/* Hardcode FBPA values other than NUM_FBPAS to 0. */
+	case GPU_LIT_FBPA_STRIDE:
+	case GPU_LIT_FBPA_BASE:
+	case GPU_LIT_FBPA_SHARED_BASE:
+		ret = 0;
+		break;
+#ifdef CONFIG_NVGPU_GRAPHICS
+	case GPU_LIT_TWOD_CLASS:
+		ret = FERMI_TWOD_A;
+		break;
+	case GPU_LIT_THREED_CLASS:
+		ret = AMPERE_B;
+		break;
+#endif
+	case GPU_LIT_COMPUTE_CLASS:
+		ret = AMPERE_COMPUTE_B;
+		break;
+	case GPU_LIT_GPFIFO_CLASS:
+		ret = AMPERE_CHANNEL_GPFIFO_B;
+		break;
+	case GPU_LIT_I2M_CLASS:
+		ret = KEPLER_INLINE_TO_MEMORY_B;
+		break;
+	case GPU_LIT_DMA_COPY_CLASS:
+		ret = AMPERE_DMA_COPY_B;
+		break;
+	case GPU_LIT_GPC_PRIV_STRIDE:
+		ret = proj_gpc_priv_stride_v();
+		break;
+	case GPU_LIT_NUM_LTC_LTS_SETS:
+		ret = proj_scal_litter_num_ltc_lts_sets_v();
+		break;
+	case GPU_LIT_NUM_LTC_LTS_WAYS:
+		ret = proj_scal_litter_num_ltc_lts_ways_v();
+		break;
+	/* TODO check these hardcoded values for ga10b: JIRA NVGPU-4709 */
+	case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START:
+		ret = 2;
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START:
+		ret = 6;
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT:
+		ret = 4;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START:
+		ret = 1;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT:
+		ret = 2;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START:
+		ret = 3;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT:
+		ret = 2;
+		break;
+	case GPU_LIT_ROP_IN_GPC_BASE:
+		ret = proj_rop_in_gpc_base_v();
+		break;
+	case GPU_LIT_ROP_IN_GPC_SHARED_BASE:
+		ret = proj_rop_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_ROP_IN_GPC_PRI_SHARED_IDX:
+		ret = proj_rop_in_gpc_pri_shared_index_v();
+		break;
+	case GPU_LIT_ROP_IN_GPC_STRIDE:
+		ret = proj_rop_in_gpc_stride_v();
+		break;
+	default:
+		nvgpu_err(g, "Missing definition %d", value);
+		BUG();
+		break;
+	}
+
+	return ret;
+}
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.h b/drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.h
new file mode 100644
index 000000000..e1ff7aae1
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_HAL_GA10B_LITTER_H
+#define NVGPU_HAL_GA10B_LITTER_H
+
+u32 ga10b_get_litter_value(struct gk20a *g, int value);
+
+#endif /* NVGPU_HAL_GA10B_LITTER_H */
diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h
new file mode 100644
index 000000000..994700e14
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h
@@ -0,0 +1,37 @@
+/*
+ * GA10B L2 INTR
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_LTC_INTR_GA10B_H
+#define NVGPU_LTC_INTR_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void ga10b_ltc_intr_configure(struct gk20a *g);
+void ga10b_ltc_intr_isr(struct gk20a *g, u32 ltc);
+void ga10b_ltc_intr3_configure_extra(struct gk20a *g, u32 *reg);
+void ga10b_ltc_intr_handle_lts_intr3_extra(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value);
+
+#endif /* NVGPU_LTC_INTR_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
new file mode 100644
index 000000000..d3f48f832
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
@@ -0,0 +1,896 @@
+/*
+ * GA10B LTC INTR
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/static_analysis.h>
+#include <nvgpu/nvgpu_err.h>
+#include <nvgpu/utils.h>
+
+#include "hal/ltc/intr/ltc_intr_gv11b.h"
+#include "ltc_intr_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_ltc_ga10b.h>
+
+static void ga10b_ltc_intr1_configure(struct gk20a *g)
+{
+	u32 reg;
+
+	/* Enable ltc interrupts indicating illegal activity */
+	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr_r());
+
+	/*
+	 * IDLE_ERROR_CBC - flag if cbc gets a request while slcg clock is
+	 * disabled
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr_en_idle_error_cbc_m(),
+		ltc_ltcs_ltss_intr_en_idle_error_cbc_enabled_f());
+
+	/*
+	 * IDLE_ERROR_TSTG - flag if tstg gets a request while slcg clock is
+	 * disabled
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr_en_idle_error_tstg_m(),
+		ltc_ltcs_ltss_intr_en_idle_error_tstg_enabled_f());
+
+	/*
+	 * IDLE_ERROR_DSTG - flag if dstg gets a request while slcg clock is
+	 * disabled
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr_en_idle_error_dstg_m(),
+		ltc_ltcs_ltss_intr_en_idle_error_dstg_enabled_f());
+
+	/*
+	 * EVICTED_CB - indicates that a CB was demoted.
+	 * Normally this should not happen because the CBs should be flushed
+	 * during context switch and/or invalidated when no longer used.
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr_en_evicted_cb_m(),
+		ltc_ltcs_ltss_intr_en_evicted_cb_enabled_f());
+
+	/*
+	 * ILLEGAL_ATOMIC - unsupported atomic op and/or size received.
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr_en_illegal_atomic_m(),
+		ltc_ltcs_ltss_intr_en_illegal_atomic_enabled_f());
+
+	/*
+	 * BLKACTIVITY_ERR - internal error in power sensing block activity
+	 * monitor
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr_en_blkactivity_err_m(),
+		ltc_ltcs_ltss_intr_en_blkactivity_err_enabled_f());
+
+	/*
+	 * ILLEGAL_COMPSTAT_ACCESS - indicates that some memory access
+	 * read/wrote into the memory space reserved for the compression bit
+	 * carveout (Bug 942161)
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(),
+		ltc_ltcs_ltss_intr_en_illegal_compstat_access_enabled_f());
+
+	nvgpu_writel(g, ltc_ltcs_ltss_intr_r(), reg);
+
+	/* Read back register for write synchronization */
+	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr_r());
+
+	/* illegal_compstat interrupts can be also controlled through
+	 * debug_fs, so enable/disable based on g->ltc_intr_en_illegal_compstat
+	 * settings
+	 */
+	if (g->ops.ltc.intr.en_illegal_compstat != NULL) {
+		g->ops.ltc.intr.en_illegal_compstat(g,
+					g->ltc_intr_en_illegal_compstat);
+	}
+}
+
+/* LTC interrupts included in intr2 are not used for ga10b */
+static void ga10b_ltc_intr2_configure(struct gk20a *g)
+{
+	u32 reg;
+
+	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr2_r());
+
+	/*
+	 * TRDONE_INVALID_TDTAG - The tdtag for a transdone does not match any
+	 * valid L2 tag (subid/tdtag) for outstanding requests/transdones.
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr2_en_trdone_invalid_tdtag_m(),
+		ltc_ltcs_ltss_intr2_en_trdone_invalid_tdtag_enabled_f());
+
+	/*
+	 * UNEXPECTED_TRDONE - Transdone is unexpected response type. The tdtag
+	 * received matches a L2 tag (subid) of a non-cache coherent request
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr2_en_unexpected_trdone_m(),
+		ltc_ltcs_ltss_intr2_en_unexpected_trdone_enabled_f());
+
+	/*
+	 * RWC_UPG_UNEXPECTED_TRDONE_DATA - Transdone.D is an unexpected
+	 * response type for a read.rwc/upgrade. The tdtag received matches a
+	 * tag (tdtag) of an oustanding transdone for a cache coherent
+	 * read.rwc/upgrade
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_data_m(),
+		ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_data_enabled_f());
+
+	/*
+	 * RWC_UPG_UNEXPECTED_TRDONE_CANCEL - Transdone.cancel is an unexpected
+	 * response type for read.rwc/upgrade. The tdtag matches a tag (tdtag)
+	 * of a cache coherent read.rwc/upgrade
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_cancel_m(),
+		ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_cancel_enabled_f());
+
+	/*
+	 * PRBRS_INVALID_SUBID - The subid of a probe response does not match
+	 * any tag (subid/tdtag) from L2 that has an outstanding requests'
+	 * response
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr2_en_prbrs_invalid_subid_m(),
+		ltc_ltcs_ltss_intr2_en_prbrs_invalid_subid_enabled_f());
+
+	/*
+	 * UNEXPECTED_PRBRS - Probe Reponse is an unexpected response type. The
+	 * subid received matches a tag (subid/tdtag) of a non-probe
+	 * request/transdone from L2
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr2_en_unexpected_prbrs_m(),
+		ltc_ltcs_ltss_intr2_en_unexpected_prbrs_enabled_f());
+
+	/*
+	 * PRBIN_UNEXPECTED_PRBRS - PrbRsp.I.ND is expected given that Prb.I.ND
+	 * is outstanding for a given address (128B granularity)
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr2_en_prbin_unexpected_prbrs_m(),
+		ltc_ltcs_ltss_intr2_en_prbin_unexpected_prbrs_enabled_f());
+
+	/*
+	 * PRBIMO_UNEXPECTED_PRBRS - PrbRsp.I is expected given that there is an
+	 * outstanding probe.I.MO for a given address
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr2_en_prbimo_unexpected_prbrs_m(),
+		ltc_ltcs_ltss_intr2_en_prbimo_unexpected_prbrs_enabled_f());
+
+	/*
+	 * PRBX_MISSING_DATA - For PrbRsp.X should receive data beats (32B) for
+	 * all the probed sectors to a given address
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr2_en_prbx_missing_data_m(),
+		ltc_ltcs_ltss_intr2_en_prbx_missing_data_enabled_f());
+
+	/*
+	 * PRBX_UNEXPECTED_DATA - For PrbRsp.X should not receive data beats
+	 * (32B) for non probed sectors to a given address
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr2_en_prbx_unexpected_data_m(),
+		ltc_ltcs_ltss_intr2_en_prbx_unexpected_data_enabled_f());
+
+	/*
+	 * PRBRS_UNEXPECTED_PA7 - pa7 in probe response (based on mask) for a
+	 * given subid should correspond to pa7 of the probe
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr2_en_prbrs_unexpected_pa7_m(),
+		ltc_ltcs_ltss_intr2_en_prbrs_unexpected_pa7_enabled_f());
+
+	/*
+	 * TRDONE_UNEXPECTED_PA7 - pa7 in downgrade trasndone (based on mask)
+	 * for a given subid should correspond to pa7 of the downgrade
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr2_en_trdone_unexpected_pa7_m(),
+		ltc_ltcs_ltss_intr2_en_trdone_unexpected_pa7_enabled_f());
+
+	/*
+	 * SYSFILL_BYPASS_INVALID_SUBID - The subid for a sysmem fill response
+	 * does not match any valid L2 tag (subid/tdtag) for outstanding
+	 * requests/transdones.
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr2_en_sysfill_bypass_invalid_subid_m(),
+		ltc_ltcs_ltss_intr2_en_sysfill_bypass_invalid_subid_enabled_f());
+
+	/*
+	 * UNEXPECTED_SYSFILL_BYPASS - Sysmem fill/data response is an
+	 * unexpected response type. The subid matches an L2 tag (subid) of a
+	 * non-read/non-atomic L2 reflected request
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr2_en_unexpected_sysfill_bypass_m(),
+		ltc_ltcs_ltss_intr2_en_unexpected_sysfill_bypass_enabled_f());
+
+	/*
+	 * CHECKEDIN_UNEXPECTED_PRBRS - PrbRsp.I.D or PrbRsp.E or PrbRsp.M
+	 * should not be received to a checked-in line (128B), i.e. after a
+	 * dgd.transdone.I in a probe/downgrade race
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr2_en_checkedin_unexpected_prbrs_m(),
+		ltc_ltcs_ltss_intr2_en_checkedin_unexpected_prbrs_enabled_f());
+
+	/*
+	 * CHECKEDIN_UNEXPECTED_TRDONE - Downgrade transdone (128B granularity)
+	 * should be cancelled if the transdone is received when the line is
+	 * checked-in, i.e. either a dgd to checked-in line or dgd losing in a
+	 * probe/downgrade race
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr2_en_checkedin_unexpected_trdone_m(),
+		ltc_ltcs_ltss_intr2_en_checkedin_unexpected_trdone_enabled_f());
+
+	nvgpu_writel(g, ltc_ltcs_ltss_intr2_r(), reg);
+
+	/* Read back register for write synchronization */
+	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr2_r());
+}
+
+void ga10b_ltc_intr3_configure_extra(struct gk20a *g, u32 *reg)
+{
+	/*
+	 * DTM_KIND_INVALID - If the kind of a comp stat req read or packed
+	 * read is invalid or pitch, the inter3_dtm_kind_invalid interrupt will
+	 * assert if enabled.
+	 */
+	*reg = set_field(*reg, ltc_ltcs_ltss_intr3_en_dtm_kind_invalid_m(),
+		ltc_ltcs_ltss_intr3_en_dtm_kind_invalid_enabled_f());
+
+	/*
+	 * DTM_COMPTAG_INVALID - If the comptag_vld of a comp stat req read or
+	 * packed read is invalid, the inter3_dtm_comptag_invalid interrupt will
+	 * assert if enabled.
+	 */
+	*reg = set_field(*reg, ltc_ltcs_ltss_intr3_en_dtm_comptag_invalid_m(),
+		ltc_ltcs_ltss_intr3_en_dtm_comptag_invalid_enabled_f());
+
+	/*
+	 * CDCMP_IP_ERROR is the OR of these outputs from the decomprIP:
+	 * - err_2x_reduced_partial_fetch_mask  -- error condition in IP with
+	 *   64B input interface where it receives a reduced 2x request with
+	 *   partial fetch_mask
+	 * - err_exp_eop_no_match_act_eop  -- error condition where actual EOP
+	 *   doesnt match the expected EOP
+	 * - err_illegal_catom_encoded_comp_info -- error indication that the
+	 *   3bit encoded comp_info is illegal
+	 * - err_sdc_has_more_sv_bits_set --  error indicating malformed SDC
+	 *   packet
+	 * - err_unsupported_comp_stat -- error condition indicating unsupported
+	 *   comp_stat condition
+	 * - err_vdc_packing -- error in vdc packing. In ga100 we merged this
+	 *   with decompr_64B_fsm_state
+	 */
+	*reg = set_field(*reg, ltc_ltcs_ltss_intr3_en_cdcmp_ip_error_m(),
+		ltc_ltcs_ltss_intr3_en_cdcmp_ip_error_enabled_f());
+}
+
+static void ga10b_ltc_intr3_configure(struct gk20a *g)
+{
+	u32 reg;
+
+	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr3_r());
+
+	/*
+	 * CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT - RWC/Upgrade to the same 256B
+	 * L2 slice address should have the same nvlink port#.
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr3_en_checkedout_rwc_upg_unexpected_nvport_m(),
+		ltc_ltcs_ltss_intr3_en_checkedout_rwc_upg_unexpected_nvport_enabled_f());
+
+	/*
+	 * CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT - TrDone to the same 256B L2
+	 * slice address should have the same nvlink port#.
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr3_en_checkedout_trdone_unexpected_nvport_m(),
+		ltc_ltcs_ltss_intr3_en_checkedout_trdone_unexpected_nvport_enabled_f());
+
+	/*
+	 * CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT - PrbRs to the same 256B L2 slice
+	 * address should have the same nvlink port#.
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr3_en_checkedout_prbrs_unexpected_nvport_m(),
+		ltc_ltcs_ltss_intr3_en_checkedout_prbrs_unexpected_nvport_enabled_f());
+
+	/*
+	 * CHECKEDOUT_NINB_NCNP_REQ - NCNP request on NISO-NB received to a 128B
+	 * line that is checked out
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr3_en_checkedout_ninb_ncnp_req_m(),
+		ltc_ltcs_ltss_intr3_en_checkedout_ninb_ncnp_req_enabled_f());
+
+	/*
+	 * CHECKEDOUT_CREQ_NCNP_REQ - NCNP request on CREQ received to a 128B
+	 * line that is checked out
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr3_en_checkedout_creq_ncnp_req_m(),
+		ltc_ltcs_ltss_intr3_en_checkedout_creq_ncnp_req_enabled_f());
+
+	/*
+	 * RMWRS_INVALID_SUBID - The subid of a RMW response does not match any
+	 * outstanding request's tag (subid) from L2.
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr3_en_rmwrs_invalid_subid_m(),
+		ltc_ltcs_ltss_intr3_en_rmwrs_invalid_subid_enabled_f());
+
+	/*
+	 * UNEXPECTED_RMWRS - RMW Reponse is an unexpected response type. The
+	 * subid received matches a tag (subid/tdtag) of a non-RMW request.
+	 */
+	reg = set_field(reg, ltc_ltcs_ltss_intr3_en_unexpected_rmwrs_m(),
+		ltc_ltcs_ltss_intr3_en_unexpected_rmwrs_enabled_f());
+
+	/*
+	 * ILLEGAL_ACCESS_KIND_TYPE1 - A read request kind does not match CBC
+	 * stored kind type1
+	 * 1.  Access kind is not color and stored kind is color with
+	 * compression status non-zero
+	 * 2.  Access kind is color and stored kind is not color and the request
+	 * is from CROP
+	 * 3.  Access kind is z and stored kind is different z
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr3_en_illegal_access_kind_type1_m(),
+		ltc_ltcs_ltss_intr3_en_illegal_access_kind_type1_enabled_f());
+
+	/*
+	 * ILLEGAL_ACCESS_KIND_TYPE2 - A read request kind does not match the
+	 * CBC stored kind type2
+	 * 1.  Access kind is not color and stored kind is color with
+	 * compression status zero
+	 * 2.  Access kind is color and stored kind is not color and the request
+	 * is from XBAR
+	 */
+	reg = set_field(reg,
+		ltc_ltcs_ltss_intr3_en_illegal_access_kind_type2_m(),
+		ltc_ltcs_ltss_intr3_en_illegal_access_kind_type2_enabled_f());
+
+	if (g->ops.ltc.intr.ltc_intr3_configure_extra != NULL) {
+		g->ops.ltc.intr.ltc_intr3_configure_extra(g, &reg);
+	}
+
+	nvgpu_writel(g, ltc_ltcs_ltss_intr3_r(), reg);
+
+	/* Read back register for write synchronization */
+	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr3_r());
+}
+
+void ga10b_ltc_intr_configure(struct gk20a *g)
+{
+	ga10b_ltc_intr1_configure(g);
+	ga10b_ltc_intr2_configure(g);
+	ga10b_ltc_intr3_configure(g);
+}
+
+static void ga10b_ltc_intr3_ecc_interrupts(struct gk20a *g, u32 ltc, u32 slice,
+				u32 offset, u32 ltc_intr3)
+{
+	u32 ecc_status, ecc_addr, dstg_ecc_addr, corrected_cnt, uncorrected_cnt;
+	u32 corrected_delta, uncorrected_delta;
+	u32 corrected_overflow, uncorrected_overflow;
+
+	/* Detect and handle ECC PARITY errors */
+	if ((ltc_intr3 &
+		(ltc_ltcs_ltss_intr3_ecc_uncorrected_m() |
+		 ltc_ltcs_ltss_intr3_ecc_corrected_m())) != 0U) {
+
+		ecc_status = nvgpu_readl(g, nvgpu_safe_add_u32(
+				ltc_ltc0_lts0_l2_cache_ecc_status_r(), offset));
+		ecc_addr = nvgpu_readl(g, nvgpu_safe_add_u32(
+			ltc_ltc0_lts0_l2_cache_ecc_address_r(), offset));
+		dstg_ecc_addr = nvgpu_readl(g, nvgpu_safe_add_u32(
+				ltc_ltc0_lts0_dstg_ecc_address_r(), offset));
+		corrected_cnt = nvgpu_readl(g, nvgpu_safe_add_u32(
+			ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(),
+			offset));
+		uncorrected_cnt = nvgpu_readl(g, nvgpu_safe_add_u32(
+			ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(),
+			offset));
+
+		corrected_delta =
+			ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(
+					corrected_cnt);
+		uncorrected_delta =
+			ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(uncorrected_cnt);
+		corrected_overflow = ecc_status &
+			ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m();
+
+		uncorrected_overflow = ecc_status &
+			ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m();
+
+		gv11b_ltc_intr_init_counters(g,
+			corrected_delta, corrected_overflow,
+			uncorrected_delta, uncorrected_overflow, offset);
+
+		nvgpu_writel(g, nvgpu_safe_add_u32(
+				ltc_ltc0_lts0_l2_cache_ecc_status_r(), offset),
+			ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f());
+
+		/* update counters per slice */
+		if (corrected_overflow != 0U) {
+			corrected_delta += BIT32(
+				ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s());
+		}
+		if (uncorrected_overflow != 0U) {
+			uncorrected_delta += BIT32(
+				ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s());
+		}
+
+		g->ecc.ltc.ecc_sec_count[ltc][slice].counter =
+				nvgpu_safe_add_u32(
+				g->ecc.ltc.ecc_sec_count[ltc][slice].counter,
+					corrected_delta);
+		g->ecc.ltc.ecc_ded_count[ltc][slice].counter =
+				nvgpu_safe_add_u32(
+				g->ecc.ltc.ecc_ded_count[ltc][slice].counter,
+					uncorrected_delta);
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d cache ecc interrupt intr: 0x%x",
+			ltc, slice, ltc_intr3);
+
+		/* This check has been added to ensure that the slice id is less
+		 * than 8-bits and hence, it can be packed as part of LSB 8-bits
+		 * along with the LTC id while reporting LTC related ECC errors.
+		 */
+		if (slice > U8_MAX) {
+			nvgpu_log(g, gpu_dbg_intr, "Invalid slice id=%d",
+					slice);
+			slice = slice & 0xFFU;
+		}
+
+		gv11b_ltc_intr_handle_rstg_ecc_interrupts(g, ltc, slice,
+						ecc_status, ecc_addr);
+
+		gv11b_ltc_intr_handle_tstg_ecc_interrupts(g, ltc, slice,
+						ecc_status, ecc_addr);
+
+		gv11b_ltc_intr_handle_dstg_ecc_interrupts(g, ltc, slice,
+						ecc_status, dstg_ecc_addr,
+								ecc_addr);
+
+		if ((corrected_overflow != 0U) ||
+				(uncorrected_overflow != 0U)) {
+			nvgpu_info(g, "ecc counter overflow!");
+		}
+
+		nvgpu_log(g, gpu_dbg_intr, "ecc error address: 0x%x", ecc_addr);
+	}
+}
+
+void ga10b_ltc_intr_handle_lts_intr3_extra(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value)
+{
+	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+	u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+
+	u32 offset = nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc_stride, ltc),
+					nvgpu_safe_mult_u32(lts_stride, slice));
+	u32 ltc_intr3 = nvgpu_readl(g, nvgpu_safe_add_u32(
+					ltc_ltc0_lts0_intr3_r(), offset));
+
+	if (ltc_intr3 == 0U) {
+		return;
+	}
+
+	if (ltc_intr3 & ltc_ltcs_ltss_intr3_dtm_kind_invalid_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d dtm_kind_invalid interrupt",
+			ltc, slice);
+		*reg_value = set_field(*reg_value,
+			ltc_ltcs_ltss_intr3_dtm_kind_invalid_m(),
+			ltc_ltcs_ltss_intr3_dtm_kind_invalid_reset_f());
+	}
+
+	if (ltc_intr3 & ltc_ltcs_ltss_intr3_dtm_comptag_invalid_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d dtm_comptag_invalid interrupt",
+			ltc, slice);
+		*reg_value = set_field(*reg_value,
+			ltc_ltcs_ltss_intr3_dtm_comptag_invalid_m(),
+			ltc_ltcs_ltss_intr3_dtm_comptag_invalid_reset_f());
+	}
+
+	if (ltc_intr3 & ltc_ltcs_ltss_intr3_cdcmp_ip_error_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d cdcmp_ip_error interrupt",
+			ltc, slice);
+		*reg_value = set_field(*reg_value,
+			ltc_ltcs_ltss_intr3_cdcmp_ip_error_m(),
+			ltc_ltcs_ltss_intr3_cdcmp_ip_error_reset_f());
+	}
+}
+
+static void ga10b_ltc_intr_handle_lts_intr3(struct gk20a *g, u32 ltc, u32 slice)
+{
+	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+	u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+
+	u32 offset = nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc_stride, ltc),
+					nvgpu_safe_mult_u32(lts_stride, slice));
+	u32 ltc_intr3 = nvgpu_readl(g, nvgpu_safe_add_u32(
+					ltc_ltc0_lts0_intr3_r(), offset));
+	u32 reg_value = ltc_intr3;
+
+	if (ltc_intr3 == 0U) {
+		return;
+	}
+
+	ga10b_ltc_intr3_ecc_interrupts(g, ltc, slice, offset, ltc_intr3);
+
+	if (ltc_intr3 &
+		ltc_ltcs_ltss_intr3_checkedout_rwc_upg_unexpected_nvport_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d checkedout_rwc_upg_unexpected_nvport interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr3_checkedout_rwc_upg_unexpected_nvport_m(),
+			ltc_ltcs_ltss_intr3_checkedout_rwc_upg_unexpected_nvport_reset_f());
+	}
+
+	if (ltc_intr3 & ltc_ltcs_ltss_intr3_checkedout_trdone_unexpected_nvport_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d checkedout_trdone_unexpected_nvport interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr3_checkedout_trdone_unexpected_nvport_m(),
+			ltc_ltcs_ltss_intr3_checkedout_trdone_unexpected_nvport_reset_f());
+	}
+
+	if (ltc_intr3 & ltc_ltcs_ltss_intr3_checkedout_prbrs_unexpected_nvport_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d checkedout_prbrs_unexpected_nvport interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr3_checkedout_prbrs_unexpected_nvport_m(),
+			ltc_ltcs_ltss_intr3_checkedout_prbrs_unexpected_nvport_reset_f());
+	}
+
+	if (ltc_intr3 & ltc_ltcs_ltss_intr3_checkedout_ninb_ncnp_req_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d checkedout_ninb_ncnp_req interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr3_checkedout_ninb_ncnp_req_m(),
+			ltc_ltcs_ltss_intr3_checkedout_ninb_ncnp_req_reset_f());
+	}
+
+	if (ltc_intr3 & ltc_ltcs_ltss_intr3_checkedout_creq_ncnp_req_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d checkedout_creq_ncnp_req interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr3_checkedout_creq_ncnp_req_m(),
+			ltc_ltcs_ltss_intr3_checkedout_creq_ncnp_req_reset_f());
+	}
+
+	if (ltc_intr3 & ltc_ltcs_ltss_intr3_rmwrs_invalid_subid_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d rmwrs_invalid_subid interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr3_rmwrs_invalid_subid_m(),
+			ltc_ltcs_ltss_intr3_rmwrs_invalid_subid_reset_f());
+	}
+
+	if (ltc_intr3 & ltc_ltcs_ltss_intr3_unexpected_rmwrs_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d unexpected_rmwrs interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr3_unexpected_rmwrs_m(),
+			ltc_ltcs_ltss_intr3_unexpected_rmwrs_reset_f());
+	}
+
+	if (ltc_intr3 & ltc_ltcs_ltss_intr3_illegal_access_kind_type1_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d illegal_access_kind_type1 interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr3_illegal_access_kind_type1_m(),
+			ltc_ltcs_ltss_intr3_illegal_access_kind_type1_reset_f());
+	}
+
+	if (ltc_intr3 & ltc_ltcs_ltss_intr3_illegal_access_kind_type2_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d illegal_access_kind_type2 interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr3_illegal_access_kind_type2_m(),
+			ltc_ltcs_ltss_intr3_illegal_access_kind_type2_reset_f());
+	}
+
+	if (g->ops.ltc.intr.isr_extra != NULL) {
+		g->ops.ltc.intr.isr_extra(g, ltc, slice, &reg_value);
+	}
+
+	/* Reset interrupts */
+	nvgpu_writel(g, nvgpu_safe_add_u32( ltc_ltc0_lts0_intr3_r(), offset),
+			reg_value);
+}
+
+static void ga10b_ltc_intr_handle_lts_intr2(struct gk20a *g, u32 ltc, u32 slice)
+{
+	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+	u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+
+	u32 offset = nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc_stride, ltc),
+					nvgpu_safe_mult_u32(lts_stride, slice));
+	u32 ltc_intr2 = nvgpu_readl(g, nvgpu_safe_add_u32(
+					ltc_ltc0_lts0_intr2_r(), offset));
+	u32 reg_value = ltc_intr2;
+
+	if (ltc_intr2 == 0U) {
+		return;
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_trdone_invalid_tdtag_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d trdone_invalid_tdtag interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_trdone_invalid_tdtag_m(),
+			ltc_ltcs_ltss_intr2_trdone_invalid_tdtag_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_unexpected_trdone_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d unexpected_trdone interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_unexpected_trdone_m(),
+			ltc_ltcs_ltss_intr2_unexpected_trdone_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_data_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d rwc_upg_unexpected_trdone_data interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_data_m(),
+			ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_data_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_cancel_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d rwc_upg_unexpected_trdone_cancel interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_cancel_m(),
+			ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_cancel_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_prbrs_invalid_subid_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d prbrs_invalid_subid interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_prbrs_invalid_subid_m(),
+			ltc_ltcs_ltss_intr2_prbrs_invalid_subid_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_unexpected_prbrs_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d unexpected_prbrs interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_unexpected_prbrs_m(),
+			ltc_ltcs_ltss_intr2_unexpected_prbrs_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_prbin_unexpected_prbrs_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d prbin_unexpected_prbrs interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_prbin_unexpected_prbrs_m(),
+			ltc_ltcs_ltss_intr2_prbin_unexpected_prbrs_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_prbimo_unexpected_prbrs_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d prbimo_unexpected_prbrs interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_prbimo_unexpected_prbrs_m(),
+			ltc_ltcs_ltss_intr2_prbimo_unexpected_prbrs_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_prbx_missing_data_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d prbx_missing_data interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_prbx_missing_data_m(),
+			ltc_ltcs_ltss_intr2_prbx_missing_data_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_prbx_unexpected_data_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d prbx_unexpected_data interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_prbx_unexpected_data_m(),
+			ltc_ltcs_ltss_intr2_prbx_unexpected_data_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_prbrs_unexpected_pa7_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d prbrs_unexpected_pa7 interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_prbrs_unexpected_pa7_m(),
+			ltc_ltcs_ltss_intr2_prbrs_unexpected_pa7_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_trdone_unexpected_pa7_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d trdone_unexpected_pa7 interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_trdone_unexpected_pa7_m(),
+			ltc_ltcs_ltss_intr2_trdone_unexpected_pa7_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_sysfill_bypass_invalid_subid_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d sysfill_bypass_invalid_subid interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_sysfill_bypass_invalid_subid_m(),
+			ltc_ltcs_ltss_intr2_sysfill_bypass_invalid_subid_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_unexpected_sysfill_bypass_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d unexpected_sysfill_bypass interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_unexpected_sysfill_bypass_m(),
+			ltc_ltcs_ltss_intr2_unexpected_sysfill_bypass_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_checkedin_unexpected_prbrs_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d checkedin_unexpected_prbrs interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_checkedin_unexpected_prbrs_m(),
+			ltc_ltcs_ltss_intr2_checkedin_unexpected_prbrs_reset_f());
+	}
+
+	if (ltc_intr2 & ltc_ltcs_ltss_intr2_checkedin_unexpected_trdone_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d checkedin_unexpected_trdone interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr2_checkedin_unexpected_trdone_m(),
+			ltc_ltcs_ltss_intr2_checkedin_unexpected_trdone_reset_f());
+	}
+
+	/* Reset interrupts */
+	nvgpu_writel(g, nvgpu_safe_add_u32( ltc_ltc0_lts0_intr2_r(), offset),
+			reg_value);
+}
+
+static void ga10b_ltc_intr_handle_lts_intr(struct gk20a *g, u32 ltc, u32 slice)
+{
+	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+	u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+
+	u32 offset = nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc_stride, ltc),
+					nvgpu_safe_mult_u32(lts_stride, slice));
+	u32 ltc_intr = nvgpu_readl(g, nvgpu_safe_add_u32(
+					ltc_ltc0_lts0_intr_r(), offset));
+	u32 reg_value = ltc_intr;
+
+	if (ltc_intr == 0U) {
+		return;
+	}
+
+	if (ltc_intr & ltc_ltcs_ltss_intr_idle_error_cbc_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d idle_error_cbc interrupt", ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr_idle_error_cbc_m(),
+			ltc_ltcs_ltss_intr_idle_error_cbc_reset_f());
+	}
+
+	if (ltc_intr & ltc_ltcs_ltss_intr_idle_error_tstg_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d idle_error_tstg interrupt", ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr_idle_error_tstg_m(),
+			ltc_ltcs_ltss_intr_idle_error_tstg_reset_f());
+	}
+
+	if (ltc_intr & ltc_ltcs_ltss_intr_idle_error_dstg_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d idle_error_dstg interrupt", ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr_idle_error_dstg_m(),
+			ltc_ltcs_ltss_intr_idle_error_dstg_reset_f());
+	}
+
+	if (ltc_intr & ltc_ltcs_ltss_intr_evicted_cb_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d evicted_cb interrupt", ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr_evicted_cb_m(),
+			ltc_ltcs_ltss_intr_evicted_cb_reset_f());
+	}
+
+	if ((ltc_intr & ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f()) &&
+		(ltc_intr & ltc_ltcs_ltss_intr_illegal_compstat_m())) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d illegal_compstat interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr_illegal_compstat_m(),
+			ltc_ltcs_ltss_intr_illegal_compstat_reset_f());
+	}
+
+	if (ltc_intr & ltc_ltcs_ltss_intr_illegal_atomic_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d illegal_atomic interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr_illegal_atomic_m(),
+			ltc_ltcs_ltss_intr_illegal_atomic_reset_f());
+	}
+
+	if (ltc_intr & ltc_ltcs_ltss_intr_blkactivity_err_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d blkactivity_err interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr_blkactivity_err_m(),
+			ltc_ltcs_ltss_intr_blkactivity_err_reset_f());
+	}
+
+	if (ltc_intr & ltc_ltcs_ltss_intr_illegal_compstat_access_m()) {
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d illegal_compstat_access interrupt",
+			ltc, slice);
+		reg_value = set_field(reg_value,
+			ltc_ltcs_ltss_intr_illegal_compstat_access_m(),
+			ltc_ltcs_ltss_intr_illegal_compstat_access_reset_f());
+	}
+
+	/* Reset interrupts */
+	nvgpu_writel(g, nvgpu_safe_add_u32( ltc_ltc0_lts0_intr_r(), offset),
+			reg_value);
+}
+
+void ga10b_ltc_intr_isr(struct gk20a *g, u32 ltc)
+{
+	u32 slice;
+
+	for (slice = 0U; slice < g->ltc->slices_per_ltc; slice++) {
+		ga10b_ltc_intr_handle_lts_intr(g, ltc, slice);
+		ga10b_ltc_intr_handle_lts_intr2(g, ltc, slice);
+		ga10b_ltc_intr_handle_lts_intr3(g, ltc, slice);
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.c
new file mode 100644
index 000000000..602001541
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gr/zbc.h>
+
+#include "ltc_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_ltc_ga10b.h>
+
+void ga10b_ltc_set_zbc_stencil_entry(struct gk20a *g, u32 stencil_depth,
+					u32 index)
+{
+	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+		ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
+
+	nvgpu_writel(g,
+ 		ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(), stencil_depth);
+}
+
+void ga10b_ltc_set_zbc_color_entry(struct gk20a *g, u32 *color_l2, u32 index)
+{
+	u32 i;
+
+	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+		ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
+
+	for (i = 0; i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v();
+									i++) {
+		nvgpu_writel(g,
+			ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
+			color_l2[i]);
+	}
+}
+
+/*
+ * Sets the ZBC depth for the passed index.
+ */
+void ga10b_ltc_set_zbc_depth_entry(struct gk20a *g, u32 depth_val, u32 index)
+{
+	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+		ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
+
+	nvgpu_writel(g,
+		ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), depth_val);
+}
+
+u32 ga10b_ltc_pri_shared_addr(struct gk20a *g, u32 addr)
+{
+	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+	u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+	u32 ltc_shared_base = ltc_ltcs_ltss_v();
+	u32 ltc_addr_mask = nvgpu_safe_sub_u32(ltc_stride, 1);
+	u32 lts_addr_mask = nvgpu_safe_sub_u32(lts_stride, 1);
+	u32 ltc_addr = addr & ltc_addr_mask;
+	u32 lts_addr = ltc_addr & lts_addr_mask;
+
+	return ltc_shared_base + lts_addr;
+}
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h
new file mode 100644
index 000000000..c4515cb99
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef LTC_GA10B_H
+#define LTC_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+u32 ga10b_ltc_zbc_table_size(struct gk20a *g);
+void ga10b_ltc_set_zbc_stencil_entry(struct gk20a *g, u32 stencil_depth,
+			u32 index);
+void ga10b_ltc_set_zbc_color_entry(struct gk20a *g, u32 *color_l2, u32 index);
+void ga10b_ltc_set_zbc_depth_entry(struct gk20a *g, u32 depth_val, u32 index);
+#endif
+
+void ga10b_ltc_init_fs_state(struct gk20a *g);
+void ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g);
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+u32 ga10b_ltc_pri_shared_addr(struct gk20a *g, u32 addr);
+int ga10b_set_l2_max_ways_evict_last(struct gk20a *g, struct nvgpu_tsg *tsg,
+		u32 num_ways);
+int ga10b_get_l2_max_ways_evict_last(struct gk20a *g, struct nvgpu_tsg *tsg,
+		u32 *num_ways);
+#endif
+
+#endif /* LTC_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c
new file mode 100644
index 000000000..b6207dadd
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/regops.h>
+#include <nvgpu/errata.h>
+
+#include "hal/gr/gr/gr_gk20a.h"
+#include "ltc_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_ltc_ga10b.h>
+
+/* Minimum value of cacheline_size */
+#define CACHELINE_SIZE_BASE		512U
+
+void ga10b_ltc_init_fs_state(struct gk20a *g)
+{
+	u32 reg;
+
+	g->ltc->max_ltc_count = g->ops.top.get_num_ltcs(g);
+	g->ltc->ltc_count = g->ops.priv_ring.enum_ltc(g);
+	nvgpu_log_info(g, "%u ltcs present out of %u total supported ltcs",
+		g->ltc->ltc_count, g->ltc->max_ltc_count);
+
+	reg = nvgpu_readl(g, ltc_ltcs_ltss_cbc_param2_r());
+	g->ltc->slices_per_ltc =
+		ltc_ltcs_ltss_cbc_param2_slices_per_ltc_v(reg);
+	g->ltc->cacheline_size = CACHELINE_SIZE_BASE <<
+		ltc_ltcs_ltss_cbc_param2_cache_line_size_v(reg);
+
+	nvgpu_log_info(g, "slices_per_ltc %u", g->ltc->slices_per_ltc);
+	nvgpu_log_info(g, "cacheline_size %u", g->ltc->cacheline_size);
+
+	/* PLC compression */
+	reg = nvgpu_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_1_r());
+	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_POST_L2_COMPRESSION)) {
+		reg = set_field(reg,
+			ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_m(),
+			ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_enabled_f());
+		reg = set_field(reg,
+			ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_m(),
+			ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_enabled_f());
+	} else {
+		reg = set_field(reg,
+			ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_m(),
+			ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_disabled_f());
+		reg = set_field(reg,
+			ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_m(),
+			ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_disabled_f());
+	}
+	nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_1_r(), reg);
+}
+
+void ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g)
+{
+	u32 reg;
+
+	if (nvgpu_is_errata_present(g, NVGPU_ERRATA_200601972)) {
+		reg = nvgpu_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_3_r());
+		reg = set_field(reg,
+			ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_ce_imm_m(),
+			ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_ce_imm_enabled_f());
+		reg = set_field(reg,
+			ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_fclr_imm_m(),
+			ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_fclr_imm_enabled_f());
+		nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_3_r(), reg);
+	}
+}
+
+int ga10b_set_l2_max_ways_evict_last(struct gk20a *g, struct nvgpu_tsg *tsg,
+		u32 num_ways)
+{
+	struct nvgpu_dbg_reg_op ops = {
+		.op = REGOP(READ_32),
+		.type = REGOP(TYPE_GR_CTX),
+		.offset = ltc_ltcs_ltss_tstg_set_mgmt0_r(),
+		.and_n_mask_lo = 0xffffffff
+	};
+	int err = -EINVAL;
+	u32 flags = NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE;
+	const u32 num_ops = 1U;
+
+	/*
+	 * MAX_WAYS_EVICT_LAST ways should not exceed the number of ways in a
+	 * L2 set.
+	 */
+	if (num_ways > g->ops.get_litter_value(g, GPU_LIT_NUM_LTC_LTS_WAYS)) {
+		nvgpu_err(g, "error: num_ways(%d) > max_ways(%d)", num_ways,
+				g->ops.get_litter_value(g, GPU_LIT_NUM_LTC_LTS_WAYS));
+		return err;
+	}
+
+	/*
+	 * Readback the current TSTG setting.
+	 */
+	err = gr_gk20a_exec_ctx_ops(tsg, &ops, num_ops, 0, num_ops, &flags);
+	if (err != 0) {
+		nvgpu_err(g, "regops_rd failed for LTCS_LTSS_TSTG_MGMT_0");
+		return err;
+	}
+	nvgpu_log_info(g, "current max_ways_l2_evict_last value=0x%x",
+		ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_v(ops.value_lo));
+
+	ops.value_lo = set_field(ops.value_lo,
+			ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_m(),
+			ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_f(num_ways));
+	nvgpu_log_info(g, "writing 0x%x to change l2 max_ways_evict_last to 0x%x",
+			ops.value_lo, num_ways);
+
+	/*
+	 * Write out the new value for L2_MAX_EVICT_LAST.
+	 */
+	ops.op = REGOP(WRITE_32);
+	err = gr_gk20a_exec_ctx_ops(tsg, &ops, num_ops, num_ops, 0, &flags);
+	if (err != 0) {
+		nvgpu_err(g, "regops_wr failed for LTCS_LTSS_TSTG_MGMT_0");
+		return err;
+	}
+
+	/*
+	 * Readback and verify L2_MAX_EVICT_LAST.
+	 */
+	ops.op = REGOP(READ_32);
+	ops.value_lo = 0U;
+	err = gr_gk20a_exec_ctx_ops(tsg, &ops, num_ops, 0, num_ops, &flags);
+	if (err != 0) {
+		nvgpu_err(g, "regops_rd failed for LTCS_LTSS_TSTG_MGMT_0");
+	}
+	if (ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_v(ops.value_lo) !=
+			num_ways) {
+		nvgpu_err(g, "mismatch, expected(%d) != readback(%d)", num_ways,
+			ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_v(ops.value_lo));
+		return -EINVAL;
+	}
+
+	return err;
+}
+
+int ga10b_get_l2_max_ways_evict_last(struct gk20a *g, struct nvgpu_tsg *tsg,
+		u32 *num_ways)
+{
+	struct nvgpu_dbg_reg_op ops = {
+		.op = REGOP(READ_32),
+		.type = REGOP(TYPE_GR_CTX),
+		.offset = ltc_ltcs_ltss_tstg_set_mgmt0_r(),
+		.and_n_mask_lo = 0xffffffff
+	};
+	int err;
+	u32 flags = NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE;
+	u32 num_ops = 1U;
+
+	if (num_ways == NULL) {
+		return -EINVAL;
+	}
+
+	/*
+	 * Readback the current TSTG setting.
+	 */
+	err = gr_gk20a_exec_ctx_ops(tsg, &ops, num_ops, 0, num_ops, &flags);
+	if (err != 0) {
+		nvgpu_err(g, "regops_rd failed for LTCS_LTSS_TSTG_MGMT_0");
+		return err;
+	}
+	*num_ways = ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_v(ops.value_lo);
+	nvgpu_log_info(g, "current max_ways_l2_evict_last value=0x%x", *num_ways);
+
+	return err;
+}
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_ga10b.h b/drivers/gpu/nvgpu/hal/mc/mc_ga10b.h
new file mode 100644
index 000000000..4462ee450
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/mc/mc_ga10b.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_MC_GA10B_H
+#define NVGPU_MC_GA10B_H
+
+#include <nvgpu/types.h>
+
+#define MC_UNIT_RESET_DELAY_US		20U
+#define MC_ENGINE_RESET_DELAY_US	500U
+
+struct gk20a;
+
+int ga10b_mc_enable_units(struct gk20a *g, u32 units, bool enable);
+int ga10b_mc_enable_dev(struct gk20a *g, const struct nvgpu_device *dev,
+			bool enable);
+int ga10b_mc_enable_devtype(struct gk20a *g, u32 devtype, bool enable);
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+void ga10b_mc_elpg_enable(struct gk20a *g);
+#endif
+
+#endif /* NVGPU_MC_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_ga10b_fusa.c
new file mode 100644
index 000000000..fb403894b
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/mc/mc_ga10b_fusa.c
@@ -0,0 +1,282 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/mc.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/device.h>
+
+#include "mc_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_mc_ga10b.h>
+
+/*
+ * In GA10B, multiple registers exist to reset various types of devices.
+ * NV_PMC_ENABLE register:
+ * - This register should be used to reset (disable then enable) available
+ *   h/w units.
+ *
+ * NV_PMC_ELPG_ENABLE register:
+ * - This register is protected by priviledge level mask and is used for secure
+ *   reset of XBAR, L2 and HUB units.
+ * - NOTE: XBAR, L2 and HUB cannot be enabled/disabled independently.
+ * - BPMP controls these units by writing to NV_PMC_ELPG_ENABLE register.
+ * - There is one bit across both PMC_ENABLE and ELPG_ENABLE used to reset
+ *   units.
+ *
+ * NV_PMC_DEVICE_ENABLE register:
+ * - This register controls reset of esched-method-driven engines enumerated
+ *   in nvgpu_device_info structure.
+ * - If device_info reset_id is VALID and is_engine is TRUE then
+ *   NV_PMC_DEVICE_ENABLE(i) index and bit position can be computed as below:
+ *    - register index, i = reset_id / 32
+ *    - bit position in 'i'th register word = reset_id % 32
+ * - If device_info reset_id is VALID but is_engine is FALSE, then this hardware
+ *   unit reset is available in NV_PMC_ENABLE register.
+ * - If device_info reset_id is invalid, given device is not driven by any
+ *   NV_PMC register.
+ *
+ * NV_PMC_DEVICE_ELPG_ENABLE register:
+ * - Behaves like NV_PMC_DEVICE_ENABLE register.
+ * - An engine is out of reset only when both NV_PMC_DEVICE_ELPG_ENABLE and
+ *   NV_PMC_DEVICE_ENABLE have same value in that engine's bit position within
+ *   the array.
+ * - BPMP controls engine state by writing to NV_PMC_DEVICE_ELPG_ENABLE
+ *   register.
+ */
+
+static int ga10b_mc_poll_device_enable(struct gk20a *g, u32 reg_idx,
+	u32 poll_val)
+{
+	u32 reg_val;
+	u32 delay = POLL_DELAY_MIN_US;
+	struct nvgpu_timeout timeout;
+	int err;
+
+	err = nvgpu_timeout_init(g, &timeout, MC_ENGINE_RESET_DELAY_US,
+				NVGPU_TIMER_CPU_TIMER);
+	if (err != 0) {
+		nvgpu_err(g, "Timeout init failed");
+		return err;
+	}
+
+	reg_val = nvgpu_readl(g, mc_device_enable_r(reg_idx));
+
+	/*
+	 * Engine disable/enable status can also be checked by using
+	 * status field of mc_device_enable_r().
+	 */
+
+	while ((poll_val != reg_val) &&
+		(nvgpu_timeout_expired(&timeout) == 0)) {
+
+		nvgpu_log(g, gpu_dbg_info,
+			"poll device_enable_r(%u) to be set to 0x%08x",
+			reg_idx, poll_val);
+
+		nvgpu_usleep_range(delay, delay * 2U);
+		delay = min_t(u32, delay << 1, POLL_DELAY_MAX_US);
+		reg_val = nvgpu_readl(g, mc_device_enable_r(reg_idx));
+	}
+
+	if (reg_val != poll_val) {
+		nvgpu_err(g, "Failed to set device_enable_r(%u) to 0x%08x",
+			reg_idx, poll_val);
+		return -ETIMEDOUT;
+	}
+	return 0;
+}
+
+static u32 ga10b_mc_unit_reset_mask(struct gk20a *g, u32 unit)
+{
+	u32 mask = 0U;
+
+	switch (unit) {
+	case NVGPU_UNIT_PERFMON:
+		mask = mc_enable_perfmon_m();
+		break;
+	case NVGPU_UNIT_FIFO:
+	case NVGPU_UNIT_GRAPH:
+	case NVGPU_UNIT_BLG:
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+	case NVGPU_UNIT_PWR:
+#endif
+		nvgpu_log_info(g, "unsupported nvgpu reset unit %d", unit);
+		break;
+	default:
+		WARN(true, "unknown nvgpu reset unit %d", unit);
+		break;
+	}
+
+	return mask;
+}
+
+static u32 ga10b_mc_get_unit_reset_mask(struct gk20a *g, u32 units)
+{
+	u32 mask = 0U;
+	unsigned long i = 0U;
+	unsigned long units_bitmask = units;
+
+	for_each_set_bit(i, &units_bitmask, 32U) {
+		mask |= ga10b_mc_unit_reset_mask(g, BIT32(i));
+	}
+	return mask;
+}
+
+int ga10b_mc_enable_units(struct gk20a *g, u32 units, bool enable)
+{
+	u32 mc_enable_val = 0U;
+	u32 reg_val = 0U;
+	u32 mask = ga10b_mc_get_unit_reset_mask(g, units);
+
+	nvgpu_log(g, gpu_dbg_info, "%s units: mc_enable mask = 0x%08x",
+			(enable ? "enable" : "disable"), mask);
+	if (enable) {
+		nvgpu_udelay(MC_RESET_DELAY_US);
+	}
+
+	nvgpu_spinlock_acquire(&g->mc.enable_lock);
+	reg_val = nvgpu_readl(g, mc_enable_r());
+	if (enable) {
+		mc_enable_val = reg_val | mask;
+	} else {
+		mc_enable_val = reg_val & (~mask);
+	}
+	nvgpu_writel(g, mc_enable_r(), mc_enable_val);
+	reg_val = nvgpu_readl(g, mc_enable_r());
+	nvgpu_spinlock_release(&g->mc.enable_lock);
+
+	nvgpu_udelay(MC_ENABLE_DELAY_US);
+
+	if (reg_val != mc_enable_val) {
+		nvgpu_err(g, "Failed to %s units: mc_enable mask = 0x%08x",
+			(enable ? "enable" : "disable"), mask);
+		return -EINVAL;
+	}
+	return 0U;
+}
+
+static int ga10b_mc_enable_engine(struct gk20a *g, u32 *device_enable_val,
+		bool enable)
+{
+	u32 reg_val;
+	u32 i;
+	int err = 0;
+
+	nvgpu_spinlock_acquire(&g->mc.enable_lock);
+
+	for (i = 0U; i < mc_device_enable__size_1_v(); i++) {
+		nvgpu_log(g, gpu_dbg_info, "%s device_enable_r[%u]: 0x%08x",
+			(enable ? "enable" : "disable"), i,
+			device_enable_val[i]);
+
+		reg_val = nvgpu_readl(g, mc_device_enable_r(i));
+
+		if (enable) {
+			reg_val |= device_enable_val[i];
+		} else {
+			reg_val &= ~device_enable_val[i];
+		}
+
+		nvgpu_writel(g, mc_device_enable_r(i), reg_val);
+		err = ga10b_mc_poll_device_enable(g, i, reg_val);
+
+		if (err != 0) {
+			nvgpu_err(g, "Couldn't %s device_enable_reg[%u]: 0x%x]",
+				(enable ? "enable" : "disable"), i, reg_val);
+		}
+	}
+
+	nvgpu_spinlock_release(&g->mc.enable_lock);
+	return err;
+}
+
+int ga10b_mc_enable_dev(struct gk20a *g, const struct nvgpu_device *dev,
+			bool enable)
+{
+	int err = 0;
+	u32 device_enable_val[mc_device_enable__size_1_v()] = {0};
+	u32 reg_index = RESET_ID_TO_REG_IDX(dev->reset_id);
+
+	device_enable_val[reg_index] |= RESET_ID_TO_REG_MASK(dev->reset_id);
+
+	err = ga10b_mc_enable_engine(g, device_enable_val, enable);
+	if (err != 0) {
+		nvgpu_log(g, gpu_dbg_info,
+			"Engine [id: %u] reset failed", dev->engine_id);
+	}
+	return 0;
+}
+
+static void ga10b_mc_get_devtype_reset_mask(struct gk20a *g, u32 devtype,
+	u32 *device_enable_reg)
+{
+	u32 reg_index = 0U;
+	const struct nvgpu_device *dev = NULL;
+
+	nvgpu_device_for_each(g, dev, devtype) {
+		reg_index = RESET_ID_TO_REG_IDX(dev->reset_id);
+		device_enable_reg[reg_index] |=
+			RESET_ID_TO_REG_MASK(dev->reset_id);
+	}
+}
+
+int ga10b_mc_enable_devtype(struct gk20a *g, u32 devtype, bool enable)
+{
+	int err = 0;
+	u32 device_enable_val[mc_device_enable__size_1_v()] = {0};
+
+	ga10b_mc_get_devtype_reset_mask(g, devtype, device_enable_val);
+
+	err = ga10b_mc_enable_engine(g, device_enable_val, enable);
+	if (err != 0) {
+		nvgpu_log(g, gpu_dbg_info, "Devtype: %u reset failed", devtype);
+	}
+	return 0;
+}
+
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+void ga10b_mc_elpg_enable(struct gk20a *g)
+{
+	/*
+	 * This is required only when bpmp is not running.
+	 * Independently resetting XBAR, L2, or HUB is not
+	 * supported. Disabling any of these will cause
+	 * XBAR, L2, and HUB to go into reset. To bring any of
+	 * these three out of reset, software should enable
+	 * all of these.
+	 */
+	if (!nvgpu_is_bpmp_running(g)) {
+		nvgpu_writel(g, mc_elpg_enable_r(),
+				mc_elpg_enable_xbar_enabled_f() |
+				mc_elpg_enable_l2_enabled_f() |
+				mc_elpg_enable_hub_enabled_f());
+		nvgpu_readl(g, mc_elpg_enable_r());
+	}
+
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b.h b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b.h
new file mode 100644
index 000000000..9def9510d
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_MC_INTR_GA10B_H
+#define NVGPU_MC_INTR_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void ga10b_intr_host2soc_0_unit_config(struct gk20a *g, u32 unit, bool enable);
+u32  ga10b_intr_host2soc_0(struct gk20a *g);
+void ga10b_intr_host2soc_0_pause(struct gk20a *g);
+void ga10b_intr_host2soc_0_resume(struct gk20a *g);
+u32  ga10b_intr_isr_host2soc_0(struct gk20a *g);
+
+void ga10b_intr_log_pending_intrs(struct gk20a *g);
+void ga10b_intr_mask_top(struct gk20a *g);
+bool ga10b_intr_is_mmu_fault_pending(struct gk20a *g);
+
+void ga10b_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
+u32  ga10b_intr_stall(struct gk20a *g);
+void ga10b_intr_stall_pause(struct gk20a *g);
+void ga10b_intr_stall_resume(struct gk20a *g);
+void ga10b_intr_isr_stall(struct gk20a *g);
+
+bool ga10b_intr_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id,
+			u32 *eng_intr_pending);
+bool ga10b_mc_intr_get_unit_info(struct gk20a *g, u32 unit);
+
+#endif /* NVGPU_MC_INTR_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c
new file mode 100644
index 000000000..610da88b5
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c
@@ -0,0 +1,1036 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/device.h>
+#include <nvgpu/mc.h>
+#include <nvgpu/cic.h>
+#include <nvgpu/power_features/pg.h>
+#include <nvgpu/gr/gr_instances.h>
+
+#include "mc_intr_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_func_ga10b.h>
+#include <nvgpu/hw/ga10b/hw_ctrl_ga10b.h>
+
+static bool ga10b_intr_is_unit_pending(struct gk20a *g,
+	u32 intr_unit, u32 intr_leaf0, u32 intr_leaf1, u64 *unit_subtree_mask)
+{
+	u64 subtree_mask;
+	u32 subtree_mask_lo, subtree_mask_hi;
+	u32 intr_unit_pending = false;
+	struct nvgpu_intr_unit_info *intr_unit_info;
+
+	intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
+
+	subtree_mask = intr_unit_info[intr_unit].subtree_mask;
+	subtree_mask_lo = u64_lo32(subtree_mask);
+	subtree_mask_hi = u64_hi32(subtree_mask);
+
+	if ((subtree_mask_lo & intr_leaf0) != 0U ||
+	    (subtree_mask_hi & intr_leaf1) != 0U) {
+		intr_unit_pending = true;
+		*unit_subtree_mask = subtree_mask;
+		nvgpu_log(g, gpu_dbg_intr, "pending intr_unit: %u", intr_unit);
+	}
+
+	return intr_unit_pending;
+}
+
+static void ga10b_intr_subtree_leaf0_leaf1_status(struct gk20a *g, u32 subtree,
+		u32 *intr_leaf0, u32 *intr_leaf1)
+{
+	/**
+	 * Get intr_leaf status for the subtree
+	 * top bit 0 -> subtree 0 -> leaf0, leaf1 -> leaf 0, 1
+	 * top bit 1 -> subtree 1 -> leaf0, leaf1 -> leaf 2, 3
+	 * top bit 2 -> subtree 2 -> leaf0, leaf1 -> leaf 4, 5
+	 * top bit 3 -> subtree 3 -> leaf0, leaf1 -> leaf 6, 7
+	 */
+
+	*intr_leaf0 = nvgpu_func_readl(g,
+			func_priv_cpu_intr_leaf_r(
+				HOST2SOC_SUBTREE_TO_LEAF0(subtree)));
+
+	*intr_leaf1 = nvgpu_func_readl(g,
+			func_priv_cpu_intr_leaf_r(
+				HOST2SOC_SUBTREE_TO_LEAF1(subtree)));
+
+	nvgpu_log(g, gpu_dbg_intr,
+		"%d_subtree: intr_leaf0: 0x%08x intr_leaf1: 0x%08x",
+			subtree, *intr_leaf0, *intr_leaf1);
+}
+
+static void ga10b_intr_subtree_clear(struct gk20a *g, u32 subtree,
+		u64 subtree_mask)
+{
+	/**
+	 * Clear interrupts in Leaf registers for the subtree.
+	 * top bit 0 -> subtree 0 -> leaf0, leaf1 -> leaf 0, 1
+	 * top bit 1 -> subtree 1 -> leaf0, leaf1 -> leaf 2, 3
+	 * top bit 2 -> subtree 2 -> leaf0, leaf1 -> leaf 4, 5
+	 * top bit 3 -> subtree 3 -> leaf0, leaf1 -> leaf 6, 7
+	 */
+
+	nvgpu_func_writel(g, func_priv_cpu_intr_leaf_r(
+				HOST2SOC_SUBTREE_TO_LEAF0(subtree)),
+				u64_lo32(subtree_mask));
+
+	nvgpu_func_writel(g, func_priv_cpu_intr_leaf_r(
+				HOST2SOC_SUBTREE_TO_LEAF1(subtree)),
+				u64_hi32(subtree_mask));
+
+	nvgpu_log(g, gpu_dbg_intr, "clear %d_subtree_mask: 0x%llx",
+			subtree, subtree_mask);
+}
+
+static void ga10b_intr_subtree_enable(struct gk20a *g, u32 subtree,
+		u64 subtree_mask)
+{
+	/**
+	 * Enable interrupts in Top and Leaf registers for the subtree.
+	 * top bit 0 -> subtree 0 -> leaf0, leaf1 -> leaf 0, 1
+	 * top bit 1 -> subtree 1 -> leaf0, leaf1 -> leaf 2, 3
+	 * top bit 2 -> subtree 2 -> leaf0, leaf1 -> leaf 4, 5
+	 * top bit 3 -> subtree 3 -> leaf0, leaf1 -> leaf 6, 7
+	 */
+	nvgpu_func_writel(g,
+		func_priv_cpu_intr_top_en_set_r(
+			HOST2SOC_SUBTREE_TO_TOP_IDX(subtree)),
+		BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(subtree)));
+
+	nvgpu_func_writel(g,
+		func_priv_cpu_intr_leaf_en_set_r(
+			HOST2SOC_SUBTREE_TO_LEAF0(subtree)),
+		u64_lo32(subtree_mask));
+	nvgpu_func_writel(g,
+		func_priv_cpu_intr_leaf_en_set_r(
+			HOST2SOC_SUBTREE_TO_LEAF1(subtree)),
+		u64_hi32(subtree_mask));
+
+	nvgpu_log(g, gpu_dbg_intr, "%d_subtree_mask: 0x%llx",
+			subtree, subtree_mask);
+}
+
+static void ga10b_intr_subtree_disable(struct gk20a *g, u32 subtree,
+		u64 subtree_mask)
+{
+	/**
+	 * Disable interrupts in Top and Leaf registers for the subtree.
+	 * top bit 0 -> subtree 0 -> leaf0, leaf1 -> leaf 0, 1
+	 * top bit 1 -> subtree 1 -> leaf0, leaf1 -> leaf 2, 3
+	 * top bit 2 -> subtree 2 -> leaf0, leaf1 -> leaf 4, 5
+	 * top bit 3 -> subtree 3 -> leaf0, leaf1 -> leaf 6, 7
+	 */
+	nvgpu_func_writel(g,
+		func_priv_cpu_intr_top_en_clear_r(
+			HOST2SOC_SUBTREE_TO_TOP_IDX(subtree)),
+		BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(subtree)));
+
+	nvgpu_func_writel(g,
+		func_priv_cpu_intr_leaf_en_clear_r(
+			HOST2SOC_SUBTREE_TO_LEAF0(subtree)),
+		u64_lo32(subtree_mask));
+	nvgpu_func_writel(g,
+		func_priv_cpu_intr_leaf_en_clear_r(
+			HOST2SOC_SUBTREE_TO_LEAF1(subtree)),
+		u64_hi32(subtree_mask));
+
+	nvgpu_log(g, gpu_dbg_intr, "%d_subtree_mask: 0x%llx",
+			subtree, subtree_mask);
+}
+
+static void ga10b_intr_config(struct gk20a *g, bool enable, u32 subtree,
+		u64 subtree_mask)
+{
+	if (enable) {
+		g->mc.nvgpu_next.subtree_mask_restore[subtree] |=
+			subtree_mask;
+		subtree_mask = g->mc.nvgpu_next.subtree_mask_restore[subtree];
+
+		ga10b_intr_subtree_enable(g, subtree, subtree_mask);
+	} else {
+		g->mc.nvgpu_next.subtree_mask_restore[subtree] &=
+			~(subtree_mask);
+		subtree_mask = g->mc.nvgpu_next.subtree_mask_restore[subtree];
+
+		ga10b_intr_subtree_disable(g, subtree, subtree_mask);
+	}
+}
+
+static void ga10b_intr_subtree_clear_unhandled(struct gk20a *g,
+	u32 subtree, u32 intr_leaf0, u32 intr_leaf1, u64 handled_subtree_mask)
+{
+	if (((u64_lo32(handled_subtree_mask)) != intr_leaf0) &&
+	    ((u64_hi32(handled_subtree_mask)) != intr_leaf1)) {
+		u64 unhandled_intr_leaf0 = intr_leaf0 &
+			~(u64_lo32(handled_subtree_mask));
+		u64 unhandled_intr_leaf1 = intr_leaf1 &
+			~(u64_hi32(handled_subtree_mask));
+		nvgpu_err(g, "unhandled host2soc_%d intr handled: 0x%llx"
+				"intr_leaf0 0x%08x intr_leaf1 0x%08x",
+			subtree, handled_subtree_mask, intr_leaf0, intr_leaf1);
+		ga10b_intr_subtree_clear(g, subtree,
+			hi32_lo32_to_u64(unhandled_intr_leaf1,
+				unhandled_intr_leaf0));
+	}
+}
+
+void ga10b_intr_host2soc_0_unit_config(struct gk20a *g, u32 unit, bool enable)
+{
+	u32 subtree = 0U;
+	u64 subtree_mask = 0ULL;
+
+	if (nvgpu_cic_intr_get_unit_info(g, unit, &subtree, &subtree_mask)
+			== false) {
+		return;
+	}
+	ga10b_intr_config(g, enable, HOST2SOC_0_SUBTREE, subtree_mask);
+}
+
+/** return non-zero if 0_subtree interrupts are pending */
+u32 ga10b_intr_host2soc_0(struct gk20a *g)
+{
+	u32 intr_status;
+	u32 intr_mask;
+
+	intr_status = nvgpu_func_readl(g, func_priv_cpu_intr_top_r(
+			HOST2SOC_SUBTREE_TO_TOP_IDX(HOST2SOC_0_SUBTREE)));
+
+	nvgpu_log(g, gpu_dbg_intr, "0_subtree intr top status: 0x%08x",
+				intr_status);
+
+	intr_mask = BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_0_SUBTREE));
+
+	return intr_status & intr_mask;
+}
+
+/** pause all 0_subtree interrupts */
+void ga10b_intr_host2soc_0_pause(struct gk20a *g)
+{
+	nvgpu_func_writel(g,
+		func_priv_cpu_intr_top_en_clear_r(
+			HOST2SOC_SUBTREE_TO_TOP_IDX(
+				HOST2SOC_0_SUBTREE)),
+		BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(
+			HOST2SOC_0_SUBTREE)));
+}
+
+/* resume all 0_subtree interrupts */
+void ga10b_intr_host2soc_0_resume(struct gk20a *g)
+{
+	nvgpu_func_writel(g,
+		func_priv_cpu_intr_top_en_set_r(
+			HOST2SOC_SUBTREE_TO_TOP_IDX(
+				HOST2SOC_0_SUBTREE)),
+		BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(
+			HOST2SOC_0_SUBTREE)));
+}
+
+/* Handle and clear 0_subtree interrupts */
+u32 ga10b_intr_isr_host2soc_0(struct gk20a *g)
+{
+	u32 intr_leaf0, intr_leaf1;
+	u64 unit_subtree_mask;
+	u64 handled_subtree_mask = 0ULL;
+	u32 subtree;
+	u32 ops = 0U;
+
+	/**
+	 * Engine Non-stall interrupts
+	 * Leaf 0 is for engine non stall interrupts used to notify.
+	 * Leaf 5 is for future use.
+	 */
+
+	subtree = HOST2SOC_0_SUBTREE;
+	ga10b_intr_subtree_leaf0_leaf1_status(g, subtree,
+		&intr_leaf0, &intr_leaf1);
+
+	if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_GR,
+			intr_leaf0, intr_leaf1, &unit_subtree_mask) == true) {
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+		ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
+				NVGPU_CIC_NONSTALL_OPS_POST_EVENTS);
+		handled_subtree_mask |= unit_subtree_mask;
+	}
+
+	if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_CE,
+			intr_leaf0, intr_leaf1, &unit_subtree_mask) == true) {
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+		ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
+				NVGPU_CIC_NONSTALL_OPS_POST_EVENTS);
+		handled_subtree_mask |= unit_subtree_mask;
+	}
+
+	ga10b_intr_subtree_clear_unhandled(g, subtree, intr_leaf0, intr_leaf1,
+				handled_subtree_mask);
+	return ops;
+}
+
+#ifdef CONFIG_NVGPU_NON_FUSA
+void ga10b_intr_log_pending_intrs(struct gk20a *g)
+{
+	u32 intr_top, intr_leaf, i, j;
+
+	for (i = 0U; i < func_priv_cpu_intr_top__size_1_v(); i++) {
+		intr_top = nvgpu_func_readl(g,
+			func_priv_cpu_intr_top_r(i));
+
+		/* Each top reg contains intr status for leaf__size */
+		for (j = 0U; j < func_priv_cpu_intr_leaf__size_1_v(); j++) {
+			intr_leaf = nvgpu_func_readl(g,
+					func_priv_cpu_intr_leaf_r(j));
+			if (intr_leaf == 0U) {
+				continue;
+			}
+			nvgpu_err(g,
+				"Pending TOP[%d]: 0x%08x, LEAF[%d]: 0x%08x",
+				i, intr_top, j, intr_leaf);
+		}
+	}
+}
+#endif
+
+void ga10b_intr_mask_top(struct gk20a *g)
+{
+	u32 i;
+
+	/* mask interrupts at the top level. leafs are not touched */
+	for (i = 0U; i < func_priv_cpu_intr_top_en_clear__size_1_v(); i++) {
+		nvgpu_func_writel(g, func_priv_cpu_intr_top_en_clear_r(i),
+				U32_MAX);
+	}
+}
+
+bool ga10b_mc_intr_get_unit_info(struct gk20a *g, u32 unit)
+{
+	u32 vectorid, reg_val, i;
+	struct nvgpu_intr_unit_info *intr_unit_info;
+	u64 tmp_subtree_mask = 0ULL;
+
+	intr_unit_info = &g->mc.nvgpu_next.intr_unit_info[unit];
+
+	switch (unit) {
+	case NVGPU_CIC_INTR_UNIT_BUS:
+		intr_unit_info->vectorid[0] =
+			func_priv_cpu_intr_pbus_vector_v();
+		intr_unit_info->vectorid_size = NVGPU_CIC_INTR_VECTORID_SIZE_ONE;
+		break;
+	case NVGPU_CIC_INTR_UNIT_PRIV_RING:
+		intr_unit_info->vectorid[0] =
+			func_priv_cpu_intr_priv_ring_vector_v();
+		intr_unit_info->vectorid_size = NVGPU_CIC_INTR_VECTORID_SIZE_ONE;
+		break;
+	case NVGPU_CIC_INTR_UNIT_LTC:
+		intr_unit_info->vectorid[0] =
+			func_priv_cpu_intr_ltc_all_vector_v();
+		intr_unit_info->vectorid_size = NVGPU_CIC_INTR_VECTORID_SIZE_ONE;
+		break;
+	case NVGPU_CIC_INTR_UNIT_PMU:
+		intr_unit_info->vectorid[0] =
+			func_priv_cpu_intr_pmu_vector_v();
+		intr_unit_info->vectorid_size = NVGPU_CIC_INTR_VECTORID_SIZE_ONE;
+		break;
+	case NVGPU_CIC_INTR_UNIT_FBPA:
+		intr_unit_info->vectorid[0] =
+			func_priv_cpu_intr_pfb_vector_v();
+		intr_unit_info->vectorid_size = NVGPU_CIC_INTR_VECTORID_SIZE_ONE;
+		break;
+	case NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR:
+	case NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT:
+	case NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR:
+	case NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT:
+	case NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT:
+	case NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR:
+		/* vectorids are set up in fb.init_hw */
+		nvgpu_log(g, gpu_dbg_intr, "MMU interrupts: %d", unit);
+		break;
+	/* GR NONSTALL interrupts */
+	case NVGPU_CIC_INTR_UNIT_GR:
+		/*
+		 * Even though each engine has separate vector id and each intr_unit
+		 * supports multiple engines, vectorid_size is set to one. This
+		 * is because engine interrupt mask is being used to configure
+		 * interrupts. Base vector is read from ctrl reg.
+		 */
+		reg_val = nvgpu_readl(g,
+			    ctrl_legacy_engine_nonstall_intr_base_vectorid_r());
+		vectorid =
+		  ctrl_legacy_engine_nonstall_intr_base_vectorid_vector_v(reg_val);
+		intr_unit_info->vectorid[0] = vectorid;
+		intr_unit_info->vectorid_size = NVGPU_CIC_INTR_VECTORID_SIZE_ONE;
+
+		intr_unit_info->subtree = GPU_VECTOR_TO_SUBTREE(vectorid);
+
+		tmp_subtree_mask = ((u64)nvgpu_gr_engine_interrupt_mask(g));
+		tmp_subtree_mask <<= GPU_VECTOR_TO_LEAF_SHIFT(vectorid);
+		intr_unit_info->subtree_mask = tmp_subtree_mask;
+
+		nvgpu_log(g, gpu_dbg_intr, "GR NONSTALL %d_subtree_mask: 0x%llx",
+			intr_unit_info->subtree, intr_unit_info->subtree_mask);
+		intr_unit_info->valid = true;
+		return true;
+	/* CE NONSTALL interrupts */
+	case NVGPU_CIC_INTR_UNIT_CE:
+		/* vectorids are setup in ce.init_hw */
+		nvgpu_log(g, gpu_dbg_intr, "CE NONSTALL interrupt");
+		break;
+	case NVGPU_CIC_INTR_UNIT_GR_STALL:
+		reg_val = nvgpu_readl(g,
+			    ctrl_legacy_engine_stall_intr_base_vectorid_r());
+		vectorid =
+		  ctrl_legacy_engine_stall_intr_base_vectorid_vector_v(reg_val);
+		intr_unit_info->vectorid[0] = vectorid;
+		intr_unit_info->vectorid_size = NVGPU_CIC_INTR_VECTORID_SIZE_ONE;
+
+		intr_unit_info->subtree = GPU_VECTOR_TO_SUBTREE(vectorid);
+
+		tmp_subtree_mask = ((u64)nvgpu_gr_engine_interrupt_mask(g));
+		tmp_subtree_mask <<= GPU_VECTOR_TO_LEAF_SHIFT(vectorid);
+		intr_unit_info->subtree_mask = tmp_subtree_mask;
+
+		nvgpu_log(g, gpu_dbg_intr, "GR STALL %d_subtree_mask: 0x%llx",
+			intr_unit_info->subtree, intr_unit_info->subtree_mask);
+		intr_unit_info->valid = true;
+		return true;
+
+	case NVGPU_CIC_INTR_UNIT_CE_STALL:
+		reg_val = nvgpu_readl(g,
+			    ctrl_legacy_engine_stall_intr_base_vectorid_r());
+		vectorid =
+		  ctrl_legacy_engine_stall_intr_base_vectorid_vector_v(reg_val);
+		intr_unit_info->vectorid[0] = vectorid;
+		intr_unit_info->vectorid_size = NVGPU_CIC_INTR_VECTORID_SIZE_ONE;
+
+		intr_unit_info->subtree = GPU_VECTOR_TO_SUBTREE(vectorid);
+
+		tmp_subtree_mask = ((u64)nvgpu_ce_engine_interrupt_mask(g));
+		tmp_subtree_mask <<= GPU_VECTOR_TO_LEAF_SHIFT(vectorid);
+		intr_unit_info->subtree_mask = tmp_subtree_mask;
+
+		nvgpu_log(g, gpu_dbg_intr, "CE STALL %d_subtree_mask: 0x%llx",
+			intr_unit_info->subtree, intr_unit_info->subtree_mask);
+		intr_unit_info->valid = true;
+		return true;
+
+	case NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0:
+	case NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_1:
+		nvgpu_log(g, gpu_dbg_intr, "RUNLIST interrupts");
+		break;
+	default:
+		nvgpu_err(g, "non supported intr unit");
+		return false;
+	}
+
+	for (i = 0U; i < intr_unit_info->vectorid_size; i++) {
+		u32 tmp_subtree;
+		vectorid = intr_unit_info->vectorid[i];
+		nvgpu_log(g, gpu_dbg_intr, "unit: %d vectorid: %d",
+				unit, vectorid);
+
+		/**
+		 * Assumption is intr unit supporting more vectorids
+		 * reside in same subtree.
+		 */
+		tmp_subtree = GPU_VECTOR_TO_SUBTREE(vectorid);
+		if (i != 0U && tmp_subtree != intr_unit_info->subtree) {
+			nvgpu_err(g,
+				"unit: %d, vectorid(%d) is outside subtree(%d)",
+				unit, vectorid, intr_unit_info->subtree);
+			return false;
+		}
+		intr_unit_info->subtree = tmp_subtree;
+
+		tmp_subtree_mask = GPU_VECTOR_TO_LEAF_MASK(vectorid);
+		tmp_subtree_mask <<= GPU_VECTOR_TO_LEAF_SHIFT(vectorid);
+		intr_unit_info->subtree_mask |= tmp_subtree_mask;
+	}
+
+	intr_unit_info->valid = true;
+
+	nvgpu_log(g, gpu_dbg_intr, "%d_subtree_mask: 0x%llx",
+			intr_unit_info->subtree, intr_unit_info->subtree_mask);
+	return true;
+}
+
+static u32 ga10b_intr_map_mc_stall_unit_to_intr_unit(struct gk20a *g,
+		u32 mc_intr_unit)
+{
+	u32 intr_unit = mc_intr_unit;
+
+	/**
+	 * Different indices are used to store unit info for
+	 * gr/ce stall/nostall intr.
+	 */
+	if (mc_intr_unit == NVGPU_CIC_INTR_UNIT_GR) {
+		intr_unit = NVGPU_CIC_INTR_UNIT_GR_STALL;
+	} else if (mc_intr_unit == NVGPU_CIC_INTR_UNIT_CE) {
+		intr_unit = NVGPU_CIC_INTR_UNIT_CE_STALL;
+	}
+	return intr_unit;
+}
+
+void ga10b_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
+{
+	u64 subtree_mask = 0ULL;
+	u32 subtree = 0U;
+
+	unit = ga10b_intr_map_mc_stall_unit_to_intr_unit(g, unit);
+
+	if (nvgpu_cic_intr_get_unit_info(g, unit, &subtree, &subtree_mask)
+			== false) {
+		return;
+	}
+
+	ga10b_intr_config(g, enable, subtree, subtree_mask);
+}
+
+/** return non-zero if subtree 1, 2, 3 interrupts are pending */
+u32 ga10b_intr_stall(struct gk20a *g)
+{
+	u32 intr_status;
+	u32 intr_mask;
+
+	intr_status = nvgpu_func_readl(g, func_priv_cpu_intr_top_r(
+			STALL_SUBTREE_TOP_IDX));
+
+	nvgpu_log(g, gpu_dbg_intr, "intr top status: 0x%08x", intr_status);
+
+	intr_mask = STALL_SUBTREE_TOP_BITS;
+
+	return intr_status & intr_mask;
+}
+
+/** pause all stall interrupts i.e. from subtree 1, 2 and 3 */
+void ga10b_intr_stall_pause(struct gk20a *g)
+{
+	nvgpu_func_writel(g, func_priv_cpu_intr_top_en_clear_r(
+			STALL_SUBTREE_TOP_IDX), STALL_SUBTREE_TOP_BITS);
+}
+
+/* resume all interrupts for subtree 1, 2 and 3 */
+void ga10b_intr_stall_resume(struct gk20a *g)
+{
+	nvgpu_func_writel(g, func_priv_cpu_intr_top_en_set_r(
+			STALL_SUBTREE_TOP_IDX), STALL_SUBTREE_TOP_BITS);
+}
+
+static u32 ga10b_intr_is_pending_2_subtree_mmu_fault(struct gk20a *g,
+		u32 intr_leaf0, u32 intr_leaf1, u64 *unit_subtree_mask)
+{
+	u32 intr_unit_bitmask = 0U;
+
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR,
+		intr_leaf0, intr_leaf1, unit_subtree_mask) == true) {
+		intr_unit_bitmask |=
+			BIT32(NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR);
+	}
+
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR,
+		intr_leaf0, intr_leaf1, unit_subtree_mask) == true) {
+		intr_unit_bitmask |=
+			BIT32(NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR);
+	}
+
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT,
+		intr_leaf0, intr_leaf1, unit_subtree_mask) == true) {
+		intr_unit_bitmask |=
+			BIT32(NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT);
+	}
+
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR,
+		intr_leaf0, intr_leaf1, unit_subtree_mask) == true) {
+		intr_unit_bitmask |=
+			BIT32(NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR);
+	}
+
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT,
+		intr_leaf0, intr_leaf1, unit_subtree_mask) == true) {
+		intr_unit_bitmask |=
+			BIT32(NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT);
+	}
+
+	if (intr_unit_bitmask != 0U) {
+		nvgpu_log(g, gpu_dbg_intr, "mmu_fault_pending: 0x%llx"
+			, *unit_subtree_mask);
+	}
+
+	return intr_unit_bitmask;
+}
+
+static void ga10b_intr_isr_stall_host2soc_1(struct gk20a *g)
+{
+	u32 intr_leaf0, intr_leaf1;
+	u64 unit_subtree_mask;
+	u64 handled_subtree_mask = 0ULL;
+	u32 subtree;
+
+	/**
+	 * New interrupt line
+	 * HOST2SOC_1_INTR_ID: 68: 1_subtree: leaf0, leaf1 (leaf 2, 3)
+	 * Leaf 2 is for mmu_replayable fault and hub_access_cntr
+	 * Leaf 3 is empty
+	 */
+
+	subtree = HOST2SOC_1_SUBTREE;
+	ga10b_intr_subtree_leaf0_leaf1_status(g, subtree,
+		&intr_leaf0, &intr_leaf1);
+
+	if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT,
+			intr_leaf0, intr_leaf1,
+			&unit_subtree_mask) == true) {
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+		handled_subtree_mask |= unit_subtree_mask;
+		g->ops.fb.intr.isr(g, BIT32(NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT));
+	}
+
+	ga10b_intr_subtree_clear_unhandled(g, subtree, intr_leaf0, intr_leaf1,
+				handled_subtree_mask);
+}
+
+static void ga10b_intr_isr_stall_host2soc_2(struct gk20a *g)
+{
+	u32 intr_leaf0, intr_leaf1;
+	u64 unit_subtree_mask;
+	u64 handled_subtree_mask = 0ULL;
+	u32 subtree;
+	u32 intr_unit_bitmask = 0U;
+
+	/**
+	 * Legacy stall
+	 * HOST2SOC_2_INTR_ID: 70: 2_subtree: leaf0, leaf1 (leaf 4, 5)
+	 * Leaf 4 is for mmu_*, pbus, priv, ltc etc.
+	 * Leaf 5 is for runlist_tree0
+	 */
+
+	subtree = HOST2SOC_2_SUBTREE;
+	ga10b_intr_subtree_leaf0_leaf1_status(g, subtree,
+		&intr_leaf0, &intr_leaf1);
+
+	if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_BUS, intr_leaf0, intr_leaf1,
+				&unit_subtree_mask) == true) {
+		handled_subtree_mask |= unit_subtree_mask;
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+		g->ops.bus.isr(g);
+	}
+
+	if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_PRIV_RING,
+		intr_leaf0, intr_leaf1, &unit_subtree_mask) == true) {
+		handled_subtree_mask |= unit_subtree_mask;
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+		g->ops.priv_ring.isr(g);
+	}
+
+	if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_FBPA,
+		intr_leaf0, intr_leaf1, &unit_subtree_mask) == true) {
+		handled_subtree_mask |= unit_subtree_mask;
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+		g->ops.mc.fbpa_isr(g);
+	}
+
+	if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_LTC, intr_leaf0, intr_leaf1,
+				&unit_subtree_mask) == true) {
+		handled_subtree_mask |= unit_subtree_mask;
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+		g->ops.mc.ltc_isr(g);
+	}
+
+	intr_unit_bitmask = ga10b_intr_is_pending_2_subtree_mmu_fault(g,
+		intr_leaf0, intr_leaf1, &unit_subtree_mask);
+	if (intr_unit_bitmask != 0U) {
+		handled_subtree_mask |= unit_subtree_mask;
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+		g->ops.fb.intr.isr(g, intr_unit_bitmask);
+	}
+
+	if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0,
+				intr_leaf0, intr_leaf1,
+				&unit_subtree_mask) == true) {
+		handled_subtree_mask |= unit_subtree_mask;
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+		g->ops.fifo.intr_0_isr(g);
+		g->ops.fifo.runlist_intr_retrigger(g, RUNLIST_INTR_TREE_0);
+	}
+
+	if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_PMU, intr_leaf0, intr_leaf1,
+				&unit_subtree_mask) == true) {
+		handled_subtree_mask |= unit_subtree_mask;
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+		g->ops.pmu.pmu_isr(g);
+	}
+
+	ga10b_intr_subtree_clear_unhandled(g, subtree, intr_leaf0, intr_leaf1,
+				handled_subtree_mask);
+}
+
+static int ga10b_intr_gr_stall_isr(struct gk20a *g)
+{
+	int err;
+
+	err = nvgpu_pg_elpg_protected_call(g, g->ops.gr.intr.stall_isr(g));
+	g->ops.gr.intr.retrigger(g);
+
+	return err;
+}
+
+static void ga10b_intr_gr_stall_interrupt_handling(struct gk20a *g,
+		u64 unit_subtree_mask)
+{
+	int err;
+	u64 engine_intr_mask;
+	u32 vectorid;
+	u32 gr_instance_id;
+	const struct nvgpu_device *dev;
+	struct nvgpu_intr_unit_info *intr_unit_info =
+		&g->mc.nvgpu_next.intr_unit_info[NVGPU_CIC_INTR_UNIT_GR_STALL];
+
+	vectorid = intr_unit_info->vectorid[0];
+
+	nvgpu_device_for_each(g, dev, NVGPU_DEVTYPE_GRAPHICS) {
+		engine_intr_mask = BIT32(dev->intr_id);
+		engine_intr_mask <<= GPU_VECTOR_TO_LEAF_SHIFT(vectorid);
+
+		if ((unit_subtree_mask & engine_intr_mask) == 0ULL) {
+			continue;
+		}
+
+		gr_instance_id =
+			nvgpu_grmgr_get_gr_instance_id_for_syspipe(
+				g, dev->inst_id);
+
+		err = nvgpu_gr_exec_with_err_for_instance(g,
+			gr_instance_id, ga10b_intr_gr_stall_isr(g));
+
+		if (err != 0) {
+			nvgpu_err(g,
+				"Unable to handle GR STALL interrupt "
+					"inst_id : %u Vectorid : 0x%08x "
+					"intr_id : 0x%08x "
+					"gr_instance_id : %u "
+					"engine_intr_mask : 0x%llx "
+					"unit_subtree_mask : 0x%llx",
+				dev->inst_id, vectorid, dev->intr_id,
+				gr_instance_id, engine_intr_mask,
+				unit_subtree_mask);
+		} else {
+			nvgpu_log(g, gpu_dbg_mig,
+				"GR STALL interrupt handled "
+					"inst_id : %u Vectorid : 0x%08x "
+					"intr_id : 0x%08x "
+					"gr_instance_id : %u "
+					"engine_intr_mask : 0x%llx "
+					"unit_subtree_mask : 0x%llx",
+				dev->inst_id, vectorid, dev->intr_id,
+				gr_instance_id, engine_intr_mask,
+				unit_subtree_mask);
+		}
+	}
+}
+
+static void ga10b_intr_isr_stall_host2soc_3(struct gk20a *g)
+{
+	u32 intr_leaf0, intr_leaf1;
+	u64 unit_subtree_mask;
+	u64 handled_subtree_mask = 0ULL;
+	u32 subtree;
+
+	/**
+	 * New interrupt line
+	 * HOST2SOC_3_INTR_ID: 71: 3_subtree: leaf0, leaf1 (leaf 6, 7)
+	 * Leaf 6 is for engine stall interrupts
+	 * Leaf 7 is for runlist_tree_1
+	 */
+
+	subtree = HOST2SOC_3_SUBTREE;
+	ga10b_intr_subtree_leaf0_leaf1_status(g, subtree,
+		&intr_leaf0, &intr_leaf1);
+
+	if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_GR_STALL,
+				intr_leaf0, intr_leaf1,
+				&unit_subtree_mask) == true) {
+
+		handled_subtree_mask |= unit_subtree_mask;
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+
+		ga10b_intr_gr_stall_interrupt_handling(g, unit_subtree_mask);
+	}
+	if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_CE_STALL,
+				intr_leaf0, intr_leaf1,
+				&unit_subtree_mask) == true) {
+		u32 i;
+		u64 engine_intr_mask;
+		u32 vectorid;
+		const struct nvgpu_device *dev;
+
+		vectorid =
+		   g->mc.nvgpu_next.intr_unit_info[NVGPU_CIC_INTR_UNIT_CE_STALL].vectorid[0];
+
+		handled_subtree_mask |= unit_subtree_mask;
+		ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask);
+
+		for (i = 0U; i < g->fifo.num_engines; i++) {
+			dev = g->fifo.active_engines[i];
+
+			engine_intr_mask = BIT32(dev->intr_id);
+			engine_intr_mask <<= GPU_VECTOR_TO_LEAF_SHIFT(vectorid);
+			if ((unit_subtree_mask & engine_intr_mask) == 0ULL) {
+				continue;
+			}
+			if (g->ops.ce.isr_stall != NULL) {
+				g->ops.ce.isr_stall(g,
+						    dev->inst_id,
+						    dev->pri_base);
+			} else {
+				nvgpu_err(g, "unhandled intr_unit_ce_stall");
+			}
+			g->ops.ce.intr_retrigger(g, dev->inst_id);
+
+		}
+	}
+	ga10b_intr_subtree_clear_unhandled(g, subtree, intr_leaf0, intr_leaf1,
+				handled_subtree_mask);
+}
+
+/* Handle and clear interrupt for subtree 1, 2 and 3 */
+void ga10b_intr_isr_stall(struct gk20a *g)
+{
+	u32 top_pending;
+
+	top_pending = g->ops.mc.intr_stall(g);
+	if (top_pending == 0U) {
+		nvgpu_err(g, "spurious stall intr");
+		return;
+	}
+	/**
+	 * Legacy nonstall
+	 * HOST2SOC_0_INTR_ID: 67: 0_subtree: leaf0, leaf1 (leaf 0, 1)
+	 * Leaf 0 is used for engine nonstall interrupts
+	 * Leaf 1 is empty
+	 *
+	 * New interrupt line
+	 * HOST2SOC_1_INTR_ID: 68: 1_subtree: leaf0, leaf1 (leaf 2, 3)
+	 * Leaf 2 is for mmu_replayable fault and hub_access_cntr
+	 * Leaf 3 is empty
+	 *
+	 * Legacy stall
+	 * HOST2SOC_2_INTR_ID: 70: 2_subtree: leaf0, leaf1 (leaf 4, 5)
+	 * Leaf 4 is for mmu_*, pbus, priv, ltc etc.
+	 * Leaf 5 is for runlist_tree0
+	 *
+	 * New interrupt line
+	 * HOST2SOC_3_INTR_ID: 71: 3_subtree: leaf0, leaf1 (leaf 6, 7)
+	 * Leaf 6 is for engine stall interrupts
+	 * Leaf 7 is for runlist_tree_1
+	 */
+
+	/*
+	 * The cpu leaf bit in each interrupt subtree is handled as follows:
+	 * - Each bit in the leaf register represents an interrupt vector.
+	 * - Each vector is mapped to a unit. A unit may have multiple
+	 *   vectors mapped to it.
+	 * - Attempt to map pending vectors in the CPU leaf register to a
+	 *   specific unit, this is accomplished using a unit level bitmask.
+	 *   - If match is found:
+	 *     - Clear the corresponding bits in the CPU leaf registers of the
+	 *       subtree.
+	 *     - Call unit level interrupt handler.
+	 *     - Call interrupt retrigger if unit implements one.
+	 *   - Not found:
+	 *     - Clear the CPU leaf register anyways.
+	 *
+	 * Interrupt Retriggering:
+	 *
+	 * In ga10b the interrupt tree is composed of two 32bit top level
+	 * registers cpu_top_0/1. The lower 4 bits of cpu_top_0 are connected
+	 * to 4 interrupt lines, while the other bits are left unused,
+	 * unconnected.
+	 *
+	 * Each bit in the cpu_top_0/1 is rolled up from a pair of registers
+	 * cpu_leaf_0/1. Similarly each bit in cpu_leaf_0/1 is latched to the
+	 * interrupt signals from respective hw units at +ve edges.
+	 * A hardware unit may further implement its own intermediate interrupt
+	 * tree, comprising of serveral status registers. The unit level
+	 * interrupt status is rolled up to the top level tree via a interrupt
+	 * output signal.
+	 *
+	 * However, the edge latching at the cpu_leaf register introduces a
+	 * possible race condition for hw units which performs level based
+	 * roll up of interrupt signal i.e. a race might happen between sw
+	 * reading the interrupt status and hw setting bits within the same
+	 * register. In such a scenario, the unhandled, pending bits in the
+	 * hardware unit will remain high. However an interrupt will not be
+	 * generated once the sw handles the seen interrupts and clears the
+	 * corresponding cpu_leaf register bit. This is on account of the edge
+	 * latching at the cpu_leaf registers, which sets bits only when there
+	 * is a +ve edge detected on the interrupt signal from the hw unit.
+	 *
+	 * In order to mitigate this race condition ga10b introduces a
+	 * *_INTR_RETRIGGER register for engines which generate level rolled up
+	 * interrupt signals. The *_INTR_RETRIGGER register is normally wired
+	 * to 1 and is logically ANDed with interrupt output of the hw unit,
+	 * which then is edge latched to the leaf register bits. Once sw
+	 * services a unit interrupt, it writes to its *_INTR_RETRIGGER
+	 * register, this causes it to be pulled down to 0 for a short time and
+	 * back to 1. This ensures unhandled hw unit interrupts are seen as a
+	 * +ve by the cpu_leaf register and would interrupt alert the CPU.
+	 */
+
+	/* Handle interrupts for 3_subtree */
+	if (top_pending &
+		BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_3_SUBTREE))) {
+
+		ga10b_intr_isr_stall_host2soc_3(g);
+	}
+
+	/* Handle interrupts for 2_subtree */
+	if (top_pending &
+		BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_2_SUBTREE))) {
+
+		ga10b_intr_isr_stall_host2soc_2(g);
+	}
+
+	/* Handle interrupts for 1_subtree */
+	if (top_pending &
+		BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_1_SUBTREE))) {
+
+		ga10b_intr_isr_stall_host2soc_1(g);
+	}
+
+	return;
+}
+
+bool ga10b_intr_is_mmu_fault_pending(struct gk20a *g)
+{
+	u64 subtree_mask = 0ULL;
+	u32 intr_leaf0, intr_leaf1;
+	bool mmu_fault_pending = false;
+
+	ga10b_intr_subtree_leaf0_leaf1_status(g, HOST2SOC_2_SUBTREE,
+		&intr_leaf0, &intr_leaf1);
+
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR,
+		intr_leaf0, intr_leaf1, &subtree_mask) == true) {
+		mmu_fault_pending = true;
+	}
+
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR,
+		intr_leaf0, intr_leaf1, &subtree_mask) == true) {
+		mmu_fault_pending = true;
+	}
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT,
+		intr_leaf0, intr_leaf1, &subtree_mask) == true) {
+		mmu_fault_pending = true;
+	}
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR,
+		intr_leaf0, intr_leaf1, &subtree_mask) == true) {
+		mmu_fault_pending = true;
+	}
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT,
+		intr_leaf0, intr_leaf1, &subtree_mask) == true) {
+		mmu_fault_pending = true;
+	}
+
+	if (mmu_fault_pending == true) {
+		nvgpu_log(g, gpu_dbg_intr, "2_subtree mmu_fault_pending: 0x%llx"
+			, subtree_mask);
+	}
+
+	ga10b_intr_subtree_leaf0_leaf1_status(g, HOST2SOC_1_SUBTREE,
+		&intr_leaf0, &intr_leaf1);
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT,
+		intr_leaf0, intr_leaf1, &subtree_mask) == true) {
+		mmu_fault_pending = true;
+		nvgpu_log(g, gpu_dbg_intr, "1_subtree mmu_fault_pending: 0x%llx"
+			, subtree_mask);
+	}
+
+	return mmu_fault_pending;
+}
+
+static bool ga10b_intr_is_eng_stall_pending(struct gk20a *g, u32 engine_id)
+{
+	u64 eng_subtree_mask = 0ULL;
+	u64 subtree_mask = 0ULL;
+	u32 intr_leaf0, intr_leaf1;
+	u32 reg_val, vectorid;
+	bool eng_stall_pending = false;
+
+	reg_val = nvgpu_readl(g,
+		    ctrl_legacy_engine_stall_intr_base_vectorid_r());
+	vectorid =
+		  ctrl_legacy_engine_stall_intr_base_vectorid_vector_v(reg_val);
+
+	eng_subtree_mask = ((u64)nvgpu_engine_act_interrupt_mask(g, engine_id));
+	eng_subtree_mask <<= GPU_VECTOR_TO_LEAF_SHIFT(vectorid);
+
+	ga10b_intr_subtree_leaf0_leaf1_status(g, HOST2SOC_3_SUBTREE,
+		&intr_leaf0, &intr_leaf1);
+
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_GR_STALL,
+		intr_leaf0, intr_leaf1, &subtree_mask) == true) {
+		if (subtree_mask & eng_subtree_mask) {
+			eng_stall_pending = true;
+		}
+	}
+
+	if (ga10b_intr_is_unit_pending(g,
+		NVGPU_CIC_INTR_UNIT_CE_STALL,
+		intr_leaf0, intr_leaf1, &subtree_mask) == true) {
+		if (subtree_mask & eng_subtree_mask) {
+			eng_stall_pending = true;
+		}
+	}
+
+	return eng_stall_pending;
+}
+
+bool ga10b_intr_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id,
+			u32 *eng_intr_pending)
+{
+	u32 stall_intr;
+
+	*eng_intr_pending = ga10b_intr_is_eng_stall_pending(g, engine_id);
+
+	stall_intr = ga10b_intr_stall(g);
+
+	nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
+		"intr_top = 0x%08x, eng_intr_pending = 0x%08x",
+		stall_intr, *eng_intr_pending);
+
+	return (stall_intr != 0U);
+}
diff --git a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b.h b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b.h
new file mode 100644
index 000000000..9bce95b25
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef HAL_MM_GMMU_GA10B_H
+#define HAL_MM_GMMU_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct gk20a_mmu_level;
+struct nvgpu_gmmu_attrs;
+
+u32 ga10b_mm_get_iommu_bit(struct gk20a *g);
+const struct gk20a_mmu_level *ga10b_mm_get_mmu_levels(struct gk20a *g,
+			u64 big_page_size);
+u32 ga10b_get_max_page_table_levels(struct gk20a *g);
+
+#endif /* HAL_MM_GMMU_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b_fusa.c
new file mode 100644
index 000000000..b0cb3e02a
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_ga10b_fusa.c
@@ -0,0 +1,391 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/gmmu.h>
+#include <nvgpu/static_analysis.h>
+
+#include <nvgpu/hw/ga10b/hw_gmmu_ga10b.h>
+
+#include "hal/mm/gmmu/gmmu_gk20a.h"
+#include "gmmu_ga10b.h"
+
+/*
+ * From page table structure, PDE0 entry uses (VA[28:21]) 8 bits i.e 256 entries
+ * Size of page directory 0 is 4KB.
+ * So, each entry is 4KB/256 = 16 bytes.
+ */
+#define GA10B_PDE0_ENTRY_SIZE		16U
+
+/*
+ * From page table structure, PDE1 entry uses (VA[37:29]) 9 bits i.e 512 entries
+ * Size of page directory 1 is 4KB.
+ * So, each entry is 4KB/512 = 8 bytes.
+ * Similarly, PDE2 entry uses (VA[46:38]) 9 bits i.e 512 entries
+ * Size of page directory 2 is 4KB.
+ * So, each entry is 4KB/512 = 8 bytes.
+ *
+ * Ideally, PDE3 can have more entries. However, PDE3 entries are limited to 8.
+ */
+#define GA10B_PDE_DEFAULT_ENTRY_SIZE	8U
+
+/*
+ * From page table structure,
+ * for small page,
+ *        PTE uses (VA[20:12]) 9 bits i.e 512 entries with 4KB size
+ *        So, each entry is 4KB/512 = 8 bytes
+ * for big page,
+ *        PTE uses (VA[20:16]) 5 bits i.e 32 entries with 256B size
+ *        So, each entry is 256B/32 = 8 bytes
+ */
+#define GA10B_PTE_ENTRY_SIZE		8U
+
+/*
+ * Ampere follows new Page Table format of 5 levels with 4 page directory levels
+ * and a page table
+ */
+#define GA10B_MAX_PAGE_TABLE_LEVELS	5U
+
+/*
+ * Compression support is provided for 128GB memory.
+ * 37 bits (0 to 36) are required for addressing compression memory.
+ * Use 37th bit to describe l3_alloc or iommu bit.
+ */
+#define GA10B_MM_IOMMU_BIT		37U
+
+u32 ga10b_mm_get_iommu_bit(struct gk20a *g)
+{
+	return GA10B_MM_IOMMU_BIT;
+}
+
+static void ga10b_update_gmmu_pde3_locked(struct vm_gk20a *vm,
+				    const struct gk20a_mmu_level *l,
+				    struct nvgpu_gmmu_pd *pd,
+				    u32 pd_idx,
+				    u64 virt_addr,
+				    u64 phys_addr,
+				    struct nvgpu_gmmu_attrs *attrs)
+{
+	struct gk20a *g = gk20a_from_vm(vm);
+	struct nvgpu_gmmu_pd *next_pd = &pd->entries[pd_idx];
+	u32 pd_offset = nvgpu_pd_offset_from_index(l, pd_idx);
+	u32 pde_v[2] = {0, 0};
+
+	phys_addr >>= gmmu_new_pde_address_shift_v();
+
+	pde_v[0] |= nvgpu_aperture_mask(g, next_pd->mem,
+					gmmu_new_pde_aperture_sys_mem_ncoh_f(),
+					gmmu_new_pde_aperture_sys_mem_coh_f(),
+					gmmu_new_pde_aperture_video_memory_f());
+	pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(phys_addr));
+	pde_v[0] |= gmmu_new_pde_vol_true_f();
+	pde_v[1] |= nvgpu_safe_cast_u64_to_u32(phys_addr >> 24);
+
+	nvgpu_pd_write(g, pd, (size_t)nvgpu_safe_add_u32(pd_offset, 0U),
+								pde_v[0]);
+	nvgpu_pd_write(g, pd, (size_t)nvgpu_safe_add_u32(pd_offset, 1U),
+								pde_v[1]);
+
+	pte_dbg(g, attrs,
+		"PDE: i=%-4u size=%-2u offs=%-4u pgsz: -- | "
+		"GPU %#-12llx  phys %#-12llx "
+		"[0x%08x, 0x%08x]",
+		pd_idx, l->entry_size, pd_offset,
+		virt_addr, phys_addr,
+		pde_v[1], pde_v[0]);
+}
+
+static void ga10b_update_gmmu_pde0_locked(struct vm_gk20a *vm,
+				    const struct gk20a_mmu_level *l,
+				    struct nvgpu_gmmu_pd *pd,
+				    u32 pd_idx,
+				    u64 virt_addr,
+				    u64 phys_addr,
+				    struct nvgpu_gmmu_attrs *attrs)
+{
+	struct gk20a *g = gk20a_from_vm(vm);
+	struct nvgpu_gmmu_pd *next_pd = &pd->entries[pd_idx];
+	bool small_valid, big_valid;
+	u32 small_addr = 0, big_addr = 0;
+	u32 pd_offset = nvgpu_pd_offset_from_index(l, pd_idx);
+	u32 pde_v[4] = {0, 0, 0, 0};
+	u64 tmp_addr;
+
+	small_valid = attrs->pgsz == GMMU_PAGE_SIZE_SMALL;
+	big_valid   = attrs->pgsz == GMMU_PAGE_SIZE_BIG;
+
+	if (small_valid) {
+		tmp_addr = phys_addr >> gmmu_new_dual_pde_address_shift_v();
+		nvgpu_assert(u64_hi32(tmp_addr) == 0U);
+		small_addr = (u32)tmp_addr;
+
+		pde_v[2] |=
+			gmmu_new_dual_pde_address_small_sys_f(small_addr);
+		pde_v[2] |= nvgpu_aperture_mask(g, next_pd->mem,
+			gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(),
+			gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(),
+			gmmu_new_dual_pde_aperture_small_video_memory_f());
+		pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f();
+		pde_v[3] |= small_addr >> 24;
+	}
+
+	if (big_valid) {
+		tmp_addr = phys_addr >> gmmu_new_dual_pde_address_big_shift_v();
+		nvgpu_assert(u64_hi32(tmp_addr) == 0U);
+		big_addr = (u32)tmp_addr;
+
+		pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(big_addr);
+		pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f();
+		pde_v[0] |= nvgpu_aperture_mask(g, next_pd->mem,
+			gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(),
+			gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(),
+			gmmu_new_dual_pde_aperture_big_video_memory_f());
+		pde_v[1] |= big_addr >> 28;
+	}
+
+	nvgpu_pd_write(g, pd, (size_t)nvgpu_safe_add_u32(pd_offset, 0U),
+								pde_v[0]);
+	nvgpu_pd_write(g, pd, (size_t)nvgpu_safe_add_u32(pd_offset, 1U),
+								pde_v[1]);
+	nvgpu_pd_write(g, pd, (size_t)nvgpu_safe_add_u32(pd_offset, 2U),
+								pde_v[2]);
+	nvgpu_pd_write(g, pd, (size_t)nvgpu_safe_add_u32(pd_offset, 3U),
+								pde_v[3]);
+
+	pte_dbg(g, attrs,
+		"PDE: i=%-4u size=%-2u offs=%-4u pgsz: %c%c | "
+		"GPU %#-12llx  phys %#-12llx "
+		"[0x%08x, 0x%08x, 0x%08x, 0x%08x]",
+		pd_idx, l->entry_size, pd_offset,
+		small_valid ? 'S' : '-',
+		big_valid ?   'B' : '-',
+		virt_addr, phys_addr,
+		pde_v[3], pde_v[2], pde_v[1], pde_v[0]);
+}
+
+static void ga10b_update_pte(struct vm_gk20a *vm,
+		       u32 *pte_w,
+		       u64 phys_addr,
+		       struct nvgpu_gmmu_attrs *attrs)
+{
+	struct gk20a *g = gk20a_from_vm(vm);
+#ifdef CONFIG_NVGPU_COMPRESSION
+	u64 ctag_granularity = g->ops.fb.compression_page_size(g);
+	u32 page_size = vm->gmmu_page_sizes[attrs->pgsz];
+#endif
+	u32 pte_valid = attrs->valid ?
+		gmmu_new_pte_valid_true_f() :
+		gmmu_new_pte_valid_false_f();
+	u64 phys_shifted = phys_addr >> gmmu_new_pte_address_shift_v();
+	u32 pte_addr = (attrs->aperture == APERTURE_SYSMEM) ?
+		gmmu_new_pte_address_sys_f(u64_lo32(phys_shifted)) :
+		gmmu_new_pte_address_vid_f(u64_lo32(phys_shifted));
+	u32 pte_tgt = nvgpu_gmmu_aperture_mask(g,
+					attrs->aperture,
+					attrs->platform_atomic,
+					gmmu_new_pte_aperture_sys_mem_ncoh_f(),
+					gmmu_new_pte_aperture_sys_mem_coh_f(),
+					gmmu_new_pte_aperture_video_memory_f());
+	u64 tmp_addr;
+
+	pte_w[0] = pte_valid | pte_addr | pte_tgt;
+
+	if (attrs->priv) {
+		pte_w[0] |= gmmu_new_pte_privilege_true_f();
+	}
+
+	tmp_addr = phys_addr >> (24U + gmmu_new_pte_address_shift_v());
+	nvgpu_assert(u64_hi32(tmp_addr) == 0U);
+	pte_w[1] = (u32)tmp_addr |
+		gmmu_new_pte_kind_f(attrs->kind_v);
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+	if (attrs->cbc_comptagline_mode) {
+		pte_w[1] |=
+			gmmu_new_pte_comptagline_f(nvgpu_safe_cast_u64_to_u32(
+			    	attrs->ctag / ctag_granularity));
+	}
+
+	if (attrs->ctag != 0ULL) {
+		attrs->ctag = nvgpu_safe_add_u64(attrs->ctag, (u64)page_size);
+	}
+#endif
+
+	if (attrs->rw_flag == gk20a_mem_flag_read_only) {
+		pte_w[0] |= gmmu_new_pte_read_only_true_f();
+	}
+
+	if (!attrs->valid && !attrs->cacheable) {
+		pte_w[0] |= gmmu_new_pte_read_only_true_f();
+	} else {
+		if (!attrs->cacheable) {
+			pte_w[0] |= gmmu_new_pte_vol_true_f();
+		}
+	}
+}
+
+static void ga10b_update_pte_sparse(u32 *pte_w)
+{
+	pte_w[0] = gmmu_new_pte_valid_false_f();
+	pte_w[0] |= gmmu_new_pte_vol_true_f();
+}
+
+static void ga10b_update_gmmu_pte_locked(struct vm_gk20a *vm,
+				   const struct gk20a_mmu_level *l,
+				   struct nvgpu_gmmu_pd *pd,
+				   u32 pd_idx,
+				   u64 virt_addr,
+				   u64 phys_addr,
+				   struct nvgpu_gmmu_attrs *attrs)
+{
+	struct gk20a *g = vm->mm->g;
+	u32 page_size  = vm->gmmu_page_sizes[attrs->pgsz];
+	u32 pd_offset = nvgpu_pd_offset_from_index(l, pd_idx);
+	u32 pte_w[2] = {0, 0};
+
+	if (phys_addr != 0ULL) {
+		ga10b_update_pte(vm, pte_w, phys_addr, attrs);
+	} else {
+		if (attrs->sparse) {
+			ga10b_update_pte_sparse(pte_w);
+		}
+	}
+
+	nvgpu_pte_dbg_print(g, attrs, vm->name, pd_idx, l->entry_size,
+		virt_addr, phys_addr, page_size, pte_w);
+
+	nvgpu_pd_write(g, pd, (size_t)nvgpu_safe_add_u32(pd_offset, 0U),
+								pte_w[0]);
+	nvgpu_pd_write(g, pd, (size_t)nvgpu_safe_add_u32(pd_offset, 1U),
+								pte_w[1]);
+}
+
+/*
+ * Calculate the pgsz of the pde level
+ * Pascal+ implements a 5 level page table structure with only the last
+ * level having a different number of entries depending on whether it holds
+ * big pages or small pages.
+ */
+static u32 ga10b_get_pde0_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
+				struct nvgpu_gmmu_pd *pd, u32 pd_idx)
+{
+	u32 pde_base = pd->mem_offs / (u32)sizeof(u32);
+	u32 pde_offset = nvgpu_safe_add_u32(pde_base,
+					nvgpu_pd_offset_from_index(l, pd_idx));
+	u32 pde_v[GA10B_PDE0_ENTRY_SIZE >> 2];
+	u32 idx;
+	u32 pgsz = GMMU_NR_PAGE_SIZES;
+
+	if (pd->mem == NULL) {
+		return pgsz;
+	}
+
+	for (idx = 0; idx < (GA10B_PDE0_ENTRY_SIZE >> 2); idx++) {
+		pde_v[idx] =
+			nvgpu_mem_rd32(g, pd->mem, (u64)pde_offset + (u64)idx);
+	}
+
+	/*
+	 * Check if the aperture AND address are set
+	 */
+	if ((pde_v[2] &
+		(gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() |
+		 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f() |
+		 gmmu_new_dual_pde_aperture_small_video_memory_f())) != 0U) {
+		u32 new_pde_addr_small_sys =
+			gmmu_new_dual_pde_address_small_sys_f(~U32(0U));
+		u64 addr = ((U64(pde_v[3]) << U64(32)) |
+			(U64(pde_v[2]) & U64(new_pde_addr_small_sys))) <<
+			U64(gmmu_new_dual_pde_address_shift_v());
+
+		if (addr != 0ULL) {
+			pgsz = GMMU_PAGE_SIZE_SMALL;
+		}
+	}
+
+	if ((pde_v[0] &
+		(gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() |
+		 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() |
+		 gmmu_new_dual_pde_aperture_big_video_memory_f())) != 0U) {
+		u32 new_pde_addr_big_sys =
+				gmmu_new_dual_pde_address_big_sys_f(~U32(0U));
+		u64 addr = ((U64(pde_v[1]) << U64(32)) |
+			(U64(pde_v[0]) & U64(new_pde_addr_big_sys))) <<
+			U64(gmmu_new_dual_pde_address_big_shift_v());
+
+		if (addr != 0ULL) {
+			/*
+			 * If small is set that means that somehow MM allowed
+			 * both small and big to be set, the PDE is not valid
+			 * and may be corrupted
+			 */
+			if (pgsz == GMMU_PAGE_SIZE_SMALL) {
+				nvgpu_err(g,
+					"both small and big apertures enabled");
+				return GMMU_NR_PAGE_SIZES;
+			}
+			pgsz = GMMU_PAGE_SIZE_BIG;
+		}
+	}
+
+	return pgsz;
+}
+
+static const struct gk20a_mmu_level ga10b_mm_levels[] = {
+	{.hi_bit = {48, 48},
+	 .lo_bit = {47, 47},
+	 .update_entry = ga10b_update_gmmu_pde3_locked,
+	 .entry_size = GA10B_PDE_DEFAULT_ENTRY_SIZE,
+	 .get_pgsz = gk20a_get_pde_pgsz},
+	{.hi_bit = {46, 46},
+	 .lo_bit = {38, 38},
+	 .update_entry = ga10b_update_gmmu_pde3_locked,
+	 .entry_size = GA10B_PDE_DEFAULT_ENTRY_SIZE,
+	 .get_pgsz = gk20a_get_pde_pgsz},
+	{.hi_bit = {37, 37},
+	 .lo_bit = {29, 29},
+	 .update_entry = ga10b_update_gmmu_pde3_locked,
+	 .entry_size = GA10B_PDE_DEFAULT_ENTRY_SIZE,
+	 .get_pgsz = gk20a_get_pde_pgsz},
+	{.hi_bit = {28, 28},
+	 .lo_bit = {21, 21},
+	 .update_entry = ga10b_update_gmmu_pde0_locked,
+	 .entry_size = GA10B_PDE0_ENTRY_SIZE,
+	 .get_pgsz = ga10b_get_pde0_pgsz},
+	{.hi_bit = {20, 20},
+	 .lo_bit = {12, 16},
+	 .update_entry = ga10b_update_gmmu_pte_locked,
+	 .entry_size = GA10B_PTE_ENTRY_SIZE,
+	 .get_pgsz = gk20a_get_pte_pgsz},
+	{.update_entry = NULL}
+};
+
+const struct gk20a_mmu_level *ga10b_mm_get_mmu_levels(struct gk20a *g,
+	u64 big_page_size)
+{
+	return ga10b_mm_levels;
+}
+
+u32 ga10b_get_max_page_table_levels(struct gk20a *g)
+{
+	return GA10B_MAX_PAGE_TABLE_LEVELS;
+}
diff --git a/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_ga10b.h b/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_ga10b.h
new file mode 100644
index 000000000..51fd06563
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_ga10b.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef HAL_MM_MMU_FAULT_MMU_FAULT_GA10B_H
+#define HAL_MM_MMU_FAULT_MMU_FAULT_GA10B_H
+
+struct mmu_fault_info;
+
+void ga10b_mm_mmu_fault_parse_mmu_fault_info(struct mmu_fault_info *mmufault);
+
+#endif /* HAL_MM_MMU_FAULT_MMU_FAULT_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_ga10b_fusa.c
new file mode 100644
index 000000000..33c812805
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_ga10b_fusa.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/dma.h>
+#include <nvgpu/log.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/gmmu.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/mmu_fault.h>
+
+#include "hal/mm/mmu_fault/mmu_fault_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_gmmu_ga10b.h>
+
+static const char mmufault_invalid_str[] = "invalid";
+
+static const char *const ga10b_fault_type_descs[] = {
+	"invalid pde",
+	"invalid pde size",
+	"invalid pte",
+	"limit violation",
+	"unbound inst block",
+	"priv violation",
+	"write, ro violation",
+	"read, wo violation",
+	"pitch mask violation",
+	"work creation",
+	"unsupported aperture",
+	"compression failure",
+	"unsupported kind",
+	"region violation",
+	"poison",
+	"atomic violation"
+};
+
+static const char *const ga10b_fault_client_type_descs[] = {
+	"gpc",
+	"hub",
+};
+
+static const char *const ga10b_hub_client_descs[] = {
+	"vip", "ce0", "ce1", "dniso",
+	"dispniso", "fe0", "fe", "fecs0",
+	"fecs", "host", "host_cpu", "host_cpu_nb",
+	"iso", "mmu", "nvdec0", "nvdec",
+	"ce3", "nvenc1", "niso", "actrs",
+	"p2p", "pd", "perf0/perf", "pmu",
+	"rastertwod", "scc", "scc nb", "sec",
+	"ssync", "grcopy/ce2", "xv", "mmu nb",
+	"nvenc0/nvenc", "unused", "sked0/sked",
+	"dont_care",
+	"hsce0", "hsce1", "hsce2", "hsce3", "hsce4", "hsce5", "hsce6",
+	"hsce7", "hsce8", "hsce9",
+	"hshub", "ptp_x0", "ptp_x1", "ptp_x2", "ptp_x3",
+	"ptp_x4", "ptp_x5", "ptp_x6", "ptp_x7",
+	"nvenc2", "vpr scrubber0", "vpr scrubber1", "dwbif", "fbfalcon",
+	"ce shim", "gsp",
+	"nvdec1", "nvdec2", "nvjpg0", "nvdec3", "nvdec4", "ofa0",
+	"hsce10", "hsce11", "hsce12", "hsce13", "hsce14", "hsce15",
+	"ptp_x8", "ptp_x9", "ptp_x10", "ptp_x11", "ptp_x12",
+	"ptp_x13", "ptp_x14", "ptp_x15",
+	"fe1", "fe2", "fe3", "fe4", "fe5", "fe6", "fe7",
+	"fecs1", "fecs2", "fecs3", "fecs4", "fecs5", "fecs6", "fecs7",
+	"sked1", "sked2", "sked3", "sked4", "sked5", "sked6", "sked7",
+	"esc"
+};
+
+static const char *const ga10b_gpc_client_descs[] = {
+	"t1_0", "t1_1", "t1_2", "t1_3",
+	"t1_4", "t1_5", "t1_6", "t1_7",
+	"pe_0", "pe_1", "pe_2", "pe_3",
+	"pe_4", "pe_5", "pe_6", "pe_7",
+	"rast", "gcc", "gpccs",
+	"prop_0", "prop_1", "prop_2", "prop_3",
+	"t1_8", "t1_9", "t1_10", "t1_11",
+	"t1_12", "t1_13", "t1_14", "t1_15",
+	"tpccs_0", "tpccs_1", "tpccs_2", "tpccs_3",
+	"tpccs_4", "tpccs_5", "tpccs_6", "tpccs_7",
+	"pe_8", "pe_9", "tpccs_8", "tpccs_9",
+	"t1_16", "t1_17", "t1_18", "t1_19",
+	"pe_8",  "pe_9", "tpccs_8", "tpccs_9",
+	"t1_16", "t1_17", "t1_18", "t1_19",
+	"pe_10", "pe_11", "tpccs_10", "tpccs_11",
+	"t1_20", "t1_21", "t1_22", "t1_23",
+	"pe_12", "pe_13", "tpccs_12", "tpccs_13",
+	"t1_24", "t1_25", "t1_26", "t1_27",
+	"pe_14", "pe_15", "tpccs_14", "tpccs_15",
+	"t1_28", "t1_29", "t1_30", "t1_31",
+	"pe_16", "pe_17", "tpccs_16", "tpccs_17",
+	"t1_32", "t1_33", "t1_34", "t1_35",
+	"pe_18", "pe_19", "tpccs_18", "tpccs_19",
+	"t1_36", "t1_37", "t1_38", "t1_39",
+	"rop_0", "rop_1", "rop_2", "rop_3",
+};
+
+void ga10b_mm_mmu_fault_parse_mmu_fault_info(struct mmu_fault_info *mmufault)
+{
+	if (mmufault->mmu_engine_id == gmmu_fault_mmu_eng_id_bar2_v()) {
+		mmufault->mmu_engine_id_type = NVGPU_MMU_ENGINE_ID_TYPE_BAR2;
+
+	} else if (mmufault->mmu_engine_id ==
+			gmmu_fault_mmu_eng_id_physical_v()) {
+		mmufault->mmu_engine_id_type = NVGPU_MMU_ENGINE_ID_TYPE_PHYSICAL;
+	} else {
+		mmufault->mmu_engine_id_type = NVGPU_MMU_ENGINE_ID_TYPE_OTHER;
+	}
+
+	if (mmufault->fault_type > gmmu_fault_fault_type_atomic_violation_v()) {
+		nvgpu_do_assert();
+		mmufault->fault_type_desc = mmufault_invalid_str;
+	} else {
+		mmufault->fault_type_desc =
+			 ga10b_fault_type_descs[mmufault->fault_type];
+	}
+
+	if (mmufault->client_type > gmmu_fault_client_type_hub_v()) {
+		nvgpu_do_assert();
+		mmufault->client_type_desc = mmufault_invalid_str;
+	} else {
+		mmufault->client_type_desc =
+			 ga10b_fault_client_type_descs[mmufault->client_type];
+	}
+
+	mmufault->client_id_desc = mmufault_invalid_str;
+	if (mmufault->client_type == gmmu_fault_client_type_hub_v()) {
+		if (mmufault->client_id <= gmmu_fault_client_hub_esc_v()) {
+			mmufault->client_id_desc =
+				 ga10b_hub_client_descs[mmufault->client_id] ==
+					NULL ? "TBD" :
+				ga10b_hub_client_descs[mmufault->client_id];
+		} else {
+			nvgpu_do_assert();
+		}
+	} else if (mmufault->client_type ==
+			gmmu_fault_client_type_gpc_v()) {
+		if (mmufault->client_id <= gmmu_fault_client_gpc_rop_3_v()) {
+			mmufault->client_id_desc =
+				 ga10b_gpc_client_descs[mmufault->client_id] ==
+					NULL ? "TBD" :
+				ga10b_gpc_client_descs[mmufault->client_id];
+		} else {
+			nvgpu_do_assert();
+		}
+	} else {
+		/* Nothing to do here */
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/netlist/netlist_ga100.c b/drivers/gpu/nvgpu/hal/netlist/netlist_ga100.c
new file mode 100644
index 000000000..6146632dd
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/netlist/netlist_ga100.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+
+#include "nvgpu_next_gpuid.h"
+
+#include "netlist_ga100.h"
+
+int ga100_netlist_get_name(struct gk20a *g, int index, char *name)
+{
+	u32 ver = g->params.gpu_arch + g->params.gpu_impl;
+	int valid = 0;
+
+	switch (ver) {
+	case NVGPU_NEXT_DGPU_GPUID:
+		(void) strcpy(name, "ga100/");
+		(void) strcat(name, GA100_NETLIST_IMAGE_FW_NAME);
+		break;
+	default:
+		nvgpu_err(g, "no support for GPUID %x", ver);
+		valid = -1;
+		break;
+	}
+
+	return valid;
+}
+
+bool ga100_netlist_is_firmware_defined(void)
+{
+#ifdef GA100_NETLIST_IMAGE_FW_NAME
+	return true;
+#else
+	return false;
+#endif
+}
diff --git a/drivers/gpu/nvgpu/hal/netlist/netlist_ga100.h b/drivers/gpu/nvgpu/hal/netlist/netlist_ga100.h
new file mode 100644
index 000000000..d8ad5a464
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/netlist/netlist_ga100.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NETLIST_GA100_H
+#define NVGPU_NETLIST_GA100_H
+
+#include <nvgpu/types.h>
+#include "common/netlist/netlist_defs.h"
+
+struct gk20a;
+
+#define GA100_NETLIST_IMAGE_FW_NAME NVGPU_NETLIST_IMAGE_C
+
+int ga100_netlist_get_name(struct gk20a *g, int index, char *name);
+bool ga100_netlist_is_firmware_defined(void);
+
+#endif /*NVGPU_NETLIST_GA100_H*/
diff --git a/drivers/gpu/nvgpu/hal/netlist/netlist_ga10b.h b/drivers/gpu/nvgpu/hal/netlist/netlist_ga10b.h
new file mode 100644
index 000000000..5f7dc51c6
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/netlist/netlist_ga10b.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NETLIST_GA10B_H
+#define NVGPU_NETLIST_GA10B_H
+
+#include <nvgpu/types.h>
+#include "common/netlist/netlist_defs.h"
+
+struct gk20a;
+
+/* NVGPU_NETLIST_IMAGE_A is FNL for ga10b */
+#define GA10B_NETLIST_IMAGE_FW_NAME NVGPU_NETLIST_IMAGE_A
+
+int ga10b_netlist_get_name(struct gk20a *g, int index, char *name);
+bool ga10b_netlist_is_firmware_defined(void);
+
+#endif /* NVGPU_NETLIST_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/netlist/netlist_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/netlist/netlist_ga10b_fusa.c
new file mode 100644
index 000000000..117686a8c
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/netlist/netlist_ga10b_fusa.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+
+#include "netlist_ga10b.h"
+
+int ga10b_netlist_get_name(struct gk20a *g, int index, char *name)
+{
+	int ret = 0;
+
+	switch (index) {
+#ifdef GA10B_NETLIST_IMAGE_FW_NAME
+	case NETLIST_FINAL:
+		(void) strcpy(name, GA10B_NETLIST_IMAGE_FW_NAME);
+		break;
+#else
+#ifdef CONFIG_NVGPU_NON_FUSA
+#ifdef NVGPU_NETLIST_IMAGE_A
+	case NETLIST_SLOT_A:
+		(void) strcpy(name, NVGPU_NETLIST_IMAGE_A);
+		break;
+#endif
+#ifdef NVGPU_NETLIST_IMAGE_B
+	case NETLIST_SLOT_B:
+		(void) strcpy(name, NVGPU_NETLIST_IMAGE_B);
+		break;
+#endif
+#ifdef NVGPU_NETLIST_IMAGE_C
+	case NETLIST_SLOT_C:
+		(void) strcpy(name, NVGPU_NETLIST_IMAGE_C);
+		break;
+#endif
+#ifdef NVGPU_NETLIST_IMAGE_D
+	case NETLIST_SLOT_D:
+		(void) strcpy(name, NVGPU_NETLIST_IMAGE_D);
+		break;
+#endif
+#endif
+#endif
+	default:
+		ret = -ENOENT;
+		break;
+
+	}
+
+	return ret;
+}
+
+bool ga10b_netlist_is_firmware_defined(void)
+{
+#ifdef GA10B_NETLIST_IMAGE_FW_NAME
+	return true;
+#else
+	return false;
+#endif
+}
diff --git a/drivers/gpu/nvgpu/hal/nvdec/nvdec_ga100.c b/drivers/gpu/nvgpu/hal/nvdec/nvdec_ga100.c
new file mode 100644
index 000000000..42405e017
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/nvdec/nvdec_ga100.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nvdec_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_pnvdec_ga100.h>
+
+u32 ga100_nvdec_falcon_base_addr(void)
+{
+	return pnvdec_falcon_irqsset_r(0);
+}
diff --git a/drivers/gpu/nvgpu/hal/nvdec/nvdec_ga100.h b/drivers/gpu/nvgpu/hal/nvdec/nvdec_ga100.h
new file mode 100644
index 000000000..22121fa90
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/nvdec/nvdec_ga100.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NVDEC_GA100_H
+#define NVGPU_NVDEC_GA100_H
+
+#include <nvgpu/types.h>
+
+u32 ga100_nvdec_falcon_base_addr(void);
+
+#endif /* NVGPU_NVDEC_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/perf/perf_ga100.c b/drivers/gpu/nvgpu/hal/perf/perf_ga100.c
new file mode 100644
index 000000000..0d1dab36d
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/perf/perf_ga100.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+
+#include "perf_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_perf_ga100.h>
+
+static const u32 hwpm_sys_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x00260000,
+	0x00260004,
+	0x00260008,
+	0x0026000c,
+	0x00260010,
+	0x00260014,
+	0x00260020,
+	0x00260024,
+	0x00260028,
+	0x0026002c,
+	0x00260030,
+	0x00260034,
+	0x00260040,
+	0x00260044,
+	0x00260048,
+	0x0026004c,
+	0x00260050,
+	0x00260054,
+	0x00260058,
+	0x0026005c,
+	0x00260060,
+	0x00260064,
+	0x00260068,
+	0x0026006c,
+	0x00260070,
+	0x00260074,
+	0x00260078,
+	0x0026007c,
+	0x00260080,
+	0x00260084,
+	0x00260088,
+	0x0026008c,
+	0x00260090,
+	0x00260094,
+	0x00260098,
+	0x0026009c,
+	0x002600a0,
+	0x002600a4,
+	0x002600a8,
+	0x002600ac,
+	0x002600b0,
+	0x002600b4,
+	0x002600b8,
+	0x002600bc,
+	0x002600c0,
+	0x002600c4,
+	0x002600c8,
+	0x002600cc,
+	0x002600d0,
+	0x002600d4,
+	0x002600d8,
+	0x002600dc,
+	0x002600e0,
+	0x002600e4,
+	0x002600e8,
+	0x002600ec,
+	0x002600f8,
+	0x002600fc,
+	0x00260104,
+	0x00260108,
+	0x0026010c,
+	0x00260110,
+	0x00260128,
+	0x00260114,
+	0x00260118,
+	0x0026011c,
+	0x00260124,
+	0x00260130,
+	0x00260100,
+};
+
+static const u32 hwpm_gpc_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x00278000,
+	0x00278004,
+	0x00278008,
+	0x0027800c,
+	0x00278010,
+	0x00278014,
+	0x00278020,
+	0x00278024,
+	0x00278028,
+	0x0027802c,
+	0x00278030,
+	0x00278034,
+	0x00278040,
+	0x00278044,
+	0x00278048,
+	0x0027804c,
+	0x00278050,
+	0x00278054,
+	0x00278058,
+	0x0027805c,
+	0x00278060,
+	0x00278064,
+	0x00278068,
+	0x0027806c,
+	0x00278070,
+	0x00278074,
+	0x00278078,
+	0x0027807c,
+	0x00278080,
+	0x00278084,
+	0x00278088,
+	0x0027808c,
+	0x00278090,
+	0x00278094,
+	0x00278098,
+	0x0027809c,
+	0x002780a0,
+	0x002780a4,
+	0x002780a8,
+	0x002780ac,
+	0x002780b0,
+	0x002780b4,
+	0x002780b8,
+	0x002780bc,
+	0x002780c0,
+	0x002780c4,
+	0x002780c8,
+	0x002780cc,
+	0x002780d0,
+	0x002780d4,
+	0x002780d8,
+	0x002780dc,
+	0x002780e0,
+	0x002780e4,
+	0x002780e8,
+	0x002780ec,
+	0x002780f8,
+	0x002780fc,
+	0x00278104,
+	0x00278108,
+	0x0027810c,
+	0x00278110,
+	0x00278128,
+	0x00278114,
+	0x00278118,
+	0x0027811c,
+	0x00278124,
+	0x00278130,
+	0x00278100,
+};
+
+static const u32 hwpm_fbp_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x0027c000,
+	0x0027c004,
+	0x0027c008,
+	0x0027c00c,
+	0x0027c010,
+	0x0027c014,
+	0x0027c020,
+	0x0027c024,
+	0x0027c028,
+	0x0027c02c,
+	0x0027c030,
+	0x0027c034,
+	0x0027c040,
+	0x0027c044,
+	0x0027c048,
+	0x0027c04c,
+	0x0027c050,
+	0x0027c054,
+	0x0027c058,
+	0x0027c05c,
+	0x0027c060,
+	0x0027c064,
+	0x0027c068,
+	0x0027c06c,
+	0x0027c070,
+	0x0027c074,
+	0x0027c078,
+	0x0027c07c,
+	0x0027c080,
+	0x0027c084,
+	0x0027c088,
+	0x0027c08c,
+	0x0027c090,
+	0x0027c094,
+	0x0027c098,
+	0x0027c09c,
+	0x0027c0a0,
+	0x0027c0a4,
+	0x0027c0a8,
+	0x0027c0ac,
+	0x0027c0b0,
+	0x0027c0b4,
+	0x0027c0b8,
+	0x0027c0bc,
+	0x0027c0c0,
+	0x0027c0c4,
+	0x0027c0c8,
+	0x0027c0cc,
+	0x0027c0d0,
+	0x0027c0d4,
+	0x0027c0d8,
+	0x0027c0dc,
+	0x0027c0e0,
+	0x0027c0e4,
+	0x0027c0e8,
+	0x0027c0ec,
+	0x0027c0f8,
+	0x0027c0fc,
+	0x0027c104,
+	0x0027c108,
+	0x0027c10c,
+	0x0027c110,
+	0x0027c128,
+	0x0027c114,
+	0x0027c118,
+	0x0027c11c,
+	0x0027c124,
+	0x0027c130,
+	0x0027c100,
+};
+
+const u32 *ga100_perf_get_hwpm_sys_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_sys_perfmon_regs) / sizeof(hwpm_sys_perfmon_regs[0]);
+	return hwpm_sys_perfmon_regs;
+}
+
+const u32 *ga100_perf_get_hwpm_gpc_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_gpc_perfmon_regs) / sizeof(hwpm_gpc_perfmon_regs[0]);
+	return hwpm_gpc_perfmon_regs;
+}
+
+const u32 *ga100_perf_get_hwpm_fbp_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_fbp_perfmon_regs) / sizeof(hwpm_fbp_perfmon_regs[0]);
+	return hwpm_fbp_perfmon_regs;
+}
+
+u32 ga100_perf_get_pmmsys_per_chiplet_offset(void)
+{
+	/*
+	 * No register to find the offset of pmmsys register.
+	 * Difference of pmmsys register address ranges plus 1 will provide
+	 * the offset
+	 */
+	u32 reg_offset = 1U;
+
+	return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + reg_offset);
+}
+
+u32 ga100_perf_get_pmmgpc_per_chiplet_offset(void)
+{
+	/*
+	 * No register to find the offset of pmmgpc register.
+	 * Difference of pmmgpc register address ranges plus 1 will provide
+	 * the offset
+	 */
+	u32 reg_offset = 1U;
+
+	return (perf_pmmgpc_extent_v() - perf_pmmgpc_base_v() + reg_offset);
+}
+
+u32 ga100_perf_get_pmmfbp_per_chiplet_offset(void)
+{
+	/*
+	 * No register to find the offset of pmmfbp register.
+	 * Difference of pmmfbp register address ranges plus 1 will provide
+	 * the offset
+	 */
+	u32 reg_offset = 1U;
+
+	return (perf_pmmfbp_extent_v() - perf_pmmfbp_base_v() + reg_offset);
+}
+
+void ga100_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
+				u32 *num_fbp_perfmon, u32 *num_gpc_perfmon)
+{
+	int err;
+	u32 buf_offset_lo, buf_offset_addr, num_offsets;
+	u32 perfmon_index = 0U;
+	u32 max_offsets = 1U;
+
+	for (perfmon_index = 0U; perfmon_index <
+			perf_pmmsys_engine_sel__size_1_v();
+			perfmon_index++) {
+		err = g->ops.gr.get_pm_ctx_buffer_offsets(g,
+				perf_pmmsys_engine_sel_r(perfmon_index),
+				max_offsets,
+				&buf_offset_lo,
+				&buf_offset_addr,
+				&num_offsets);
+		if (err != 0U) {
+			break;
+		}
+	}
+	*num_sys_perfmon = perfmon_index;
+
+	for (perfmon_index = 0U; perfmon_index <
+			perf_pmmfbp_engine_sel__size_1_v();
+			perfmon_index++) {
+		err = g->ops.gr.get_pm_ctx_buffer_offsets(g,
+				perf_pmmfbp_engine_sel_r(perfmon_index),
+				max_offsets,
+				&buf_offset_lo,
+				&buf_offset_addr,
+				&num_offsets);
+		if (err != 0U) {
+			break;
+		}
+	}
+	*num_fbp_perfmon = perfmon_index;
+
+	for (perfmon_index = 0U; perfmon_index <
+			perf_pmmgpc_engine_sel__size_1_v();
+			perfmon_index++) {
+		err = g->ops.gr.get_pm_ctx_buffer_offsets(g,
+				perf_pmmgpc_engine_sel_r(perfmon_index),
+				max_offsets,
+				&buf_offset_lo,
+				&buf_offset_addr,
+				&num_offsets);
+		if (err != 0U) {
+			break;
+		}
+	}
+	*num_gpc_perfmon = perfmon_index;
+}
diff --git a/drivers/gpu/nvgpu/hal/perf/perf_ga100.h b/drivers/gpu/nvgpu/hal/perf/perf_ga100.h
new file mode 100644
index 000000000..5c7592653
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/perf/perf_ga100.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GA100_PERF
+#define NVGPU_GA100_PERF
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+u32 ga100_perf_get_pmmsys_per_chiplet_offset(void);
+u32 ga100_perf_get_pmmgpc_per_chiplet_offset(void);
+u32 ga100_perf_get_pmmfbp_per_chiplet_offset(void);
+
+const u32 *ga100_perf_get_hwpm_sys_perfmon_regs(u32 *count);
+const u32 *ga100_perf_get_hwpm_gpc_perfmon_regs(u32 *count);
+const u32 *ga100_perf_get_hwpm_fbp_perfmon_regs(u32 *count);
+
+void ga100_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
+		u32 *num_fbp_perfmon, u32 *num_gpc_perfmon);
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#endif
diff --git a/drivers/gpu/nvgpu/hal/perf/perf_ga10b.c b/drivers/gpu/nvgpu/hal/perf/perf_ga10b.c
new file mode 100644
index 000000000..68e144cfa
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/perf/perf_ga10b.c
@@ -0,0 +1,743 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/mm.h>
+#include <nvgpu/fbp.h>
+#include <nvgpu/gr/gr_utils.h>
+#include <nvgpu/gr/config.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/gk20a.h>
+
+#include "perf_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_perf_ga10b.h>
+
+#define PMM_ROUTER_OFFSET	0x200U
+
+/*
+ * Only 1 instance is supported for pmasys_channel_* registers in ga10b
+ */
+const u32 pmasys_channel_instance_max_size = 0x1U;
+const u32 inst_zero = 0U;
+
+static const u32 hwpm_sys_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x00260000,
+	0x00260004,
+	0x00260008,
+	0x0026000c,
+	0x00260010,
+	0x00260014,
+	0x00260020,
+	0x00260024,
+	0x00260028,
+	0x0026002c,
+	0x00260030,
+	0x00260034,
+	0x00260040,
+	0x00260044,
+	0x00260048,
+	0x0026004c,
+	0x00260050,
+	0x00260054,
+	0x00260058,
+	0x0026005c,
+	0x00260060,
+	0x00260064,
+	0x00260068,
+	0x0026006c,
+	0x00260070,
+	0x00260074,
+	0x00260078,
+	0x0026007c,
+	0x00260080,
+	0x00260084,
+	0x00260088,
+	0x0026008c,
+	0x00260090,
+	0x00260098,
+	0x0026009c,
+	0x002600a0,
+	0x002600a4,
+	0x002600a8,
+	0x002600ac,
+	0x002600b0,
+	0x002600b4,
+	0x002600b8,
+	0x002600bc,
+	0x002600c0,
+	0x002600c4,
+	0x002600c8,
+	0x002600cc,
+	0x002600d0,
+	0x002600d4,
+	0x002600d8,
+	0x002600dc,
+	0x002600e0,
+	0x002600e4,
+	0x002600e8,
+	0x002600ec,
+	0x002600f8,
+	0x002600fc,
+	0x00260108,
+	0x00260110,
+	0x00260128,
+	0x00260114,
+	0x00260118,
+	0x0026011c,
+	0x00260124,
+	0x00260130,
+	0x00260100,
+};
+
+static const u32 hwpm_gpc_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x00278000,
+	0x00278004,
+	0x00278008,
+	0x0027800c,
+	0x00278010,
+	0x00278014,
+	0x00278020,
+	0x00278024,
+	0x00278028,
+	0x0027802c,
+	0x00278030,
+	0x00278034,
+	0x00278040,
+	0x00278044,
+	0x00278048,
+	0x0027804c,
+	0x00278050,
+	0x00278054,
+	0x00278058,
+	0x0027805c,
+	0x00278060,
+	0x00278064,
+	0x00278068,
+	0x0027806c,
+	0x00278070,
+	0x00278074,
+	0x00278078,
+	0x0027807c,
+	0x00278080,
+	0x00278084,
+	0x00278088,
+	0x0027808c,
+	0x00278090,
+	0x00278098,
+	0x0027809c,
+	0x002780a0,
+	0x002780a4,
+	0x002780a8,
+	0x002780ac,
+	0x002780b0,
+	0x002780b4,
+	0x002780b8,
+	0x002780bc,
+	0x002780c0,
+	0x002780c4,
+	0x002780c8,
+	0x002780cc,
+	0x002780d0,
+	0x002780d4,
+	0x002780d8,
+	0x002780dc,
+	0x002780e0,
+	0x002780e4,
+	0x002780e8,
+	0x002780ec,
+	0x002780f8,
+	0x002780fc,
+	0x00278108,
+	0x00278110,
+	0x00278128,
+	0x00278114,
+	0x00278118,
+	0x0027811c,
+	0x00278124,
+	0x00278130,
+	0x00278100,
+};
+
+static const u32 hwpm_fbp_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x0027c000,
+	0x0027c004,
+	0x0027c008,
+	0x0027c00c,
+	0x0027c010,
+	0x0027c014,
+	0x0027c020,
+	0x0027c024,
+	0x0027c028,
+	0x0027c02c,
+	0x0027c030,
+	0x0027c034,
+	0x0027c040,
+	0x0027c044,
+	0x0027c048,
+	0x0027c04c,
+	0x0027c050,
+	0x0027c054,
+	0x0027c058,
+	0x0027c05c,
+	0x0027c060,
+	0x0027c064,
+	0x0027c068,
+	0x0027c06c,
+	0x0027c070,
+	0x0027c074,
+	0x0027c078,
+	0x0027c07c,
+	0x0027c080,
+	0x0027c084,
+	0x0027c088,
+	0x0027c08c,
+	0x0027c090,
+	0x0027c098,
+	0x0027c09c,
+	0x0027c0a0,
+	0x0027c0a4,
+	0x0027c0a8,
+	0x0027c0ac,
+	0x0027c0b0,
+	0x0027c0b4,
+	0x0027c0b8,
+	0x0027c0bc,
+	0x0027c0c0,
+	0x0027c0c4,
+	0x0027c0c8,
+	0x0027c0cc,
+	0x0027c0d0,
+	0x0027c0d4,
+	0x0027c0d8,
+	0x0027c0dc,
+	0x0027c0e0,
+	0x0027c0e4,
+	0x0027c0e8,
+	0x0027c0ec,
+	0x0027c0f8,
+	0x0027c0fc,
+	0x0027c108,
+	0x0027c110,
+	0x0027c128,
+	0x0027c114,
+	0x0027c118,
+	0x0027c11c,
+	0x0027c124,
+	0x0027c130,
+	0x0027c100,
+};
+
+const u32 *ga10b_perf_get_hwpm_sys_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_sys_perfmon_regs) / sizeof(hwpm_sys_perfmon_regs[0]);
+	return hwpm_sys_perfmon_regs;
+}
+
+const u32 *ga10b_perf_get_hwpm_gpc_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_gpc_perfmon_regs) / sizeof(hwpm_gpc_perfmon_regs[0]);
+	return hwpm_gpc_perfmon_regs;
+}
+
+const u32 *ga10b_perf_get_hwpm_fbp_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_fbp_perfmon_regs) / sizeof(hwpm_fbp_perfmon_regs[0]);
+	return hwpm_fbp_perfmon_regs;
+}
+
+bool ga10b_perf_get_membuf_overflow_status(struct gk20a *g)
+{
+	const u32 st =
+		perf_pmasys_channel_control_membuf_status_overflowed_f();
+
+	nvgpu_assert(perf_pmasys_channel_control__size_1_v() ==
+				pmasys_channel_instance_max_size);
+
+	return st == (nvgpu_readl(g,
+			perf_pmasys_channel_control_r(inst_zero)) & st);
+}
+
+u32 ga10b_perf_get_membuf_pending_bytes(struct gk20a *g)
+{
+	nvgpu_assert(perf_pmasys_channel_mem_bytes__size_1_v() ==
+				pmasys_channel_instance_max_size);
+
+	return nvgpu_readl(g,
+		perf_pmasys_channel_mem_bytes_r(inst_zero));
+}
+
+void ga10b_perf_set_membuf_handled_bytes(struct gk20a *g,
+	u32 entries, u32 entry_size)
+{
+	nvgpu_assert(perf_pmasys_channel_mem_bump__size_1_v() ==
+				pmasys_channel_instance_max_size);
+
+	if (entries > 0U) {
+		nvgpu_writel(g,
+			perf_pmasys_channel_mem_bump_r(inst_zero),
+			entries * entry_size);
+	}
+}
+
+void ga10b_perf_membuf_reset_streaming(struct gk20a *g)
+{
+	u32 engine_status;
+	u32 num_unread_bytes;
+	u32 i;
+
+	nvgpu_assert(perf_pmasys_channel_control__size_1_v() ==
+				pmasys_channel_instance_max_size);
+	nvgpu_assert(perf_pmasys_channel_mem_bytes__size_1_v() ==
+				pmasys_channel_instance_max_size);
+	nvgpu_assert(perf_pmasys_channel_mem_bump__size_1_v() ==
+				pmasys_channel_instance_max_size);
+
+	engine_status = nvgpu_readl(g, perf_pmasys_enginestatus_r());
+	WARN_ON(0U ==
+	       (engine_status & perf_pmasys_enginestatus_rbufempty_empty_f()));
+
+	for (i = 0U; i < perf_pmasys_channel_control__size_1_v(); i++) {
+		nvgpu_writel(g, perf_pmasys_channel_control_r(i),
+		     perf_pmasys_channel_control_membuf_clear_status_doit_f());
+	}
+
+	for (i = 0U; i < perf_pmasys_channel_mem_bytes__size_1_v(); i++) {
+		num_unread_bytes = nvgpu_readl(g,
+					perf_pmasys_channel_mem_bytes_r(i));
+		if (num_unread_bytes != 0U) {
+			nvgpu_writel(g, perf_pmasys_channel_mem_bump_r(i),
+					num_unread_bytes);
+		}
+	}
+}
+
+void ga10b_perf_enable_membuf(struct gk20a *g, u32 size, u64 buf_addr)
+{
+	u32 addr_lo;
+	u32 addr_hi;
+	u32 i;
+
+	nvgpu_assert(perf_pmasys_channel_outbase__size_1_v() ==
+				pmasys_channel_instance_max_size);
+	nvgpu_assert(perf_pmasys_channel_outbaseupper__size_1_v() ==
+				pmasys_channel_instance_max_size);
+	nvgpu_assert(perf_pmasys_channel_outsize__size_1_v() ==
+				pmasys_channel_instance_max_size);
+
+	addr_lo = u64_lo32(buf_addr);
+	addr_hi = u64_hi32(buf_addr);
+
+	for (i = 0U; i < perf_pmasys_channel_outbase__size_1_v(); i++) {
+		nvgpu_writel(g, perf_pmasys_channel_outbase_r(i), addr_lo);
+	}
+
+	for (i = 0U; i < perf_pmasys_channel_outbaseupper__size_1_v(); i++) {
+		nvgpu_writel(g, perf_pmasys_channel_outbaseupper_r(i),
+			perf_pmasys_channel_outbaseupper_ptr_f(addr_hi));
+	}
+
+	for (i = 0U; i < perf_pmasys_channel_outsize__size_1_v(); i++) {
+		nvgpu_writel(g, perf_pmasys_channel_outsize_r(i), size);
+	}
+}
+
+void ga10b_perf_disable_membuf(struct gk20a *g)
+{
+	int zero_value = 0;
+	u32 i;
+
+	nvgpu_assert(perf_pmasys_channel_outbase__size_1_v() ==
+				pmasys_channel_instance_max_size);
+	nvgpu_assert(perf_pmasys_channel_outbaseupper__size_1_v() ==
+				pmasys_channel_instance_max_size);
+	nvgpu_assert(perf_pmasys_channel_outsize__size_1_v() ==
+				pmasys_channel_instance_max_size);
+
+	for (i = 0U; i < perf_pmasys_channel_outbase__size_1_v(); i++) {
+		nvgpu_writel(g, perf_pmasys_channel_outbase_r(i), zero_value);
+	}
+
+	for (i = 0U; i < perf_pmasys_channel_outbaseupper__size_1_v(); i++) {
+		nvgpu_writel(g, perf_pmasys_channel_outbaseupper_r(i),
+			perf_pmasys_channel_outbaseupper_ptr_f(zero_value));
+	}
+
+	for (i = 0U; i < perf_pmasys_channel_outsize__size_1_v(); i++) {
+		nvgpu_writel(g, perf_pmasys_channel_outsize_r(i), zero_value);
+	}
+}
+
+void ga10b_perf_bind_mem_bytes_buffer_addr(struct gk20a *g, u64 buf_addr)
+{
+	u32 addr_lo;
+	u32 i;
+
+	nvgpu_assert(perf_pmasys_channel_mem_bytes_addr__size_1_v() ==
+				pmasys_channel_instance_max_size);
+
+	buf_addr = buf_addr >> perf_pmasys_channel_mem_bytes_addr_ptr_b();
+	addr_lo = nvgpu_safe_cast_u64_to_u32(buf_addr);
+
+	for (i = 0U; i < perf_pmasys_channel_mem_bytes_addr__size_1_v(); i++) {
+		nvgpu_writel(g, perf_pmasys_channel_mem_bytes_addr_r(i),
+				perf_pmasys_channel_mem_bytes_addr_ptr_f(addr_lo));
+	}
+}
+
+void ga10b_perf_init_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block)
+{
+	u32 inst_block_ptr;
+	u32 i;
+
+	nvgpu_assert(perf_pmasys_channel_mem_block__size_1_v() ==
+				pmasys_channel_instance_max_size);
+
+	for (i = 0U; i < perf_pmasys_channel_mem_block__size_1_v(); i++) {
+		inst_block_ptr = nvgpu_inst_block_ptr(g, inst_block);
+
+		nvgpu_writel(g, perf_pmasys_channel_mem_block_r(i),
+		     perf_pmasys_channel_mem_block_base_f(inst_block_ptr) |
+		     perf_pmasys_channel_mem_block_valid_true_f() |
+			nvgpu_aperture_mask(g, inst_block,
+			     perf_pmasys_channel_mem_block_target_sys_ncoh_f(),
+			     perf_pmasys_channel_mem_block_target_sys_coh_f(),
+			     perf_pmasys_channel_mem_block_target_lfb_f()));
+	}
+}
+
+void ga10b_perf_deinit_inst_block(struct gk20a *g)
+{
+	int zero_value = 0;
+	u32 i;
+
+	nvgpu_assert(perf_pmasys_channel_mem_block__size_1_v() ==
+				pmasys_channel_instance_max_size);
+
+	for (i = 0U; i < perf_pmasys_channel_mem_block__size_1_v(); i++) {
+		nvgpu_writel(g, perf_pmasys_channel_mem_block_r(i),
+			perf_pmasys_channel_mem_block_base_f(zero_value) |
+			perf_pmasys_channel_mem_block_valid_false_f() |
+			perf_pmasys_channel_mem_block_target_f(zero_value));
+	}
+}
+
+u32 ga10b_perf_get_pmmsys_per_chiplet_offset(void)
+{
+	/*
+	 * No register to find the offset of pmmsys register.
+	 * Difference of pmmsys register address ranges plus 1 will provide
+	 * the offset
+	 */
+	u32 reg_offset = 1U;
+
+	return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + reg_offset);
+}
+
+u32 ga10b_perf_get_pmmgpc_per_chiplet_offset(void)
+{
+	/*
+	 * No register to find the offset of pmmgpc register.
+	 * Difference of pmmgpc register address ranges plus 1 will provide
+	 * the offset
+	 */
+	u32 reg_offset = 1U;
+
+	return (perf_pmmgpc_extent_v() - perf_pmmgpc_base_v() + reg_offset);
+}
+
+u32 ga10b_perf_get_pmmfbp_per_chiplet_offset(void)
+{
+	/*
+	 * No register to find the offset of pmmfbp register.
+	 * Difference of pmmfbp register address ranges plus 1 will provide
+	 * the offset
+	 */
+	u32 reg_offset = 1U;
+
+	return (perf_pmmfbp_extent_v() - perf_pmmfbp_base_v() + reg_offset);
+}
+
+void ga10b_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
+				u32 *num_fbp_perfmon, u32 *num_gpc_perfmon)
+{
+	int err;
+	u32 buf_offset_lo, buf_offset_addr, num_offsets;
+	u32 perfmon_index = 0U;
+	u32 max_offsets = 1U;
+
+	for (perfmon_index = 0U; perfmon_index <
+			perf_pmmsys_engine_sel__size_1_v();
+			perfmon_index++) {
+		err = g->ops.gr.get_pm_ctx_buffer_offsets(g,
+				perf_pmmsys_engine_sel_r(perfmon_index),
+				max_offsets,
+				&buf_offset_lo,
+				&buf_offset_addr,
+				&num_offsets);
+		if (err != 0U) {
+			break;
+		}
+	}
+	*num_sys_perfmon = perfmon_index;
+
+	for (perfmon_index = 0U; perfmon_index <
+			perf_pmmfbp_engine_sel__size_1_v();
+			perfmon_index++) {
+		err = g->ops.gr.get_pm_ctx_buffer_offsets(g,
+				perf_pmmfbp_engine_sel_r(perfmon_index),
+				max_offsets,
+				&buf_offset_lo,
+				&buf_offset_addr,
+				&num_offsets);
+		if (err != 0U) {
+			break;
+		}
+	}
+	*num_fbp_perfmon = perfmon_index;
+
+	for (perfmon_index = 0U; perfmon_index <
+			perf_pmmgpc_engine_sel__size_1_v();
+			perfmon_index++) {
+		err = g->ops.gr.get_pm_ctx_buffer_offsets(g,
+				perf_pmmgpc_engine_sel_r(perfmon_index),
+				max_offsets,
+				&buf_offset_lo,
+				&buf_offset_addr,
+				&num_offsets);
+		if (err != 0U) {
+			break;
+		}
+	}
+	*num_gpc_perfmon = perfmon_index;
+}
+
+void ga10b_perf_init_hwpm_pmm_register(struct gk20a *g)
+{
+	/* Recheck g10ab can support more  than one chiplet */
+	u32 num_chiplets    = 1U;
+	u32 base_index      = 0U;
+
+	g->ops.perf.set_pmm_register(g, perf_pmmsys_engine_sel_r(base_index),
+				   U32_MAX, num_chiplets,
+				   g->ops.perf.get_pmmsys_per_chiplet_offset(),
+				   g->num_sys_perfmon);
+	g->ops.perf.set_pmm_register(g, perf_pmmfbp_engine_sel_r(base_index),
+				   U32_MAX, nvgpu_fbp_get_num_fbps(g->fbp),
+				   g->ops.perf.get_pmmfbp_per_chiplet_offset(),
+				   g->num_fbp_perfmon);
+	g->ops.perf.set_pmm_register(g, perf_pmmgpc_engine_sel_r(base_index),
+				   U32_MAX,
+				   nvgpu_gr_config_get_gpc_count(nvgpu_gr_get_config_ptr(g)),
+				   g->ops.perf.get_pmmgpc_per_chiplet_offset(),
+				   g->num_gpc_perfmon);
+}
+
+void ga10b_perf_disable_all_perfmons(struct gk20a *g)
+{
+	g->ops.perf.set_pmm_register(g, perf_pmmsys_control_r(0U), 0U, 1U,
+		g->ops.perf.get_pmmsys_per_chiplet_offset(),
+		g->num_sys_perfmon);
+
+	g->ops.perf.set_pmm_register(g, perf_pmmfbp_fbps_control_r(0U), 0U, 1U,
+		g->ops.perf.get_pmmfbp_per_chiplet_offset(),
+		g->num_fbp_perfmon);
+
+	g->ops.perf.set_pmm_register(g, perf_pmmgpc_gpcs_control_r(0U), 0U, 1U,
+		g->ops.perf.get_pmmgpc_per_chiplet_offset(),
+		g->num_gpc_perfmon);
+
+	if (g->ops.priv_ring.read_pri_fence != NULL) {
+		g->ops.priv_ring.read_pri_fence(g);
+	}
+}
+
+int ga10b_perf_update_get_put(struct gk20a *g, u64 bytes_consumed,
+		bool update_available_bytes, u64 *put_ptr,
+		bool *overflowed)
+{
+	u32 val;
+
+	nvgpu_assert(perf_pmasys_channel_mem_bump__size_1_v() ==
+				pmasys_channel_instance_max_size);
+	nvgpu_assert(perf_pmasys_channel_control_user__size_1_v() ==
+				pmasys_channel_instance_max_size);
+	nvgpu_assert(perf_pmasys_channel_mem_head__size_1_v() ==
+				pmasys_channel_instance_max_size);
+
+
+	if (bytes_consumed != 0U) {
+		nvgpu_writel(g, perf_pmasys_channel_mem_bump_r(inst_zero), bytes_consumed);
+	}
+
+	if (update_available_bytes) {
+		val = nvgpu_readl(g, perf_pmasys_channel_control_user_r(inst_zero));
+		val = set_field(val, perf_pmasys_channel_control_user_update_bytes_m(),
+				     perf_pmasys_channel_control_user_update_bytes_doit_f());
+		nvgpu_writel(g, perf_pmasys_channel_control_user_r(inst_zero), val);
+	}
+
+	if (put_ptr) {
+		*put_ptr = (u64)nvgpu_readl(g, perf_pmasys_channel_mem_head_r(inst_zero));
+	}
+
+	if (overflowed) {
+		*overflowed = g->ops.perf.get_membuf_overflow_status(g);
+	}
+
+	return 0;
+}
+
+void ga10b_perf_pma_stream_enable(struct gk20a *g, bool enable)
+{
+	u32 reg_val;
+
+	nvgpu_assert(perf_pmasys_channel_control_user__size_1_v() ==
+				pmasys_channel_instance_max_size);
+
+	reg_val = nvgpu_readl(g, perf_pmasys_channel_control_user_r(inst_zero));
+
+	if (enable) {
+		reg_val = set_field(reg_val,
+				perf_pmasys_channel_control_user_stream_m(),
+				perf_pmasys_channel_control_user_stream_enable_f());
+	} else {
+		reg_val = set_field(reg_val,
+				perf_pmasys_channel_control_user_stream_m(),
+				perf_pmasys_channel_control_user_stream_disable_f());
+	}
+
+	nvgpu_writel(g, perf_pmasys_channel_control_user_r(inst_zero), reg_val);
+}
+
+int ga10b_perf_wait_for_idle_pma(struct gk20a *g)
+{
+	struct nvgpu_timeout timeout;
+	u32 status, rbufempty_status;
+	u32 timeout_ms = 1;
+	u32 reg_val;
+	int err;
+
+	err = nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init timeout");
+		return err;
+	}
+
+	do {
+		reg_val = nvgpu_readl(g, perf_pmasys_enginestatus_r());
+
+		status = perf_pmasys_enginestatus_status_v(reg_val);
+		rbufempty_status = perf_pmasys_enginestatus_rbufempty_v(reg_val);
+
+		if ((status == perf_pmasys_enginestatus_status_empty_v()) &&
+		    (rbufempty_status == perf_pmasys_enginestatus_rbufempty_empty_v())) {
+			return 0;
+		}
+
+		nvgpu_usleep_range(20, 40);
+	} while (nvgpu_timeout_expired(&timeout) == 0);
+
+	return -ETIMEDOUT;
+}
+
+void ga10b_perf_enable_hs_streaming(struct gk20a *g, bool enable)
+{
+	u32 num_gpc, num_fbp;
+	u32 i;
+	u32 val = 0;
+
+	num_gpc = nvgpu_gr_config_get_gpc_count(nvgpu_gr_get_config_ptr(g));
+	num_fbp = nvgpu_fbp_get_num_fbps(g->fbp);
+
+	val = nvgpu_readl(g, perf_pmmsysrouter_global_cntrl_r());
+	if (enable) {
+		val = set_field(val, perf_pmmsysrouter_global_cntrl_hs_stream_enable_m(),
+				perf_pmmsysrouter_global_cntrl_hs_stream_enable_true_f());
+	} else {
+		val = set_field(val, perf_pmmsysrouter_global_cntrl_hs_stream_enable_m(),
+				perf_pmmsysrouter_global_cntrl_hs_stream_enable_false_f());
+	}
+
+	nvgpu_writel(g, perf_pmmsysrouter_global_cntrl_r(), val);
+
+	for (i = 0U; i < num_gpc; ++i) {
+		nvgpu_writel(g, perf_pmmgpcrouter_global_cntrl_r() + (i * PMM_ROUTER_OFFSET),
+				val);
+	}
+
+	for (i = 0U; i < num_fbp; ++i) {
+		nvgpu_writel(g, perf_pmmfbprouter_global_cntrl_r() + (i * PMM_ROUTER_OFFSET),
+				val);
+	}
+
+	if (g->ops.priv_ring.read_pri_fence != NULL) {
+		g->ops.priv_ring.read_pri_fence(g);
+	}
+}
+
+void ga10b_perf_reset_hs_streaming_credits(struct gk20a *g)
+{
+	u32 num_gpc, num_fbp;
+	u32 i;
+	const u32 val = 0; // Set credits to 0.
+
+	num_gpc = nvgpu_gr_config_get_gpc_count(nvgpu_gr_get_config_ptr(g));
+	num_fbp = nvgpu_fbp_get_num_fbps(g->fbp);
+
+	nvgpu_writel(g, perf_pmmsysrouter_hs_config_r(), val);
+	for (i = 0U; i < num_gpc; ++i) {
+		nvgpu_writel(g, perf_pmmgpcrouter_hs_config_r() + (i * PMM_ROUTER_OFFSET),
+				val);
+	}
+
+	for (i = 0U; i < num_fbp; ++i) {
+		nvgpu_writel(g, perf_pmmfbprouter_hs_config_r() + (i * PMM_ROUTER_OFFSET),
+				val);
+	}
+
+	if (g->ops.priv_ring.read_pri_fence != NULL) {
+		g->ops.priv_ring.read_pri_fence(g);
+	}
+}
+
+void ga10b_perf_enable_pmasys_legacy_mode(struct gk20a *g, bool enable)
+{
+	u32 val = 0;
+
+	val = nvgpu_readl(g, perf_pmasys_controlreg_r());
+	if (enable) {
+		val = set_field(val, perf_pmasys_controlreg_legacy_mode_m(),
+				perf_pmasys_controlreg_legacy_mode_enable_f());
+	} else {
+		val = set_field(val, perf_pmasys_controlreg_legacy_mode_m(),
+				perf_pmasys_controlreg_legacy_mode_disable_f());
+	}
+
+	nvgpu_writel(g, perf_pmasys_controlreg_r(), val);
+}
diff --git a/drivers/gpu/nvgpu/hal/perf/perf_ga10b.h b/drivers/gpu/nvgpu/hal/perf/perf_ga10b.h
new file mode 100644
index 000000000..5f25c6027
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/perf/perf_ga10b.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GA10B_PERF
+#define NVGPU_GA10B_PERF
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_mem;
+
+bool ga10b_perf_get_membuf_overflow_status(struct gk20a *g);
+u32 ga10b_perf_get_membuf_pending_bytes(struct gk20a *g);
+void ga10b_perf_set_membuf_handled_bytes(struct gk20a *g,
+	u32 entries, u32 entry_size);
+
+void ga10b_perf_membuf_reset_streaming(struct gk20a *g);
+
+void ga10b_perf_enable_membuf(struct gk20a *g, u32 size, u64 buf_addr);
+void ga10b_perf_disable_membuf(struct gk20a *g);
+void ga10b_perf_bind_mem_bytes_buffer_addr(struct gk20a *g, u64 buf_addr);
+
+void ga10b_perf_init_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
+void ga10b_perf_deinit_inst_block(struct gk20a *g);
+
+u32 ga10b_perf_get_pmmsys_per_chiplet_offset(void);
+u32 ga10b_perf_get_pmmgpc_per_chiplet_offset(void);
+u32 ga10b_perf_get_pmmfbp_per_chiplet_offset(void);
+
+const u32 *ga10b_perf_get_hwpm_sys_perfmon_regs(u32 *count);
+const u32 *ga10b_perf_get_hwpm_gpc_perfmon_regs(u32 *count);
+const u32 *ga10b_perf_get_hwpm_fbp_perfmon_regs(u32 *count);
+
+void ga10b_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
+		u32 *num_fbp_perfmon, u32 *num_gpc_perfmon);
+void ga10b_perf_init_hwpm_pmm_register(struct gk20a *g);
+void ga10b_perf_disable_all_perfmons(struct gk20a *g);
+void ga10b_perf_pma_stream_enable(struct gk20a *g, bool enable);
+int ga10b_perf_wait_for_idle_pma(struct gk20a *g);
+int ga10b_perf_update_get_put(struct gk20a *g, u64 bytes_consumed,
+	bool update_available_bytes, u64 *put_ptr, bool *overflowed);
+void ga10b_perf_enable_hs_streaming(struct gk20a *g, bool enable);
+void ga10b_perf_reset_hs_streaming_credits(struct gk20a *g);
+void ga10b_perf_enable_pmasys_legacy_mode(struct gk20a *g, bool enable);
+
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#endif
diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_ga100.c b/drivers/gpu/nvgpu/hal/pmu/pmu_ga100.c
new file mode 100644
index 000000000..a6cd49f44
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/pmu/pmu_ga100.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/enabled.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+
+#include "pmu_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_pwr_ga100.h>
+
+bool ga100_is_pmu_supported(struct gk20a *g)
+{
+#ifdef CONFIG_NVGPU_SIM
+	/* PMU not supported in dGpu Simulation */
+	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
+		return false;
+	} else
+#endif
+	{
+		/* PMU support not required until PSTATE support enabled */
+		return false;
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_ga100.h b/drivers/gpu/nvgpu/hal/pmu/pmu_ga100.h
new file mode 100644
index 000000000..3325a068b
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/pmu/pmu_ga100.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef PMU_GA100_H
+#define PMU_GA100_H
+
+struct gk20a;
+
+bool ga100_is_pmu_supported(struct gk20a *g);
+
+#endif /* PMU_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c
new file mode 100644
index 000000000..15e0b1298
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <nvgpu/pmu.h>
+#include <nvgpu/falcon.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/firmware.h>
+#include <nvgpu/mm.h>
+#include <nvgpu/io.h>
+#include <nvgpu/soc.h>
+
+#include "pmu_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_pwr_ga10b.h>
+
+bool ga10b_is_pmu_supported(struct gk20a *g)
+{
+	return nvgpu_platform_is_simulation(g) ? false : true;
+}
+
+u32 ga10b_pmu_falcon2_base_addr(void)
+{
+	return pwr_falcon2_pwr_base_r();
+}
+
+u32 ga10b_pmu_get_irqmask(struct gk20a *g)
+{
+	u32 mask = 0U;
+
+	if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
+		nvgpu_pmu_dbg(g, "RISCV core INTR");
+		mask = nvgpu_readl(g, pwr_riscv_irqmask_r());
+		mask &= nvgpu_readl(g, pwr_riscv_irqdest_r());
+	} else {
+		nvgpu_pmu_dbg(g, "Falcon core INTR");
+		mask = nvgpu_readl(g, pwr_falcon_irqmask_r());
+		mask &= nvgpu_readl(g, pwr_falcon_irqdest_r());
+	}
+
+	return mask;
+}
+
+static int ga10b_pmu_ns_falcon_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
+			u32 args_offset)
+{
+	struct mm_gk20a *mm = &g->mm;
+	struct nvgpu_firmware *fw = NULL;
+	struct pmu_ucode_desc_v1 *desc = NULL;
+	u32 addr_code_lo, addr_data_lo, addr_load_lo;
+	u32 addr_code_hi, addr_data_hi;
+	u32  blocks, i, err;
+	u32 inst_block_ptr;
+
+	nvgpu_log_fn(g, " ");
+
+	fw = nvgpu_pmu_fw_desc_desc(g, pmu);
+	desc = (struct pmu_ucode_desc_v1 *)(void *)fw->data;
+
+	nvgpu_writel(g, pwr_falcon_itfen_r(),
+		nvgpu_readl(g, pwr_falcon_itfen_r()) |
+		pwr_falcon_itfen_ctxen_enable_f());
+
+	inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->pmu.inst_block);
+	nvgpu_writel(g, pwr_pmu_new_instblk_r(),
+			pwr_pmu_new_instblk_ptr_f(inst_block_ptr) |
+			pwr_pmu_new_instblk_valid_f(1) |
+				(nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) ?
+			pwr_pmu_new_instblk_target_sys_coh_f() :
+			pwr_pmu_new_instblk_target_sys_ncoh_f()));
+
+	nvgpu_writel(g, pwr_falcon_dmemc_r(0),
+			pwr_falcon_dmemc_offs_f(0) |
+			pwr_falcon_dmemc_blk_f(0)  |
+			pwr_falcon_dmemc_aincw_f(1));
+
+	addr_code_lo = u64_lo32(right_shift_8bits((pmu->fw->ucode.gpu_va +
+				desc->app_start_offset +
+				desc->app_resident_code_offset)));
+
+	addr_code_hi = u64_hi32(right_shift_8bits((pmu->fw->ucode.gpu_va +
+				desc->app_start_offset +
+				desc->app_resident_code_offset)));
+	addr_data_lo = u64_lo32(right_shift_8bits((pmu->fw->ucode.gpu_va +
+				desc->app_start_offset +
+				desc->app_resident_data_offset)));
+	addr_data_hi = u64_hi32(right_shift_8bits((pmu->fw->ucode.gpu_va +
+				desc->app_start_offset +
+				desc->app_resident_data_offset)));
+	addr_load_lo = u64_lo32(right_shift_8bits((pmu->fw->ucode.gpu_va +
+				desc->bootloader_start_offset)));
+
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), DMEM_DATA_0);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), DMEM_DATA_0);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), DMEM_DATA_0);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), DMEM_DATA_0);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), DMEM_DATA_0);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), DMEM_DATA_0);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), DMEM_DATA_0);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), DMEM_DATA_0);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), GK20A_PMU_DMAIDX_UCODE);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), left_shift_8bits(addr_code_lo));
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), addr_code_hi);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), desc->app_resident_code_offset);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), desc->app_resident_code_size);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), DMEM_DATA_0);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), DMEM_DATA_0);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), desc->app_imem_entry);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), left_shift_8bits(addr_data_lo));
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), addr_data_hi);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), desc->app_resident_data_size);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), DMEM_DATA_1);
+	nvgpu_writel(g, pwr_falcon_dmemd_r(0), args_offset);
+
+	g->ops.pmu.write_dmatrfbase(g,
+		addr_load_lo -
+		(right_shift_8bits(desc->bootloader_imem_offset)));
+
+	blocks = right_shift_8bits(((desc->bootloader_size + U8_MAX) & ~U8_MAX));
+
+	for (i = DMA_OFFSET_START; i < blocks; i++) {
+		nvgpu_writel(g, pwr_falcon_dmatrfmoffs_r(),
+			desc->bootloader_imem_offset + left_shift_8bits(i));
+		nvgpu_writel(g, pwr_falcon_dmatrffboffs_r(),
+			desc->bootloader_imem_offset + left_shift_8bits(i));
+		nvgpu_writel(g, pwr_falcon_dmatrfcmd_r(),
+			pwr_falcon_dmatrfcmd_imem_f(1)  |
+			pwr_falcon_dmatrfcmd_write_f(0) |
+			pwr_falcon_dmatrfcmd_size_f(6)  |
+			pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE));
+	}
+
+	err = nvgpu_falcon_bootstrap(pmu->flcn, desc->bootloader_entry_point);
+
+	nvgpu_writel(g, pwr_falcon_os_r(), desc->app_version);
+
+	return err;
+}
+
+u32 ga10b_pmu_get_inst_block_config(struct gk20a *g)
+{
+	struct mm_gk20a *mm = &g->mm;
+	u32 inst_block_ptr = 0;
+
+	inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->pmu.inst_block);
+	return (pwr_pmu_new_instblk_ptr_f(inst_block_ptr) |
+			pwr_pmu_new_instblk_valid_f(1) |
+			(nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) ?
+				pwr_pmu_new_instblk_target_sys_coh_f() :
+				pwr_pmu_new_instblk_target_sys_ncoh_f()));
+}
+
+static int ga10b_pmu_ns_nvriscv_bootstrap(struct gk20a *g,  struct nvgpu_pmu *pmu,
+		u32 args_offset)
+{
+	struct falcon_next_core_ucode_desc *desc;
+	struct pmu_rtos_fw *rtos_fw = g->pmu->fw;
+	u64 fmc_code_addr = 0;
+	u64 fmc_data_addr = 0;
+	u64 manifest_addr = 0;
+
+	desc = (struct falcon_next_core_ucode_desc *)(void *)
+			rtos_fw->fw_desc->data;
+
+	fmc_code_addr = right_shift_8bits((nvgpu_mem_get_addr(g,
+			&pmu->fw->ucode) + desc->monitor_code_offset));
+
+	fmc_data_addr = right_shift_8bits((nvgpu_mem_get_addr(g,
+			&pmu->fw->ucode) + desc->monitor_data_offset));
+
+	manifest_addr = right_shift_8bits((nvgpu_mem_get_addr(g,
+			&pmu->fw->ucode) + desc->manifest_offset));
+
+	g->ops.falcon.brom_config(pmu->flcn, fmc_code_addr, fmc_data_addr,
+			manifest_addr);
+
+	g->ops.falcon.bootstrap(pmu->flcn, 0U);
+
+	return 0;
+}
+
+int ga10b_pmu_ns_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
+		u32 args_offset)
+{
+	int err = 0;
+
+	if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
+		err = ga10b_pmu_ns_nvriscv_bootstrap(g, pmu, args_offset);
+	} else {
+		err = ga10b_pmu_ns_falcon_bootstrap(g, pmu, args_offset);
+	}
+
+	return err;
+}
+
+void ga10b_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu)
+{
+	struct gk20a *g = pmu->g;
+
+	nvgpu_pmu_dbg(g, "pwr_pmu_idle_mask_supp_r(3): 0x%08x",
+		nvgpu_readl(g, pwr_pmu_idle_mask_supp_r(3)));
+	nvgpu_pmu_dbg(g, "pwr_pmu_idle_mask_1_supp_r(3): 0x%08x",
+		nvgpu_readl(g, pwr_pmu_idle_mask_1_supp_r(3)));
+	nvgpu_pmu_dbg(g, "pwr_pmu_idle_ctrl_supp_r(3): 0x%08x",
+		nvgpu_readl(g, pwr_pmu_idle_ctrl_supp_r(3)));
+	nvgpu_pmu_dbg(g, "pwr_pmu_pg_idle_cnt_r(0): 0x%08x",
+		nvgpu_readl(g, pwr_pmu_pg_idle_cnt_r(0)));
+	nvgpu_pmu_dbg(g, "pwr_pmu_pg_intren_r(0): 0x%08x",
+		nvgpu_readl(g, pwr_pmu_pg_intren_r(0)));
+
+	nvgpu_pmu_dbg(g, "pwr_pmu_idle_count_r(3): 0x%08x",
+		nvgpu_readl(g, pwr_pmu_idle_count_r(3)));
+	nvgpu_pmu_dbg(g, "pwr_pmu_idle_count_r(4): 0x%08x",
+		nvgpu_readl(g, pwr_pmu_idle_count_r(4)));
+	nvgpu_pmu_dbg(g, "pwr_pmu_idle_count_r(7): 0x%08x",
+		nvgpu_readl(g, pwr_pmu_idle_count_r(7)));
+}
+
+void ga10b_pmu_init_perfmon_counter(struct gk20a *g)
+{
+	u32 data;
+
+	/* use counter #3 for GR && CE2 busy cycles */
+	nvgpu_writel(g, pwr_pmu_idle_mask_r(IDLE_COUNTER_3),
+		pwr_pmu_idle_mask_gr_enabled_f() |
+		pwr_pmu_idle_mask_ce_2_enabled_f());
+
+	/* disable idle filtering for counters 3 and 6 */
+	data = nvgpu_readl(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_3));
+	data = set_field(data, pwr_pmu_idle_ctrl_value_m() |
+		pwr_pmu_idle_ctrl_filter_m(),
+		pwr_pmu_idle_ctrl_value_busy_f() |
+		pwr_pmu_idle_ctrl_filter_disabled_f());
+	nvgpu_writel(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_3), data);
+
+	/* use counter #6 for total cycles */
+	data = nvgpu_readl(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_6));
+	data = set_field(data, pwr_pmu_idle_ctrl_value_m() |
+		pwr_pmu_idle_ctrl_filter_m(),
+		pwr_pmu_idle_ctrl_value_always_f() |
+		pwr_pmu_idle_ctrl_filter_disabled_f());
+	nvgpu_writel(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_6), data);
+
+	/*
+	 * We don't want to disturb counters #3 and #6, which are used by
+	 * perfmon, so we add wiring also to counters #1 and #2 for
+	 * exposing raw counter readings.
+	 */
+	nvgpu_writel(g, pwr_pmu_idle_mask_r(IDLE_COUNTER_1),
+		pwr_pmu_idle_mask_gr_enabled_f() |
+		pwr_pmu_idle_mask_ce_2_enabled_f());
+
+	data = nvgpu_readl(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_1));
+	data = set_field(data, pwr_pmu_idle_ctrl_value_m() |
+		pwr_pmu_idle_ctrl_filter_m(),
+		pwr_pmu_idle_ctrl_value_busy_f() |
+		pwr_pmu_idle_ctrl_filter_disabled_f());
+	nvgpu_writel(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_1), data);
+
+	data = nvgpu_readl(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_2));
+	data = set_field(data, pwr_pmu_idle_ctrl_value_m() |
+		pwr_pmu_idle_ctrl_filter_m(),
+		pwr_pmu_idle_ctrl_value_always_f() |
+		pwr_pmu_idle_ctrl_filter_disabled_f());
+	nvgpu_writel(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_2), data);
+
+	/*
+	* use counters 4 and 0 for perfmon to log busy cycles and total
+	* cycles counter #0 overflow sets pmu idle intr status bit
+	*/
+	nvgpu_writel(g, pwr_pmu_idle_intr_r(),
+		pwr_pmu_idle_intr_en_f(0));
+
+	nvgpu_writel(g, pwr_pmu_idle_threshold_r(IDLE_COUNTER_0),
+		pwr_pmu_idle_threshold_value_f(PMU_IDLE_THRESHOLD_V));
+
+	data = nvgpu_readl(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_0));
+	data = set_field(data, pwr_pmu_idle_ctrl_value_m() |
+		pwr_pmu_idle_ctrl_filter_m(),
+		pwr_pmu_idle_ctrl_value_always_f() |
+		pwr_pmu_idle_ctrl_filter_disabled_f());
+	nvgpu_writel(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_0), data);
+
+	nvgpu_writel(g, pwr_pmu_idle_mask_r(IDLE_COUNTER_4),
+		pwr_pmu_idle_mask_gr_enabled_f() |
+		pwr_pmu_idle_mask_ce_2_enabled_f());
+
+	data = nvgpu_readl(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_4));
+	data = set_field(data, pwr_pmu_idle_ctrl_value_m() |
+		pwr_pmu_idle_ctrl_filter_m(),
+		pwr_pmu_idle_ctrl_value_busy_f() |
+		pwr_pmu_idle_ctrl_filter_disabled_f());
+	nvgpu_writel(g, pwr_pmu_idle_ctrl_r(IDLE_COUNTER_4), data);
+
+	nvgpu_writel(g, pwr_pmu_idle_count_r(IDLE_COUNTER_0),
+		pwr_pmu_idle_count_reset_f(1));
+	nvgpu_writel(g, pwr_pmu_idle_count_r(IDLE_COUNTER_4),
+		pwr_pmu_idle_count_reset_f(1));
+	nvgpu_writel(g, pwr_pmu_idle_intr_status_r(),
+		pwr_pmu_idle_intr_status_intr_f(1));
+}
+
+u32 ga10b_pmu_read_idle_counter(struct gk20a *g, u32 counter_id)
+{
+	return pwr_pmu_idle_count_value_v(
+		nvgpu_readl(g, pwr_pmu_idle_count_r(counter_id)));
+}
+
+void ga10b_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id)
+{
+	nvgpu_writel(g, pwr_pmu_idle_count_r(counter_id),
+		pwr_pmu_idle_count_reset_f(1));
+}
+
+bool ga10b_pmu_is_debug_mode_en(struct gk20a *g)
+{
+	u32 ctl_stat =  nvgpu_readl(g, pwr_falcon_hwcfg2_r());
+
+	if (pwr_falcon_hwcfg2_dbgmode_v(ctl_stat) ==
+		pwr_falcon_hwcfg2_dbgmode_enable_v()) {
+		nvgpu_info(g, "DEBUG MODE");
+		return true;
+	} else {
+		nvgpu_info(g, "PROD MODE");
+		return false;
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.h b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.h
new file mode 100644
index 000000000..d87220d3a
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_GA10B_H
+#define NVGPU_PMU_GA10B_H
+
+#include <nvgpu/types.h>
+
+#define DMA_OFFSET_START	0U
+#define DMEM_DATA_0             0x0U
+#define DMEM_DATA_1             0x1U
+#define PMU_IDLE_THRESHOLD_V    0x7FFFFFFF
+#define IDLE_COUNTER_0          0
+#define IDLE_COUNTER_1          1
+#define IDLE_COUNTER_2          2
+#define IDLE_COUNTER_3          3
+#define IDLE_COUNTER_4          4
+#define IDLE_COUNTER_6          6
+#define right_shift_8bits(v)    (v >> 8U)
+#define left_shift_8bits(v)     (v << 8U)
+
+struct gk20a;
+struct nvgpu_pmu;
+
+bool ga10b_is_pmu_supported(struct gk20a *g);
+u32 ga10b_pmu_falcon2_base_addr(void);
+int ga10b_pmu_ns_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
+		u32 args_offset);
+u32 ga10b_pmu_get_inst_block_config(struct gk20a *g);
+void ga10b_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu);
+void ga10b_pmu_init_perfmon_counter(struct gk20a *g);
+u32 ga10b_pmu_read_idle_counter(struct gk20a *g, u32 counter_id);
+void ga10b_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id);
+u32 ga10b_pmu_get_irqmask(struct gk20a *g);
+bool ga10b_pmu_is_debug_mode_en(struct gk20a *g);
+
+#endif /* NVGPU_PMU_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c b/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c
new file mode 100644
index 000000000..5bd1cb0cb
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c
@@ -0,0 +1,958 @@
+/*
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/io.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/static_analysis.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/nvgpu_next_runlist.h>
+
+#include "hal/power_features/cg/gating_reglist.h"
+#include "ga100_gating_reglist.h"
+
+#define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc))
+
+/* slcg bus */
+static const struct gating_desc ga100_slcg_bus[] = {
+	{.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU},
+};
+
+/* slcg ce2 */
+static const struct gating_desc ga100_slcg_ce2[] = {
+	{.addr = 0x00104204U, .prod = 0x00000000U, .disable = 0x000007feU},
+};
+
+/* slcg chiplet */
+static const struct gating_desc ga100_slcg_chiplet[] = {
+	{.addr = 0x0010e07cU, .prod = 0x00000004U, .disable = 0x00000007U},
+	{.addr = 0x0010e17cU, .prod = 0x00000004U, .disable = 0x00000007U},
+};
+
+/* slcg fb */
+static const struct gating_desc ga100_slcg_fb[] = {
+	{.addr = 0x00100d14U, .prod = 0x00200020U, .disable = 0xfffffffeU},
+	{.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x0000a0b4U, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x0000a4b4U, .prod = 0x00000000U, .disable = 0x000001feU},
+};
+
+/* slcg runlist*/
+static const struct gating_desc ga100_slcg_runlist[] = {
+	{.addr = 0x00000054U, .prod = 0x00000002U, .disable = 0x0001fffeU},
+};
+
+/* slcg gr */
+static const struct gating_desc ga100_slcg_gr[] = {
+	{.addr = 0x004041f4U, .prod = 0x00000000U, .disable = 0x0ffffffeU},
+	{.addr = 0x00409134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
+	{.addr = 0x00409894U, .prod = 0x00000000U, .disable = 0x0000fffeU},
+	{.addr = 0x00406004U, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x00405bf4U, .prod = 0x00000000U, .disable = 0x00000002U},
+	{.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
+	{.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x00000ffeU},
+	{.addr = 0x00407004U, .prod = 0x00000002U, .disable = 0x000001feU},
+	{.addr = 0x0041a134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
+	{.addr = 0x0041a894U, .prod = 0x00000000U, .disable = 0x0000fffeU},
+	{.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU},
+	{.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x0041949cU, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x0041959cU, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x007ffffeU},
+	{.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU},
+	{.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x000003feU},
+	{.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U},
+	{.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x00418c74U, .prod = 0xffffff80U, .disable = 0xfffffffeU},
+	{.addr = 0x00418cf4U, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
+	{.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
+	{.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
+	{.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU},
+	{.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x000000ffU},
+	{.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU},
+	{.addr = 0x00419c84U, .prod = 0x0003fffcU, .disable = 0x0003fffeU},
+	{.addr = 0x00419c8cU, .prod = 0xfff1ff84U, .disable = 0xfffffffeU},
+	{.addr = 0x00419c94U, .prod = 0x00120040U, .disable = 0x001ffffeU},
+	{.addr = 0x00419ca4U, .prod = 0x00003ffeU, .disable = 0x00003ffeU},
+	{.addr = 0x00419cacU, .prod = 0x0001f800U, .disable = 0x0001fffeU},
+	{.addr = 0x00419cb4U, .prod = 0x00000000U, .disable = 0x0000001eU},
+	{.addr = 0x00419a44U, .prod = 0x00000008U, .disable = 0x0000000eU},
+	{.addr = 0x00419a4cU, .prod = 0x000001f8U, .disable = 0x000001feU},
+	{.addr = 0x00419a54U, .prod = 0x0000003cU, .disable = 0x0000003eU},
+	{.addr = 0x00419a5cU, .prod = 0x0000000cU, .disable = 0x0000000eU},
+	{.addr = 0x00419a64U, .prod = 0x000001a6U, .disable = 0x000001feU},
+	{.addr = 0x00419a7cU, .prod = 0x0000003cU, .disable = 0x0000003eU},
+	{.addr = 0x00419a84U, .prod = 0x0000000cU, .disable = 0x0000000eU},
+	{.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU},
+	{.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU},
+	{.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
+	{.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},
+	{.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x000000ffU},
+	{.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU},
+};
+
+/* slcg ltc */
+static const struct gating_desc ga100_slcg_ltc[] = {
+	{.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU},
+	{.addr = 0x0017e35cU, .prod = 0x00000020U, .disable = 0xfffffffeU},
+};
+
+/* slcg perf */
+static const struct gating_desc ga100_slcg_perf[] = {
+	{.addr = 0x00248018U, .prod = 0x80000001U, .disable = 0x00000000U},
+	{.addr = 0x00251a18U, .prod = 0x80000001U, .disable = 0x00000000U},
+	{.addr = 0x00251818U, .prod = 0x80000001U, .disable = 0x00000000U},
+	{.addr = 0x0024a044U, .prod = 0x00000001U, .disable = 0x00000000U},
+};
+
+/* slcg PriRing */
+static const struct gating_desc ga100_slcg_priring[] = {
+	{.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U},
+};
+
+/* slcg pmu */
+static const struct gating_desc ga100_slcg_pmu[] = {
+	{.addr = 0x0010a134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
+	{.addr = 0x0010aa74U, .prod = 0x0000444aU, .disable = 0x00007ffeU},
+	{.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU},
+};
+
+/* therm gr */
+static const struct gating_desc ga100_slcg_therm[] = {
+	{.addr = 0x000206b8U, .prod = 0x00000009U, .disable = 0x0000000fU},
+};
+
+/* slcg Xbar */
+static const struct gating_desc ga100_slcg_xbar[] = {
+	{.addr = 0x0013c824U, .prod = 0x00000000U, .disable = 0x7ffffffeU},
+	{.addr = 0x0013c8a4U, .prod = 0x00000000U, .disable = 0x7ffffffeU},
+	{.addr = 0x0013dc08U, .prod = 0x00000000U, .disable = 0xfffffffeU},
+	{.addr = 0x0013c924U, .prod = 0x00000000U, .disable = 0x7ffffffeU},
+	{.addr = 0x0013cb84U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
+};
+
+/* slcg Hshub */
+static const struct gating_desc ga100_slcg_hshub[] = {
+	{.addr = 0x00004c40U, .prod = 0x00000000U, .disable = 0x00000004U},
+	{.addr = 0x000043f4U, .prod = 0x00000000U, .disable = 0xfffffffeU},
+	{.addr = 0x000047f4U, .prod = 0x00000000U, .disable = 0xfffffffeU},
+	{.addr = 0x00004bf4U, .prod = 0x00000000U, .disable = 0xfffffffeU},
+};
+
+/* slcg timer */
+static const struct gating_desc ga100_slcg_timer[] = {
+	{.addr = 0x00009600U, .prod = 0x00000000U, .disable = 0x00000002U},
+};
+
+/* blcg bus */
+static const struct gating_desc ga100_blcg_bus[] = {
+	{.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U},
+};
+
+/* blcg ce */
+static const struct gating_desc ga100_blcg_ce[] = {
+	{.addr = 0x00104200U, .prod = 0x0000c244U, .disable = 0x00000000U},
+};
+
+/* blcg fb */
+static const struct gating_desc ga100_blcg_fb[] = {
+	{.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U},
+	{.addr = 0x0000a0b0U, .prod = 0x00004242U, .disable = 0x00000000U},
+	{.addr = 0x0000a4b0U, .prod = 0x00004242U, .disable = 0x00000000U},
+};
+
+/* blcg runlist */
+static const struct gating_desc ga100_blcg_runlist[] = {
+	{.addr = 0x00000050U, .prod = 0x0000c242U, .disable = 0x00000000U},
+};
+
+/* blcg gr */
+static const struct gating_desc ga100_blcg_gr[] = {
+	{.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U},
+	{.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U},
+	{.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
+	{.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U},
+	{.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00408040U, .prod = 0x00000404U, .disable = 0x00000000U},
+	{.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U},
+	{.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U},
+	{.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
+	{.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00418e0cU, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U},
+	{.addr = 0x00419498U, .prod = 0x00004242U, .disable = 0x00000000U},
+	{.addr = 0x00419598U, .prod = 0x00004242U, .disable = 0x00000000U},
+	{.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U},
+	{.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U},
+	{.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U},
+	{.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00419868U, .prod = 0x00008242U, .disable = 0x00000000U},
+	{.addr = 0x00419c80U, .prod = 0x00004045U, .disable = 0x00000000U},
+	{.addr = 0x00419c88U, .prod = 0x00004047U, .disable = 0x00000000U},
+	{.addr = 0x00419c90U, .prod = 0x00004046U, .disable = 0x00000000U},
+	{.addr = 0x00419c98U, .prod = 0x00000042U, .disable = 0x00000000U},
+	{.addr = 0x00419ca0U, .prod = 0x00004047U, .disable = 0x00000000U},
+	{.addr = 0x00419ca8U, .prod = 0x00000046U, .disable = 0x00000000U},
+	{.addr = 0x00419cb0U, .prod = 0x00000045U, .disable = 0x00000000U},
+	{.addr = 0x00419a40U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a48U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a50U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a58U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a60U, .prod = 0x00000244U, .disable = 0x00000000U},
+	{.addr = 0x00419a68U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a78U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a80U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a70U, .prod = 0x00000545U, .disable = 0x00000000U},
+	{.addr = 0x00419a88U, .prod = 0x00000545U, .disable = 0x00000000U},
+	{.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U},
+	{.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00408a80U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00408810U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x004089a8U, .prod = 0x0000c242U, .disable = 0x00000000U},
+};
+
+/* blcg ltc */
+static const struct gating_desc ga100_blcg_ltc[] = {
+	{.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U},
+	{.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U},
+	{.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U},
+	{.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U},
+};
+
+/* blcg pmu */
+static const struct gating_desc ga100_blcg_pmu[] = {
+	{.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U},
+};
+
+/* blcg Xbar */
+static const struct gating_desc ga100_blcg_xbar[] = {
+	{.addr = 0x0013c820U, .prod = 0x0001004aU, .disable = 0x00000000U},
+	{.addr = 0x0013c8a0U, .prod = 0x0001004aU, .disable = 0x00000000U},
+	{.addr = 0x0013dc04U, .prod = 0x0001004aU, .disable = 0x00000000U},
+	{.addr = 0x0013c920U, .prod = 0x0000004aU, .disable = 0x00000000U},
+	{.addr = 0x0013cb80U, .prod = 0x00000042U, .disable = 0x00000000U},
+};
+
+/* blcg Hshub */
+static const struct gating_desc ga100_blcg_hshub[] = {
+	{.addr = 0x000043f0U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x000047f0U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00004bf0U, .prod = 0x0000c242U, .disable = 0x00000000U},
+};
+
+/* elcg ce */
+static const struct gating_desc ga100_elcg_ce[] = {
+	{.addr = 0x00104044U, .prod = 0x00000001U, .disable = 0x00000000U},
+};
+
+/* inline functions */
+void ga100_slcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_bus)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_bus[i].addr;
+			u32 val = prod ? ga100_slcg_bus[i].prod :
+					 ga100_slcg_bus[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_bus_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_bus));
+}
+
+const struct gating_desc *ga100_slcg_bus_get_gating_prod(void)
+{
+	return ga100_slcg_bus;
+}
+
+void ga100_slcg_ce2_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_ce2)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_ce2[i].addr;
+			u32 val = prod ? ga100_slcg_ce2[i].prod :
+					 ga100_slcg_ce2[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_ce2_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_ce2));
+}
+
+const struct gating_desc *ga100_slcg_ce2_get_gating_prod(void)
+{
+	return ga100_slcg_ce2;
+}
+
+void ga100_slcg_chiplet_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_chiplet)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_chiplet[i].addr;
+			u32 val = prod ? ga100_slcg_chiplet[i].prod :
+					 ga100_slcg_chiplet[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_chiplet_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_chiplet));
+}
+
+const struct gating_desc *ga100_slcg_chiplet_get_gating_prod(void)
+{
+	return ga100_slcg_chiplet;
+}
+
+void ga100_slcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_fb)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_fb[i].addr;
+			u32 val = prod ? ga100_slcg_fb[i].prod :
+					 ga100_slcg_fb[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_fb_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_fb));
+}
+
+const struct gating_desc *ga100_slcg_fb_get_gating_prod(void)
+{
+	return ga100_slcg_fb;
+}
+
+void ga100_slcg_runlist_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_runlist)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			struct nvgpu_fifo *f = &g->fifo;
+			struct nvgpu_runlist *runlist;
+			u32 j, runlist_pri_base;
+			u32 reg = ga100_slcg_runlist[i].addr;
+			u32 val = prod ? ga100_slcg_runlist[i].prod :
+					 ga100_slcg_runlist[i].disable;
+			for (j = 0U; j < f->num_runlists; j++) {
+				runlist = &f->active_runlists[j];
+				runlist_pri_base = runlist->nvgpu_next.runlist_pri_base;
+				nvgpu_writel(g, nvgpu_safe_add_u32(reg, runlist_pri_base), val);
+			}
+		}
+	}
+}
+
+u32 ga100_slcg_runlist_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_runlist));
+}
+
+const struct gating_desc *ga100_slcg_runlist_get_gating_prod(void)
+{
+	return ga100_slcg_runlist;
+}
+
+void ga100_slcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_gr)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_gr[i].addr;
+			u32 val = prod ? ga100_slcg_gr[i].prod :
+					 ga100_slcg_gr[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_gr_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_gr));
+}
+
+const struct gating_desc *ga100_slcg_gr_get_gating_prod(void)
+{
+	return ga100_slcg_gr;
+}
+
+void ga100_slcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_ltc)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_ltc[i].addr;
+			u32 val = prod ? ga100_slcg_ltc[i].prod :
+					 ga100_slcg_ltc[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_ltc_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_ltc));
+}
+
+const struct gating_desc *ga100_slcg_ltc_get_gating_prod(void)
+{
+	return ga100_slcg_ltc;
+}
+
+void ga100_slcg_perf_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_perf)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_perf[i].addr;
+			u32 val = prod ? ga100_slcg_perf[i].prod :
+					 ga100_slcg_perf[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_perf_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_perf));
+}
+
+const struct gating_desc *ga100_slcg_perf_get_gating_prod(void)
+{
+	return ga100_slcg_perf;
+}
+
+void ga100_slcg_priring_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_priring)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_priring[i].addr;
+			u32 val = prod ? ga100_slcg_priring[i].prod :
+					 ga100_slcg_priring[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_priring_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_priring));
+}
+
+const struct gating_desc *ga100_slcg_priring_get_gating_prod(void)
+{
+	return ga100_slcg_priring;
+}
+
+void ga100_slcg_timer_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_timer)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_timer[i].addr;
+			u32 val = prod ? ga100_slcg_timer[i].prod :
+					 ga100_slcg_timer[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_timer_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_timer));
+}
+
+const struct gating_desc *ga100_slcg_timer_get_gating_prod(void)
+{
+	return ga100_slcg_timer;
+}
+
+void ga100_slcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_pmu)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_pmu[i].addr;
+			u32 val = prod ? ga100_slcg_pmu[i].prod :
+					 ga100_slcg_pmu[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_pmu_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_pmu));
+}
+
+const struct gating_desc *ga100_slcg_pmu_get_gating_prod(void)
+{
+	return ga100_slcg_pmu;
+}
+
+void ga100_slcg_therm_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_therm)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_therm[i].addr;
+			u32 val = prod ? ga100_slcg_therm[i].prod :
+					 ga100_slcg_therm[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_therm_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_therm));
+}
+
+const struct gating_desc *ga100_slcg_therm_get_gating_prod(void)
+{
+	return ga100_slcg_therm;
+}
+
+void ga100_slcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_xbar)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_xbar[i].addr;
+			u32 val = prod ? ga100_slcg_xbar[i].prod :
+					 ga100_slcg_xbar[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_xbar_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_xbar));
+}
+
+const struct gating_desc *ga100_slcg_xbar_get_gating_prod(void)
+{
+	return ga100_slcg_xbar;
+}
+
+void ga100_slcg_hshub_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_slcg_hshub)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_slcg_hshub[i].addr;
+			u32 val = prod ? ga100_slcg_hshub[i].prod :
+					 ga100_slcg_hshub[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_slcg_hshub_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_slcg_hshub));
+}
+
+const struct gating_desc *ga100_slcg_hshub_get_gating_prod(void)
+{
+	return ga100_slcg_hshub;
+}
+
+void ga100_blcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_blcg_bus)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_blcg_bus[i].addr;
+			u32 val = prod ? ga100_blcg_bus[i].prod :
+					 ga100_blcg_bus[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_blcg_bus_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_blcg_bus));
+}
+
+const struct gating_desc *ga100_blcg_bus_get_gating_prod(void)
+{
+	return ga100_blcg_bus;
+}
+
+void ga100_blcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_blcg_ce)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_blcg_ce[i].addr;
+			u32 val = prod ? ga100_blcg_ce[i].prod :
+					 ga100_blcg_ce[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_blcg_ce_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_blcg_ce));
+}
+
+const struct gating_desc *ga100_blcg_ce_get_gating_prod(void)
+{
+	return ga100_blcg_ce;
+}
+
+void ga100_blcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_blcg_fb)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_blcg_fb[i].addr;
+			u32 val = prod ? ga100_blcg_fb[i].prod :
+					 ga100_blcg_fb[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_blcg_fb_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_blcg_fb));
+}
+
+const struct gating_desc *ga100_blcg_fb_get_gating_prod(void)
+{
+	return ga100_blcg_fb;
+}
+
+void ga100_blcg_runlist_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_blcg_runlist)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			struct nvgpu_fifo *f = &g->fifo;
+			struct nvgpu_runlist *runlist;
+			u32 j, runlist_pri_base;
+			u32 reg = ga100_blcg_runlist[i].addr;
+			u32 val = prod ? ga100_blcg_runlist[i].prod :
+					 ga100_blcg_runlist[i].disable;
+			for (j = 0U; j < f->num_runlists; j++) {
+				runlist = &f->active_runlists[j];
+				runlist_pri_base = runlist->nvgpu_next.runlist_pri_base;
+				nvgpu_writel(g, nvgpu_safe_add_u32(reg, runlist_pri_base), val);
+			}
+		}
+	}
+}
+
+u32 ga100_blcg_runlist_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_blcg_runlist));
+}
+
+const struct gating_desc *ga100_blcg_runlist_get_gating_prod(void)
+{
+	return ga100_blcg_runlist;
+}
+
+void ga100_blcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_blcg_gr)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_blcg_gr[i].addr;
+			u32 val = prod ? ga100_blcg_gr[i].prod :
+					 ga100_blcg_gr[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_blcg_gr_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_blcg_gr));
+}
+
+const struct gating_desc *ga100_blcg_gr_get_gating_prod(void)
+{
+	return ga100_blcg_gr;
+}
+
+void ga100_blcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_blcg_ltc)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_blcg_ltc[i].addr;
+			u32 val = prod ? ga100_blcg_ltc[i].prod :
+					 ga100_blcg_ltc[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_blcg_ltc_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_blcg_ltc));
+}
+
+const struct gating_desc *ga100_blcg_ltc_get_gating_prod(void)
+{
+	return ga100_blcg_ltc;
+}
+
+void ga100_blcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_blcg_pmu)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_blcg_pmu[i].addr;
+			u32 val = prod ? ga100_blcg_pmu[i].prod :
+					 ga100_blcg_pmu[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_blcg_pmu_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_blcg_pmu));
+}
+
+const struct gating_desc *ga100_blcg_pmu_get_gating_prod(void)
+{
+	return ga100_blcg_pmu;
+}
+
+void ga100_blcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_blcg_xbar)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_blcg_xbar[i].addr;
+			u32 val = prod ? ga100_blcg_xbar[i].prod :
+					 ga100_blcg_xbar[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_blcg_xbar_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_blcg_xbar));
+}
+
+const struct gating_desc *ga100_blcg_xbar_get_gating_prod(void)
+{
+	return ga100_blcg_xbar;
+}
+
+void ga100_blcg_hshub_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_blcg_hshub)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_blcg_hshub[i].addr;
+			u32 val = prod ? ga100_blcg_hshub[i].prod :
+					 ga100_blcg_hshub[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_blcg_hshub_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_blcg_hshub));
+}
+
+const struct gating_desc *ga100_blcg_hshub_get_gating_prod(void)
+{
+	return ga100_blcg_hshub;
+}
+
+void ga100_elcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga100_elcg_ce)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga100_elcg_ce[i].addr;
+			u32 val = prod ? ga100_elcg_ce[i].prod :
+					 ga100_elcg_ce[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga100_elcg_ce_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga100_elcg_ce));
+}
+
+const struct gating_desc *ga100_elcg_ce_get_gating_prod(void)
+{
+	return ga100_elcg_ce;
+}
+
diff --git a/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.h b/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.h
new file mode 100644
index 000000000..2c116d30c
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#ifndef GA100_GATING_REGLIST_H
+#define GA100_GATING_REGLIST_H
+
+#include <nvgpu/types.h>
+
+struct gating_desc;
+struct gk20a;
+
+void ga100_slcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_bus_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_bus_get_gating_prod(void);
+
+void ga100_slcg_ce2_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_ce2_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_ce2_get_gating_prod(void);
+
+void ga100_slcg_chiplet_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_chiplet_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_chiplet_get_gating_prod(void);
+
+void ga100_slcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_fb_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_fb_get_gating_prod(void);
+
+void ga100_slcg_runlist_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_runlist_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_runlist_get_gating_prod(void);
+
+void ga100_slcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_gr_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_gr_get_gating_prod(void);
+
+void ga100_slcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_ltc_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_ltc_get_gating_prod(void);
+
+void ga100_slcg_perf_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_perf_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_perf_get_gating_prod(void);
+
+void ga100_slcg_priring_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_priring_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_priring_get_gating_prod(void);
+
+void ga100_slcg_timer_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_timer_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_timer_get_gating_prod(void);
+
+void ga100_slcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_pmu_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_pmu_get_gating_prod(void);
+
+void ga100_slcg_therm_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_therm_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_therm_get_gating_prod(void);
+
+void ga100_slcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_xbar_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_xbar_get_gating_prod(void);
+
+void ga100_slcg_hshub_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_slcg_hshub_gating_prod_size(void);
+const struct gating_desc *ga100_slcg_hshub_get_gating_prod(void);
+
+void ga100_blcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_blcg_bus_gating_prod_size(void);
+const struct gating_desc *ga100_blcg_bus_get_gating_prod(void);
+
+void ga100_blcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_blcg_ce_gating_prod_size(void);
+const struct gating_desc *ga100_blcg_ce_get_gating_prod(void);
+
+void ga100_blcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_blcg_fb_gating_prod_size(void);
+const struct gating_desc *ga100_blcg_fb_get_gating_prod(void);
+
+void ga100_blcg_runlist_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_blcg_runlist_gating_prod_size(void);
+const struct gating_desc *ga100_blcg_runlist_get_gating_prod(void);
+
+void ga100_blcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_blcg_gr_gating_prod_size(void);
+const struct gating_desc *ga100_blcg_gr_get_gating_prod(void);
+
+void ga100_blcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_blcg_ltc_gating_prod_size(void);
+const struct gating_desc *ga100_blcg_ltc_get_gating_prod(void);
+
+void ga100_blcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_blcg_pmu_gating_prod_size(void);
+const struct gating_desc *ga100_blcg_pmu_get_gating_prod(void);
+
+void ga100_blcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_blcg_xbar_gating_prod_size(void);
+const struct gating_desc *ga100_blcg_xbar_get_gating_prod(void);
+
+void ga100_blcg_hshub_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_blcg_hshub_gating_prod_size(void);
+const struct gating_desc *ga100_blcg_hshub_get_gating_prod(void);
+
+void ga100_elcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga100_elcg_ce_gating_prod_size(void);
+const struct gating_desc *ga100_elcg_ce_get_gating_prod(void);
+
+#endif /* GA100_GATING_REGLIST_H */
diff --git a/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c b/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c
new file mode 100644
index 000000000..0c471f2f0
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c
@@ -0,0 +1,1148 @@
+/*
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/io.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/static_analysis.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/nvgpu_next_runlist.h>
+
+#include "hal/power_features/cg/gating_reglist.h"
+#include "ga10b_gating_reglist.h"
+
+#define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc))
+
+/* slcg bus */
+static const struct gating_desc ga10b_slcg_bus[] = {
+	{.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU},
+};
+
+/* slcg ce2 */
+static const struct gating_desc ga10b_slcg_ce2[] = {
+	{.addr = 0x00104204U, .prod = 0x00000000U, .disable = 0x000007feU},
+};
+
+/* slcg chiplet */
+static const struct gating_desc ga10b_slcg_chiplet[] = {
+	{.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000001U},
+	{.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000001U},
+};
+
+/* slcg fb */
+static const struct gating_desc ga10b_slcg_fb[] = {
+	{.addr = 0x00100d14U, .prod = 0x00010c20U, .disable = 0xfffffffeU},
+	{.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU},
+};
+
+/* slcg runlist*/
+static const struct gating_desc ga10b_slcg_runlist[] = {
+	{.addr = 0x00000054U, .prod = 0x00000000U, .disable = 0x0001fffeU},
+};
+
+/* slcg gr */
+static const struct gating_desc ga10b_slcg_gr[] = {
+	{.addr = 0x004041f4U, .prod = 0x00200000U, .disable = 0x0ffffffeU},
+	{.addr = 0x00409134U, .prod = 0x00000140U, .disable = 0x0003fffeU},
+	{.addr = 0x00409894U, .prod = 0x00000000U, .disable = 0x0000fffeU},
+	{.addr = 0x00406004U, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x00405bf4U, .prod = 0x00000000U, .disable = 0x00000002U},
+	{.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
+	{.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x00000ffeU},
+	{.addr = 0x00407004U, .prod = 0x00000002U, .disable = 0x000001feU},
+	{.addr = 0x0041a134U, .prod = 0x00000140U, .disable = 0x0003fffeU},
+	{.addr = 0x0041a894U, .prod = 0x00000000U, .disable = 0x0000fffeU},
+	{.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU},
+	{.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x0041949cU, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x01fffffeU},
+	{.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU},
+	{.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x000003feU},
+	{.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U},
+	{.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU},
+	{.addr = 0x00418c74U, .prod = 0xffffff80U, .disable = 0xfffffffeU},
+	{.addr = 0x00418cf4U, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
+	{.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
+	{.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
+	{.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU},
+	{.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x000000ffU},
+	{.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU},
+	{.addr = 0x00419c84U, .prod = 0x0003fffcU, .disable = 0x0003fffeU},
+	{.addr = 0x00419c8cU, .prod = 0xff71f384U, .disable = 0xfffffffeU},
+	{.addr = 0x00419c94U, .prod = 0x38f00340U, .disable = 0x3ffffffeU},
+	{.addr = 0x00419ca4U, .prod = 0x00003ffcU, .disable = 0x00003ffeU},
+	{.addr = 0x00419cacU, .prod = 0x0001f800U, .disable = 0x0001fffeU},
+	{.addr = 0x00419cb4U, .prod = 0x00001d00U, .disable = 0x00001ffeU},
+	{.addr = 0x00419a44U, .prod = 0x00000008U, .disable = 0x0000000eU},
+	{.addr = 0x00419a4cU, .prod = 0x000001f8U, .disable = 0x000001feU},
+	{.addr = 0x00419a54U, .prod = 0x0000003cU, .disable = 0x0000003eU},
+	{.addr = 0x00419a5cU, .prod = 0x0000000cU, .disable = 0x0000000eU},
+	{.addr = 0x00419a64U, .prod = 0x00000182U, .disable = 0x000001feU},
+	{.addr = 0x00419a7cU, .prod = 0x0000003cU, .disable = 0x0000003eU},
+	{.addr = 0x00419a84U, .prod = 0x0000000cU, .disable = 0x0000000eU},
+	{.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU},
+	{.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU},
+	{.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
+	{.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},
+	{.addr = 0x0041b81cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x0041b878U, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x0041b89cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x0041bc1cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x0041bc78U, .prod = 0x00000000U, .disable = 0x0001fffeU},
+	{.addr = 0x0041bc9cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
+};
+
+/* slcg ltc */
+static const struct gating_desc ga10b_slcg_ltc[] = {
+	{.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU},
+	{.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
+};
+
+/* slcg perf */
+static const struct gating_desc ga10b_slcg_perf[] = {
+	{.addr = 0x00248018U, .prod = 0x00000000U, .disable = 0x00000003U},
+	{.addr = 0x00251a18U, .prod = 0x00000000U, .disable = 0x00000003U},
+	{.addr = 0x00251818U, .prod = 0x00000000U, .disable = 0x00000003U},
+	{.addr = 0x0024a044U, .prod = 0x00000000U, .disable = 0x00000001U},
+};
+
+/* slcg PriRing */
+static const struct gating_desc ga10b_slcg_priring[] = {
+	{.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U},
+};
+
+/* slcg pmu */
+static const struct gating_desc ga10b_slcg_pmu[] = {
+	{.addr = 0x0010a134U, .prod = 0x00040140U, .disable = 0x0003fffeU},
+	{.addr = 0x0010aa74U, .prod = 0x00000400U, .disable = 0x000007feU},
+	{.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU},
+};
+
+/* therm gr */
+static const struct gating_desc ga10b_slcg_therm[] = {
+	{.addr = 0x000206b8U, .prod = 0x00000000U, .disable = 0x00000007U},
+};
+
+/* slcg Xbar */
+static const struct gating_desc ga10b_slcg_xbar[] = {
+	{.addr = 0x0013c824U, .prod = 0x00000000U, .disable = 0x7ffffffeU},
+	{.addr = 0x0013dc08U, .prod = 0x00000000U, .disable = 0xfffffffeU},
+	{.addr = 0x0013c924U, .prod = 0x00000000U, .disable = 0x7ffffffeU},
+	{.addr = 0x0013cb84U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
+	{.addr = 0x0013cb8cU, .prod = 0x00000000U, .disable = 0x1ffffffeU},
+};
+
+/* slcg Hshub */
+static const struct gating_desc ga10b_slcg_hshub[] = {
+	{.addr = 0x000043f4U, .prod = 0x00000000U, .disable = 0xfffffffeU},
+	{.addr = 0x000047f4U, .prod = 0x00000000U, .disable = 0xfffffffeU},
+	{.addr = 0x00004bf4U, .prod = 0x00000000U, .disable = 0xfffffffeU},
+};
+
+/* slcg timer */
+static const struct gating_desc ga10b_slcg_timer[] = {
+	{.addr = 0x00009600U, .prod = 0x00000000U, .disable = 0x00000002U},
+};
+
+/* slcg rs_ctrl_fbp */
+static const struct gating_desc ga10b_slcg_rs_ctrl_fbp[] = {
+	{.addr = 0x00128048U, .prod = 0x00000000U, .disable = 0x00000003U},
+};
+
+/* slcg rs_ctrl_gpc */
+static const struct gating_desc ga10b_slcg_rs_ctrl_gpc[] = {
+	{.addr = 0x00124048U, .prod = 0x00000000U, .disable = 0x00000003U},
+};
+
+/* slcg rs_ctrl_sys */
+static const struct gating_desc ga10b_slcg_rs_ctrl_sys[] = {
+	{.addr = 0x00122048U, .prod = 0x00000000U, .disable = 0x00000003U},
+};
+
+/* slcg rs_fbp */
+static const struct gating_desc ga10b_slcg_rs_fbp[] = {
+	{.addr = 0x00128250U, .prod = 0x00000000U, .disable = 0x000007ffU},
+	{.addr = 0x00121250U, .prod = 0x00000000U, .disable = 0x000007ffU},
+};
+
+/* slcg rs_gpc */
+static const struct gating_desc ga10b_slcg_rs_gpc[] = {
+	{.addr = 0x00124250U, .prod = 0x00000000U, .disable = 0x000007ffU},
+	{.addr = 0x00120a50U, .prod = 0x00000000U, .disable = 0x000007ffU},
+};
+
+/* slcg rs_sys */
+static const struct gating_desc ga10b_slcg_rs_sys[] = {
+	{.addr = 0x00122250U, .prod = 0x00000000U, .disable = 0x000007ffU},
+};
+
+/* blcg bus */
+static const struct gating_desc ga10b_blcg_bus[] = {
+	{.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U},
+};
+
+/* blcg ce */
+static const struct gating_desc ga10b_blcg_ce[] = {
+	{.addr = 0x00104200U, .prod = 0x0000c244U, .disable = 0x00000000U},
+};
+
+/* blcg fb */
+static const struct gating_desc ga10b_blcg_fb[] = {
+	{.addr = 0x00100d10U, .prod = 0x0000c270U, .disable = 0x00000000U},
+	{.addr = 0x00100d30U, .prod = 0x0000c270U, .disable = 0x00000000U},
+	{.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U},
+};
+
+/* blcg runlist */
+static const struct gating_desc ga10b_blcg_runlist[] = {
+	{.addr = 0x00000050U, .prod = 0x00004042U, .disable = 0x00000000U},
+};
+
+/* blcg gr */
+static const struct gating_desc ga10b_blcg_gr[] = {
+	{.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U},
+	{.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U},
+	{.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
+	{.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U},
+	{.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00408040U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U},
+	{.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U},
+	{.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
+	{.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00418e0cU, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U},
+	{.addr = 0x00419498U, .prod = 0x00004242U, .disable = 0x00000000U},
+	{.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U},
+	{.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U},
+	{.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U},
+	{.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00419868U, .prod = 0x00008242U, .disable = 0x00000000U},
+	{.addr = 0x00419c80U, .prod = 0x00004045U, .disable = 0x00000000U},
+	{.addr = 0x00419c88U, .prod = 0x00004047U, .disable = 0x00000000U},
+	{.addr = 0x00419c90U, .prod = 0x00004046U, .disable = 0x00000000U},
+	{.addr = 0x00419c98U, .prod = 0x00000042U, .disable = 0x00000000U},
+	{.addr = 0x00419ca0U, .prod = 0x00004047U, .disable = 0x00000000U},
+	{.addr = 0x00419ca8U, .prod = 0x00000046U, .disable = 0x00000000U},
+	{.addr = 0x00419cb0U, .prod = 0x00000045U, .disable = 0x00000000U},
+	{.addr = 0x00419a40U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a48U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a50U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a58U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a60U, .prod = 0x00000244U, .disable = 0x00000000U},
+	{.addr = 0x00419a68U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a78U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a80U, .prod = 0x00000242U, .disable = 0x00000000U},
+	{.addr = 0x00419a70U, .prod = 0x00000545U, .disable = 0x00000000U},
+	{.addr = 0x00419a88U, .prod = 0x00000545U, .disable = 0x00000000U},
+	{.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U},
+	{.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U},
+	{.addr = 0x0041b818U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x0041b874U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x0041b898U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x0041bc18U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x0041bc74U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x0041bc98U, .prod = 0x0000c242U, .disable = 0x00000000U},
+};
+
+/* blcg ltc */
+static const struct gating_desc ga10b_blcg_ltc[] = {
+	{.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U},
+	{.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U},
+	{.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U},
+	{.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U},
+};
+
+/* blcg pmu */
+static const struct gating_desc ga10b_blcg_pmu[] = {
+	{.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U},
+};
+
+/* blcg Xbar */
+static const struct gating_desc ga10b_blcg_xbar[] = {
+	{.addr = 0x0013c820U, .prod = 0x0001004aU, .disable = 0x00000000U},
+	{.addr = 0x0013dc04U, .prod = 0x0001004aU, .disable = 0x00000000U},
+	{.addr = 0x0013c920U, .prod = 0x0000004aU, .disable = 0x00000000U},
+	{.addr = 0x0013cb80U, .prod = 0x00000042U, .disable = 0x00000000U},
+	{.addr = 0x0013cb88U, .prod = 0x00000042U, .disable = 0x00000000U},
+};
+
+/* blcg Hshub */
+static const struct gating_desc ga10b_blcg_hshub[] = {
+	{.addr = 0x000043f0U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x000047f0U, .prod = 0x0000c242U, .disable = 0x00000000U},
+	{.addr = 0x00004bf0U, .prod = 0x0000c242U, .disable = 0x00000000U},
+};
+
+/* elcg ce */
+static const struct gating_desc ga10b_elcg_ce[] = {
+	{.addr = 0x00104044U, .prod = 0x00000001U, .disable = 0x00000000U},
+};
+
+/* inline functions */
+void ga10b_slcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_bus)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_bus[i].addr;
+			u32 val = prod ? ga10b_slcg_bus[i].prod :
+					 ga10b_slcg_bus[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_bus_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_bus));
+}
+
+const struct gating_desc *ga10b_slcg_bus_get_gating_prod(void)
+{
+	return ga10b_slcg_bus;
+}
+
+void ga10b_slcg_ce2_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_ce2)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_ce2[i].addr;
+			u32 val = prod ? ga10b_slcg_ce2[i].prod :
+					 ga10b_slcg_ce2[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_ce2_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_ce2));
+}
+
+const struct gating_desc *ga10b_slcg_ce2_get_gating_prod(void)
+{
+	return ga10b_slcg_ce2;
+}
+
+void ga10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_chiplet)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_chiplet[i].addr;
+			u32 val = prod ? ga10b_slcg_chiplet[i].prod :
+					 ga10b_slcg_chiplet[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_chiplet_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_chiplet));
+}
+
+const struct gating_desc *ga10b_slcg_chiplet_get_gating_prod(void)
+{
+	return ga10b_slcg_chiplet;
+}
+
+void ga10b_slcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_fb)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_fb[i].addr;
+			u32 val = prod ? ga10b_slcg_fb[i].prod :
+					 ga10b_slcg_fb[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_fb_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_fb));
+}
+
+const struct gating_desc *ga10b_slcg_fb_get_gating_prod(void)
+{
+	return ga10b_slcg_fb;
+}
+
+void ga10b_slcg_runlist_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_runlist)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			struct nvgpu_fifo *f = &g->fifo;
+			struct nvgpu_runlist *runlist;
+			u32 j, runlist_pri_base;
+			u32 reg = ga10b_slcg_runlist[i].addr;
+			u32 val = prod ? ga10b_slcg_runlist[i].prod :
+					 ga10b_slcg_runlist[i].disable;
+			for (j = 0U; j < f->num_runlists; j++) {
+				runlist = &f->active_runlists[j];
+				runlist_pri_base = runlist->nvgpu_next.runlist_pri_base;
+				nvgpu_writel(g, nvgpu_safe_add_u32(reg, runlist_pri_base), val);
+			}
+		}
+	}
+}
+
+u32 ga10b_slcg_runlist_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_runlist));
+}
+
+const struct gating_desc *ga10b_slcg_runlist_get_gating_prod(void)
+{
+	return ga10b_slcg_runlist;
+}
+
+void ga10b_slcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_gr)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_gr[i].addr;
+			u32 val = prod ? ga10b_slcg_gr[i].prod :
+					 ga10b_slcg_gr[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_gr_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_gr));
+}
+
+const struct gating_desc *ga10b_slcg_gr_get_gating_prod(void)
+{
+	return ga10b_slcg_gr;
+}
+
+void ga10b_slcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_ltc)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_ltc[i].addr;
+			u32 val = prod ? ga10b_slcg_ltc[i].prod :
+					 ga10b_slcg_ltc[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_ltc_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_ltc));
+}
+
+const struct gating_desc *ga10b_slcg_ltc_get_gating_prod(void)
+{
+	return ga10b_slcg_ltc;
+}
+
+void ga10b_slcg_perf_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_perf)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_perf[i].addr;
+			u32 val = prod ? ga10b_slcg_perf[i].prod :
+					 ga10b_slcg_perf[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_perf_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_perf));
+}
+
+const struct gating_desc *ga10b_slcg_perf_get_gating_prod(void)
+{
+	return ga10b_slcg_perf;
+}
+
+void ga10b_slcg_priring_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_priring)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_priring[i].addr;
+			u32 val = prod ? ga10b_slcg_priring[i].prod :
+					 ga10b_slcg_priring[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_priring_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_priring));
+}
+
+const struct gating_desc *ga10b_slcg_priring_get_gating_prod(void)
+{
+	return ga10b_slcg_priring;
+}
+
+void ga10b_slcg_rs_ctrl_fbp_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_rs_ctrl_fbp)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_rs_ctrl_fbp[i].addr;
+			u32 val = prod ? ga10b_slcg_rs_ctrl_fbp[i].prod :
+					 ga10b_slcg_rs_ctrl_fbp[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_rs_ctrl_fbp_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_rs_ctrl_fbp));
+}
+
+const struct gating_desc *ga10b_slcg_rs_ctrl_fbp_get_gating_prod(void)
+{
+	return ga10b_slcg_rs_ctrl_fbp;
+}
+
+void ga10b_slcg_rs_ctrl_gpc_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_rs_ctrl_gpc)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_rs_ctrl_gpc[i].addr;
+			u32 val = prod ? ga10b_slcg_rs_ctrl_gpc[i].prod :
+					 ga10b_slcg_rs_ctrl_gpc[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_rs_ctrl_gpc_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_rs_ctrl_gpc));
+}
+
+const struct gating_desc *ga10b_slcg_rs_ctrl_gpc_get_gating_prod(void)
+{
+	return ga10b_slcg_rs_ctrl_gpc;
+}
+
+void ga10b_slcg_rs_ctrl_sys_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_rs_ctrl_sys)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_rs_ctrl_sys[i].addr;
+			u32 val = prod ? ga10b_slcg_rs_ctrl_sys[i].prod :
+					 ga10b_slcg_rs_ctrl_sys[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_rs_ctrl_sys_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_rs_ctrl_sys));
+}
+
+const struct gating_desc *ga10b_slcg_rs_ctrl_sys_get_gating_prod(void)
+{
+	return ga10b_slcg_rs_ctrl_sys;
+}
+
+void ga10b_slcg_rs_fbp_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_rs_fbp)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_rs_fbp[i].addr;
+			u32 val = prod ? ga10b_slcg_rs_fbp[i].prod :
+					 ga10b_slcg_rs_fbp[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_rs_fbp_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_rs_fbp));
+}
+
+const struct gating_desc *ga10b_slcg_rs_fbp_get_gating_prod(void)
+{
+	return ga10b_slcg_rs_fbp;
+}
+
+void ga10b_slcg_rs_gpc_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_rs_gpc)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_rs_gpc[i].addr;
+			u32 val = prod ? ga10b_slcg_rs_gpc[i].prod :
+					 ga10b_slcg_rs_gpc[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_rs_gpc_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_rs_gpc));
+}
+
+const struct gating_desc *ga10b_slcg_rs_gpc_get_gating_prod(void)
+{
+	return ga10b_slcg_rs_gpc;
+}
+
+void ga10b_slcg_rs_sys_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_rs_sys)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_rs_sys[i].addr;
+			u32 val = prod ? ga10b_slcg_rs_sys[i].prod :
+					 ga10b_slcg_rs_sys[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_rs_sys_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_rs_sys));
+}
+
+const struct gating_desc *ga10b_slcg_rs_sys_get_gating_prod(void)
+{
+	return ga10b_slcg_rs_sys;
+}
+
+void ga10b_slcg_timer_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_timer)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_timer[i].addr;
+			u32 val = prod ? ga10b_slcg_timer[i].prod :
+					 ga10b_slcg_timer[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_timer_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_timer));
+}
+
+const struct gating_desc *ga10b_slcg_timer_get_gating_prod(void)
+{
+	return ga10b_slcg_timer;
+}
+
+void ga10b_slcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_pmu)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_pmu[i].addr;
+			u32 val = prod ? ga10b_slcg_pmu[i].prod :
+					 ga10b_slcg_pmu[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_pmu_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_pmu));
+}
+
+const struct gating_desc *ga10b_slcg_pmu_get_gating_prod(void)
+{
+	return ga10b_slcg_pmu;
+}
+
+void ga10b_slcg_therm_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_therm)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_therm[i].addr;
+			u32 val = prod ? ga10b_slcg_therm[i].prod :
+					 ga10b_slcg_therm[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_therm_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_therm));
+}
+
+const struct gating_desc *ga10b_slcg_therm_get_gating_prod(void)
+{
+	return ga10b_slcg_therm;
+}
+
+void ga10b_slcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_xbar)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_xbar[i].addr;
+			u32 val = prod ? ga10b_slcg_xbar[i].prod :
+					 ga10b_slcg_xbar[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_xbar_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_xbar));
+}
+
+const struct gating_desc *ga10b_slcg_xbar_get_gating_prod(void)
+{
+	return ga10b_slcg_xbar;
+}
+
+void ga10b_slcg_hshub_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_hshub)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_slcg_hshub[i].addr;
+			u32 val = prod ? ga10b_slcg_hshub[i].prod :
+					 ga10b_slcg_hshub[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_slcg_hshub_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_hshub));
+}
+
+const struct gating_desc *ga10b_slcg_hshub_get_gating_prod(void)
+{
+	return ga10b_slcg_hshub;
+}
+
+void ga10b_blcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_blcg_bus)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_blcg_bus[i].addr;
+			u32 val = prod ? ga10b_blcg_bus[i].prod :
+					 ga10b_blcg_bus[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_blcg_bus_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_blcg_bus));
+}
+
+const struct gating_desc *ga10b_blcg_bus_get_gating_prod(void)
+{
+	return ga10b_blcg_bus;
+}
+
+void ga10b_blcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_blcg_ce)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_blcg_ce[i].addr;
+			u32 val = prod ? ga10b_blcg_ce[i].prod :
+					 ga10b_blcg_ce[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_blcg_ce_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_blcg_ce));
+}
+
+const struct gating_desc *ga10b_blcg_ce_get_gating_prod(void)
+{
+	return ga10b_blcg_ce;
+}
+
+void ga10b_blcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_blcg_fb)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_blcg_fb[i].addr;
+			u32 val = prod ? ga10b_blcg_fb[i].prod :
+					 ga10b_blcg_fb[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_blcg_fb_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_blcg_fb));
+}
+
+const struct gating_desc *ga10b_blcg_fb_get_gating_prod(void)
+{
+	return ga10b_blcg_fb;
+}
+
+void ga10b_blcg_runlist_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_blcg_runlist)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			struct nvgpu_fifo *f = &g->fifo;
+			struct nvgpu_runlist *runlist;
+			u32 j, runlist_pri_base;
+			u32 reg = ga10b_blcg_runlist[i].addr;
+			u32 val = prod ? ga10b_blcg_runlist[i].prod :
+					 ga10b_blcg_runlist[i].disable;
+			for (j = 0U; j < f->num_runlists; j++) {
+				runlist = &f->active_runlists[j];
+				runlist_pri_base = runlist->nvgpu_next.runlist_pri_base;
+				nvgpu_writel(g, nvgpu_safe_add_u32(reg, runlist_pri_base), val);
+			}
+		}
+	}
+}
+
+u32 ga10b_blcg_runlist_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_blcg_runlist));
+}
+
+const struct gating_desc *ga10b_blcg_runlist_get_gating_prod(void)
+{
+	return ga10b_blcg_runlist;
+}
+
+void ga10b_blcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_blcg_gr)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_blcg_gr[i].addr;
+			u32 val = prod ? ga10b_blcg_gr[i].prod :
+					 ga10b_blcg_gr[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_blcg_gr_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_blcg_gr));
+}
+
+const struct gating_desc *ga10b_blcg_gr_get_gating_prod(void)
+{
+	return ga10b_blcg_gr;
+}
+
+void ga10b_blcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_blcg_ltc)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_blcg_ltc[i].addr;
+			u32 val = prod ? ga10b_blcg_ltc[i].prod :
+					 ga10b_blcg_ltc[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_blcg_ltc_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_blcg_ltc));
+}
+
+const struct gating_desc *ga10b_blcg_ltc_get_gating_prod(void)
+{
+	return ga10b_blcg_ltc;
+}
+
+void ga10b_blcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_blcg_pmu)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_blcg_pmu[i].addr;
+			u32 val = prod ? ga10b_blcg_pmu[i].prod :
+					 ga10b_blcg_pmu[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_blcg_pmu_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_blcg_pmu));
+}
+
+const struct gating_desc *ga10b_blcg_pmu_get_gating_prod(void)
+{
+	return ga10b_blcg_pmu;
+}
+
+void ga10b_blcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_blcg_xbar)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_blcg_xbar[i].addr;
+			u32 val = prod ? ga10b_blcg_xbar[i].prod :
+					 ga10b_blcg_xbar[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_blcg_xbar_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_blcg_xbar));
+}
+
+const struct gating_desc *ga10b_blcg_xbar_get_gating_prod(void)
+{
+	return ga10b_blcg_xbar;
+}
+
+void ga10b_blcg_hshub_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_blcg_hshub)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_blcg_hshub[i].addr;
+			u32 val = prod ? ga10b_blcg_hshub[i].prod :
+					 ga10b_blcg_hshub[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_blcg_hshub_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_blcg_hshub));
+}
+
+const struct gating_desc *ga10b_blcg_hshub_get_gating_prod(void)
+{
+	return ga10b_blcg_hshub;
+}
+
+void ga10b_elcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_elcg_ce)
+							/ GATING_DESC_SIZE);
+
+	if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) {
+		for (i = 0U; i < size; i++) {
+			u32 reg = ga10b_elcg_ce[i].addr;
+			u32 val = prod ? ga10b_elcg_ce[i].prod :
+					 ga10b_elcg_ce[i].disable;
+			nvgpu_writel(g, reg, val);
+		}
+	}
+}
+
+u32 ga10b_elcg_ce_gating_prod_size(void)
+{
+	return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_elcg_ce));
+}
+
+const struct gating_desc *ga10b_elcg_ce_get_gating_prod(void)
+{
+	return ga10b_elcg_ce;
+}
+
diff --git a/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.h b/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.h
new file mode 100644
index 000000000..5041a65d9
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#ifndef GA10B_GATING_REGLIST_H
+#define GA10B_GATING_REGLIST_H
+
+#include <nvgpu/types.h>
+
+struct gating_desc;
+struct gk20a;
+
+void ga10b_slcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_bus_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_bus_get_gating_prod(void);
+
+void ga10b_slcg_ce2_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_ce2_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_ce2_get_gating_prod(void);
+
+void ga10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_chiplet_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_chiplet_get_gating_prod(void);
+
+void ga10b_slcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_fb_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_fb_get_gating_prod(void);
+
+void ga10b_slcg_runlist_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_runlist_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_runlist_get_gating_prod(void);
+
+void ga10b_slcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_gr_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_gr_get_gating_prod(void);
+
+void ga10b_slcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_ltc_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_ltc_get_gating_prod(void);
+
+void ga10b_slcg_perf_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_perf_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_perf_get_gating_prod(void);
+
+void ga10b_slcg_priring_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_priring_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_priring_get_gating_prod(void);
+
+void ga10b_slcg_rs_ctrl_fbp_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_rs_ctrl_fbp_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_rs_ctrl_fbp_get_gating_prod(void);
+
+void ga10b_slcg_rs_ctrl_gpc_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_rs_ctrl_gpc_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_rs_ctrl_gpc_get_gating_prod(void);
+
+void ga10b_slcg_rs_ctrl_sys_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_rs_ctrl_sys_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_rs_ctrl_sys_get_gating_prod(void);
+
+void ga10b_slcg_rs_fbp_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_rs_fbp_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_rs_fbp_get_gating_prod(void);
+
+void ga10b_slcg_rs_gpc_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_rs_gpc_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_rs_gpc_get_gating_prod(void);
+
+void ga10b_slcg_rs_sys_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_rs_sys_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_rs_sys_get_gating_prod(void);
+
+void ga10b_slcg_timer_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_timer_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_timer_get_gating_prod(void);
+
+void ga10b_slcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_pmu_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_pmu_get_gating_prod(void);
+
+void ga10b_slcg_therm_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_therm_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_therm_get_gating_prod(void);
+
+void ga10b_slcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_xbar_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_xbar_get_gating_prod(void);
+
+void ga10b_slcg_hshub_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_slcg_hshub_gating_prod_size(void);
+const struct gating_desc *ga10b_slcg_hshub_get_gating_prod(void);
+
+void ga10b_blcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_blcg_bus_gating_prod_size(void);
+const struct gating_desc *ga10b_blcg_bus_get_gating_prod(void);
+
+void ga10b_blcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_blcg_ce_gating_prod_size(void);
+const struct gating_desc *ga10b_blcg_ce_get_gating_prod(void);
+
+void ga10b_blcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_blcg_fb_gating_prod_size(void);
+const struct gating_desc *ga10b_blcg_fb_get_gating_prod(void);
+
+void ga10b_blcg_runlist_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_blcg_runlist_gating_prod_size(void);
+const struct gating_desc *ga10b_blcg_runlist_get_gating_prod(void);
+
+void ga10b_blcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_blcg_gr_gating_prod_size(void);
+const struct gating_desc *ga10b_blcg_gr_get_gating_prod(void);
+
+void ga10b_blcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_blcg_ltc_gating_prod_size(void);
+const struct gating_desc *ga10b_blcg_ltc_get_gating_prod(void);
+
+void ga10b_blcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_blcg_pmu_gating_prod_size(void);
+const struct gating_desc *ga10b_blcg_pmu_get_gating_prod(void);
+
+void ga10b_blcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_blcg_xbar_gating_prod_size(void);
+const struct gating_desc *ga10b_blcg_xbar_get_gating_prod(void);
+
+void ga10b_blcg_hshub_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_blcg_hshub_gating_prod_size(void);
+const struct gating_desc *ga10b_blcg_hshub_get_gating_prod(void);
+
+void ga10b_elcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod);
+u32 ga10b_elcg_ce_gating_prod_size(void);
+const struct gating_desc *ga10b_elcg_ce_get_gating_prod(void);
+
+#endif /* GA10B_GATING_REGLIST_H */
diff --git a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga100.h b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga100.h
new file mode 100644
index 000000000..8435a3493
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga100.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_PRIV_RING_GA100_H
+#define NVGPU_PRIV_RING_GA100_H
+
+#include <nvgpu/types.h>
+
+#ifdef CONFIG_NVGPU_MIG
+int ga100_priv_ring_config_gpc_rs_map(struct gk20a *g, bool enable);
+#endif
+
+#endif /* NVGPU_PRIV_RING_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga100_fusa.c b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga100_fusa.c
new file mode 100644
index 000000000..e80fb32a2
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga100_fusa.c
@@ -0,0 +1,110 @@
+/*
+ * GA100 priv ring
+ *
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <nvgpu/log.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/nvgpu_err.h>
+#include <nvgpu/static_analysis.h>
+
+#include "priv_ring_ga100.h"
+
+#include <nvgpu/hw/ga100/hw_pri_ringmaster_ga100.h>
+
+#ifdef CONFIG_NVGPU_MIG
+#include <nvgpu/grmgr.h>
+
+int ga100_priv_ring_config_gpc_rs_map(struct gk20a *g, bool enable)
+{
+	u32 reg_val;
+	u32 index;
+	u32 local_id;
+	u32 logical_gpc_id = 0U;
+	struct nvgpu_gr_syspipe *gr_syspipe;
+
+	for (index = 0U; index < g->mig.num_gpu_instances; index++) {
+		if (!nvgpu_grmgr_is_mig_type_gpu_instance(
+				&g->mig.gpu_instance[index])) {
+			nvgpu_log(g, gpu_dbg_mig, "skip physical instance[%u]",
+				index);
+			continue;
+		}
+		gr_syspipe = &g->mig.gpu_instance[index].gr_syspipe;
+
+		for (local_id = 0U; local_id < gr_syspipe->num_gpc; local_id++) {
+			logical_gpc_id = gr_syspipe->gpcs[local_id].logical_id;
+			reg_val = nvgpu_readl(g, pri_ringmaster_gpc_rs_map_r(
+				logical_gpc_id));
+
+			if (enable) {
+				reg_val = set_field(reg_val,
+					pri_ringmaster_gpc_rs_map_smc_engine_id_m(),
+					pri_ringmaster_gpc_rs_map_smc_engine_id_f(
+						gr_syspipe->gr_syspipe_id));
+				reg_val = set_field(reg_val,
+					pri_ringmaster_gpc_rs_map_smc_engine_local_cluster_id_m(),
+					pri_ringmaster_gpc_rs_map_smc_engine_local_cluster_id_f(
+						local_id));
+				reg_val = set_field(reg_val,
+					pri_ringmaster_gpc_rs_map_smc_valid_m(),
+					pri_ringmaster_gpc_rs_map_smc_valid_f(
+						pri_ringmaster_gpc_rs_map_smc_valid_true_v()));
+			} else {
+				reg_val = set_field(reg_val,
+					pri_ringmaster_gpc_rs_map_smc_valid_m(),
+					pri_ringmaster_gpc_rs_map_smc_valid_f(
+						pri_ringmaster_gpc_rs_map_smc_valid_false_v()));
+			}
+
+			nvgpu_writel(g, pri_ringmaster_gpc_rs_map_r(logical_gpc_id),
+				reg_val);
+
+			nvgpu_log(g, gpu_dbg_mig,
+				"[%d] gpu_instance_id[%u] gr_syspipe_id[%u] gr_instance_id[%u] "
+					"local_gpc_id[%u] physical_id[%u] logical_id[%u] "
+					"gpcgrp_id[%u] reg_val[%x] enable[%d] ",
+				index,
+				g->mig.gpu_instance[index].gpu_instance_id,
+				gr_syspipe->gr_syspipe_id,
+				gr_syspipe->gr_instance_id,
+				local_id,
+				gr_syspipe->gpcs[local_id].physical_id,
+				gr_syspipe->gpcs[local_id].logical_id,
+				gr_syspipe->gpcs[local_id].gpcgrp_id,
+				reg_val,
+				enable);
+		}
+		/*
+		 * Do a dummy read on last written GPC to ensure that RS_MAP has been acked
+		 * by all slave ringstations.
+		 */
+		reg_val = nvgpu_readl(g, pri_ringmaster_gpc_rs_map_r(
+			logical_gpc_id));
+	}
+
+	return 0;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b.h b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b.h
new file mode 100644
index 000000000..e1380563b
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_PRIV_RING_GA10B_H
+#define NVGPU_PRIV_RING_GA10B_H
+
+#include <nvgpu/types.h>
+
+/*
+ * Helper macros for decoding falcon mem access violation of pattern:
+ * BADF54xx - FALCON_MEM_ACCESS_PRIV_LEVEL_VIOLATION.
+ * Where xx is interpreted as follows:
+ * bit [7] = 0 - IMEM, 1 - DMEM.
+ * bit [6] = 0 - last transaction caused violation.
+ * bits [5:4] = access level.
+ * bits [3:0] = existing priv level mask.
+ */
+#define FALCON_DMEM_VIOLATION_MSK()	BIT32(7U)
+#define FALCON_MEM_VIOLATION_PRIVLEVEL_ACCESS_VAL(x) \
+	(((x) & (BIT32(5U) | BIT32(4U))) >> 4U)
+#define FALCON_MEM_VIOLATION_PRIVLEVEL_MSK_VAL(x) \
+	 ((x) & (BIT32(3U) | BIT32(2U) | BIT32(1U) | BIT32(0U)))
+
+/*
+ * Helper macros for decoding source id mask violation of pattern:
+ * BADF41xx - TARGET_MASK_VIOLATION.
+ * Where xx is interpreted as follows:
+ * bits [7:6] = target mask:
+ *              00 - all rd/wr is blocked.
+ *              01 - all wr is blocked, rd is downgraded to priv_level 0.
+ *              02 - rd/wr is downgraded to priv_level 0.
+ *              03 - rd/wr is allowed as it is.
+ * bit [5] = b'0.
+ * bits [4:0] = source id.
+ */
+#define TARGET_MASK_VIOLATION_MSK_VAL(x) \
+	(((x) & (BIT32(7U) | BIT32(6U))) >> 6U)
+#define TARGET_MASK_VIOLATION_SRCID_VAL(x) \
+	((x) & (BIT32(4U) | BIT32(3U) | BIT32(2U) | BIT32(1U) | BIT32(0U)))
+
+/*
+ * Helper macros for decoding PRI access violation error of pattern:
+ * BADF51xx, BADF52xx - direct/indirect PRIV_LEVEL_VIOLATION.
+ * Where xx is interpreted as follows:
+ * bits [7:6] = b'00
+ * bits [5:4] = request_priv_level
+ * bits [3:0] = rd/wr protection mask
+ */
+#define PRI_ACCESS_VIOLATION_MSK_VAL(x) \
+	(((x) & (BIT32(3U) | BIT32(2U) | BIT32(1U) | BIT32(0U))))
+#define PRI_ACCESS_VIOLATON_LEVEL_VAL(x) \
+	(((x) & (BIT32(5U) | BIT32(4U))) >> 4U)
+
+/*
+ * Helper macros for decoding source enable violations of pattern:
+ * BADF57xx and BADF59xx - direct/indirect SOURCE_ENABLE_VIOLATION.
+ * Where xx is interpreted as follows:
+ * bits [7:6] = request_priv_level
+ * bits [5] = source violation control
+ * bits [4:0] = source id
+ */
+#define SRC_EN_VIOLAION_CTRL_VAL(x)	(((x) & BIT32(5U)) >> 5U)
+#define SRC_EN_VIOLATION_PRIV_LEVEL_VAL(x) \
+	(((x) & (BIT32(7U) | BIT32(6U))) >> 6U)
+#define SRC_EN_VIOLATION_SRCID_VAL(x) \
+	((x) & (BIT32(4U) | BIT32(3U) | BIT32(2U) | BIT32(1U) | BIT32(0U)))
+
+/*
+ * Helper macros for decoding local priv ring errors of pattern:
+ * BADF53xx - LOCAL_PRIV_RING_ERR
+ * bits [6:0] = local target index
+ */
+#define PRIV_LOCAL_TARGET_INDEX(x) \
+	((x) & (BIT32(6U) | BIT32(5U) | BIT32(4U) | BIT32(3U) | BIT32(2U) |\
+		BIT32(1U) | BIT32(0U)))
+
+struct gk20a;
+
+void ga10b_priv_ring_isr_handle_0(struct gk20a *g, u32 status0);
+void ga10b_priv_ring_isr_handle_1(struct gk20a *g, u32 status1);
+void ga10b_priv_ring_decode_error_code(struct gk20a *g, u32 error_code);
+u32 ga10b_priv_ring_enum_ltc(struct gk20a *g);
+void ga10b_priv_ring_read_pri_fence(struct gk20a *g);
+
+#ifdef CONFIG_NVGPU_MIG
+int ga10b_priv_ring_config_gr_remap_window(struct gk20a *g, u32 gr_syspipe_id,
+		bool enable);
+int ga10b_priv_ring_config_gpc_rs_map(struct gk20a *g, bool enable);
+#endif
+
+#endif /* NVGPU_PRIV_RING_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b_fusa.c
new file mode 100644
index 000000000..6c52be5c7
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b_fusa.c
@@ -0,0 +1,712 @@
+/*
+ * GA10B priv ring
+ *
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <nvgpu/log.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/nvgpu_err.h>
+#include <nvgpu/static_analysis.h>
+
+#include "priv_ring_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_proj_ga10b.h>
+#include <nvgpu/hw/ga10b/hw_pri_ringmaster_ga10b.h>
+#include <nvgpu/hw/ga10b/hw_pri_sys_ga10b.h>
+#include <nvgpu/hw/ga10b/hw_pri_gpc_ga10b.h>
+#include <nvgpu/hw/ga10b/hw_pri_fbp_ga10b.h>
+
+#ifdef CONFIG_NVGPU_MIG
+#include <nvgpu/hw/ga10b/hw_pri_ringstation_sys_ga10b.h>
+#include <nvgpu/grmgr.h>
+#endif
+
+/*
+ * PRI Error decoding
+ *
+ * Each PRI error is associated with a 32 bit error code. Out of which bits 31:8
+ * convey a specific error type and bits 7:0 provide additional information
+ * relevant to the specific error type.
+ *
+ * pri_error_code captures all various types of PRI errors and provides a
+ * brief description about the error along with a function to decode the extra
+ * error information contained in bits 7:0. Each reported error is attempted to
+ * be matched against an entry in the error types list, if a match is found the
+ * error is decoded with the information from the matched entry. In case of no
+ * matches the error code is reported as "unknown".
+ */
+
+/*
+ * Helper functions to decode error extra fields: bits 7:0.
+ */
+static void decode_pri_client_error(struct gk20a *g, u32 value);
+static void decode_pri_local_error(struct gk20a *g, u32 value);
+static void decode_pri_access_violation(struct gk20a *g, u32 value);
+static void decode_pri_falcom_mem_violation(struct gk20a *g, u32 value);
+static void decode_pri_route_error(struct gk20a *g, u32 value);
+static void decode_pri_source_en_violation(struct gk20a *g, u32 value);
+static void decode_pri_target_mask_violation(struct gk20a *g, u32 value);
+static void decode_pri_undefined_error_extra_info(struct gk20a *g, u32 value);
+
+/*
+ * Helper functions to handle priv_ring bits associated with status0.
+ */
+static void ga10b_priv_ring_handle_sys_write_errors(struct gk20a *g, u32 status);
+static void ga10b_priv_ring_handle_fbp_write_errors(struct gk20a *g, u32 status);
+
+/*
+ * Map error code bits 31:8 to a brief description and assign a function
+ * pointer capable of decoding the associated error extra bits.
+ */
+struct pri_error_code {
+	const char *desc;
+	void (*decode_pri_error_extra_info)(struct gk20a *g, u32 error_extra);
+};
+
+/*
+ * Group pri error codes in the range [0xbadf001xx - 0xbadf001xx].
+ */
+static struct pri_error_code bad001xx[] = {
+	{ "host pri timeout error", decode_pri_client_error },
+	{ "undefined", decode_pri_undefined_error_extra_info }
+};
+static const size_t nbad001xx_entries = sizeof(bad001xx) / sizeof(*bad001xx);
+
+/*
+ * Group pri error codes in the range [0xbad00fxx - 0xbad00fxx].
+ */
+static struct pri_error_code bad00fxx[] = {
+	{ "host fecs error", decode_pri_client_error },
+	{ "undefined", decode_pri_undefined_error_extra_info }
+};
+static const size_t nbad00fxx_entries = sizeof(bad00fxx) / sizeof(*bad00fxx);
+
+/*
+ * Group pri error codes in the range [0xbad0b0xx - 0xbad0b0xx].
+ */
+static struct pri_error_code bad0b0xx[] = {
+	{ "fb ack timeout error", decode_pri_client_error },
+	{ "undefined", decode_pri_undefined_error_extra_info }
+};
+static const size_t nbad0b0xx_entries = sizeof(bad0b0xx) / sizeof(*bad0b0xx);
+
+/*
+ * Group pri error codes in the range [0xbadf10xx - 0xbadf19xx].
+ */
+static struct pri_error_code badf1yxx[] = {
+	{ "client timeout", decode_pri_client_error },
+	{ "decode error", decode_pri_client_error },
+	{ "client in reset", decode_pri_client_error },
+	{ "client floorswept", decode_pri_client_error },
+	{ "client stuck ack", decode_pri_client_error },
+	{ "client expected ack", decode_pri_client_error },
+	{ "fence error", decode_pri_client_error },
+	{ "subid error", decode_pri_client_error },
+	{ "rdata wait violation", decode_pri_client_error },
+	{ "write byte enable errror", decode_pri_client_error },
+	{ "undefined", decode_pri_undefined_error_extra_info }
+};
+static const size_t nbadf1yxx_entries =  sizeof(badf1yxx) / sizeof(*badf1yxx);
+
+/*
+ * Group pri error codes in the range [0xbadf20xx - 0xbadf23xx].
+ */
+static struct pri_error_code badf2yxx[] = {
+	{ "orphan(gpc/fbp)",  decode_pri_client_error },
+	{ "power ok timeout",  decode_pri_client_error },
+	{ "orphan(gpc/fbp) powergated",  decode_pri_client_error },
+	{ "target powergated",  decode_pri_client_error },
+	{ "undefined", decode_pri_undefined_error_extra_info }
+};
+static const size_t nbadf2yxx_entries =  sizeof(badf2yxx) / sizeof(*badf2yxx);
+
+/*
+ * Group pri error codes in the range [0xbadf30xx - 0xbadf31xx].
+ */
+static struct pri_error_code badf3yxx[] = {
+	{ "priv ring dead",  decode_pri_client_error },
+	{ "priv ring dead low power",  decode_pri_client_error },
+	{ "undefined", decode_pri_undefined_error_extra_info }
+};
+static const size_t nbadf3yxx_entries =  sizeof(badf3yxx) / sizeof(*badf3yxx);
+
+/*
+ * Group pri error codes in the range [0xbadf40xx - 0xbadf41xx].
+ */
+static struct pri_error_code badf4yxx[] = {
+	{ "trap",  decode_pri_client_error },
+	{ "target mask violation", decode_pri_target_mask_violation },
+	{ "undefined", decode_pri_undefined_error_extra_info }
+};
+static const size_t nbadf4yxx_entries =  sizeof(badf4yxx) / sizeof(*badf4yxx);
+
+/*
+ * Group pri error codes in the range [0xbadf50xx - 0xbadf59xx].
+ */
+static struct pri_error_code badf5yxx[] = {
+	{ "client error", decode_pri_client_error },
+	{ "priv level violation", decode_pri_access_violation },
+	{ "indirect priv level violation", decode_pri_access_violation },
+	{ "local priv ring error", decode_pri_local_error },
+	{ "falcon mem priv level violation", decode_pri_falcom_mem_violation },
+	{ "route error", decode_pri_route_error },
+	{ "custom error", decode_pri_undefined_error_extra_info },
+	{ "source enable violation", decode_pri_source_en_violation },
+	{ "unknown", decode_pri_undefined_error_extra_info },
+	{ "indirect source enable violation", decode_pri_source_en_violation },
+	{ "undefined", decode_pri_undefined_error_extra_info }
+};
+static const size_t nbadf5yxx_entries = sizeof(badf5yxx) / sizeof(*badf5yxx);
+
+/*
+ * Group pri error codes in the range [0xbadf60xx].
+ */
+static struct pri_error_code badf6yxx[] = {
+	{ "lock from security sensor", decode_pri_undefined_error_extra_info },
+	{ "undefined", decode_pri_undefined_error_extra_info }
+};
+static const size_t nbadf6yxx_entries = sizeof(badf6yxx) / sizeof(*badf6yxx);
+
+/*
+ * Group error extra values in range [0x1 - 0x5].
+ */
+static const char *pri_client_error_extra_0x[] = {
+	"async idle",
+	"async req",
+	"async read data wait",
+	"async hold",
+	"async wait ack",
+	"undefined"
+};
+static const size_t npri_client_error_extra_0x =
+sizeof(pri_client_error_extra_0x) / sizeof(*pri_client_error_extra_0x);
+
+/*
+ * Group error extra values in range [0x20 - 0x21].
+ */
+static const char *pri_client_error_extra_2x[] = {
+	"extra sync req",
+	"extra sync read data wait",
+	"undefined"
+};
+static const size_t npri_client_error_extra_2x =
+sizeof(pri_client_error_extra_2x) / sizeof(*pri_client_error_extra_2x);
+
+/*
+ * Group error extra values in range [0x40 - 0x48].
+ */
+static const char *pri_client_error_extra_4x[] = {
+	"no such address",
+	"external error",
+	"index range errror",
+	"reset",
+	"register in reset",
+	"power gated",
+	"subpri floor swept",
+	"subpri clock off",
+	"undefined"
+};
+static const size_t npri_client_error_extra_4x =
+sizeof(pri_client_error_extra_4x) / sizeof(*pri_client_error_extra_4x);
+
+/*
+ * Group error extra values for route error in range [0x45 - 0x46].
+ */
+static const char *pri_route_error_extra_4x[] = {
+	"write only address",
+	"timeout",
+	"undefined"
+};
+static const size_t npri_route_error_extra_4x =
+sizeof(pri_route_error_extra_4x) / sizeof(*pri_route_error_extra_4x);
+
+static void decode_pri_undefined_error_extra_info(struct gk20a *g, u32 value)
+{
+	nvgpu_err(g, "[Extra Info]: undefined, value(0x%x)", value);
+}
+
+static void decode_pri_client_error(struct gk20a *g, u32 value)
+{
+	const char **lookup_table = { (const char* []){ "undefined" } };
+	size_t lookup_table_size = 1;
+	size_t index = 0;
+
+	if (value >= pri_sys_pri_error_extra_no_such_address_v()) {
+		index = value - pri_sys_pri_error_extra_no_such_address_v();
+		lookup_table = pri_client_error_extra_4x;
+		lookup_table_size = npri_client_error_extra_4x;
+
+	} else if (value >= pri_sys_pri_error_extra_extra_sync_req_v()) {
+		index = value - pri_sys_pri_error_extra_extra_sync_req_v();
+		lookup_table = pri_client_error_extra_2x;
+		lookup_table_size = npri_client_error_extra_2x;
+
+	} else if (value >= pri_sys_pri_error_extra_async_idle_v()) {
+		index = value - pri_sys_pri_error_extra_async_idle_v();
+		lookup_table = pri_client_error_extra_0x;
+		lookup_table_size = npri_client_error_extra_0x;
+	}
+
+	/*
+	 * An index which falls outside the lookup table size is considered
+	 * unknown. The index is updated to the last valid entry of the table,
+	 * which is reserved for this purpose.
+	 */
+	if (index >= lookup_table_size) {
+		index = lookup_table_size - 1;
+	}
+
+	nvgpu_err(g, "[Extra Info]: %s, value(0x%x)",
+			lookup_table[index], value);
+}
+
+static void decode_pri_target_mask_violation(struct gk20a *g, u32 value)
+{
+	u32 target_mask, source_id;
+
+	target_mask = TARGET_MASK_VIOLATION_MSK_VAL(value);
+	source_id = TARGET_MASK_VIOLATION_SRCID_VAL(value);
+
+	nvgpu_err(g, "[Extra Info]: target_mask(0x%x), source_id(0x%x)",
+			target_mask, source_id);
+}
+
+static void decode_pri_access_violation(struct gk20a *g, u32 value)
+{
+	u32 priv_mask = PRI_ACCESS_VIOLATION_MSK_VAL(value);
+	u32 priv_level = PRI_ACCESS_VIOLATON_LEVEL_VAL(value);
+
+	nvgpu_err(g, "[Extra Info]: priv_level(0x%x), priv_mask(0x%x)",
+			priv_level, priv_mask);
+}
+
+static void decode_pri_falcom_mem_violation(struct gk20a *g, u32 value)
+{
+	bool imem_violation = true;
+	u32 fault_priv_level;
+	u32 mem_priv_level_mask;
+
+	if (value & FALCON_DMEM_VIOLATION_MSK()) {
+		imem_violation = false;
+	}
+	fault_priv_level = FALCON_MEM_VIOLATION_PRIVLEVEL_ACCESS_VAL(value);
+	mem_priv_level_mask = FALCON_MEM_VIOLATION_PRIVLEVEL_MSK_VAL(value);
+	nvgpu_err(g, "[Extra Info]: %s violation, fault_priv_level(0x%x),"\
+			"mem_priv_level_mask(0x%x)",
+			imem_violation ? "IMEM" : "DMEM",
+			fault_priv_level, mem_priv_level_mask);
+}
+
+static void decode_pri_route_error(struct gk20a *g, u32 value)
+{
+	const char **lookup_table = { (const char* []){ "undefined" } };
+	size_t lookup_table_size = 1;
+	size_t index = 0;
+
+	if (value >= pri_sys_pri_error_fecs_pri_route_err_extra_write_only_v()) {
+		index = value - pri_sys_pri_error_fecs_pri_route_err_extra_write_only_v();
+		lookup_table = pri_route_error_extra_4x;
+		lookup_table_size = npri_route_error_extra_4x;
+	}
+
+	/*
+	 * An index which falls outside the lookup table size is considered
+	 * unknown. The index is updated to the last valid entry of the table,
+	 * which is reserved for this purpose.
+	 */
+	if (index >= lookup_table_size) {
+		index = lookup_table_size - 1;
+	}
+
+	nvgpu_err(g, "[Extra Info]: %s, value(0x%x)", lookup_table[index],
+			value);
+}
+
+static void decode_pri_source_en_violation(struct gk20a *g, u32 value)
+{
+	u32 priv_level, source_id, source_ctrl;
+
+	priv_level = SRC_EN_VIOLATION_PRIV_LEVEL_VAL(value);
+	source_ctrl = SRC_EN_VIOLAION_CTRL_VAL(value);
+	source_id = SRC_EN_VIOLATION_SRCID_VAL(value);
+
+	nvgpu_err(g, "[Extra Info]: priv_level(0x%x), source_ctrl(0x%x),"\
+			" source_id(0x%x)", priv_level, source_ctrl, source_id);
+}
+
+static void decode_pri_local_error(struct gk20a *g, u32 value)
+{
+	if (value == pri_sys_pri_error_local_priv_ring_extra_no_such_target_v()) {
+		nvgpu_err(g, "[Extra Info]: no such target, value(0x%x)",
+				value);
+		return;
+	}
+
+	nvgpu_err(g, "[Extra Info]: target index(0x%x)",
+			PRIV_LOCAL_TARGET_INDEX(value));
+}
+
+void ga10b_priv_ring_decode_error_code(struct gk20a *g, u32 error_code)
+{
+	u32 err_code;
+	u32 error_extra;
+	const struct pri_error_code unknown_error_code =
+			{ "undefined", decode_pri_undefined_error_extra_info };
+	const struct pri_error_code *error_lookup_table = &unknown_error_code;
+	size_t lookup_table_size = 1;
+	size_t index = 0;
+
+	nvgpu_report_pri_err(g, NVGPU_ERR_MODULE_PRI, 0,
+		GPU_PRI_ACCESS_VIOLATION, 0, error_code);
+
+	err_code = pri_sys_pri_error_code_v(error_code);
+	error_extra = pri_sys_pri_error_extra_v(error_code);
+
+	if (err_code >= pri_sys_pri_error_code_fecs_pri_lock_from_security_sensor_v()) {
+		index = err_code -
+			pri_sys_pri_error_code_fecs_pri_lock_from_security_sensor_v();
+		error_lookup_table = badf6yxx;
+		lookup_table_size = nbadf6yxx_entries;
+	} else if (err_code >= pri_sys_pri_error_code_fecs_pri_client_err_v()) {
+		index = err_code - pri_sys_pri_error_code_fecs_pri_client_err_v();
+		error_lookup_table = badf5yxx;
+		lookup_table_size = nbadf5yxx_entries;
+	} else if (err_code >= pri_sys_pri_error_code_fecs_trap_v()) {
+		index = err_code - pri_sys_pri_error_code_fecs_trap_v();
+		error_lookup_table = badf4yxx;
+		lookup_table_size = nbadf4yxx_entries;
+	} else if (err_code >= pri_sys_pri_error_code_fecs_dead_ring_v()) {
+		index = err_code - pri_sys_pri_error_code_fecs_dead_ring_v();
+		error_lookup_table = badf3yxx;
+		lookup_table_size = nbadf3yxx_entries;
+	} else if (err_code >= pri_sys_pri_error_code_fecs_pri_orphan_v()) {
+		index = err_code - pri_sys_pri_error_code_fecs_pri_orphan_v();
+		error_lookup_table = badf2yxx;
+		lookup_table_size = nbadf2yxx_entries;
+	} else if (err_code >=  pri_sys_pri_error_code_fecs_pri_timeout_v()) {
+		index = err_code - pri_sys_pri_error_code_fecs_pri_timeout_v();
+		error_lookup_table = badf1yxx;
+		lookup_table_size = nbadf1yxx_entries;
+	} else if (err_code ==  pri_sys_pri_error_code_host_fb_ack_timeout_v()) {
+		error_lookup_table = bad0b0xx;
+		lookup_table_size = nbad0b0xx_entries;
+	} else if (err_code == pri_sys_pri_error_code_host_fecs_err_v()) {
+		error_lookup_table = bad00fxx;
+		lookup_table_size = nbad00fxx_entries;
+	} else if (err_code == pri_sys_pri_error_code_host_pri_timeout_v()) {
+		error_lookup_table = bad001xx;
+		lookup_table_size = nbad001xx_entries;
+	}
+
+	/*
+	 * An index which falls outside the lookup table size is considered
+	 * unknown. The index is updated to the last valid entry of the table,
+	 * which is reserved for this purpose.
+	 */
+	if (index >= lookup_table_size) {
+		index = lookup_table_size - 1;
+	}
+
+	nvgpu_err(g, "[Error Type]: %s", error_lookup_table[index].desc);
+	error_lookup_table[index].decode_pri_error_extra_info(g, error_extra);
+}
+
+static void ga10b_priv_ring_handle_sys_write_errors(struct gk20a *g, u32 status)
+{
+	u32 error_info;
+	u32 error_code;
+	u32 error_adr, error_wrdat;
+
+	if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status) == 0U) {
+		return;
+	}
+
+	error_info = nvgpu_readl(g, pri_sys_priv_error_info_r());
+	error_code = nvgpu_readl(g, pri_sys_priv_error_code_r());
+	error_adr = nvgpu_readl(g, pri_sys_priv_error_adr_r());
+	error_wrdat = nvgpu_readl(g, pri_sys_priv_error_wrdat_r());
+	nvgpu_err(g, "SYS write error: ADR 0x%08x WRDAT 0x%08x master 0x%08x",
+		error_adr, error_wrdat,
+		pri_sys_priv_error_info_priv_master_v(error_info));
+	nvgpu_err(g,
+		"INFO 0x%08x: (subid 0x%08x priv_level %d local_ordering %d)",
+		error_info, pri_sys_priv_error_info_subid_v(error_info),
+		pri_sys_priv_error_info_priv_level_v(error_info),
+		pri_sys_priv_error_info_local_ordering_v(error_info));
+	nvgpu_err(g , "CODE 0x%08x", error_code);
+	g->ops.priv_ring.decode_error_code(g, error_code);
+}
+
+static void ga10b_priv_ring_handle_fbp_write_errors(struct gk20a *g, u32 status)
+{
+	u32 fbp_status, fbp_stride, fbp_offset, fbp;
+	u32 error_info;
+	u32 error_code;
+	u32 error_adr, error_wrdat;
+
+	fbp_status = pri_ringmaster_intr_status0_gbl_write_error_fbp_v(status);
+	if (fbp_status == 0U) {
+		return;
+	}
+
+	fbp_stride = proj_fbp_priv_stride_v();
+	for (fbp = 0U; fbp < g->ops.priv_ring.get_fbp_count(g); fbp++) {
+		if ((fbp_status & BIT32(fbp)) == 0U) {
+			continue;
+		}
+		fbp_offset = nvgpu_safe_mult_u32(fbp, fbp_stride);
+		error_info = nvgpu_readl(g, nvgpu_safe_add_u32(
+					pri_fbp_fbp0_priv_error_info_r(),
+					fbp_offset));
+		error_code = nvgpu_readl(g, nvgpu_safe_add_u32(
+					pri_fbp_fbp0_priv_error_code_r(),
+					fbp_offset));
+		error_adr = nvgpu_readl(g, nvgpu_safe_add_u32(
+					pri_fbp_fbp0_priv_error_adr_r(),
+					fbp_offset));
+		error_wrdat = nvgpu_readl(g, nvgpu_safe_add_u32(
+					pri_fbp_fbp0_priv_error_wrdat_r(),
+					fbp_offset));
+
+		nvgpu_err(g, "FBP%u write error: "\
+			"ADR 0x%08x WRDAT 0x%08x master 0x%08x", fbp, error_adr,
+			error_wrdat,
+			pri_fbp_fbp0_priv_error_info_priv_master_v(error_info));
+		nvgpu_err(g, "INFO 0x%08x: "\
+			"(subid 0x%08x priv_level %d local_ordering %d)",
+			error_info,
+			pri_fbp_fbp0_priv_error_info_subid_v(error_info),
+			pri_fbp_fbp0_priv_error_info_priv_level_v(error_info),
+			pri_fbp_fbp0_priv_error_info_local_ordering_v(error_info));
+		nvgpu_err(g, "CODE 0x%08x", error_code);
+		g->ops.priv_ring.decode_error_code(g, error_code);
+
+		fbp_status = fbp_status & (~(BIT32(fbp)));
+		if (fbp == 0U) {
+			break;
+		}
+	}
+}
+
+void ga10b_priv_ring_isr_handle_0(struct gk20a *g, u32 status0)
+{
+	if (status0 == 0) {
+		return;
+	}
+
+	if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0U) {
+		nvgpu_err(g, "connectivity problem on the startup sequence");
+	}
+
+	if (pri_ringmaster_intr_status0_disconnect_fault_v(status0) != 0U) {
+		nvgpu_err(g, "ring disconnected");
+	}
+
+	if (pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0U) {
+		nvgpu_err(g, "ring overflowed");
+	}
+
+	if (pri_ringmaster_intr_status0_ring_enum_fault_v(status0) != 0U) {
+		nvgpu_err(g, "mismatch between FS and enumerated RSs");
+	}
+
+	if (pri_ringmaster_intr_status0_gpc_rs_map_config_fault_v(status0) != 0U) {
+		nvgpu_err(g, "invalid GPC_RS_MAP");
+	}
+
+	ga10b_priv_ring_handle_sys_write_errors(g, status0);
+	ga10b_priv_ring_handle_fbp_write_errors(g, status0);
+}
+
+void ga10b_priv_ring_isr_handle_1(struct gk20a *g, u32 status1)
+{
+	u32 error_info;
+	u32 error_code;
+	u32 error_adr, error_wrdat;
+	u32 gpc;
+	u32 gpc_stride, gpc_offset;
+
+	if (status1 == 0U) {
+		return;
+	}
+
+	gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE);
+	for (gpc = 0U; gpc < g->ops.priv_ring.get_gpc_count(g); gpc++) {
+		if ((status1 & BIT32(gpc)) == 0U) {
+			continue;
+		}
+		gpc_offset = nvgpu_safe_mult_u32(gpc, gpc_stride);
+		error_info = nvgpu_readl(g, nvgpu_safe_add_u32(
+					pri_gpc_gpc0_priv_error_info_r(),
+					gpc_offset));
+		error_code = nvgpu_readl(g, nvgpu_safe_add_u32(
+					pri_gpc_gpc0_priv_error_code_r(),
+					gpc_offset));
+		error_adr = nvgpu_readl(g, nvgpu_safe_add_u32(
+					pri_gpc_gpc0_priv_error_adr_r(),
+					gpc_offset));
+		error_wrdat = nvgpu_readl(g, nvgpu_safe_add_u32(
+					pri_gpc_gpc0_priv_error_wrdat_r(),
+					gpc_offset));
+
+		nvgpu_err(g, "GPC%u write error: "\
+			"ADR 0x%08x WRDAT 0x%08x master 0x%08x", gpc, error_adr,
+			error_wrdat,
+			pri_gpc_gpc0_priv_error_info_priv_master_v(error_info));
+		nvgpu_err(g,"INFO 0x%08x: "\
+			"(subid 0x%08x priv_level %d local_ordering %d)",
+			error_info,
+			pri_gpc_gpc0_priv_error_info_subid_v(error_info),
+			pri_gpc_gpc0_priv_error_info_priv_level_v(error_info),
+			pri_gpc_gpc0_priv_error_info_local_ordering_v(error_info));
+		nvgpu_err(g, "CODE 0x%08x", error_code);
+
+		g->ops.priv_ring.decode_error_code(g, error_code);
+
+		status1 = status1 & (~(BIT32(gpc)));
+		if (status1 == 0U) {
+			break;
+		}
+	}
+}
+
+u32 ga10b_priv_ring_enum_ltc(struct gk20a *g)
+{
+	return nvgpu_readl(g, pri_ringmaster_enum_ltc_r());
+}
+
+void ga10b_priv_ring_read_pri_fence(struct gk20a *g)
+{
+	/* Read back to ensure all writes to all chiplets are complete. */
+	nvgpu_readl(g, pri_sys_pri_fence_r());
+	nvgpu_readl(g, pri_gpc_pri_fence_r());
+	nvgpu_readl(g, pri_fbp_pri_fence_r());
+}
+
+#ifdef CONFIG_NVGPU_MIG
+int ga10b_priv_ring_config_gr_remap_window(struct gk20a *g, u32 gr_syspipe_id,
+		bool enable)
+{
+	u32 reg_val;
+
+	reg_val = nvgpu_readl(g, pri_ringstation_sys_bar0_to_pri_window_r());
+
+	reg_val = set_field(reg_val,
+		pri_ringstation_sys_bar0_to_pri_window_index_m(),
+		pri_ringstation_sys_bar0_to_pri_window_index_f(
+			gr_syspipe_id));
+
+	if(enable) {
+		reg_val = set_field(reg_val,
+			pri_ringstation_sys_bar0_to_pri_window_enable_m(),
+			pri_ringstation_sys_bar0_to_pri_window_enable_f(
+				pri_ringstation_sys_bar0_to_pri_window_enable_enable_v()));
+	} else {
+		reg_val = set_field(reg_val,
+			pri_ringstation_sys_bar0_to_pri_window_enable_m(),
+			pri_ringstation_sys_bar0_to_pri_window_enable_f(
+				pri_ringstation_sys_bar0_to_pri_window_enable_disable_v()));
+	}
+	nvgpu_writel(g, pri_ringstation_sys_bar0_to_pri_window_r(), reg_val);
+
+	nvgpu_log(g, gpu_dbg_mig,
+		"old_gr_syspipe_id[%u] new_gr_syspipe_id[%u] "
+			"enable[%u] reg_val[%x] ",
+		g->mig.current_gr_syspipe_id, gr_syspipe_id, enable, reg_val);
+
+	return 0;
+}
+
+int ga10b_priv_ring_config_gpc_rs_map(struct gk20a *g, bool enable)
+{
+	u32 reg_val;
+	u32 index;
+	u32 local_id;
+	u32 logical_gpc_id = 0U;
+	struct nvgpu_gr_syspipe *gr_syspipe;
+
+	for (index = 0U; index < g->mig.num_gpu_instances; index++) {
+		if (!nvgpu_grmgr_is_mig_type_gpu_instance(
+				&g->mig.gpu_instance[index])) {
+			nvgpu_log(g, gpu_dbg_mig, "skip physical instance[%u]",
+				index);
+			continue;
+		}
+		gr_syspipe = &g->mig.gpu_instance[index].gr_syspipe;
+
+		for (local_id = 0U; local_id < gr_syspipe->num_gpc; local_id++) {
+			logical_gpc_id = gr_syspipe->gpcs[local_id].logical_id;
+			reg_val = nvgpu_readl(g, pri_ringmaster_gpc_rs_map_r(
+				logical_gpc_id));
+
+			if (enable) {
+				reg_val = set_field(reg_val,
+					pri_ringmaster_gpc_rs_map_smc_engine_id_m(),
+					pri_ringmaster_gpc_rs_map_smc_engine_id_f(
+						gr_syspipe->gr_syspipe_id));
+				reg_val = set_field(reg_val,
+					pri_ringmaster_gpc_rs_map_smc_engine_local_cluster_id_m(),
+					pri_ringmaster_gpc_rs_map_smc_engine_local_cluster_id_f(
+						local_id));
+				reg_val = set_field(reg_val,
+					pri_ringmaster_gpc_rs_map_smc_enable_m(),
+					pri_ringmaster_gpc_rs_map_smc_enable_f(
+						pri_ringmaster_gpc_rs_map_smc_enable_true_v()));
+			} else {
+				reg_val = set_field(reg_val,
+					pri_ringmaster_gpc_rs_map_smc_enable_m(),
+					pri_ringmaster_gpc_rs_map_smc_enable_f(
+						pri_ringmaster_gpc_rs_map_smc_enable_false_v()));
+			}
+
+			nvgpu_writel(g, pri_ringmaster_gpc_rs_map_r(logical_gpc_id),
+				reg_val);
+
+			nvgpu_log(g, gpu_dbg_mig,
+				"[%d] gpu_instance_id[%u] gr_syspipe_id[%u] gr_instance_id[%u] "
+					"local_gpc_id[%u] physical_id[%u] logical_id[%u] "
+					"gpcgrp_id[%u] reg_val[%x] enable[%d] ",
+				index,
+				g->mig.gpu_instance[index].gpu_instance_id,
+				gr_syspipe->gr_syspipe_id,
+				gr_syspipe->gr_instance_id,
+				local_id,
+				gr_syspipe->gpcs[local_id].physical_id,
+				gr_syspipe->gpcs[local_id].logical_id,
+				gr_syspipe->gpcs[local_id].gpcgrp_id,
+				reg_val,
+				enable);
+		}
+		/*
+		 * Do a dummy read on last written GPC to ensure that RS_MAP has been acked
+		 * by all slave ringstations.
+		 */
+		reg_val = nvgpu_readl(g, pri_ringmaster_gpc_rs_map_r(
+			logical_gpc_id));
+	}
+
+	return 0;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b.h b/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b.h
new file mode 100644
index 000000000..8f6604b37
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef PTIMER_GA10B_H
+#define PTIMER_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void ga10b_ptimer_isr(struct gk20a *g);
+
+#endif /* PTIMER_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b_fusa.c
new file mode 100644
index 000000000..07bdc7c7a
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b_fusa.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/nvgpu_err.h>
+
+#include "ptimer_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_timer_ga10b.h>
+
+void ga10b_ptimer_isr(struct gk20a *g)
+{
+	u32 save0, save1, fecs_errcode = 0;
+	u32 inst = 0U;
+	u32 error_addr;
+
+	save0 = nvgpu_readl(g, timer_pri_timeout_save_0_r());
+	if (timer_pri_timeout_save_0_fecs_tgt_v(save0) != 0U) {
+		/*
+		 * write & addr fields in timeout_save0
+		 * might not be reliable
+		 */
+		fecs_errcode = nvgpu_readl(g,
+				timer_pri_timeout_fecs_errcode_r());
+	}
+
+	save1 = nvgpu_readl(g, timer_pri_timeout_save_1_r());
+	error_addr = timer_pri_timeout_save_0_addr_v(save0) << 2;
+	nvgpu_err(g, "PRI timeout: ADR 0x%08x "
+		"%s  DATA 0x%08x",
+		error_addr,
+		(timer_pri_timeout_save_0_write_v(save0) != 0U) ?
+		"WRITE" : "READ", save1);
+
+	nvgpu_writel(g, timer_pri_timeout_save_0_r(), 0);
+	nvgpu_writel(g, timer_pri_timeout_save_1_r(), 0);
+
+	if (fecs_errcode != 0U) {
+		nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode);
+		if (g->ops.priv_ring.decode_error_code != NULL) {
+			g->ops.priv_ring.decode_error_code(g,
+						fecs_errcode);
+		}
+		/* FECS was the target of PRI access */
+		inst = 1U;
+		/* SAVE_0_ADDR cannot be used in this case */
+		error_addr = 0U;
+	}
+
+	nvgpu_report_pri_err(g, NVGPU_ERR_MODULE_PRI,
+		inst, GPU_PRI_TIMEOUT_ERROR,
+		error_addr, fecs_errcode);
+}
diff --git a/drivers/gpu/nvgpu/hal/regops/allowlist_ga100.c b/drivers/gpu/nvgpu/hal/regops/allowlist_ga100.c
new file mode 100644
index 000000000..a8d4fdb70
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/regops/allowlist_ga100.c
@@ -0,0 +1,1722 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/regops_allowlist.h>
+#include "allowlist_ga100.h"
+
+u32 ga100_hwpm_perfmon_register_offset_allowlist[] = {
+	0x00000000,
+	0x00000004,
+	0x00000008,
+	0x0000000c,
+	0x00000010,
+	0x00000014,
+	0x00000020,
+	0x00000024,
+	0x00000028,
+	0x0000002c,
+	0x00000030,
+	0x00000034,
+	0x00000040,
+	0x00000044,
+	0x00000048,
+	0x0000004c,
+	0x00000050,
+	0x00000054,
+	0x00000058,
+	0x0000005c,
+	0x00000060,
+	0x00000064,
+	0x00000068,
+	0x0000006c,
+	0x00000070,
+	0x00000074,
+	0x00000078,
+	0x0000007c,
+	0x00000080,
+	0x00000084,
+	0x00000088,
+	0x0000008c,
+	0x00000090,
+	0x00000094,
+	0x00000098,
+	0x0000009c,
+	0x000000a0,
+	0x000000a4,
+	0x000000a8,
+	0x000000ac,
+	0x000000b0,
+	0x000000b4,
+	0x000000b8,
+	0x000000bc,
+	0x000000c0,
+	0x000000c4,
+	0x000000c8,
+	0x000000cc,
+	0x000000d0,
+	0x000000d4,
+	0x000000d8,
+	0x000000dc,
+	0x000000e0,
+	0x000000ec,
+	0x000000f8,
+	0x000000fc,
+	0x00000100,
+	0x00000104,
+	0x00000108,
+	0x0000010c,
+	0x00000110,
+	0x00000124,
+	0x00000128,
+	0x00000130,
+};
+
+u32 ga100_hwpm_router_register_offset_allowlist[] = {
+	0x00000000,
+	0x00000008,
+	0x00000010,
+	0x00000014,
+	0x00000150,
+};
+
+u32 ga100_hwpm_pma_channel_register_offset_allowlist[] = {
+	0x0000000c,
+	0x00000610,
+	0x00000618,
+	0x00000620,
+	0x0000063c,
+	0x00000640,
+	0x00000650,
+	0x00000654,
+	0x0000075c,
+};
+
+u32 ga100_hwpm_pma_trigger_register_offset_allowlist[] = {
+	0x00000008,
+	0x00000600,
+	0x00000604,
+	0x00000608,
+	0x0000060c,
+	0x0000062c,
+	0x0000065c,
+	0x00000660,
+	0x00000664,
+	0x00000668,
+	0x0000066c,
+	0x00000670,
+	0x00000674,
+	0x00000678,
+	0x0000067c,
+	0x00000680,
+	0x00000684,
+	0x00000688,
+	0x0000068c,
+	0x00000690,
+	0x00000694,
+	0x00000698,
+	0x0000069c,
+	0x000006a0,
+	0x000006a4,
+	0x000006a8,
+	0x000006ac,
+	0x000006b0,
+	0x000006b4,
+	0x000006b8,
+	0x000006bc,
+	0x000006c0,
+	0x000006c4,
+	0x000006c8,
+	0x000006cc,
+	0x000006d0,
+	0x000006d4,
+	0x000006d8,
+	0x000006dc,
+	0x000006e0,
+	0x000006e4,
+	0x000006e8,
+	0x000006ec,
+	0x000006f0,
+	0x000006f4,
+	0x000006f8,
+	0x000006fc,
+	0x00000700,
+	0x00000704,
+	0x00000708,
+	0x0000070c,
+	0x00000710,
+	0x00000714,
+	0x00000718,
+	0x0000071c,
+	0x00000720,
+	0x00000724,
+	0x00000728,
+	0x0000072c,
+	0x0000075c,
+};
+
+u32 ga100_smpc_register_offset_allowlist[] = {
+	0x00000200,
+	0x00000204,
+	0x00000208,
+	0x0000020c,
+	0x00000210,
+	0x00000214,
+	0x00000218,
+	0x0000021c,
+	0x00000220,
+	0x00000224,
+	0x00000228,
+	0x0000022c,
+	0x00000230,
+	0x00000234,
+	0x00000238,
+	0x0000023c,
+	0x00000240,
+	0x00000244,
+	0x00000248,
+	0x00000300,
+	0x00000304,
+	0x00000308,
+	0x0000030c,
+	0x00000310,
+	0x00000314,
+	0x00000318,
+	0x0000031c,
+	0x00000320,
+	0x00000324,
+	0x00000328,
+	0x0000032c,
+	0x00000330,
+	0x00000334,
+	0x00000338,
+	0x0000033c,
+	0x00000340,
+	0x00000344,
+	0x00000348,
+	0x0000034c,
+	0x00000350,
+	0x00000354,
+	0x00000358,
+	0x0000035c,
+	0x00000360,
+	0x00000364,
+	0x00000368,
+	0x0000036c,
+	0x00000370,
+	0x00000374,
+	0x00000378,
+	0x0000037c,
+	0x00000380,
+	0x00000384,
+	0x00000388,
+	0x0000038c,
+	0x00000390,
+	0x00000394,
+	0x00000398,
+	0x0000039c,
+	0x000003a0,
+	0x000003a4,
+	0x000003a8,
+	0x000003ac,
+	0x000003b0,
+	0x000003b4,
+	0x000003b8,
+	0x000003bc,
+	0x000003c0,
+	0x000003c4,
+	0x00000600,
+	0x00000604,
+	0x00000608,
+	0x0000060c,
+	0x00000610,
+	0x00000614,
+	0x00000618,
+	0x0000061c,
+	0x00000620,
+	0x00000624,
+	0x00000628,
+	0x0000062c,
+	0x00000630,
+	0x00000634,
+	0x00000638,
+	0x0000063c,
+	0x00000640,
+	0x00000644,
+	0x00000648,
+	0x0000064c,
+	0x00000650,
+	0x00000654,
+	0x00000658,
+	0x0000065c,
+	0x00000660,
+	0x00000664,
+	0x00000668,
+	0x0000066c,
+	0x00000670,
+	0x00000674,
+	0x00000678,
+	0x0000067c,
+	0x00000680,
+	0x00000684,
+	0x00000688,
+	0x0000068c,
+	0x00000690,
+	0x00000694,
+	0x00000698,
+	0x0000069c,
+	0x000006a0,
+	0x000006a4,
+	0x000006a8,
+	0x000006ac,
+	0x000006b0,
+	0x000006b4,
+	0x000006b8,
+	0x000006bc,
+	0x000006c0,
+	0x000006c4,
+	0x00000700,
+	0x00000704,
+	0x00000708,
+	0x0000070c,
+	0x00000710,
+	0x00000714,
+	0x00000718,
+	0x0000071c,
+	0x00000720,
+	0x00000724,
+	0x00000728,
+	0x0000072c,
+	0x00000730,
+	0x00000734,
+	0x00000738,
+	0x0000073c,
+	0x00000740,
+	0x00000744,
+	0x00000748,
+	0x0000074c,
+	0x00000750,
+	0x00000754,
+	0x00000758,
+	0x0000075c,
+	0x00000760,
+	0x00000764,
+	0x00000768,
+	0x0000076c,
+	0x00000770,
+	0x00000774,
+	0x00000778,
+	0x0000077c,
+	0x00000780,
+	0x00000784,
+	0x00000788,
+	0x0000078c,
+	0x00000790,
+	0x00000794,
+	0x00000798,
+	0x0000079c,
+	0x000007a0,
+	0x000007a4,
+	0x000007a8,
+	0x000007ac,
+	0x000007b0,
+	0x000007b4,
+	0x000007b8,
+	0x000007bc,
+	0x000007c0,
+	0x000007c4,
+};
+
+u32 ga100_cau_register_offset_allowlist[] = {
+	0x00000000,
+	0x00000004,
+	0x00000008,
+	0x0000000c,
+	0x00000010,
+	0x00000014,
+	0x00000018,
+	0x0000001c,
+	0x00000024,
+};
+
+const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmon_register_ranges[] = {
+	{0x00180000, 0x0019fffc},
+	{0x00250040, 0x00250124},
+	{0x00250240, 0x00250324},
+	{0x00278040, 0x0027b324},
+	{0x00200000, 0x0022fffc},
+	{0x00260000, 0x00267ffc},
+};
+
+const struct nvgpu_pm_resource_register_range ga100_hwpm_router_register_ranges[] = {
+	{0x00244000, 0x00244ffc},
+	{0x00246000, 0x002477fc},
+	{0x00248000, 0x002481fc},
+	{0x00251800, 0x00251814},
+	{0x00251a00, 0x00251a14},
+	{0x00251950, 0x00251950},
+	{0x00251b50, 0x00251b50},
+};
+
+const struct nvgpu_pm_resource_register_range ga100_hwpm_pma_channel_register_ranges[] = {
+	{0x0024a610, 0x0024a628},
+	{0x0024a634, 0x0024a658},
+	{0x0024a730, 0x0024a734},
+	{0x0024a00c, 0x0024a00c},
+};
+
+const struct nvgpu_pm_resource_register_range ga100_hwpm_pma_trigger_register_ranges[] = {
+	{0x0024a000, 0x0024a008},
+	{0x0024a010, 0x0024a60c},
+	{0x0024a62c, 0x0024a62c},
+	{0x0024a65c, 0x0024a72c},
+};
+
+const struct nvgpu_pm_resource_register_range ga100_smpc_register_ranges[] = {
+	{0x00580000, 0x005bfffc},
+	{0x00480000, 0x004bfffc},
+};
+
+const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmux_register_ranges[] = {
+	{0x00140028, 0x00140028},
+	{0x00142028, 0x00142028},
+	{0x00144028, 0x00144028},
+	{0x00146028, 0x00146028},
+	{0x00148028, 0x00148028},
+	{0x0014a028, 0x0014a028},
+	{0x0014c028, 0x0014c028},
+	{0x0014e028, 0x0014e028},
+	{0x00150028, 0x00150028},
+	{0x00152028, 0x00152028},
+	{0x00154028, 0x00154028},
+	{0x00156028, 0x00156028},
+	{0x00158028, 0x00158028},
+	{0x0015a028, 0x0015a028},
+	{0x0015c028, 0x0015c028},
+	{0x0015e028, 0x0015e028},
+	{0x00160028, 0x00160028},
+	{0x00162028, 0x00162028},
+	{0x00164028, 0x00164028},
+	{0x00166028, 0x00166028},
+	{0x00168028, 0x00168028},
+	{0x0016a028, 0x0016a028},
+	{0x0016c028, 0x0016c028},
+	{0x0016e028, 0x0016e028},
+	{0x0017e028, 0x0017e028},
+	{0x00900100, 0x00900100},
+	{0x00904100, 0x00904100},
+	{0x00908100, 0x00908100},
+	{0x0090c100, 0x0090c100},
+	{0x00910100, 0x00910100},
+	{0x00914100, 0x00914100},
+	{0x00918100, 0x00918100},
+	{0x0091c100, 0x0091c100},
+	{0x00920100, 0x00920100},
+	{0x00924100, 0x00924100},
+	{0x00928100, 0x00928100},
+	{0x0092c100, 0x0092c100},
+	{0x00930100, 0x00930100},
+	{0x00934100, 0x00934100},
+	{0x00938100, 0x00938100},
+	{0x0093c100, 0x0093c100},
+	{0x00940100, 0x00940100},
+	{0x00944100, 0x00944100},
+	{0x00948100, 0x00948100},
+	{0x0094c100, 0x0094c100},
+	{0x00950100, 0x00950100},
+	{0x00954100, 0x00954100},
+	{0x00958100, 0x00958100},
+	{0x0095c100, 0x0095c100},
+	{0x009a0100, 0x009a0100},
+	{0x00140550, 0x00140550},
+	{0x00140750, 0x00140750},
+	{0x00140950, 0x00140950},
+	{0x00140b50, 0x00140b50},
+	{0x00142550, 0x00142550},
+	{0x00142750, 0x00142750},
+	{0x00142950, 0x00142950},
+	{0x00142b50, 0x00142b50},
+	{0x00144550, 0x00144550},
+	{0x00144750, 0x00144750},
+	{0x00144950, 0x00144950},
+	{0x00144b50, 0x00144b50},
+	{0x00146550, 0x00146550},
+	{0x00146750, 0x00146750},
+	{0x00146950, 0x00146950},
+	{0x00146b50, 0x00146b50},
+	{0x00148550, 0x00148550},
+	{0x00148750, 0x00148750},
+	{0x00148950, 0x00148950},
+	{0x00148b50, 0x00148b50},
+	{0x0014a550, 0x0014a550},
+	{0x0014a750, 0x0014a750},
+	{0x0014a950, 0x0014a950},
+	{0x0014ab50, 0x0014ab50},
+	{0x0014c550, 0x0014c550},
+	{0x0014c750, 0x0014c750},
+	{0x0014c950, 0x0014c950},
+	{0x0014cb50, 0x0014cb50},
+	{0x0014e550, 0x0014e550},
+	{0x0014e750, 0x0014e750},
+	{0x0014e950, 0x0014e950},
+	{0x0014eb50, 0x0014eb50},
+	{0x00150550, 0x00150550},
+	{0x00150750, 0x00150750},
+	{0x00150950, 0x00150950},
+	{0x00150b50, 0x00150b50},
+	{0x00152550, 0x00152550},
+	{0x00152750, 0x00152750},
+	{0x00152950, 0x00152950},
+	{0x00152b50, 0x00152b50},
+	{0x00154550, 0x00154550},
+	{0x00154750, 0x00154750},
+	{0x00154950, 0x00154950},
+	{0x00154b50, 0x00154b50},
+	{0x00156550, 0x00156550},
+	{0x00156750, 0x00156750},
+	{0x00156950, 0x00156950},
+	{0x00156b50, 0x00156b50},
+	{0x00158550, 0x00158550},
+	{0x00158750, 0x00158750},
+	{0x00158950, 0x00158950},
+	{0x00158b50, 0x00158b50},
+	{0x0015a550, 0x0015a550},
+	{0x0015a750, 0x0015a750},
+	{0x0015a950, 0x0015a950},
+	{0x0015ab50, 0x0015ab50},
+	{0x0015c550, 0x0015c550},
+	{0x0015c750, 0x0015c750},
+	{0x0015c950, 0x0015c950},
+	{0x0015cb50, 0x0015cb50},
+	{0x0015e550, 0x0015e550},
+	{0x0015e750, 0x0015e750},
+	{0x0015e950, 0x0015e950},
+	{0x0015eb50, 0x0015eb50},
+	{0x00160550, 0x00160550},
+	{0x00160750, 0x00160750},
+	{0x00160950, 0x00160950},
+	{0x00160b50, 0x00160b50},
+	{0x00162550, 0x00162550},
+	{0x00162750, 0x00162750},
+	{0x00162950, 0x00162950},
+	{0x00162b50, 0x00162b50},
+	{0x00164550, 0x00164550},
+	{0x00164750, 0x00164750},
+	{0x00164950, 0x00164950},
+	{0x00164b50, 0x00164b50},
+	{0x00166550, 0x00166550},
+	{0x00166750, 0x00166750},
+	{0x00166950, 0x00166950},
+	{0x00166b50, 0x00166b50},
+	{0x00168550, 0x00168550},
+	{0x00168750, 0x00168750},
+	{0x00168950, 0x00168950},
+	{0x00168b50, 0x00168b50},
+	{0x0016a550, 0x0016a550},
+	{0x0016a750, 0x0016a750},
+	{0x0016a950, 0x0016a950},
+	{0x0016ab50, 0x0016ab50},
+	{0x0016c550, 0x0016c550},
+	{0x0016c750, 0x0016c750},
+	{0x0016c950, 0x0016c950},
+	{0x0016cb50, 0x0016cb50},
+	{0x0016e550, 0x0016e550},
+	{0x0016e750, 0x0016e750},
+	{0x0016e950, 0x0016e950},
+	{0x0016eb50, 0x0016eb50},
+	{0x00140350, 0x00140350},
+	{0x00142350, 0x00142350},
+	{0x00144350, 0x00144350},
+	{0x00146350, 0x00146350},
+	{0x00148350, 0x00148350},
+	{0x0014a350, 0x0014a350},
+	{0x0014c350, 0x0014c350},
+	{0x0014e350, 0x0014e350},
+	{0x00150350, 0x00150350},
+	{0x00152350, 0x00152350},
+	{0x00154350, 0x00154350},
+	{0x00156350, 0x00156350},
+	{0x00158350, 0x00158350},
+	{0x0015a350, 0x0015a350},
+	{0x0015c350, 0x0015c350},
+	{0x0015e350, 0x0015e350},
+	{0x00160350, 0x00160350},
+	{0x00162350, 0x00162350},
+	{0x00164350, 0x00164350},
+	{0x00166350, 0x00166350},
+	{0x00168350, 0x00168350},
+	{0x0016a350, 0x0016a350},
+	{0x0016c350, 0x0016c350},
+	{0x0016e350, 0x0016e350},
+	{0x0017e350, 0x0017e350},
+	{0x0017e550, 0x0017e550},
+	{0x0017e750, 0x0017e750},
+	{0x0017e950, 0x0017e950},
+	{0x0017eb50, 0x0017eb50},
+	{0x009001e0, 0x009001e4},
+	{0x009041e0, 0x009041e4},
+	{0x009081e0, 0x009081e4},
+	{0x0090c1e0, 0x0090c1e4},
+	{0x009101e0, 0x009101e4},
+	{0x009141e0, 0x009141e4},
+	{0x009181e0, 0x009181e4},
+	{0x0091c1e0, 0x0091c1e4},
+	{0x009201e0, 0x009201e4},
+	{0x009241e0, 0x009241e4},
+	{0x009281e0, 0x009281e4},
+	{0x0092c1e0, 0x0092c1e4},
+	{0x009301e0, 0x009301e4},
+	{0x009341e0, 0x009341e4},
+	{0x009381e0, 0x009381e4},
+	{0x0093c1e0, 0x0093c1e4},
+	{0x009401e0, 0x009401e4},
+	{0x009441e0, 0x009441e4},
+	{0x009481e0, 0x009481e4},
+	{0x0094c1e0, 0x0094c1e4},
+	{0x009501e0, 0x009501e4},
+	{0x009541e0, 0x009541e4},
+	{0x009581e0, 0x009581e4},
+	{0x0095c1e0, 0x0095c1e4},
+	{0x009a01e0, 0x009a01e4},
+	{0x00500384, 0x00500384},
+	{0x005004a0, 0x005004a0},
+	{0x00500604, 0x00500604},
+	{0x00500680, 0x00500680},
+	{0x00500714, 0x00500714},
+	{0x0050081c, 0x0050081c},
+	{0x00500884, 0x00500884},
+	{0x005008c8, 0x005008cc},
+	{0x00500b04, 0x00500b04},
+	{0x00500c04, 0x00500c04},
+	{0x00500c88, 0x00500c88},
+	{0x00500d00, 0x00500d00},
+	{0x00500e08, 0x00500e08},
+	{0x00500f08, 0x00500f08},
+	{0x0050100c, 0x0050100c},
+	{0x005020a8, 0x005020a8},
+	{0x005028a0, 0x005028a8},
+	{0x00508384, 0x00508384},
+	{0x005084a0, 0x005084a0},
+	{0x00508604, 0x00508604},
+	{0x00508680, 0x00508680},
+	{0x00508714, 0x00508714},
+	{0x0050881c, 0x0050881c},
+	{0x00508884, 0x00508884},
+	{0x005088c8, 0x005088cc},
+	{0x00508b04, 0x00508b04},
+	{0x00508c04, 0x00508c04},
+	{0x00508c88, 0x00508c88},
+	{0x00508d00, 0x00508d00},
+	{0x00508e08, 0x00508e08},
+	{0x00508f08, 0x00508f08},
+	{0x0050900c, 0x0050900c},
+	{0x0050a0a8, 0x0050a0a8},
+	{0x0050a8a0, 0x0050a8a8},
+	{0x00510384, 0x00510384},
+	{0x005104a0, 0x005104a0},
+	{0x00510604, 0x00510604},
+	{0x00510680, 0x00510680},
+	{0x00510714, 0x00510714},
+	{0x0051081c, 0x0051081c},
+	{0x00510884, 0x00510884},
+	{0x005108c8, 0x005108cc},
+	{0x00510b04, 0x00510b04},
+	{0x00510c04, 0x00510c04},
+	{0x00510c88, 0x00510c88},
+	{0x00510d00, 0x00510d00},
+	{0x00510e08, 0x00510e08},
+	{0x00510f08, 0x00510f08},
+	{0x0051100c, 0x0051100c},
+	{0x005120a8, 0x005120a8},
+	{0x005128a0, 0x005128a8},
+	{0x00518384, 0x00518384},
+	{0x005184a0, 0x005184a0},
+	{0x00518604, 0x00518604},
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+	{0x00537b04, 0x00537b04},
+	{0x00537bdc, 0x00537bdc},
+	{0x00537c0c, 0x00537c0c},
+	{0x00537e64, 0x00537e64},
+	{0x0053c054, 0x0053c054},
+	{0x0053c2b0, 0x0053c2b0},
+	{0x0053c304, 0x0053c304},
+	{0x0053c3dc, 0x0053c3dc},
+	{0x0053c40c, 0x0053c40c},
+	{0x0053c664, 0x0053c664},
+	{0x0053c854, 0x0053c854},
+	{0x0053cab0, 0x0053cab0},
+	{0x0053cb04, 0x0053cb04},
+	{0x0053cbdc, 0x0053cbdc},
+	{0x0053cc0c, 0x0053cc0c},
+	{0x0053ce64, 0x0053ce64},
+	{0x0053d054, 0x0053d054},
+	{0x0053d2b0, 0x0053d2b0},
+	{0x0053d304, 0x0053d304},
+	{0x0053d3dc, 0x0053d3dc},
+	{0x0053d40c, 0x0053d40c},
+	{0x0053d664, 0x0053d664},
+	{0x0053d854, 0x0053d854},
+	{0x0053dab0, 0x0053dab0},
+	{0x0053db04, 0x0053db04},
+	{0x0053dbdc, 0x0053dbdc},
+	{0x0053dc0c, 0x0053dc0c},
+	{0x0053de64, 0x0053de64},
+	{0x0053e054, 0x0053e054},
+	{0x0053e2b0, 0x0053e2b0},
+	{0x0053e304, 0x0053e304},
+	{0x0053e3dc, 0x0053e3dc},
+	{0x0053e40c, 0x0053e40c},
+	{0x0053e664, 0x0053e664},
+	{0x0053e854, 0x0053e854},
+	{0x0053eab0, 0x0053eab0},
+	{0x0053eb04, 0x0053eb04},
+	{0x0053ebdc, 0x0053ebdc},
+	{0x0053ec0c, 0x0053ec0c},
+	{0x0053ee64, 0x0053ee64},
+	{0x0053f054, 0x0053f054},
+	{0x0053f2b0, 0x0053f2b0},
+	{0x0053f304, 0x0053f304},
+	{0x0053f3dc, 0x0053f3dc},
+	{0x0053f40c, 0x0053f40c},
+	{0x0053f664, 0x0053f664},
+	{0x0053f854, 0x0053f854},
+	{0x0053fab0, 0x0053fab0},
+	{0x0053fb04, 0x0053fb04},
+	{0x0053fbdc, 0x0053fbdc},
+	{0x0053fc0c, 0x0053fc0c},
+	{0x0053fe64, 0x0053fe64},
+	{0x00419854, 0x00419854},
+	{0x00419ab0, 0x00419ab0},
+	{0x00419b04, 0x00419b04},
+	{0x00419bdc, 0x00419bdc},
+	{0x00419c0c, 0x00419c0c},
+	{0x00419e64, 0x00419e64},
+	{0x0041c054, 0x0041c054},
+	{0x0041c2b0, 0x0041c2b0},
+	{0x0041c304, 0x0041c304},
+	{0x0041c3dc, 0x0041c3dc},
+	{0x0041c40c, 0x0041c40c},
+	{0x0041c664, 0x0041c664},
+	{0x0041c854, 0x0041c854},
+	{0x0041cab0, 0x0041cab0},
+	{0x0041cb04, 0x0041cb04},
+	{0x0041cbdc, 0x0041cbdc},
+	{0x0041cc0c, 0x0041cc0c},
+	{0x0041ce64, 0x0041ce64},
+	{0x0041d054, 0x0041d054},
+	{0x0041d2b0, 0x0041d2b0},
+	{0x0041d304, 0x0041d304},
+	{0x0041d3dc, 0x0041d3dc},
+	{0x0041d40c, 0x0041d40c},
+	{0x0041d664, 0x0041d664},
+	{0x0041d854, 0x0041d854},
+	{0x0041dab0, 0x0041dab0},
+	{0x0041db04, 0x0041db04},
+	{0x0041dbdc, 0x0041dbdc},
+	{0x0041dc0c, 0x0041dc0c},
+	{0x0041de64, 0x0041de64},
+	{0x0041e054, 0x0041e054},
+	{0x0041e2b0, 0x0041e2b0},
+	{0x0041e304, 0x0041e304},
+	{0x0041e3dc, 0x0041e3dc},
+	{0x0041e40c, 0x0041e40c},
+	{0x0041e664, 0x0041e664},
+	{0x0041e854, 0x0041e854},
+	{0x0041eab0, 0x0041eab0},
+	{0x0041eb04, 0x0041eb04},
+	{0x0041ebdc, 0x0041ebdc},
+	{0x0041ec0c, 0x0041ec0c},
+	{0x0041ee64, 0x0041ee64},
+	{0x0041f054, 0x0041f054},
+	{0x0041f2b0, 0x0041f2b0},
+	{0x0041f304, 0x0041f304},
+	{0x0041f3dc, 0x0041f3dc},
+	{0x0041f40c, 0x0041f40c},
+	{0x0041f664, 0x0041f664},
+	{0x0041f854, 0x0041f854},
+	{0x0041fab0, 0x0041fab0},
+	{0x0041fb04, 0x0041fb04},
+	{0x0041fbdc, 0x0041fbdc},
+	{0x0041fc0c, 0x0041fc0c},
+	{0x0041fe64, 0x0041fe64},
+	{0x00501854, 0x00501854},
+	{0x00501ab0, 0x00501ab0},
+	{0x00501b04, 0x00501b04},
+	{0x00501bdc, 0x00501bdc},
+	{0x00501c0c, 0x00501c0c},
+	{0x00501e64, 0x00501e64},
+	{0x00509854, 0x00509854},
+	{0x00509ab0, 0x00509ab0},
+	{0x00509b04, 0x00509b04},
+	{0x00509bdc, 0x00509bdc},
+	{0x00509c0c, 0x00509c0c},
+	{0x00509e64, 0x00509e64},
+	{0x00511854, 0x00511854},
+	{0x00511ab0, 0x00511ab0},
+	{0x00511b04, 0x00511b04},
+	{0x00511bdc, 0x00511bdc},
+	{0x00511c0c, 0x00511c0c},
+	{0x00511e64, 0x00511e64},
+	{0x00519854, 0x00519854},
+	{0x00519ab0, 0x00519ab0},
+	{0x00519b04, 0x00519b04},
+	{0x00519bdc, 0x00519bdc},
+	{0x00519c0c, 0x00519c0c},
+	{0x00519e64, 0x00519e64},
+	{0x00521854, 0x00521854},
+	{0x00521ab0, 0x00521ab0},
+	{0x00521b04, 0x00521b04},
+	{0x00521bdc, 0x00521bdc},
+	{0x00521c0c, 0x00521c0c},
+	{0x00521e64, 0x00521e64},
+	{0x00529854, 0x00529854},
+	{0x00529ab0, 0x00529ab0},
+	{0x00529b04, 0x00529b04},
+	{0x00529bdc, 0x00529bdc},
+	{0x00529c0c, 0x00529c0c},
+	{0x00529e64, 0x00529e64},
+	{0x00531854, 0x00531854},
+	{0x00531ab0, 0x00531ab0},
+	{0x00531b04, 0x00531b04},
+	{0x00531bdc, 0x00531bdc},
+	{0x00531c0c, 0x00531c0c},
+	{0x00531e64, 0x00531e64},
+	{0x00539854, 0x00539854},
+	{0x00539ab0, 0x00539ab0},
+	{0x00539b04, 0x00539b04},
+	{0x00539bdc, 0x00539bdc},
+	{0x00539c0c, 0x00539c0c},
+	{0x00539e64, 0x00539e64},
+	{0x00503014, 0x00503014},
+	{0x005030cc, 0x005030cc},
+	{0x005031dc, 0x005031dc},
+	{0x00503214, 0x00503214},
+	{0x005032cc, 0x005032cc},
+	{0x005033dc, 0x005033dc},
+	{0x00503414, 0x00503414},
+	{0x005034cc, 0x005034cc},
+	{0x005035dc, 0x005035dc},
+	{0x0050b014, 0x0050b014},
+	{0x0050b0cc, 0x0050b0cc},
+	{0x0050b1dc, 0x0050b1dc},
+	{0x0050b214, 0x0050b214},
+	{0x0050b2cc, 0x0050b2cc},
+	{0x0050b3dc, 0x0050b3dc},
+	{0x0050b414, 0x0050b414},
+	{0x0050b4cc, 0x0050b4cc},
+	{0x0050b5dc, 0x0050b5dc},
+	{0x00513014, 0x00513014},
+	{0x005130cc, 0x005130cc},
+	{0x005131dc, 0x005131dc},
+	{0x00513214, 0x00513214},
+	{0x005132cc, 0x005132cc},
+	{0x005133dc, 0x005133dc},
+	{0x00513414, 0x00513414},
+	{0x005134cc, 0x005134cc},
+	{0x005135dc, 0x005135dc},
+	{0x0051b014, 0x0051b014},
+	{0x0051b0cc, 0x0051b0cc},
+	{0x0051b1dc, 0x0051b1dc},
+	{0x0051b214, 0x0051b214},
+	{0x0051b2cc, 0x0051b2cc},
+	{0x0051b3dc, 0x0051b3dc},
+	{0x0051b414, 0x0051b414},
+	{0x0051b4cc, 0x0051b4cc},
+	{0x0051b5dc, 0x0051b5dc},
+	{0x00523014, 0x00523014},
+	{0x005230cc, 0x005230cc},
+	{0x005231dc, 0x005231dc},
+	{0x00523214, 0x00523214},
+	{0x005232cc, 0x005232cc},
+	{0x005233dc, 0x005233dc},
+	{0x00523414, 0x00523414},
+	{0x005234cc, 0x005234cc},
+	{0x005235dc, 0x005235dc},
+	{0x0052b014, 0x0052b014},
+	{0x0052b0cc, 0x0052b0cc},
+	{0x0052b1dc, 0x0052b1dc},
+	{0x0052b214, 0x0052b214},
+	{0x0052b2cc, 0x0052b2cc},
+	{0x0052b3dc, 0x0052b3dc},
+	{0x0052b414, 0x0052b414},
+	{0x0052b4cc, 0x0052b4cc},
+	{0x0052b5dc, 0x0052b5dc},
+	{0x00533014, 0x00533014},
+	{0x005330cc, 0x005330cc},
+	{0x005331dc, 0x005331dc},
+	{0x00533214, 0x00533214},
+	{0x005332cc, 0x005332cc},
+	{0x005333dc, 0x005333dc},
+	{0x00533414, 0x00533414},
+	{0x005334cc, 0x005334cc},
+	{0x005335dc, 0x005335dc},
+	{0x0053b014, 0x0053b014},
+	{0x0053b0cc, 0x0053b0cc},
+	{0x0053b1dc, 0x0053b1dc},
+	{0x0053b214, 0x0053b214},
+	{0x0053b2cc, 0x0053b2cc},
+	{0x0053b3dc, 0x0053b3dc},
+	{0x0053b414, 0x0053b414},
+	{0x0053b4cc, 0x0053b4cc},
+	{0x0053b5dc, 0x0053b5dc},
+	{0x0041b014, 0x0041b014},
+	{0x0041b0cc, 0x0041b0cc},
+	{0x0041b1dc, 0x0041b1dc},
+	{0x0041b214, 0x0041b214},
+	{0x0041b2cc, 0x0041b2cc},
+	{0x0041b3dc, 0x0041b3dc},
+	{0x0041b414, 0x0041b414},
+	{0x0041b4cc, 0x0041b4cc},
+	{0x0041b5dc, 0x0041b5dc},
+	{0x0041be14, 0x0041be14},
+	{0x0041becc, 0x0041becc},
+	{0x0041bfdc, 0x0041bfdc},
+	{0x00503e14, 0x00503e14},
+	{0x00503ecc, 0x00503ecc},
+	{0x00503fdc, 0x00503fdc},
+	{0x0050be14, 0x0050be14},
+	{0x0050becc, 0x0050becc},
+	{0x0050bfdc, 0x0050bfdc},
+	{0x00513e14, 0x00513e14},
+	{0x00513ecc, 0x00513ecc},
+	{0x00513fdc, 0x00513fdc},
+	{0x0051be14, 0x0051be14},
+	{0x0051becc, 0x0051becc},
+	{0x0051bfdc, 0x0051bfdc},
+	{0x00523e14, 0x00523e14},
+	{0x00523ecc, 0x00523ecc},
+	{0x00523fdc, 0x00523fdc},
+	{0x0052be14, 0x0052be14},
+	{0x0052becc, 0x0052becc},
+	{0x0052bfdc, 0x0052bfdc},
+	{0x00533e14, 0x00533e14},
+	{0x00533ecc, 0x00533ecc},
+	{0x00533fdc, 0x00533fdc},
+	{0x0053be14, 0x0053be14},
+	{0x0053becc, 0x0053becc},
+	{0x0053bfdc, 0x0053bfdc},
+	{0x0040415c, 0x0040415c},
+	{0x00405b50, 0x00405b50},
+	{0x00407010, 0x00407010},
+	{0x004090a8, 0x004090a8},
+	{0x004098a0, 0x004098a0},
+	{0x0040a270, 0x0040a274},
+	{0x00001a00, 0x00001a00},
+	{0x00004000, 0x00004000},
+	{0x00004400, 0x00004400},
+	{0x00004800, 0x00004800},
+	{0x00006000, 0x00006000},
+	{0x00006400, 0x00006400},
+	{0x00006800, 0x00006800},
+	{0x0000cc98, 0x0000cc98},
+	{0x000884e0, 0x000884e0},
+	{0x000884f4, 0x000884f4},
+	{0x0008e00c, 0x0008e00c},
+	{0x00100c18, 0x00100c20},
+	{0x00100c84, 0x00100c84},
+	{0x00105068, 0x00105068},
+	{0x00105128, 0x00105128},
+	{0x001051e8, 0x001051e8},
+	{0x001052a8, 0x001052a8},
+	{0x00105368, 0x00105368},
+	{0x00105428, 0x00105428},
+	{0x001054e8, 0x001054e8},
+	{0x001055a8, 0x001055a8},
+	{0x00105668, 0x00105668},
+	{0x00105728, 0x00105728},
+	{0x001057e8, 0x001057e8},
+	{0x001058a8, 0x001058a8},
+	{0x00105968, 0x00105968},
+	{0x00105a28, 0x00105a28},
+	{0x00105ae8, 0x00105ae8},
+	{0x00105ba8, 0x00105ba8},
+	{0x00105c68, 0x00105c68},
+	{0x00105d28, 0x00105d28},
+	{0x0010a0a8, 0x0010a0a8},
+	{0x0010a4f0, 0x0010a4f0},
+	{0x0013cc14, 0x0013cc14},
+	{0x0013cc24, 0x0013cc28},
+	{0x0013cc54, 0x0013cc54},
+	{0x0013cc64, 0x0013cc68},
+	{0x0013cc94, 0x0013cc94},
+	{0x0013cca4, 0x0013cca8},
+	{0x0013ccd4, 0x0013ccd4},
+	{0x0013cce4, 0x0013cce8},
+	{0x0013cd14, 0x0013cd14},
+	{0x0013cd24, 0x0013cd28},
+	{0x0013cd54, 0x0013cd54},
+	{0x0013cd64, 0x0013cd68},
+	{0x0013cd94, 0x0013cd94},
+	{0x0013cda4, 0x0013cda8},
+	{0x0013cdd4, 0x0013cdd4},
+	{0x0013cde4, 0x0013cde8},
+	{0x0013ce14, 0x0013ce14},
+	{0x0013ce24, 0x0013ce28},
+	{0x0013ce54, 0x0013ce54},
+	{0x0013ce64, 0x0013ce68},
+	{0x0013ce94, 0x0013ce94},
+	{0x0013cea4, 0x0013cea8},
+	{0x0013ced4, 0x0013ced4},
+	{0x0013cee4, 0x0013cee8},
+	{0x0013cf14, 0x0013cf14},
+	{0x0013cf24, 0x0013cf28},
+	{0x0013cf54, 0x0013cf54},
+	{0x0013cf64, 0x0013cf68},
+	{0x0013cf94, 0x0013cf94},
+	{0x0013cfa4, 0x0013cfa8},
+	{0x0013cfd4, 0x0013cfd4},
+	{0x0013cfe4, 0x0013cfe8},
+	{0x00405850, 0x00405850},
+	{0x00405908, 0x00405908},
+	{0x00405a00, 0x00405a00},
+	{0x00406024, 0x00406024},
+	{0x00407808, 0x00407808},
+	{0x0040803c, 0x0040803c},
+	{0x00b668b0, 0x00b6690c},
+	{0x0013cb94, 0x0013cb94},
+};
+
+const struct nvgpu_pm_resource_register_range ga100_cau_register_ranges[] = {
+	{0x00504180, 0x005041b4},
+	{0x005041c0, 0x005041f4},
+	{0x00504980, 0x005049b4},
+	{0x005049c0, 0x005049f4},
+	{0x00505180, 0x005051b4},
+	{0x005051c0, 0x005051f4},
+	{0x00505980, 0x005059b4},
+	{0x005059c0, 0x005059f4},
+	{0x00506180, 0x005061b4},
+	{0x005061c0, 0x005061f4},
+	{0x00506980, 0x005069b4},
+	{0x005069c0, 0x005069f4},
+	{0x00507180, 0x005071b4},
+	{0x005071c0, 0x005071f4},
+	{0x00507980, 0x005079b4},
+	{0x005079c0, 0x005079f4},
+	{0x0050c180, 0x0050c1b4},
+	{0x0050c1c0, 0x0050c1f4},
+	{0x0050c980, 0x0050c9b4},
+	{0x0050c9c0, 0x0050c9f4},
+	{0x0050d180, 0x0050d1b4},
+	{0x0050d1c0, 0x0050d1f4},
+	{0x0050d980, 0x0050d9b4},
+	{0x0050d9c0, 0x0050d9f4},
+	{0x0050e180, 0x0050e1b4},
+	{0x0050e1c0, 0x0050e1f4},
+	{0x0050e980, 0x0050e9b4},
+	{0x0050e9c0, 0x0050e9f4},
+	{0x0050f180, 0x0050f1b4},
+	{0x0050f1c0, 0x0050f1f4},
+	{0x0050f980, 0x0050f9b4},
+	{0x0050f9c0, 0x0050f9f4},
+	{0x00514180, 0x005141b4},
+	{0x005141c0, 0x005141f4},
+	{0x00514980, 0x005149b4},
+	{0x005149c0, 0x005149f4},
+	{0x00515180, 0x005151b4},
+	{0x005151c0, 0x005151f4},
+	{0x00515980, 0x005159b4},
+	{0x005159c0, 0x005159f4},
+	{0x00516180, 0x005161b4},
+	{0x005161c0, 0x005161f4},
+	{0x00516980, 0x005169b4},
+	{0x005169c0, 0x005169f4},
+	{0x00517180, 0x005171b4},
+	{0x005171c0, 0x005171f4},
+	{0x00517980, 0x005179b4},
+	{0x005179c0, 0x005179f4},
+	{0x0051c180, 0x0051c1b4},
+	{0x0051c1c0, 0x0051c1f4},
+	{0x0051c980, 0x0051c9b4},
+	{0x0051c9c0, 0x0051c9f4},
+	{0x0051d180, 0x0051d1b4},
+	{0x0051d1c0, 0x0051d1f4},
+	{0x0051d980, 0x0051d9b4},
+	{0x0051d9c0, 0x0051d9f4},
+	{0x0051e180, 0x0051e1b4},
+	{0x0051e1c0, 0x0051e1f4},
+	{0x0051e980, 0x0051e9b4},
+	{0x0051e9c0, 0x0051e9f4},
+	{0x0051f180, 0x0051f1b4},
+	{0x0051f1c0, 0x0051f1f4},
+	{0x0051f980, 0x0051f9b4},
+	{0x0051f9c0, 0x0051f9f4},
+	{0x00524180, 0x005241b4},
+	{0x005241c0, 0x005241f4},
+	{0x00524980, 0x005249b4},
+	{0x005249c0, 0x005249f4},
+	{0x00525180, 0x005251b4},
+	{0x005251c0, 0x005251f4},
+	{0x00525980, 0x005259b4},
+	{0x005259c0, 0x005259f4},
+	{0x00526180, 0x005261b4},
+	{0x005261c0, 0x005261f4},
+	{0x00526980, 0x005269b4},
+	{0x005269c0, 0x005269f4},
+	{0x00527180, 0x005271b4},
+	{0x005271c0, 0x005271f4},
+	{0x00527980, 0x005279b4},
+	{0x005279c0, 0x005279f4},
+	{0x0052c180, 0x0052c1b4},
+	{0x0052c1c0, 0x0052c1f4},
+	{0x0052c980, 0x0052c9b4},
+	{0x0052c9c0, 0x0052c9f4},
+	{0x0052d180, 0x0052d1b4},
+	{0x0052d1c0, 0x0052d1f4},
+	{0x0052d980, 0x0052d9b4},
+	{0x0052d9c0, 0x0052d9f4},
+	{0x0052e180, 0x0052e1b4},
+	{0x0052e1c0, 0x0052e1f4},
+	{0x0052e980, 0x0052e9b4},
+	{0x0052e9c0, 0x0052e9f4},
+	{0x0052f180, 0x0052f1b4},
+	{0x0052f1c0, 0x0052f1f4},
+	{0x0052f980, 0x0052f9b4},
+	{0x0052f9c0, 0x0052f9f4},
+	{0x00534180, 0x005341b4},
+	{0x005341c0, 0x005341f4},
+	{0x00534980, 0x005349b4},
+	{0x005349c0, 0x005349f4},
+	{0x00535180, 0x005351b4},
+	{0x005351c0, 0x005351f4},
+	{0x00535980, 0x005359b4},
+	{0x005359c0, 0x005359f4},
+	{0x00536180, 0x005361b4},
+	{0x005361c0, 0x005361f4},
+	{0x00536980, 0x005369b4},
+	{0x005369c0, 0x005369f4},
+	{0x00537180, 0x005371b4},
+	{0x005371c0, 0x005371f4},
+	{0x00537980, 0x005379b4},
+	{0x005379c0, 0x005379f4},
+	{0x0053c180, 0x0053c1b4},
+	{0x0053c1c0, 0x0053c1f4},
+	{0x0053c980, 0x0053c9b4},
+	{0x0053c9c0, 0x0053c9f4},
+	{0x0053d180, 0x0053d1b4},
+	{0x0053d1c0, 0x0053d1f4},
+	{0x0053d980, 0x0053d9b4},
+	{0x0053d9c0, 0x0053d9f4},
+	{0x0053e180, 0x0053e1b4},
+	{0x0053e1c0, 0x0053e1f4},
+	{0x0053e980, 0x0053e9b4},
+	{0x0053e9c0, 0x0053e9f4},
+	{0x0053f180, 0x0053f1b4},
+	{0x0053f1c0, 0x0053f1f4},
+	{0x0053f980, 0x0053f9b4},
+	{0x0053f9c0, 0x0053f9f4},
+	{0x00419980, 0x004199b4},
+	{0x004199c0, 0x004199f4},
+	{0x0041c180, 0x0041c1b4},
+	{0x0041c1c0, 0x0041c1f4},
+	{0x0041c980, 0x0041c9b4},
+	{0x0041c9c0, 0x0041c9f4},
+	{0x0041d180, 0x0041d1b4},
+	{0x0041d1c0, 0x0041d1f4},
+	{0x0041d980, 0x0041d9b4},
+	{0x0041d9c0, 0x0041d9f4},
+	{0x0041e180, 0x0041e1b4},
+	{0x0041e1c0, 0x0041e1f4},
+	{0x0041e980, 0x0041e9b4},
+	{0x0041e9c0, 0x0041e9f4},
+	{0x0041f180, 0x0041f1b4},
+	{0x0041f1c0, 0x0041f1f4},
+	{0x0041f980, 0x0041f9b4},
+	{0x0041f9c0, 0x0041f9f4},
+	{0x00501980, 0x005019b4},
+	{0x005019c0, 0x005019f4},
+	{0x00509980, 0x005099b4},
+	{0x005099c0, 0x005099f4},
+	{0x00511980, 0x005119b4},
+	{0x005119c0, 0x005119f4},
+	{0x00519980, 0x005199b4},
+	{0x005199c0, 0x005199f4},
+	{0x00521980, 0x005219b4},
+	{0x005219c0, 0x005219f4},
+	{0x00529980, 0x005299b4},
+	{0x005299c0, 0x005299f4},
+	{0x00531980, 0x005319b4},
+	{0x005319c0, 0x005319f4},
+	{0x00539980, 0x005399b4},
+	{0x005399c0, 0x005399f4},
+};
+
+u32 ga100_get_hwpm_perfmon_register_stride(void)
+{
+	return 0x00000200;
+}
+
+u32 ga100_get_hwpm_router_register_stride(void)
+{
+	return 0x00000200;
+}
+
+u32 ga100_get_hwpm_pma_channel_register_stride(void)
+{
+	return 0x00002000;
+}
+
+u32 ga100_get_hwpm_pma_trigger_register_stride(void)
+{
+	return 0x00002000;
+}
+
+u32 ga100_get_smpc_register_stride(void)
+{
+	return 0x00000800;
+}
+
+u32 ga100_get_cau_register_stride(void)
+{
+	return 0x00000040;
+}
+
+const u32 *ga100_get_hwpm_perfmon_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_hwpm_perfmon_register_offset_allowlist) /
+		sizeof(ga100_hwpm_perfmon_register_offset_allowlist[0]));
+	return ga100_hwpm_perfmon_register_offset_allowlist;
+}
+
+const u32 *ga100_get_hwpm_router_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_hwpm_router_register_offset_allowlist) /
+		sizeof(ga100_hwpm_router_register_offset_allowlist[0]));
+	return ga100_hwpm_router_register_offset_allowlist;
+}
+
+const u32 *ga100_get_hwpm_pma_channel_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_hwpm_pma_channel_register_offset_allowlist) /
+		sizeof(ga100_hwpm_pma_channel_register_offset_allowlist[0]));
+	return ga100_hwpm_pma_channel_register_offset_allowlist;
+}
+
+const u32 *ga100_get_hwpm_pma_trigger_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_hwpm_pma_trigger_register_offset_allowlist) /
+		sizeof(ga100_hwpm_pma_trigger_register_offset_allowlist[0]));
+	return ga100_hwpm_pma_trigger_register_offset_allowlist;
+}
+
+const u32 *ga100_get_smpc_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_smpc_register_offset_allowlist) /
+		sizeof(ga100_smpc_register_offset_allowlist[0]));
+	return ga100_smpc_register_offset_allowlist;
+}
+
+const u32 *ga100_get_cau_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_cau_register_offset_allowlist) /
+		sizeof(ga100_cau_register_offset_allowlist[0]));
+	return ga100_cau_register_offset_allowlist;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga100_get_hwpm_perfmon_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_hwpm_perfmon_register_ranges) /
+		sizeof(ga100_hwpm_perfmon_register_ranges[0]));
+	return ga100_hwpm_perfmon_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga100_get_hwpm_router_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_hwpm_router_register_ranges) /
+		sizeof(ga100_hwpm_router_register_ranges[0]));
+	return ga100_hwpm_router_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga100_get_hwpm_pma_channel_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_hwpm_pma_channel_register_ranges) /
+		sizeof(ga100_hwpm_pma_channel_register_ranges[0]));
+	return ga100_hwpm_pma_channel_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga100_get_hwpm_pma_trigger_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_hwpm_pma_trigger_register_ranges) /
+		sizeof(ga100_hwpm_pma_trigger_register_ranges[0]));
+	return ga100_hwpm_pma_trigger_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga100_get_smpc_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_smpc_register_ranges) /
+		sizeof(ga100_smpc_register_ranges[0]));
+	return ga100_smpc_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga100_get_hwpm_perfmux_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_hwpm_perfmux_register_ranges) /
+		sizeof(ga100_hwpm_perfmux_register_ranges[0]));
+	return ga100_hwpm_perfmux_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga100_get_cau_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga100_cau_register_ranges) /
+		sizeof(ga100_cau_register_ranges[0]));
+	return ga100_cau_register_ranges;
+}
+
diff --git a/drivers/gpu/nvgpu/hal/regops/allowlist_ga100.h b/drivers/gpu/nvgpu/hal/regops/allowlist_ga100.h
new file mode 100644
index 000000000..2ed7767b4
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/regops/allowlist_ga100.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#ifndef NVGPU_GA100_REGOPS_ALLOWLIST_H
+#define NVGPU_GA100_REGOPS_ALLOWLIST_H
+
+#include <nvgpu/types.h>
+
+struct nvgpu_pm_resource_register_range;
+
+u32 ga100_get_hwpm_perfmon_register_stride(void);
+u32 ga100_get_hwpm_router_register_stride(void);
+u32 ga100_get_hwpm_pma_channel_register_stride(void);
+u32 ga100_get_hwpm_pma_trigger_register_stride(void);
+u32 ga100_get_smpc_register_stride(void);
+u32 ga100_get_cau_register_stride(void);
+
+const u32 *ga100_get_hwpm_perfmon_register_offset_allowlist(u32 *count);
+const u32 *ga100_get_hwpm_router_register_offset_allowlist(u32 *count);
+const u32 *ga100_get_hwpm_pma_channel_register_offset_allowlist(u32 *count);
+const u32 *ga100_get_hwpm_pma_trigger_register_offset_allowlist(u32 *count);
+const u32 *ga100_get_smpc_register_offset_allowlist(u32 *count);
+const u32 *ga100_get_cau_register_offset_allowlist(u32 *count);
+
+const struct nvgpu_pm_resource_register_range
+	*ga100_get_hwpm_perfmon_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga100_get_hwpm_router_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga100_get_hwpm_pma_channel_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga100_get_hwpm_pma_trigger_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga100_get_smpc_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga100_get_hwpm_perfmux_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga100_get_cau_register_ranges(u32 *count);
+
+#endif /* NVGPU_GA100_REGOPS_ALLOWLIST_H */
diff --git a/drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.c b/drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.c
new file mode 100644
index 000000000..f9df6e4b3
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.c
@@ -0,0 +1,826 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/regops_allowlist.h>
+#include "allowlist_ga10b.h"
+
+u32 ga10b_hwpm_perfmon_register_offset_allowlist[] = {
+	0x00000000,
+	0x00000004,
+	0x00000008,
+	0x0000000c,
+	0x00000010,
+	0x00000014,
+	0x00000020,
+	0x00000024,
+	0x00000028,
+	0x0000002c,
+	0x00000030,
+	0x00000034,
+	0x00000040,
+	0x00000044,
+	0x00000048,
+	0x0000004c,
+	0x00000050,
+	0x00000054,
+	0x00000058,
+	0x0000005c,
+	0x00000060,
+	0x00000064,
+	0x00000068,
+	0x0000006c,
+	0x00000070,
+	0x00000074,
+	0x00000078,
+	0x0000007c,
+	0x00000080,
+	0x00000084,
+	0x00000088,
+	0x0000008c,
+	0x00000090,
+	0x00000098,
+	0x0000009c,
+	0x000000a0,
+	0x000000a4,
+	0x000000a8,
+	0x000000ac,
+	0x000000b0,
+	0x000000b4,
+	0x000000b8,
+	0x000000bc,
+	0x000000c0,
+	0x000000c4,
+	0x000000c8,
+	0x000000cc,
+	0x000000d0,
+	0x000000d4,
+	0x000000d8,
+	0x000000dc,
+	0x000000e0,
+	0x000000ec,
+	0x000000f8,
+	0x000000fc,
+	0x00000100,
+	0x00000108,
+	0x00000110,
+	0x00000120,
+	0x00000124,
+	0x00000128,
+	0x00000130,
+};
+
+u32 ga10b_hwpm_router_register_offset_allowlist[] = {
+	0x00000000,
+	0x00000008,
+	0x00000010,
+	0x00000014,
+	0x00000150,
+};
+
+u32 ga10b_hwpm_pma_channel_register_offset_allowlist[] = {
+	0x0000000c,
+	0x00000610,
+	0x00000618,
+	0x00000620,
+	0x0000063c,
+	0x00000640,
+	0x00000650,
+	0x00000654,
+	0x0000075c,
+};
+
+u32 ga10b_hwpm_pma_trigger_register_offset_allowlist[] = {
+	0x00000008,
+	0x00000600,
+	0x00000604,
+	0x00000608,
+	0x0000060c,
+	0x0000062c,
+	0x0000065c,
+	0x00000660,
+	0x00000664,
+	0x00000668,
+	0x0000066c,
+	0x00000670,
+	0x00000674,
+	0x00000678,
+	0x0000067c,
+	0x00000680,
+	0x00000684,
+	0x00000688,
+	0x0000068c,
+	0x00000690,
+	0x00000694,
+	0x00000698,
+	0x0000069c,
+	0x000006a0,
+	0x000006a4,
+	0x000006a8,
+	0x000006ac,
+	0x000006b0,
+	0x000006b4,
+	0x000006b8,
+	0x000006bc,
+	0x000006c0,
+	0x000006c4,
+	0x000006c8,
+	0x000006cc,
+	0x000006d0,
+	0x000006d4,
+	0x000006d8,
+	0x000006dc,
+	0x000006e0,
+	0x000006e4,
+	0x000006e8,
+	0x000006ec,
+	0x000006f0,
+	0x000006f4,
+	0x000006f8,
+	0x000006fc,
+	0x00000700,
+	0x00000704,
+	0x00000708,
+	0x0000070c,
+	0x00000710,
+	0x00000714,
+	0x00000718,
+	0x0000071c,
+	0x00000720,
+	0x00000724,
+	0x00000728,
+	0x0000072c,
+	0x0000075c,
+};
+
+u32 ga10b_smpc_register_offset_allowlist[] = {
+	0x00000200,
+	0x00000204,
+	0x00000208,
+	0x0000020c,
+	0x00000210,
+	0x00000214,
+	0x00000218,
+	0x0000021c,
+	0x00000220,
+	0x00000224,
+	0x00000228,
+	0x0000022c,
+	0x00000230,
+	0x00000234,
+	0x00000238,
+	0x0000023c,
+	0x00000240,
+	0x00000244,
+	0x00000248,
+	0x00000300,
+	0x00000304,
+	0x00000308,
+	0x0000030c,
+	0x00000310,
+	0x00000314,
+	0x00000318,
+	0x0000031c,
+	0x00000320,
+	0x00000324,
+	0x00000328,
+	0x0000032c,
+	0x00000330,
+	0x00000334,
+	0x00000338,
+	0x0000033c,
+	0x00000340,
+	0x00000344,
+	0x00000348,
+	0x0000034c,
+	0x00000350,
+	0x00000354,
+	0x00000358,
+	0x0000035c,
+	0x00000360,
+	0x00000364,
+	0x00000368,
+	0x0000036c,
+	0x00000370,
+	0x00000374,
+	0x00000378,
+	0x0000037c,
+	0x00000380,
+	0x00000384,
+	0x00000388,
+	0x0000038c,
+	0x00000390,
+	0x00000394,
+	0x00000398,
+	0x0000039c,
+	0x000003a0,
+	0x000003a4,
+	0x000003a8,
+	0x000003ac,
+	0x000003b0,
+	0x000003b4,
+	0x000003b8,
+	0x000003bc,
+	0x000003c0,
+	0x000003c4,
+	0x00000600,
+	0x00000604,
+	0x00000608,
+	0x0000060c,
+	0x00000610,
+	0x00000614,
+	0x00000618,
+	0x0000061c,
+	0x00000620,
+	0x00000624,
+	0x00000628,
+	0x0000062c,
+	0x00000630,
+	0x00000634,
+	0x00000638,
+	0x0000063c,
+	0x00000640,
+	0x00000644,
+	0x00000648,
+	0x0000064c,
+	0x00000650,
+	0x00000654,
+	0x00000658,
+	0x0000065c,
+	0x00000660,
+	0x00000664,
+	0x00000668,
+	0x0000066c,
+	0x00000670,
+	0x00000674,
+	0x00000678,
+	0x0000067c,
+	0x00000680,
+	0x00000684,
+	0x00000688,
+	0x0000068c,
+	0x00000690,
+	0x00000694,
+	0x00000698,
+	0x0000069c,
+	0x000006a0,
+	0x000006a4,
+	0x000006a8,
+	0x000006ac,
+	0x000006b0,
+	0x000006b4,
+	0x000006b8,
+	0x000006bc,
+	0x000006c0,
+	0x000006c4,
+	0x00000700,
+	0x00000704,
+	0x00000708,
+	0x0000070c,
+	0x00000710,
+	0x00000714,
+	0x00000718,
+	0x0000071c,
+	0x00000720,
+	0x00000724,
+	0x00000728,
+	0x0000072c,
+	0x00000730,
+	0x00000734,
+	0x00000738,
+	0x0000073c,
+	0x00000740,
+	0x00000744,
+	0x00000748,
+	0x0000074c,
+	0x00000750,
+	0x00000754,
+	0x00000758,
+	0x0000075c,
+	0x00000760,
+	0x00000764,
+	0x00000768,
+	0x0000076c,
+	0x00000770,
+	0x00000774,
+	0x00000778,
+	0x0000077c,
+	0x00000780,
+	0x00000784,
+	0x00000788,
+	0x0000078c,
+	0x00000790,
+	0x00000794,
+	0x00000798,
+	0x0000079c,
+	0x000007a0,
+	0x000007a4,
+	0x000007a8,
+	0x000007ac,
+	0x000007b0,
+	0x000007b4,
+	0x000007b8,
+	0x000007bc,
+	0x000007c0,
+	0x000007c4,
+};
+
+u32 ga10b_cau_register_offset_allowlist[] = {
+	0x00000000,
+	0x00000004,
+	0x00000008,
+	0x0000000c,
+	0x00000010,
+	0x00000014,
+	0x00000018,
+	0x0000001c,
+	0x00000024,
+};
+
+const struct nvgpu_pm_resource_register_range ga10b_hwpm_perfmon_register_ranges[] = {
+	{0x00180000, 0x00187ffc},
+	{0x00250040, 0x00250124},
+	{0x00250240, 0x00250324},
+	{0x00278040, 0x00279f24},
+	{0x00200000, 0x00207ffc},
+	{0x00260000, 0x00263ffc},
+};
+
+const struct nvgpu_pm_resource_register_range ga10b_hwpm_router_register_ranges[] = {
+	{0x00244000, 0x002443fc},
+	{0x00246000, 0x002463fc},
+	{0x00248000, 0x002481fc},
+	{0x00251800, 0x00251814},
+	{0x00251a00, 0x00251a14},
+	{0x00251950, 0x00251950},
+	{0x00251b50, 0x00251b50},
+};
+
+const struct nvgpu_pm_resource_register_range ga10b_hwpm_pma_channel_register_ranges[] = {
+	{0x0024a610, 0x0024a628},
+	{0x0024a634, 0x0024a658},
+	{0x0024a730, 0x0024a734},
+};
+
+const struct nvgpu_pm_resource_register_range ga10b_hwpm_pma_trigger_register_ranges[] = {
+	{0x0024a000, 0x0024a60c},
+	{0x0024a62c, 0x0024a62c},
+	{0x0024a65c, 0x0024a72c},
+};
+
+const struct nvgpu_pm_resource_register_range ga10b_smpc_register_ranges[] = {
+	{0x00580000, 0x0058fffc},
+	{0x00480000, 0x0048fffc},
+};
+
+const struct nvgpu_pm_resource_register_range ga10b_hwpm_perfmux_register_ranges[] = {
+	{0x00140028, 0x00140028},
+	{0x00142028, 0x00142028},
+	{0x0017e028, 0x0017e028},
+	{0x00900100, 0x00900100},
+	{0x00904100, 0x00904100},
+	{0x009a0100, 0x009a0100},
+	{0x00503814, 0x00503814},
+	{0x00503870, 0x00503870},
+	{0x00503894, 0x00503894},
+	{0x00503a14, 0x00503a14},
+	{0x00503a70, 0x00503a70},
+	{0x00503a94, 0x00503a94},
+	{0x0050b814, 0x0050b814},
+	{0x0050b870, 0x0050b870},
+	{0x0050b894, 0x0050b894},
+	{0x0050ba14, 0x0050ba14},
+	{0x0050ba70, 0x0050ba70},
+	{0x0050ba94, 0x0050ba94},
+	{0x0041b814, 0x0041b814},
+	{0x0041b870, 0x0041b870},
+	{0x0041b894, 0x0041b894},
+	{0x0041ba14, 0x0041ba14},
+	{0x0041ba70, 0x0041ba70},
+	{0x0041ba94, 0x0041ba94},
+	{0x0041bc14, 0x0041bc14},
+	{0x0041bc70, 0x0041bc70},
+	{0x0041bc94, 0x0041bc94},
+	{0x00503c14, 0x00503c14},
+	{0x00503c70, 0x00503c70},
+	{0x00503c94, 0x00503c94},
+	{0x0050bc14, 0x0050bc14},
+	{0x0050bc70, 0x0050bc70},
+	{0x0050bc94, 0x0050bc94},
+	{0x00140550, 0x00140550},
+	{0x00140750, 0x00140750},
+	{0x00140950, 0x00140950},
+	{0x00140b50, 0x00140b50},
+	{0x00142550, 0x00142550},
+	{0x00142750, 0x00142750},
+	{0x00142950, 0x00142950},
+	{0x00142b50, 0x00142b50},
+	{0x00140350, 0x00140350},
+	{0x00142350, 0x00142350},
+	{0x0017e350, 0x0017e350},
+	{0x0017e550, 0x0017e550},
+	{0x0017e750, 0x0017e750},
+	{0x0017e950, 0x0017e950},
+	{0x0017eb50, 0x0017eb50},
+	{0x009001e0, 0x009001e4},
+	{0x009041e0, 0x009041e4},
+	{0x009a01e0, 0x009a01e4},
+	{0x00500384, 0x00500384},
+	{0x005004a0, 0x005004a0},
+	{0x00500604, 0x00500604},
+	{0x00500680, 0x00500680},
+	{0x00500714, 0x00500714},
+	{0x0050081c, 0x0050081c},
+	{0x00500884, 0x00500884},
+	{0x005008c8, 0x005008cc},
+	{0x00500b04, 0x00500b04},
+	{0x00500c04, 0x00500c04},
+	{0x00500c88, 0x00500c88},
+	{0x00500d00, 0x00500d00},
+	{0x00500e08, 0x00500e08},
+	{0x00500f08, 0x00500f08},
+	{0x0050100c, 0x0050100c},
+	{0x005020a8, 0x005020a8},
+	{0x005028a0, 0x005028a8},
+	{0x00508384, 0x00508384},
+	{0x005084a0, 0x005084a0},
+	{0x00508604, 0x00508604},
+	{0x00508680, 0x00508680},
+	{0x00508714, 0x00508714},
+	{0x0050881c, 0x0050881c},
+	{0x00508884, 0x00508884},
+	{0x005088c8, 0x005088cc},
+	{0x00508b04, 0x00508b04},
+	{0x00508c04, 0x00508c04},
+	{0x00508c88, 0x00508c88},
+	{0x00508d00, 0x00508d00},
+	{0x00508e08, 0x00508e08},
+	{0x00508f08, 0x00508f08},
+	{0x0050900c, 0x0050900c},
+	{0x0050a0a8, 0x0050a0a8},
+	{0x0050a8a0, 0x0050a8a8},
+	{0x00418384, 0x00418384},
+	{0x004184a0, 0x004184a0},
+	{0x00418604, 0x00418604},
+	{0x00418680, 0x00418680},
+	{0x00418714, 0x00418714},
+	{0x0041881c, 0x0041881c},
+	{0x00418884, 0x00418884},
+	{0x004188c8, 0x004188cc},
+	{0x00418b04, 0x00418b04},
+	{0x00418c04, 0x00418c04},
+	{0x00418c88, 0x00418c88},
+	{0x00418d00, 0x00418d00},
+	{0x00418e08, 0x00418e08},
+	{0x00418f08, 0x00418f08},
+	{0x0041900c, 0x0041900c},
+	{0x0041a0a8, 0x0041a0a8},
+	{0x0041a8a0, 0x0041a8a8},
+	{0x00504054, 0x00504054},
+	{0x005042b0, 0x005042b0},
+	{0x00504304, 0x00504304},
+	{0x005043dc, 0x005043dc},
+	{0x0050440c, 0x0050440c},
+	{0x00504664, 0x00504664},
+	{0x00504854, 0x00504854},
+	{0x00504ab0, 0x00504ab0},
+	{0x00504b04, 0x00504b04},
+	{0x00504bdc, 0x00504bdc},
+	{0x00504c0c, 0x00504c0c},
+	{0x00504e64, 0x00504e64},
+	{0x00505054, 0x00505054},
+	{0x005052b0, 0x005052b0},
+	{0x00505304, 0x00505304},
+	{0x005053dc, 0x005053dc},
+	{0x0050540c, 0x0050540c},
+	{0x00505664, 0x00505664},
+	{0x00505854, 0x00505854},
+	{0x00505ab0, 0x00505ab0},
+	{0x00505b04, 0x00505b04},
+	{0x00505bdc, 0x00505bdc},
+	{0x00505c0c, 0x00505c0c},
+	{0x00505e64, 0x00505e64},
+	{0x0050c054, 0x0050c054},
+	{0x0050c2b0, 0x0050c2b0},
+	{0x0050c304, 0x0050c304},
+	{0x0050c3dc, 0x0050c3dc},
+	{0x0050c40c, 0x0050c40c},
+	{0x0050c664, 0x0050c664},
+	{0x0050c854, 0x0050c854},
+	{0x0050cab0, 0x0050cab0},
+	{0x0050cb04, 0x0050cb04},
+	{0x0050cbdc, 0x0050cbdc},
+	{0x0050cc0c, 0x0050cc0c},
+	{0x0050ce64, 0x0050ce64},
+	{0x0050d054, 0x0050d054},
+	{0x0050d2b0, 0x0050d2b0},
+	{0x0050d304, 0x0050d304},
+	{0x0050d3dc, 0x0050d3dc},
+	{0x0050d40c, 0x0050d40c},
+	{0x0050d664, 0x0050d664},
+	{0x0050d854, 0x0050d854},
+	{0x0050dab0, 0x0050dab0},
+	{0x0050db04, 0x0050db04},
+	{0x0050dbdc, 0x0050dbdc},
+	{0x0050dc0c, 0x0050dc0c},
+	{0x0050de64, 0x0050de64},
+	{0x00419854, 0x00419854},
+	{0x00419ab0, 0x00419ab0},
+	{0x00419b04, 0x00419b04},
+	{0x00419bdc, 0x00419bdc},
+	{0x00419c0c, 0x00419c0c},
+	{0x00419e64, 0x00419e64},
+	{0x0041c054, 0x0041c054},
+	{0x0041c2b0, 0x0041c2b0},
+	{0x0041c304, 0x0041c304},
+	{0x0041c3dc, 0x0041c3dc},
+	{0x0041c40c, 0x0041c40c},
+	{0x0041c664, 0x0041c664},
+	{0x0041c854, 0x0041c854},
+	{0x0041cab0, 0x0041cab0},
+	{0x0041cb04, 0x0041cb04},
+	{0x0041cbdc, 0x0041cbdc},
+	{0x0041cc0c, 0x0041cc0c},
+	{0x0041ce64, 0x0041ce64},
+	{0x0041d054, 0x0041d054},
+	{0x0041d2b0, 0x0041d2b0},
+	{0x0041d304, 0x0041d304},
+	{0x0041d3dc, 0x0041d3dc},
+	{0x0041d40c, 0x0041d40c},
+	{0x0041d664, 0x0041d664},
+	{0x0041d854, 0x0041d854},
+	{0x0041dab0, 0x0041dab0},
+	{0x0041db04, 0x0041db04},
+	{0x0041dbdc, 0x0041dbdc},
+	{0x0041dc0c, 0x0041dc0c},
+	{0x0041de64, 0x0041de64},
+	{0x00501854, 0x00501854},
+	{0x00501ab0, 0x00501ab0},
+	{0x00501b04, 0x00501b04},
+	{0x00501bdc, 0x00501bdc},
+	{0x00501c0c, 0x00501c0c},
+	{0x00501e64, 0x00501e64},
+	{0x00509854, 0x00509854},
+	{0x00509ab0, 0x00509ab0},
+	{0x00509b04, 0x00509b04},
+	{0x00509bdc, 0x00509bdc},
+	{0x00509c0c, 0x00509c0c},
+	{0x00509e64, 0x00509e64},
+	{0x00503014, 0x00503014},
+	{0x005030cc, 0x005030cc},
+	{0x005031dc, 0x005031dc},
+	{0x00503214, 0x00503214},
+	{0x005032cc, 0x005032cc},
+	{0x005033dc, 0x005033dc},
+	{0x0050b014, 0x0050b014},
+	{0x0050b0cc, 0x0050b0cc},
+	{0x0050b1dc, 0x0050b1dc},
+	{0x0050b214, 0x0050b214},
+	{0x0050b2cc, 0x0050b2cc},
+	{0x0050b3dc, 0x0050b3dc},
+	{0x0041b014, 0x0041b014},
+	{0x0041b0cc, 0x0041b0cc},
+	{0x0041b1dc, 0x0041b1dc},
+	{0x0041b214, 0x0041b214},
+	{0x0041b2cc, 0x0041b2cc},
+	{0x0041b3dc, 0x0041b3dc},
+	{0x0041be14, 0x0041be14},
+	{0x0041becc, 0x0041becc},
+	{0x0041bfdc, 0x0041bfdc},
+	{0x00503e14, 0x00503e14},
+	{0x00503ecc, 0x00503ecc},
+	{0x00503fdc, 0x00503fdc},
+	{0x0050be14, 0x0050be14},
+	{0x0050becc, 0x0050becc},
+	{0x0050bfdc, 0x0050bfdc},
+	{0x0040415c, 0x0040415c},
+	{0x00405b50, 0x00405b50},
+	{0x00407010, 0x00407010},
+	{0x004090a8, 0x004090a8},
+	{0x004098a0, 0x004098a0},
+	{0x0040a270, 0x0040a274},
+	{0x00001a00, 0x00001a00},
+	{0x00004000, 0x00004000},
+	{0x00004400, 0x00004400},
+	{0x00004800, 0x00004800},
+	{0x0000cc98, 0x0000cc98},
+	{0x000884e0, 0x000884e0},
+	{0x000884f4, 0x000884f4},
+	{0x0008e00c, 0x0008e00c},
+	{0x00100c18, 0x00100c20},
+	{0x00100c84, 0x00100c84},
+	{0x00105068, 0x00105068},
+	{0x00105128, 0x00105128},
+	{0x0010a0a8, 0x0010a0a8},
+	{0x0010a4f0, 0x0010a4f0},
+	{0x0013cc14, 0x0013cc14},
+	{0x0013cc24, 0x0013cc28},
+	{0x0013cc94, 0x0013cc94},
+	{0x0013cca4, 0x0013cca8},
+	{0x00405850, 0x00405850},
+	{0x00405908, 0x00405908},
+	{0x00405a00, 0x00405a00},
+	{0x00406024, 0x00406024},
+	{0x00407808, 0x00407808},
+	{0x0040803c, 0x0040803c},
+	{0x00b668b0, 0x00b6690c},
+	{0x0013cb94, 0x0013cb94},
+};
+
+const struct nvgpu_pm_resource_register_range ga10b_cau_register_ranges[] = {
+	{0x00504180, 0x005041b8},
+	{0x005041c0, 0x005041e8},
+	{0x005041f0, 0x005041f8},
+	{0x00504980, 0x005049b8},
+	{0x005049c0, 0x005049e8},
+	{0x005049f0, 0x005049f8},
+	{0x00505180, 0x005051b8},
+	{0x005051c0, 0x005051e8},
+	{0x005051f0, 0x005051f8},
+	{0x00505980, 0x005059b8},
+	{0x005059c0, 0x005059e8},
+	{0x005059f0, 0x005059f8},
+	{0x0050c180, 0x0050c1b8},
+	{0x0050c1c0, 0x0050c1e8},
+	{0x0050c1f0, 0x0050c1f8},
+	{0x0050c980, 0x0050c9b8},
+	{0x0050c9c0, 0x0050c9e8},
+	{0x0050c9f0, 0x0050c9f8},
+	{0x0050d180, 0x0050d1b8},
+	{0x0050d1c0, 0x0050d1e8},
+	{0x0050d1f0, 0x0050d1f8},
+	{0x0050d980, 0x0050d9b8},
+	{0x0050d9c0, 0x0050d9e8},
+	{0x0050d9f0, 0x0050d9f8},
+	{0x00419980, 0x004199b8},
+	{0x004199c0, 0x004199e8},
+	{0x004199f0, 0x004199f8},
+	{0x0041c180, 0x0041c1b8},
+	{0x0041c1c0, 0x0041c1e8},
+	{0x0041c1f0, 0x0041c1f8},
+	{0x0041c980, 0x0041c9b8},
+	{0x0041c9c0, 0x0041c9e8},
+	{0x0041c9f0, 0x0041c9f8},
+	{0x0041d180, 0x0041d1b8},
+	{0x0041d1c0, 0x0041d1e8},
+	{0x0041d1f0, 0x0041d1f8},
+	{0x0041d980, 0x0041d9b8},
+	{0x0041d9c0, 0x0041d9e8},
+	{0x0041d9f0, 0x0041d9f8},
+	{0x00501980, 0x005019b8},
+	{0x005019c0, 0x005019e8},
+	{0x005019f0, 0x005019f8},
+	{0x00509980, 0x005099b8},
+	{0x005099c0, 0x005099e8},
+	{0x005099f0, 0x005099f8},
+};
+
+u32 ga10b_get_hwpm_perfmon_register_stride(void)
+{
+	return 0x00000200;
+}
+
+u32 ga10b_get_hwpm_router_register_stride(void)
+{
+	return 0x00000200;
+}
+
+u32 ga10b_get_hwpm_pma_channel_register_stride(void)
+{
+	return 0x00002000;
+}
+
+u32 ga10b_get_hwpm_pma_trigger_register_stride(void)
+{
+	return 0x00002000;
+}
+
+u32 ga10b_get_smpc_register_stride(void)
+{
+	return 0x00000800;
+}
+
+u32 ga10b_get_cau_register_stride(void)
+{
+	return 0x00000040;
+}
+
+const u32 *ga10b_get_hwpm_perfmon_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_hwpm_perfmon_register_offset_allowlist) /
+		sizeof(ga10b_hwpm_perfmon_register_offset_allowlist[0]));
+	return ga10b_hwpm_perfmon_register_offset_allowlist;
+}
+
+const u32 *ga10b_get_hwpm_router_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_hwpm_router_register_offset_allowlist) /
+		sizeof(ga10b_hwpm_router_register_offset_allowlist[0]));
+	return ga10b_hwpm_router_register_offset_allowlist;
+}
+
+const u32 *ga10b_get_hwpm_pma_channel_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_hwpm_pma_channel_register_offset_allowlist) /
+		sizeof(ga10b_hwpm_pma_channel_register_offset_allowlist[0]));
+	return ga10b_hwpm_pma_channel_register_offset_allowlist;
+}
+
+const u32 *ga10b_get_hwpm_pma_trigger_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_hwpm_pma_trigger_register_offset_allowlist) /
+		sizeof(ga10b_hwpm_pma_trigger_register_offset_allowlist[0]));
+	return ga10b_hwpm_pma_trigger_register_offset_allowlist;
+}
+
+const u32 *ga10b_get_smpc_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_smpc_register_offset_allowlist) /
+		sizeof(ga10b_smpc_register_offset_allowlist[0]));
+	return ga10b_smpc_register_offset_allowlist;
+}
+
+const u32 *ga10b_get_cau_register_offset_allowlist(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_cau_register_offset_allowlist) /
+		sizeof(ga10b_cau_register_offset_allowlist[0]));
+	return ga10b_cau_register_offset_allowlist;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga10b_get_hwpm_perfmon_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_hwpm_perfmon_register_ranges) /
+		sizeof(ga10b_hwpm_perfmon_register_ranges[0]));
+	return ga10b_hwpm_perfmon_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga10b_get_hwpm_router_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_hwpm_router_register_ranges) /
+		sizeof(ga10b_hwpm_router_register_ranges[0]));
+	return ga10b_hwpm_router_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga10b_get_hwpm_pma_channel_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_hwpm_pma_channel_register_ranges) /
+		sizeof(ga10b_hwpm_pma_channel_register_ranges[0]));
+	return ga10b_hwpm_pma_channel_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga10b_get_hwpm_pma_trigger_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_hwpm_pma_trigger_register_ranges) /
+		sizeof(ga10b_hwpm_pma_trigger_register_ranges[0]));
+	return ga10b_hwpm_pma_trigger_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga10b_get_smpc_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_smpc_register_ranges) /
+		sizeof(ga10b_smpc_register_ranges[0]));
+	return ga10b_smpc_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga10b_get_hwpm_perfmux_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_hwpm_perfmux_register_ranges) /
+		sizeof(ga10b_hwpm_perfmux_register_ranges[0]));
+	return ga10b_hwpm_perfmux_register_ranges;
+}
+
+const struct nvgpu_pm_resource_register_range
+		*ga10b_get_cau_register_ranges(u32 *count)
+{
+	*count = (u32)(sizeof(ga10b_cau_register_ranges) /
+		sizeof(ga10b_cau_register_ranges[0]));
+	return ga10b_cau_register_ranges;
+}
+
diff --git a/drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.h b/drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.h
new file mode 100644
index 000000000..639ce8dbe
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#ifndef NVGPU_GA10B_REGOPS_ALLOWLIST_H
+#define NVGPU_GA10B_REGOPS_ALLOWLIST_H
+
+#include <nvgpu/types.h>
+
+struct nvgpu_pm_resource_register_range;
+
+u32 ga10b_get_hwpm_perfmon_register_stride(void);
+u32 ga10b_get_hwpm_router_register_stride(void);
+u32 ga10b_get_hwpm_pma_channel_register_stride(void);
+u32 ga10b_get_hwpm_pma_trigger_register_stride(void);
+u32 ga10b_get_smpc_register_stride(void);
+u32 ga10b_get_cau_register_stride(void);
+
+const u32 *ga10b_get_hwpm_perfmon_register_offset_allowlist(u32 *count);
+const u32 *ga10b_get_hwpm_router_register_offset_allowlist(u32 *count);
+const u32 *ga10b_get_hwpm_pma_channel_register_offset_allowlist(u32 *count);
+const u32 *ga10b_get_hwpm_pma_trigger_register_offset_allowlist(u32 *count);
+const u32 *ga10b_get_smpc_register_offset_allowlist(u32 *count);
+const u32 *ga10b_get_cau_register_offset_allowlist(u32 *count);
+
+const struct nvgpu_pm_resource_register_range
+	*ga10b_get_hwpm_perfmon_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga10b_get_hwpm_router_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga10b_get_hwpm_pma_channel_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga10b_get_hwpm_pma_trigger_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga10b_get_smpc_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga10b_get_hwpm_perfmux_register_ranges(u32 *count);
+const struct nvgpu_pm_resource_register_range
+	*ga10b_get_cau_register_ranges(u32 *count);
+
+#endif /* NVGPU_GA10B_REGOPS_ALLOWLIST_H */
diff --git a/drivers/gpu/nvgpu/hal/regops/regops_ga100.c b/drivers/gpu/nvgpu/hal/regops/regops_ga100.c
new file mode 100644
index 000000000..512207dd6
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/regops/regops_ga100.c
@@ -0,0 +1,9395 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/regops.h>
+
+#include "regops_ga100.h"
+
+static const struct regop_offset_range ga100_global_whitelist_ranges[] = {
+	{ 0x000004f0,   1},
+	{ 0x000010c0,   2},
+	{ 0x00001a00,   1},
+	{ 0x00004000,   1},
+	{ 0x00004400,   1},
+	{ 0x00004800,   1},
+	{ 0x00006000,   1},
+	{ 0x00006400,   1},
+	{ 0x00006800,   1},
+	{ 0x00009400,   1},
+	{ 0x00009410,   1},
+	{ 0x00009480,   1},
+	{ 0x0000cc98,   1},
+	{ 0x000200d0,   1},
+	{ 0x00020200,  26},
+	{ 0x00022430,   7},
+	{ 0x00022450,   1},
+	{ 0x0002245c,   2},
+	{ 0x00070000,   5},
+	{ 0x000884e0,   1},
+	{ 0x000884f4,   1},
+	{ 0x0008e00c,   1},
+	{ 0x00100c18,   3},
+	{ 0x00100c84,   1},
+	{ 0x00105068,   1},
+	{ 0x00105128,   1},
+	{ 0x001051e8,   1},
+	{ 0x001052a8,   1},
+	{ 0x00105368,   1},
+	{ 0x00105428,   1},
+	{ 0x001054e8,   1},
+	{ 0x001055a8,   1},
+	{ 0x00105668,   1},
+	{ 0x00105728,   1},
+	{ 0x001057e8,   1},
+	{ 0x001058a8,   1},
+	{ 0x00105968,   1},
+	{ 0x00105a28,   1},
+	{ 0x00105ae8,   1},
+	{ 0x00105ba8,   1},
+	{ 0x00105c68,   1},
+	{ 0x00105d28,   1},
+	{ 0x0010a0a8,   1},
+	{ 0x0010a4f0,   1},
+	{ 0x0013cb94,   1},
+	{ 0x0013cc14,   1},
+	{ 0x0013cc24,   2},
+	{ 0x0013cc54,   1},
+	{ 0x0013cc64,   2},
+	{ 0x0013cc94,   1},
+	{ 0x0013cca4,   2},
+	{ 0x0013ccd4,   1},
+	{ 0x0013cce4,   2},
+	{ 0x0013cd14,   1},
+	{ 0x0013cd24,   2},
+	{ 0x0013cd54,   1},
+	{ 0x0013cd64,   2},
+	{ 0x0013cd94,   1},
+	{ 0x0013cda4,   2},
+	{ 0x0013cdd4,   1},
+	{ 0x0013cde4,   2},
+	{ 0x0013ce14,   1},
+	{ 0x0013ce24,   2},
+	{ 0x0013ce54,   1},
+	{ 0x0013ce64,   2},
+	{ 0x0013ce94,   1},
+	{ 0x0013cea4,   2},
+	{ 0x0013ced4,   1},
+	{ 0x0013cee4,   2},
+	{ 0x0013cf14,   1},
+	{ 0x0013cf24,   2},
+	{ 0x0013cf54,   1},
+	{ 0x0013cf64,   2},
+	{ 0x0013cf94,   1},
+	{ 0x0013cfa4,   2},
+	{ 0x0013cfd4,   1},
+	{ 0x0013cfe4,   2},
+	{ 0x0013ec18,   1},
+	{ 0x00140028,   1},
+	{ 0x00140280,   1},
+	{ 0x001402a0,   1},
+	{ 0x00140350,   1},
+	{ 0x00140480,   1},
+	{ 0x001404a0,   1},
+	{ 0x00140550,   1},
+	{ 0x00140680,   1},
+	{ 0x001406a0,   1},
+	{ 0x00140750,   1},
+	{ 0x00140880,   1},
+	{ 0x001408a0,   1},
+	{ 0x00140950,   1},
+	{ 0x00140a80,   1},
+	{ 0x00140aa0,   1},
+	{ 0x00140b50,   1},
+	{ 0x00142028,   1},
+	{ 0x00142280,   1},
+	{ 0x001422a0,   1},
+	{ 0x00142350,   1},
+	{ 0x00142480,   1},
+	{ 0x001424a0,   1},
+	{ 0x00142550,   1},
+	{ 0x00142680,   1},
+	{ 0x001426a0,   1},
+	{ 0x00142750,   1},
+	{ 0x00142880,   1},
+	{ 0x001428a0,   1},
+	{ 0x00142950,   1},
+	{ 0x00142a80,   1},
+	{ 0x00142aa0,   1},
+	{ 0x00142b50,   1},
+	{ 0x00144028,   1},
+	{ 0x00144280,   1},
+	{ 0x00144350,   1},
+	{ 0x00144480,   1},
+	{ 0x00144550,   1},
+	{ 0x00144680,   1},
+	{ 0x00144750,   1},
+	{ 0x00144880,   1},
+	{ 0x00144950,   1},
+	{ 0x00144a80,   1},
+	{ 0x00144b50,   1},
+	{ 0x00146028,   1},
+	{ 0x00146280,   1},
+	{ 0x00146350,   1},
+	{ 0x00146480,   1},
+	{ 0x00146550,   1},
+	{ 0x00146680,   1},
+	{ 0x00146750,   1},
+	{ 0x00146880,   1},
+	{ 0x00146950,   1},
+	{ 0x00146a80,   1},
+	{ 0x00146b50,   1},
+	{ 0x00148028,   1},
+	{ 0x00148280,   1},
+	{ 0x00148350,   1},
+	{ 0x00148480,   1},
+	{ 0x00148550,   1},
+	{ 0x00148680,   1},
+	{ 0x00148750,   1},
+	{ 0x00148880,   1},
+	{ 0x00148950,   1},
+	{ 0x00148a80,   1},
+	{ 0x00148b50,   1},
+	{ 0x0014a028,   1},
+	{ 0x0014a280,   1},
+	{ 0x0014a350,   1},
+	{ 0x0014a480,   1},
+	{ 0x0014a550,   1},
+	{ 0x0014a680,   1},
+	{ 0x0014a750,   1},
+	{ 0x0014a880,   1},
+	{ 0x0014a950,   1},
+	{ 0x0014aa80,   1},
+	{ 0x0014ab50,   1},
+	{ 0x0014c028,   1},
+	{ 0x0014c280,   1},
+	{ 0x0014c350,   1},
+	{ 0x0014c480,   1},
+	{ 0x0014c550,   1},
+	{ 0x0014c680,   1},
+	{ 0x0014c750,   1},
+	{ 0x0014c880,   1},
+	{ 0x0014c950,   1},
+	{ 0x0014ca80,   1},
+	{ 0x0014cb50,   1},
+	{ 0x0014e028,   1},
+	{ 0x0014e280,   1},
+	{ 0x0014e350,   1},
+	{ 0x0014e480,   1},
+	{ 0x0014e550,   1},
+	{ 0x0014e680,   1},
+	{ 0x0014e750,   1},
+	{ 0x0014e880,   1},
+	{ 0x0014e950,   1},
+	{ 0x0014ea80,   1},
+	{ 0x0014eb50,   1},
+	{ 0x00150028,   1},
+	{ 0x00150280,   1},
+	{ 0x00150350,   1},
+	{ 0x00150480,   1},
+	{ 0x00150550,   1},
+	{ 0x00150680,   1},
+	{ 0x00150750,   1},
+	{ 0x00150880,   1},
+	{ 0x00150950,   1},
+	{ 0x00150a80,   1},
+	{ 0x00150b50,   1},
+	{ 0x00152028,   1},
+	{ 0x00152280,   1},
+	{ 0x00152350,   1},
+	{ 0x00152480,   1},
+	{ 0x00152550,   1},
+	{ 0x00152680,   1},
+	{ 0x00152750,   1},
+	{ 0x00152880,   1},
+	{ 0x00152950,   1},
+	{ 0x00152a80,   1},
+	{ 0x00152b50,   1},
+	{ 0x00154028,   1},
+	{ 0x00154280,   1},
+	{ 0x00154350,   1},
+	{ 0x00154480,   1},
+	{ 0x00154550,   1},
+	{ 0x00154680,   1},
+	{ 0x00154750,   1},
+	{ 0x00154880,   1},
+	{ 0x00154950,   1},
+	{ 0x00154a80,   1},
+	{ 0x00154b50,   1},
+	{ 0x00156028,   1},
+	{ 0x00156280,   1},
+	{ 0x00156350,   1},
+	{ 0x00156480,   1},
+	{ 0x00156550,   1},
+	{ 0x00156680,   1},
+	{ 0x00156750,   1},
+	{ 0x00156880,   1},
+	{ 0x00156950,   1},
+	{ 0x00156a80,   1},
+	{ 0x00156b50,   1},
+	{ 0x00158028,   1},
+	{ 0x00158280,   1},
+	{ 0x00158350,   1},
+	{ 0x00158480,   1},
+	{ 0x00158550,   1},
+	{ 0x00158680,   1},
+	{ 0x00158750,   1},
+	{ 0x00158880,   1},
+	{ 0x00158950,   1},
+	{ 0x00158a80,   1},
+	{ 0x00158b50,   1},
+	{ 0x0015a028,   1},
+	{ 0x0015a280,   1},
+	{ 0x0015a350,   1},
+	{ 0x0015a480,   1},
+	{ 0x0015a550,   1},
+	{ 0x0015a680,   1},
+	{ 0x0015a750,   1},
+	{ 0x0015a880,   1},
+	{ 0x0015a950,   1},
+	{ 0x0015aa80,   1},
+	{ 0x0015ab50,   1},
+	{ 0x0015c028,   1},
+	{ 0x0015c280,   1},
+	{ 0x0015c350,   1},
+	{ 0x0015c480,   1},
+	{ 0x0015c550,   1},
+	{ 0x0015c680,   1},
+	{ 0x0015c750,   1},
+	{ 0x0015c880,   1},
+	{ 0x0015c950,   1},
+	{ 0x0015ca80,   1},
+	{ 0x0015cb50,   1},
+	{ 0x0015e028,   1},
+	{ 0x0015e280,   1},
+	{ 0x0015e350,   1},
+	{ 0x0015e480,   1},
+	{ 0x0015e550,   1},
+	{ 0x0015e680,   1},
+	{ 0x0015e750,   1},
+	{ 0x0015e880,   1},
+	{ 0x0015e950,   1},
+	{ 0x0015ea80,   1},
+	{ 0x0015eb50,   1},
+	{ 0x00160028,   1},
+	{ 0x00160280,   1},
+	{ 0x00160350,   1},
+	{ 0x00160480,   1},
+	{ 0x00160550,   1},
+	{ 0x00160680,   1},
+	{ 0x00160750,   1},
+	{ 0x00160880,   1},
+	{ 0x00160950,   1},
+	{ 0x00160a80,   1},
+	{ 0x00160b50,   1},
+	{ 0x00162028,   1},
+	{ 0x00162280,   1},
+	{ 0x00162350,   1},
+	{ 0x00162480,   1},
+	{ 0x00162550,   1},
+	{ 0x00162680,   1},
+	{ 0x00162750,   1},
+	{ 0x00162880,   1},
+	{ 0x00162950,   1},
+	{ 0x00162a80,   1},
+	{ 0x00162b50,   1},
+	{ 0x00164028,   1},
+	{ 0x00164280,   1},
+	{ 0x00164350,   1},
+	{ 0x00164480,   1},
+	{ 0x00164550,   1},
+	{ 0x00164680,   1},
+	{ 0x00164750,   1},
+	{ 0x00164880,   1},
+	{ 0x00164950,   1},
+	{ 0x00164a80,   1},
+	{ 0x00164b50,   1},
+	{ 0x00166028,   1},
+	{ 0x00166280,   1},
+	{ 0x00166350,   1},
+	{ 0x00166480,   1},
+	{ 0x00166550,   1},
+	{ 0x00166680,   1},
+	{ 0x00166750,   1},
+	{ 0x00166880,   1},
+	{ 0x00166950,   1},
+	{ 0x00166a80,   1},
+	{ 0x00166b50,   1},
+	{ 0x00168028,   1},
+	{ 0x00168280,   1},
+	{ 0x00168350,   1},
+	{ 0x00168480,   1},
+	{ 0x00168550,   1},
+	{ 0x00168680,   1},
+	{ 0x00168750,   1},
+	{ 0x00168880,   1},
+	{ 0x00168950,   1},
+	{ 0x00168a80,   1},
+	{ 0x00168b50,   1},
+	{ 0x0016a028,   1},
+	{ 0x0016a280,   1},
+	{ 0x0016a350,   1},
+	{ 0x0016a480,   1},
+	{ 0x0016a550,   1},
+	{ 0x0016a680,   1},
+	{ 0x0016a750,   1},
+	{ 0x0016a880,   1},
+	{ 0x0016a950,   1},
+	{ 0x0016aa80,   1},
+	{ 0x0016ab50,   1},
+	{ 0x0016c028,   1},
+	{ 0x0016c280,   1},
+	{ 0x0016c350,   1},
+	{ 0x0016c480,   1},
+	{ 0x0016c550,   1},
+	{ 0x0016c680,   1},
+	{ 0x0016c750,   1},
+	{ 0x0016c880,   1},
+	{ 0x0016c950,   1},
+	{ 0x0016ca80,   1},
+	{ 0x0016cb50,   1},
+	{ 0x0016e028,   1},
+	{ 0x0016e280,   1},
+	{ 0x0016e350,   1},
+	{ 0x0016e480,   1},
+	{ 0x0016e550,   1},
+	{ 0x0016e680,   1},
+	{ 0x0016e750,   1},
+	{ 0x0016e880,   1},
+	{ 0x0016e950,   1},
+	{ 0x0016ea80,   1},
+	{ 0x0016eb50,   1},
+	{ 0x0017e028,   1},
+	{ 0x0017e280,   1},
+	{ 0x0017e294,   1},
+	{ 0x0017e29c,   2},
+	{ 0x0017e2ac,   1},
+	{ 0x0017e350,   1},
+	{ 0x0017e39c,   1},
+	{ 0x0017e480,   1},
+	{ 0x0017e4a0,   1},
+	{ 0x0017e550,   1},
+	{ 0x0017e680,   1},
+	{ 0x0017e6a0,   1},
+	{ 0x0017e750,   1},
+	{ 0x0017e880,   1},
+	{ 0x0017e8a0,   1},
+	{ 0x0017e950,   1},
+	{ 0x0017ea80,   1},
+	{ 0x0017eaa0,   1},
+	{ 0x0017eb50,   1},
+	{ 0x00180000,   6},
+	{ 0x00180020,   6},
+	{ 0x00180040,  41},
+	{ 0x001800ec,   1},
+	{ 0x001800f8,   7},
+	{ 0x00180124,   2},
+	{ 0x00180130,   1},
+	{ 0x00180200,   6},
+	{ 0x00180220,   6},
+	{ 0x00180240,  41},
+	{ 0x001802ec,   1},
+	{ 0x001802f8,   7},
+	{ 0x00180324,   2},
+	{ 0x00180330,   1},
+	{ 0x00180400,   6},
+	{ 0x00180420,   6},
+	{ 0x00180440,  41},
+	{ 0x001804ec,   1},
+	{ 0x001804f8,   7},
+	{ 0x00180524,   2},
+	{ 0x00180530,   1},
+	{ 0x00180600,   6},
+	{ 0x00180620,   6},
+	{ 0x00180640,  41},
+	{ 0x001806ec,   1},
+	{ 0x001806f8,   7},
+	{ 0x00180724,   2},
+	{ 0x00180730,   1},
+	{ 0x00180800,   6},
+	{ 0x00180820,   6},
+	{ 0x00180840,  41},
+	{ 0x001808ec,   1},
+	{ 0x001808f8,   7},
+	{ 0x00180924,   2},
+	{ 0x00180930,   1},
+	{ 0x00180a00,   6},
+	{ 0x00180a20,   6},
+	{ 0x00180a40,  41},
+	{ 0x00180aec,   1},
+	{ 0x00180af8,   7},
+	{ 0x00180b24,   2},
+	{ 0x00180b30,   1},
+	{ 0x00180c00,   6},
+	{ 0x00180c20,   6},
+	{ 0x00180c40,  41},
+	{ 0x00180cec,   1},
+	{ 0x00180cf8,   7},
+	{ 0x00180d24,   2},
+	{ 0x00180d30,   1},
+	{ 0x00180e00,   6},
+	{ 0x00180e20,   6},
+	{ 0x00180e40,  41},
+	{ 0x00180eec,   1},
+	{ 0x00180ef8,   7},
+	{ 0x00180f24,   2},
+	{ 0x00180f30,   1},
+	{ 0x00181000,   6},
+	{ 0x00181020,   6},
+	{ 0x00181040,  41},
+	{ 0x001810ec,   1},
+	{ 0x001810f8,   7},
+	{ 0x00181124,   2},
+	{ 0x00181130,   1},
+	{ 0x00181200,   6},
+	{ 0x00181220,   6},
+	{ 0x00181240,  41},
+	{ 0x001812ec,   1},
+	{ 0x001812f8,   7},
+	{ 0x00181324,   2},
+	{ 0x00181330,   1},
+	{ 0x00181400,   6},
+	{ 0x00181420,   6},
+	{ 0x00181440,  41},
+	{ 0x001814ec,   1},
+	{ 0x001814f8,   7},
+	{ 0x00181524,   2},
+	{ 0x00181530,   1},
+	{ 0x00181600,   6},
+	{ 0x00181620,   6},
+	{ 0x00181640,  41},
+	{ 0x001816ec,   1},
+	{ 0x001816f8,   7},
+	{ 0x00181724,   2},
+	{ 0x00181730,   1},
+	{ 0x00181800,   6},
+	{ 0x00181820,   6},
+	{ 0x00181840,  41},
+	{ 0x001818ec,   1},
+	{ 0x001818f8,   7},
+	{ 0x00181924,   2},
+	{ 0x00181930,   1},
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+	{ 0x0053cab0,   1},
+	{ 0x0053cb04,   1},
+	{ 0x0053cb3c,   1},
+	{ 0x0053cb48,   1},
+	{ 0x0053cb50,   1},
+	{ 0x0053cba0,   2},
+	{ 0x0053cbb0,   1},
+	{ 0x0053cbdc,   1},
+	{ 0x0053cc0c,   1},
+	{ 0x0053cd00,   1},
+	{ 0x0053cd08,   2},
+	{ 0x0053ce08,   1},
+	{ 0x0053ce64,   1},
+	{ 0x0053ce80,   8},
+	{ 0x0053cea8,   5},
+	{ 0x0053cf00,   8},
+	{ 0x0053cf28,   5},
+	{ 0x0053cf80,   8},
+	{ 0x0053cfa8,   5},
+	{ 0x0053d054,   1},
+	{ 0x0053d180,   8},
+	{ 0x0053d1a4,   1},
+	{ 0x0053d1ac,   1},
+	{ 0x0053d1c0,   8},
+	{ 0x0053d1e4,   1},
+	{ 0x0053d1ec,   1},
+	{ 0x0053d2b0,   1},
+	{ 0x0053d304,   1},
+	{ 0x0053d33c,   1},
+	{ 0x0053d348,   1},
+	{ 0x0053d350,   1},
+	{ 0x0053d3a0,   2},
+	{ 0x0053d3b0,   1},
+	{ 0x0053d3dc,   1},
+	{ 0x0053d40c,   1},
+	{ 0x0053d500,   1},
+	{ 0x0053d508,   2},
+	{ 0x0053d608,   1},
+	{ 0x0053d664,   1},
+	{ 0x0053d680,   8},
+	{ 0x0053d6a8,   5},
+	{ 0x0053d700,   8},
+	{ 0x0053d728,   5},
+	{ 0x0053d780,   8},
+	{ 0x0053d7a8,   5},
+	{ 0x0053d854,   1},
+	{ 0x0053d980,   8},
+	{ 0x0053d9a4,   1},
+	{ 0x0053d9ac,   1},
+	{ 0x0053d9c0,   8},
+	{ 0x0053d9e4,   1},
+	{ 0x0053d9ec,   1},
+	{ 0x0053dab0,   1},
+	{ 0x0053db04,   1},
+	{ 0x0053db3c,   1},
+	{ 0x0053db48,   1},
+	{ 0x0053db50,   1},
+	{ 0x0053dba0,   2},
+	{ 0x0053dbb0,   1},
+	{ 0x0053dbdc,   1},
+	{ 0x0053dc0c,   1},
+	{ 0x0053dd00,   1},
+	{ 0x0053dd08,   2},
+	{ 0x0053de08,   1},
+	{ 0x0053de64,   1},
+	{ 0x0053de80,   8},
+	{ 0x0053dea8,   5},
+	{ 0x0053df00,   8},
+	{ 0x0053df28,   5},
+	{ 0x0053df80,   8},
+	{ 0x0053dfa8,   5},
+	{ 0x0053e054,   1},
+	{ 0x0053e180,   8},
+	{ 0x0053e1a4,   1},
+	{ 0x0053e1ac,   1},
+	{ 0x0053e1c0,   8},
+	{ 0x0053e1e4,   1},
+	{ 0x0053e1ec,   1},
+	{ 0x0053e2b0,   1},
+	{ 0x0053e304,   1},
+	{ 0x0053e33c,   1},
+	{ 0x0053e348,   1},
+	{ 0x0053e350,   1},
+	{ 0x0053e3a0,   2},
+	{ 0x0053e3b0,   1},
+	{ 0x0053e3dc,   1},
+	{ 0x0053e40c,   1},
+	{ 0x0053e500,   1},
+	{ 0x0053e508,   2},
+	{ 0x0053e608,   1},
+	{ 0x0053e664,   1},
+	{ 0x0053e680,   8},
+	{ 0x0053e6a8,   5},
+	{ 0x0053e700,   8},
+	{ 0x0053e728,   5},
+	{ 0x0053e780,   8},
+	{ 0x0053e7a8,   5},
+	{ 0x0053e854,   1},
+	{ 0x0053e980,   8},
+	{ 0x0053e9a4,   1},
+	{ 0x0053e9ac,   1},
+	{ 0x0053e9c0,   8},
+	{ 0x0053e9e4,   1},
+	{ 0x0053e9ec,   1},
+	{ 0x0053eab0,   1},
+	{ 0x0053eb04,   1},
+	{ 0x0053eb3c,   1},
+	{ 0x0053eb48,   1},
+	{ 0x0053eb50,   1},
+	{ 0x0053eba0,   2},
+	{ 0x0053ebb0,   1},
+	{ 0x0053ebdc,   1},
+	{ 0x0053ec0c,   1},
+	{ 0x0053ed00,   1},
+	{ 0x0053ed08,   2},
+	{ 0x0053ee08,   1},
+	{ 0x0053ee64,   1},
+	{ 0x0053ee80,   8},
+	{ 0x0053eea8,   5},
+	{ 0x0053ef00,   8},
+	{ 0x0053ef28,   5},
+	{ 0x0053ef80,   8},
+	{ 0x0053efa8,   5},
+	{ 0x0053f054,   1},
+	{ 0x0053f180,   8},
+	{ 0x0053f1a4,   1},
+	{ 0x0053f1ac,   1},
+	{ 0x0053f1c0,   8},
+	{ 0x0053f1e4,   1},
+	{ 0x0053f1ec,   1},
+	{ 0x0053f2b0,   1},
+	{ 0x0053f304,   1},
+	{ 0x0053f33c,   1},
+	{ 0x0053f348,   1},
+	{ 0x0053f350,   1},
+	{ 0x0053f3a0,   2},
+	{ 0x0053f3b0,   1},
+	{ 0x0053f3dc,   1},
+	{ 0x0053f40c,   1},
+	{ 0x0053f500,   1},
+	{ 0x0053f508,   2},
+	{ 0x0053f608,   1},
+	{ 0x0053f664,   1},
+	{ 0x0053f680,   8},
+	{ 0x0053f6a8,   5},
+	{ 0x0053f700,   8},
+	{ 0x0053f728,   5},
+	{ 0x0053f780,   8},
+	{ 0x0053f7a8,   5},
+	{ 0x0053f854,   1},
+	{ 0x0053f980,   8},
+	{ 0x0053f9a4,   1},
+	{ 0x0053f9ac,   1},
+	{ 0x0053f9c0,   8},
+	{ 0x0053f9e4,   1},
+	{ 0x0053f9ec,   1},
+	{ 0x0053fab0,   1},
+	{ 0x0053fb04,   1},
+	{ 0x0053fb48,   1},
+	{ 0x0053fb50,   1},
+	{ 0x0053fba0,   2},
+	{ 0x0053fbb0,   1},
+	{ 0x0053fbdc,   1},
+	{ 0x0053fc0c,   1},
+	{ 0x0053fd00,   1},
+	{ 0x0053fd08,   1},
+	{ 0x0053fe64,   1},
+	{ 0x0053fe84,   1},
+	{ 0x0053fea8,   5},
+	{ 0x0053ff04,   1},
+	{ 0x0053ff28,   5},
+	{ 0x0053ff84,   1},
+	{ 0x0053ffa8,   5},
+	{ 0x00581a00,  19},
+	{ 0x00581b00,  50},
+	{ 0x00581e00,  50},
+	{ 0x00581f00,  50},
+	{ 0x00584200,  19},
+	{ 0x00584300,  50},
+	{ 0x00584600,  50},
+	{ 0x00584700,  50},
+	{ 0x00584a00,  19},
+	{ 0x00584b00,  50},
+	{ 0x00584e00,  50},
+	{ 0x00584f00,  50},
+	{ 0x00585200,  19},
+	{ 0x00585300,  50},
+	{ 0x00585600,  50},
+	{ 0x00585700,  50},
+	{ 0x00585a00,  19},
+	{ 0x00585b00,  50},
+	{ 0x00585e00,  50},
+	{ 0x00585f00,  50},
+	{ 0x00586200,  19},
+	{ 0x00586300,  50},
+	{ 0x00586600,  50},
+	{ 0x00586700,  50},
+	{ 0x00586a00,  19},
+	{ 0x00586b00,  50},
+	{ 0x00586e00,  50},
+	{ 0x00586f00,  50},
+	{ 0x00587200,  19},
+	{ 0x00587300,  50},
+	{ 0x00587600,  50},
+	{ 0x00587700,  50},
+	{ 0x00587a00,  19},
+	{ 0x00587b00,  50},
+	{ 0x00587e00,  50},
+	{ 0x00587f00,  50},
+	{ 0x00589a00,  19},
+	{ 0x00589b00,  50},
+	{ 0x00589e00,  50},
+	{ 0x00589f00,  50},
+	{ 0x0058c200,  19},
+	{ 0x0058c300,  50},
+	{ 0x0058c600,  50},
+	{ 0x0058c700,  50},
+	{ 0x0058ca00,  19},
+	{ 0x0058cb00,  50},
+	{ 0x0058ce00,  50},
+	{ 0x0058cf00,  50},
+	{ 0x0058d200,  19},
+	{ 0x0058d300,  50},
+	{ 0x0058d600,  50},
+	{ 0x0058d700,  50},
+	{ 0x0058da00,  19},
+	{ 0x0058db00,  50},
+	{ 0x0058de00,  50},
+	{ 0x0058df00,  50},
+	{ 0x0058e200,  19},
+	{ 0x0058e300,  50},
+	{ 0x0058e600,  50},
+	{ 0x0058e700,  50},
+	{ 0x0058ea00,  19},
+	{ 0x0058eb00,  50},
+	{ 0x0058ee00,  50},
+	{ 0x0058ef00,  50},
+	{ 0x0058f200,  19},
+	{ 0x0058f300,  50},
+	{ 0x0058f600,  50},
+	{ 0x0058f700,  50},
+	{ 0x0058fa00,  19},
+	{ 0x0058fb00,  50},
+	{ 0x0058fe00,  50},
+	{ 0x0058ff00,  50},
+	{ 0x00591a00,  19},
+	{ 0x00591b00,  50},
+	{ 0x00591e00,  50},
+	{ 0x00591f00,  50},
+	{ 0x00594200,  19},
+	{ 0x00594300,  50},
+	{ 0x00594600,  50},
+	{ 0x00594700,  50},
+	{ 0x00594a00,  19},
+	{ 0x00594b00,  50},
+	{ 0x00594e00,  50},
+	{ 0x00594f00,  50},
+	{ 0x00595200,  19},
+	{ 0x00595300,  50},
+	{ 0x00595600,  50},
+	{ 0x00595700,  50},
+	{ 0x00595a00,  19},
+	{ 0x00595b00,  50},
+	{ 0x00595e00,  50},
+	{ 0x00595f00,  50},
+	{ 0x00596200,  19},
+	{ 0x00596300,  50},
+	{ 0x00596600,  50},
+	{ 0x00596700,  50},
+	{ 0x00596a00,  19},
+	{ 0x00596b00,  50},
+	{ 0x00596e00,  50},
+	{ 0x00596f00,  50},
+	{ 0x00597200,  19},
+	{ 0x00597300,  50},
+	{ 0x00597600,  50},
+	{ 0x00597700,  50},
+	{ 0x00597a00,  19},
+	{ 0x00597b00,  50},
+	{ 0x00597e00,  50},
+	{ 0x00597f00,  50},
+	{ 0x00599a00,  19},
+	{ 0x00599b00,  50},
+	{ 0x00599e00,  50},
+	{ 0x00599f00,  50},
+	{ 0x0059c200,  19},
+	{ 0x0059c300,  50},
+	{ 0x0059c600,  50},
+	{ 0x0059c700,  50},
+	{ 0x0059ca00,  19},
+	{ 0x0059cb00,  50},
+	{ 0x0059ce00,  50},
+	{ 0x0059cf00,  50},
+	{ 0x0059d200,  19},
+	{ 0x0059d300,  50},
+	{ 0x0059d600,  50},
+	{ 0x0059d700,  50},
+	{ 0x0059da00,  19},
+	{ 0x0059db00,  50},
+	{ 0x0059de00,  50},
+	{ 0x0059df00,  50},
+	{ 0x0059e200,  19},
+	{ 0x0059e300,  50},
+	{ 0x0059e600,  50},
+	{ 0x0059e700,  50},
+	{ 0x0059ea00,  19},
+	{ 0x0059eb00,  50},
+	{ 0x0059ee00,  50},
+	{ 0x0059ef00,  50},
+	{ 0x0059f200,  19},
+	{ 0x0059f300,  50},
+	{ 0x0059f600,  50},
+	{ 0x0059f700,  50},
+	{ 0x0059fa00,  19},
+	{ 0x0059fb00,  50},
+	{ 0x0059fe00,  50},
+	{ 0x0059ff00,  50},
+	{ 0x005a1a00,  19},
+	{ 0x005a1b00,  50},
+	{ 0x005a1e00,  50},
+	{ 0x005a1f00,  50},
+	{ 0x005a4200,  19},
+	{ 0x005a4300,  50},
+	{ 0x005a4600,  50},
+	{ 0x005a4700,  50},
+	{ 0x005a4a00,  19},
+	{ 0x005a4b00,  50},
+	{ 0x005a4e00,  50},
+	{ 0x005a4f00,  50},
+	{ 0x005a5200,  19},
+	{ 0x005a5300,  50},
+	{ 0x005a5600,  50},
+	{ 0x005a5700,  50},
+	{ 0x005a5a00,  19},
+	{ 0x005a5b00,  50},
+	{ 0x005a5e00,  50},
+	{ 0x005a5f00,  50},
+	{ 0x005a6200,  19},
+	{ 0x005a6300,  50},
+	{ 0x005a6600,  50},
+	{ 0x005a6700,  50},
+	{ 0x005a6a00,  19},
+	{ 0x005a6b00,  50},
+	{ 0x005a6e00,  50},
+	{ 0x005a6f00,  50},
+	{ 0x005a7200,  19},
+	{ 0x005a7300,  50},
+	{ 0x005a7600,  50},
+	{ 0x005a7700,  50},
+	{ 0x005a7a00,  19},
+	{ 0x005a7b00,  50},
+	{ 0x005a7e00,  50},
+	{ 0x005a7f00,  50},
+	{ 0x005a9a00,  19},
+	{ 0x005a9b00,  50},
+	{ 0x005a9e00,  50},
+	{ 0x005a9f00,  50},
+	{ 0x005ac200,  19},
+	{ 0x005ac300,  50},
+	{ 0x005ac600,  50},
+	{ 0x005ac700,  50},
+	{ 0x005aca00,  19},
+	{ 0x005acb00,  50},
+	{ 0x005ace00,  50},
+	{ 0x005acf00,  50},
+	{ 0x005ad200,  19},
+	{ 0x005ad300,  50},
+	{ 0x005ad600,  50},
+	{ 0x005ad700,  50},
+	{ 0x005ada00,  19},
+	{ 0x005adb00,  50},
+	{ 0x005ade00,  50},
+	{ 0x005adf00,  50},
+	{ 0x005ae200,  19},
+	{ 0x005ae300,  50},
+	{ 0x005ae600,  50},
+	{ 0x005ae700,  50},
+	{ 0x005aea00,  19},
+	{ 0x005aeb00,  50},
+	{ 0x005aee00,  50},
+	{ 0x005aef00,  50},
+	{ 0x005af200,  19},
+	{ 0x005af300,  50},
+	{ 0x005af600,  50},
+	{ 0x005af700,  50},
+	{ 0x005afa00,  19},
+	{ 0x005afb00,  50},
+	{ 0x005afe00,  50},
+	{ 0x005aff00,  50},
+	{ 0x005b1a00,  19},
+	{ 0x005b1b00,  50},
+	{ 0x005b1e00,  50},
+	{ 0x005b1f00,  50},
+	{ 0x005b4200,  19},
+	{ 0x005b4300,  50},
+	{ 0x005b4600,  50},
+	{ 0x005b4700,  50},
+	{ 0x005b4a00,  19},
+	{ 0x005b4b00,  50},
+	{ 0x005b4e00,  50},
+	{ 0x005b4f00,  50},
+	{ 0x005b5200,  19},
+	{ 0x005b5300,  50},
+	{ 0x005b5600,  50},
+	{ 0x005b5700,  50},
+	{ 0x005b5a00,  19},
+	{ 0x005b5b00,  50},
+	{ 0x005b5e00,  50},
+	{ 0x005b5f00,  50},
+	{ 0x005b6200,  19},
+	{ 0x005b6300,  50},
+	{ 0x005b6600,  50},
+	{ 0x005b6700,  50},
+	{ 0x005b6a00,  19},
+	{ 0x005b6b00,  50},
+	{ 0x005b6e00,  50},
+	{ 0x005b6f00,  50},
+	{ 0x005b7200,  19},
+	{ 0x005b7300,  50},
+	{ 0x005b7600,  50},
+	{ 0x005b7700,  50},
+	{ 0x005b7a00,  19},
+	{ 0x005b7b00,  50},
+	{ 0x005b7e00,  50},
+	{ 0x005b7f00,  50},
+	{ 0x005b9a00,  19},
+	{ 0x005b9b00,  50},
+	{ 0x005b9e00,  50},
+	{ 0x005b9f00,  50},
+	{ 0x005bc200,  19},
+	{ 0x005bc300,  50},
+	{ 0x005bc600,  50},
+	{ 0x005bc700,  50},
+	{ 0x005bca00,  19},
+	{ 0x005bcb00,  50},
+	{ 0x005bce00,  50},
+	{ 0x005bcf00,  50},
+	{ 0x005bd200,  19},
+	{ 0x005bd300,  50},
+	{ 0x005bd600,  50},
+	{ 0x005bd700,  50},
+	{ 0x005bda00,  19},
+	{ 0x005bdb00,  50},
+	{ 0x005bde00,  50},
+	{ 0x005bdf00,  50},
+	{ 0x005be200,  19},
+	{ 0x005be300,  50},
+	{ 0x005be600,  50},
+	{ 0x005be700,  50},
+	{ 0x005bea00,  19},
+	{ 0x005beb00,  50},
+	{ 0x005bee00,  50},
+	{ 0x005bef00,  50},
+	{ 0x005bf200,  19},
+	{ 0x005bf300,  50},
+	{ 0x005bf600,  50},
+	{ 0x005bf700,  50},
+	{ 0x005bfa00,  19},
+	{ 0x005bfb00,  50},
+	{ 0x005bfe00,  50},
+	{ 0x005bff00,  50},
+	{ 0x00820c04,   2},
+	{ 0x00820c14,  41},
+	{ 0x00820d38,   1},
+	{ 0x00820d68,  18},
+	{ 0x00820db8,  17},
+	{ 0x008400a8,   1},
+	{ 0x008480a8,   1},
+	{ 0x00848b5c,   1},
+	{ 0x0084c0a8,   1},
+	{ 0x0084cb5c,   1},
+	{ 0x008500a8,   1},
+	{ 0x00850b5c,   1},
+	{ 0x008540a8,   1},
+	{ 0x00854b5c,   1},
+	{ 0x008580a8,   1},
+	{ 0x00858b5c,   1},
+	{ 0x00900100,   1},
+	{ 0x00904100,   1},
+	{ 0x00908100,   1},
+	{ 0x0090c100,   1},
+	{ 0x00910100,   1},
+	{ 0x00914100,   1},
+	{ 0x00918100,   1},
+	{ 0x0091c100,   1},
+	{ 0x00920100,   1},
+	{ 0x00924100,   1},
+	{ 0x00928100,   1},
+	{ 0x0092c100,   1},
+	{ 0x00930100,   1},
+	{ 0x00934100,   1},
+	{ 0x00938100,   1},
+	{ 0x0093c100,   1},
+	{ 0x00940100,   1},
+	{ 0x00944100,   1},
+	{ 0x00948100,   1},
+	{ 0x0094c100,   1},
+	{ 0x00950100,   1},
+	{ 0x00954100,   1},
+	{ 0x00958100,   1},
+	{ 0x0095c100,   1},
+	{ 0x009a0100,   1},
+	{ 0x009a01e0,   2},
+	{ 0x00a0e500,   2},
+	{ 0x00a0ed00,   2},
+	{ 0x00a16500,   2},
+	{ 0x00a16d00,   2},
+	{ 0x00a1e500,   2},
+	{ 0x00a1ed00,   2},
+	{ 0x00a26500,   2},
+	{ 0x00a26d00,   2},
+	{ 0x00a2e500,   2},
+	{ 0x00a2ed00,   2},
+	{ 0x00a4e500,   2},
+	{ 0x00a4ed00,   2},
+	{ 0x00a56500,   2},
+	{ 0x00a56d00,   2},
+	{ 0x00a5e500,   2},
+	{ 0x00a5ed00,   2},
+	{ 0x00a66500,   2},
+	{ 0x00a66d00,   2},
+	{ 0x00a6e500,   2},
+	{ 0x00a6ed00,   2},
+	{ 0x00a8e500,   2},
+	{ 0x00a8ed00,   2},
+	{ 0x00a96500,   2},
+	{ 0x00a96d00,   2},
+	{ 0x00a9e500,   2},
+	{ 0x00a9ed00,   2},
+	{ 0x00aa6500,   2},
+	{ 0x00aa6d00,   2},
+	{ 0x00aae500,   2},
+	{ 0x00aaed00,   2},
+	{ 0x00b668b0,  24},
+};
+
+static const u64 ga100_global_whitelist_ranges_count =
+	ARRAY_SIZE(ga100_global_whitelist_ranges);
+
+/* context */
+
+/* runcontrol */
+static const u32 ga100_runcontrol_whitelist[] = {
+};
+static const u64 ga100_runcontrol_whitelist_count =
+	ARRAY_SIZE(ga100_runcontrol_whitelist);
+
+const struct regop_offset_range *ga100_get_global_whitelist_ranges(void)
+{
+	return ga100_global_whitelist_ranges;
+}
+
+u64 ga100_get_global_whitelist_ranges_count(void)
+{
+	return ga100_global_whitelist_ranges_count;
+}
+
+const struct regop_offset_range *ga100_get_context_whitelist_ranges(void)
+{
+	return ga100_global_whitelist_ranges;
+}
+
+u64 ga100_get_context_whitelist_ranges_count(void)
+{
+	return ga100_global_whitelist_ranges_count;
+}
+
+const u32 *ga100_get_runcontrol_whitelist(void)
+{
+	return ga100_runcontrol_whitelist;
+}
+
+u64 ga100_get_runcontrol_whitelist_count(void)
+{
+	return ga100_runcontrol_whitelist_count;
+}
diff --git a/drivers/gpu/nvgpu/hal/regops/regops_ga100.h b/drivers/gpu/nvgpu/hal/regops/regops_ga100.h
new file mode 100644
index 000000000..4a07ddabc
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/regops/regops_ga100.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_REGOPS_GA100_H
+#define NVGPU_REGOPS_GA100_H
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+
+const struct regop_offset_range *ga100_get_global_whitelist_ranges(void);
+u64 ga100_get_global_whitelist_ranges_count(void);
+const struct regop_offset_range *ga100_get_context_whitelist_ranges(void);
+u64 ga100_get_context_whitelist_ranges_count(void);
+const u32 *ga100_get_runcontrol_whitelist(void);
+u64 ga100_get_runcontrol_whitelist_count(void);
+const struct regop_offset_range *ga100_get_runcontrol_whitelist_ranges(void);
+u64 ga100_get_runcontrol_whitelist_ranges_count(void);
+
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#endif /* NVGPU_REGOPS_GA100_H */
diff --git a/drivers/gpu/nvgpu/hal/regops/regops_ga10b.c b/drivers/gpu/nvgpu/hal/regops/regops_ga10b.c
new file mode 100644
index 000000000..b0395ab7a
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/regops/regops_ga10b.c
@@ -0,0 +1,1760 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/regops.h>
+
+#include "regops_ga10b.h"
+
+static const struct regop_offset_range ga10b_global_whitelist_ranges[] = {
+	{ 0x000004f0,   1},
+	{ 0x000010c0,   2},
+	{ 0x00001a00,   1},
+	{ 0x00004000,   1},
+	{ 0x00004400,   1},
+	{ 0x00004800,   1},
+	{ 0x00009400,   1},
+	{ 0x00009410,   1},
+	{ 0x00009480,   1},
+	{ 0x0000cc98,   1},
+	{ 0x000200d0,   1},
+	{ 0x00020200,   6},
+	{ 0x00022430,   7},
+	{ 0x00022450,   1},
+	{ 0x0002245c,   2},
+	{ 0x00022480,   1},
+	{ 0x00022704,  12},
+	{ 0x00070000,   5},
+	{ 0x000884e0,   1},
+	{ 0x000884f4,   1},
+	{ 0x0008e00c,   1},
+	{ 0x00100c18,   3},
+	{ 0x00100c84,   1},
+	{ 0x00105068,   1},
+	{ 0x00105128,   1},
+	{ 0x0010a0a8,   1},
+	{ 0x0010a4f0,   1},
+	{ 0x0013cb94,   1},
+	{ 0x0013cc14,   1},
+	{ 0x0013cc24,   2},
+	{ 0x0013cc94,   1},
+	{ 0x0013cca4,   2},
+	{ 0x0013ec18,   1},
+	{ 0x00140028,   1},
+	{ 0x00140280,   1},
+	{ 0x001402a0,   1},
+	{ 0x00140350,   1},
+	{ 0x00140480,   1},
+	{ 0x001404a0,   1},
+	{ 0x00140550,   1},
+	{ 0x00140680,   1},
+	{ 0x001406a0,   1},
+	{ 0x00140750,   1},
+	{ 0x00140880,   1},
+	{ 0x001408a0,   1},
+	{ 0x00140950,   1},
+	{ 0x00140a80,   1},
+	{ 0x00140aa0,   1},
+	{ 0x00140b50,   1},
+	{ 0x00142028,   1},
+	{ 0x00142280,   1},
+	{ 0x001422a0,   1},
+	{ 0x00142350,   1},
+	{ 0x00142480,   1},
+	{ 0x001424a0,   1},
+	{ 0x00142550,   1},
+	{ 0x00142680,   1},
+	{ 0x001426a0,   1},
+	{ 0x00142750,   1},
+	{ 0x00142880,   1},
+	{ 0x001428a0,   1},
+	{ 0x00142950,   1},
+	{ 0x00142a80,   1},
+	{ 0x00142aa0,   1},
+	{ 0x00142b50,   1},
+	{ 0x0017e028,   1},
+	{ 0x0017e280,   1},
+	{ 0x0017e294,   1},
+	{ 0x0017e29c,   2},
+	{ 0x0017e2ac,   1},
+	{ 0x0017e350,   1},
+	{ 0x0017e39c,   1},
+	{ 0x0017e480,   1},
+	{ 0x0017e4a0,   1},
+	{ 0x0017e550,   1},
+	{ 0x0017e680,   1},
+	{ 0x0017e6a0,   1},
+	{ 0x0017e750,   1},
+	{ 0x0017e880,   1},
+	{ 0x0017e8a0,   1},
+	{ 0x0017e950,   1},
+	{ 0x0017ea80,   1},
+	{ 0x0017eaa0,   1},
+	{ 0x0017eb50,   1},
+	{ 0x00180000,   6},
+	{ 0x00180020,   6},
+	{ 0x00180040,  21},
+	{ 0x00180098,  19},
+	{ 0x001800ec,   1},
+	{ 0x001800f8,   3},
+	{ 0x00180108,   1},
+	{ 0x00180110,   1},
+	{ 0x00180120,   3},
+	{ 0x00180130,   1},
+	{ 0x00180200,   6},
+	{ 0x00180220,   6},
+	{ 0x00180240,  21},
+	{ 0x00180298,  19},
+	{ 0x001802ec,   1},
+	{ 0x001802f8,   3},
+	{ 0x00180308,   1},
+	{ 0x00180310,   1},
+	{ 0x00180320,   3},
+	{ 0x00180330,   1},
+	{ 0x00180400,   6},
+	{ 0x00180420,   6},
+	{ 0x00180440,  21},
+	{ 0x00180498,  19},
+	{ 0x001804ec,   1},
+	{ 0x001804f8,   3},
+	{ 0x00180508,   1},
+	{ 0x00180510,   1},
+	{ 0x00180520,   3},
+	{ 0x00180530,   1},
+	{ 0x00180600,   6},
+	{ 0x00180620,   6},
+	{ 0x00180640,  21},
+	{ 0x00180698,  19},
+	{ 0x001806ec,   1},
+	{ 0x001806f8,   3},
+	{ 0x00180708,   1},
+	{ 0x00180710,   1},
+	{ 0x00180720,   3},
+	{ 0x00180730,   1},
+	{ 0x00180800,   6},
+	{ 0x00180820,   6},
+	{ 0x00180840,  21},
+	{ 0x00180898,  19},
+	{ 0x001808ec,   1},
+	{ 0x001808f8,   3},
+	{ 0x00180908,   1},
+	{ 0x00180910,   1},
+	{ 0x00180920,   3},
+	{ 0x00180930,   1},
+	{ 0x00180a00,   6},
+	{ 0x00180a20,   6},
+	{ 0x00180a40,  21},
+	{ 0x00180a98,  19},
+	{ 0x00180aec,   1},
+	{ 0x00180af8,   3},
+	{ 0x00180b08,   1},
+	{ 0x00180b10,   1},
+	{ 0x00180b20,   3},
+	{ 0x00180b30,   1},
+	{ 0x00180c00,   6},
+	{ 0x00180c20,   6},
+	{ 0x00180c40,  21},
+	{ 0x00180c98,  19},
+	{ 0x00180cec,   1},
+	{ 0x00180cf8,   3},
+	{ 0x00180d08,   1},
+	{ 0x00180d10,   1},
+	{ 0x00180d20,   3},
+	{ 0x00180d30,   1},
+	{ 0x00180e00,   6},
+	{ 0x00180e20,   6},
+	{ 0x00180e40,  21},
+	{ 0x00180e98,  19},
+	{ 0x00180eec,   1},
+	{ 0x00180ef8,   3},
+	{ 0x00180f08,   1},
+	{ 0x00180f10,   1},
+	{ 0x00180f20,   3},
+	{ 0x00180f30,   1},
+	{ 0x00181000,   6},
+	{ 0x00181020,   6},
+	{ 0x00181040,  21},
+	{ 0x00181098,  19},
+	{ 0x001810ec,   1},
+	{ 0x001810f8,   3},
+	{ 0x00181108,   1},
+	{ 0x00181110,   1},
+	{ 0x00181120,   3},
+	{ 0x00181130,   1},
+	{ 0x00181200,   6},
+	{ 0x00181220,   6},
+	{ 0x00181240,  21},
+	{ 0x00181298,  19},
+	{ 0x001812ec,   1},
+	{ 0x001812f8,   3},
+	{ 0x00181308,   1},
+	{ 0x00181310,   1},
+	{ 0x00181320,   3},
+	{ 0x00181330,   1},
+	{ 0x00181400,   6},
+	{ 0x00181420,   6},
+	{ 0x00181440,  21},
+	{ 0x00181498,  19},
+	{ 0x001814ec,   1},
+	{ 0x001814f8,   3},
+	{ 0x00181508,   1},
+	{ 0x00181510,   1},
+	{ 0x00181520,   3},
+	{ 0x00181530,   1},
+	{ 0x00181600,   6},
+	{ 0x00181620,   6},
+	{ 0x00181640,  21},
+	{ 0x00181698,  19},
+	{ 0x001816ec,   1},
+	{ 0x001816f8,   3},
+	{ 0x00181708,   1},
+	{ 0x00181710,   1},
+	{ 0x00181720,   3},
+	{ 0x00181730,   1},
+	{ 0x00181800,   6},
+	{ 0x00181820,   6},
+	{ 0x00181840,  21},
+	{ 0x00181898,  19},
+	{ 0x001818ec,   1},
+	{ 0x001818f8,   3},
+	{ 0x00181908,   1},
+	{ 0x00181910,   1},
+	{ 0x00181920,   3},
+	{ 0x00181930,   1},
+	{ 0x00181a00,   6},
+	{ 0x00181a20,   6},
+	{ 0x00181a40,  21},
+	{ 0x00181a98,  19},
+	{ 0x00181aec,   1},
+	{ 0x00181af8,   3},
+	{ 0x00181b08,   1},
+	{ 0x00181b10,   1},
+	{ 0x00181b20,   3},
+	{ 0x00181b30,   1},
+	{ 0x00181c00,   6},
+	{ 0x00181c20,   6},
+	{ 0x00181c40,  21},
+	{ 0x00181c98,  19},
+	{ 0x00181cec,   1},
+	{ 0x00181cf8,   3},
+	{ 0x00181d08,   1},
+	{ 0x00181d10,   1},
+	{ 0x00181d20,   3},
+	{ 0x00181d30,   1},
+	{ 0x00181e00,   6},
+	{ 0x00181e20,   6},
+	{ 0x00181e40,  21},
+	{ 0x00181e98,  19},
+	{ 0x00181eec,   1},
+	{ 0x00181ef8,   3},
+	{ 0x00181f08,   1},
+	{ 0x00181f10,   1},
+	{ 0x00181f20,   3},
+	{ 0x00181f30,   1},
+	{ 0x00184000,   6},
+	{ 0x00184020,   6},
+	{ 0x00184040,  21},
+	{ 0x00184098,  19},
+	{ 0x001840ec,   1},
+	{ 0x001840f8,   3},
+	{ 0x00184108,   1},
+	{ 0x00184110,   1},
+	{ 0x00184120,   3},
+	{ 0x00184130,   1},
+	{ 0x00184200,   6},
+	{ 0x00184220,   6},
+	{ 0x00184240,  21},
+	{ 0x00184298,  19},
+	{ 0x001842ec,   1},
+	{ 0x001842f8,   3},
+	{ 0x00184308,   1},
+	{ 0x00184310,   1},
+	{ 0x00184320,   3},
+	{ 0x00184330,   1},
+	{ 0x00184400,   6},
+	{ 0x00184420,   6},
+	{ 0x00184440,  21},
+	{ 0x00184498,  19},
+	{ 0x001844ec,   1},
+	{ 0x001844f8,   3},
+	{ 0x00184508,   1},
+	{ 0x00184510,   1},
+	{ 0x00184520,   3},
+	{ 0x00184530,   1},
+	{ 0x00184600,   6},
+	{ 0x00184620,   6},
+	{ 0x00184640,  21},
+	{ 0x00184698,  19},
+	{ 0x001846ec,   1},
+	{ 0x001846f8,   3},
+	{ 0x00184708,   1},
+	{ 0x00184710,   1},
+	{ 0x00184720,   3},
+	{ 0x00184730,   1},
+	{ 0x00184800,   6},
+	{ 0x00184820,   6},
+	{ 0x00184840,  21},
+	{ 0x00184898,  19},
+	{ 0x001848ec,   1},
+	{ 0x001848f8,   3},
+	{ 0x00184908,   1},
+	{ 0x00184910,   1},
+	{ 0x00184920,   3},
+	{ 0x00184930,   1},
+	{ 0x00184a00,   6},
+	{ 0x00184a20,   6},
+	{ 0x00184a40,  21},
+	{ 0x00184a98,  19},
+	{ 0x00184aec,   1},
+	{ 0x00184af8,   3},
+	{ 0x00184b08,   1},
+	{ 0x00184b10,   1},
+	{ 0x00184b20,   3},
+	{ 0x00184b30,   1},
+	{ 0x00184c00,   6},
+	{ 0x00184c20,   6},
+	{ 0x00184c40,  21},
+	{ 0x00184c98,  19},
+	{ 0x00184cec,   1},
+	{ 0x00184cf8,   3},
+	{ 0x00184d08,   1},
+	{ 0x00184d10,   1},
+	{ 0x00184d20,   3},
+	{ 0x00184d30,   1},
+	{ 0x00184e00,   6},
+	{ 0x00184e20,   6},
+	{ 0x00184e40,  21},
+	{ 0x00184e98,  19},
+	{ 0x00184eec,   1},
+	{ 0x00184ef8,   3},
+	{ 0x00184f08,   1},
+	{ 0x00184f10,   1},
+	{ 0x00184f20,   3},
+	{ 0x00184f30,   1},
+	{ 0x00185000,   6},
+	{ 0x00185020,   6},
+	{ 0x00185040,  21},
+	{ 0x00185098,  19},
+	{ 0x001850ec,   1},
+	{ 0x001850f8,   3},
+	{ 0x00185108,   1},
+	{ 0x00185110,   1},
+	{ 0x00185120,   3},
+	{ 0x00185130,   1},
+	{ 0x00185200,   6},
+	{ 0x00185220,   6},
+	{ 0x00185240,  21},
+	{ 0x00185298,  19},
+	{ 0x001852ec,   1},
+	{ 0x001852f8,   3},
+	{ 0x00185308,   1},
+	{ 0x00185310,   1},
+	{ 0x00185320,   3},
+	{ 0x00185330,   1},
+	{ 0x00185400,   6},
+	{ 0x00185420,   6},
+	{ 0x00185440,  21},
+	{ 0x00185498,  19},
+	{ 0x001854ec,   1},
+	{ 0x001854f8,   3},
+	{ 0x00185508,   1},
+	{ 0x00185510,   1},
+	{ 0x00185520,   3},
+	{ 0x00185530,   1},
+	{ 0x00185600,   6},
+	{ 0x00185620,   6},
+	{ 0x00185640,  21},
+	{ 0x00185698,  19},
+	{ 0x001856ec,   1},
+	{ 0x001856f8,   3},
+	{ 0x00185708,   1},
+	{ 0x00185710,   1},
+	{ 0x00185720,   3},
+	{ 0x00185730,   1},
+	{ 0x00185800,   6},
+	{ 0x00185820,   6},
+	{ 0x00185840,  21},
+	{ 0x00185898,  19},
+	{ 0x001858ec,   1},
+	{ 0x001858f8,   3},
+	{ 0x00185908,   1},
+	{ 0x00185910,   1},
+	{ 0x00185920,   3},
+	{ 0x00185930,   1},
+	{ 0x00185a00,   6},
+	{ 0x00185a20,   6},
+	{ 0x00185a40,  21},
+	{ 0x00185a98,  19},
+	{ 0x00185aec,   1},
+	{ 0x00185af8,   3},
+	{ 0x00185b08,   1},
+	{ 0x00185b10,   1},
+	{ 0x00185b20,   3},
+	{ 0x00185b30,   1},
+	{ 0x00185c00,   6},
+	{ 0x00185c20,   6},
+	{ 0x00185c40,  21},
+	{ 0x00185c98,  19},
+	{ 0x00185cec,   1},
+	{ 0x00185cf8,   3},
+	{ 0x00185d08,   1},
+	{ 0x00185d10,   1},
+	{ 0x00185d20,   3},
+	{ 0x00185d30,   1},
+	{ 0x00185e00,   6},
+	{ 0x00185e20,   6},
+	{ 0x00185e40,  21},
+	{ 0x00185e98,  19},
+	{ 0x00185eec,   1},
+	{ 0x00185ef8,   3},
+	{ 0x00185f08,   1},
+	{ 0x00185f10,   1},
+	{ 0x00185f20,   3},
+	{ 0x00185f30,   1},
+	{ 0x00188128,   1},
+	{ 0x00188130,   1},
+	{ 0x00188328,   1},
+	{ 0x00188330,   1},
+	{ 0x00188528,   1},
+	{ 0x00188530,   1},
+	{ 0x00188728,   1},
+	{ 0x00188730,   1},
+	{ 0x00188928,   1},
+	{ 0x00188930,   1},
+	{ 0x00188b28,   1},
+	{ 0x00188b30,   1},
+	{ 0x00188d28,   1},
+	{ 0x00188d30,   1},
+	{ 0x00188f28,   1},
+	{ 0x00188f30,   1},
+	{ 0x00189128,   1},
+	{ 0x00189130,   1},
+	{ 0x00189328,   1},
+	{ 0x00189330,   1},
+	{ 0x00189528,   1},
+	{ 0x00189530,   1},
+	{ 0x00189728,   1},
+	{ 0x00189730,   1},
+	{ 0x00189928,   1},
+	{ 0x00189930,   1},
+	{ 0x00189b28,   1},
+	{ 0x00189b30,   1},
+	{ 0x00189d28,   1},
+	{ 0x00189d30,   1},
+	{ 0x00189f28,   1},
+	{ 0x00189f30,   1},
+	{ 0x00200000,   6},
+	{ 0x00200020,   6},
+	{ 0x00200040,  21},
+	{ 0x00200098,  19},
+	{ 0x002000ec,   1},
+	{ 0x002000f8,   3},
+	{ 0x00200108,   1},
+	{ 0x00200110,   1},
+	{ 0x00200120,   3},
+	{ 0x00200130,   1},
+	{ 0x00200200,   6},
+	{ 0x00200220,   6},
+	{ 0x00200240,  21},
+	{ 0x00200298,  19},
+	{ 0x002002ec,   1},
+	{ 0x002002f8,   3},
+	{ 0x00200308,   1},
+	{ 0x00200310,   1},
+	{ 0x00200320,   3},
+	{ 0x00200330,   1},
+	{ 0x00200400,   6},
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+	{ 0x0050cba0,   2},
+	{ 0x0050cbb0,   1},
+	{ 0x0050cbdc,   1},
+	{ 0x0050cc0c,   1},
+	{ 0x0050cd00,   1},
+	{ 0x0050cd08,   2},
+	{ 0x0050ce08,   1},
+	{ 0x0050ce64,   1},
+	{ 0x0050ce80,   8},
+	{ 0x0050cea8,   5},
+	{ 0x0050cf00,   8},
+	{ 0x0050cf28,   5},
+	{ 0x0050cf80,   8},
+	{ 0x0050cfa8,   5},
+	{ 0x0050d054,   1},
+	{ 0x0050d180,   8},
+	{ 0x0050d1a4,   1},
+	{ 0x0050d1ac,   1},
+	{ 0x0050d1c0,   8},
+	{ 0x0050d1e4,   1},
+	{ 0x0050d2b0,   1},
+	{ 0x0050d304,   1},
+	{ 0x0050d33c,   1},
+	{ 0x0050d348,   1},
+	{ 0x0050d350,   1},
+	{ 0x0050d3a0,   2},
+	{ 0x0050d3b0,   1},
+	{ 0x0050d3dc,   1},
+	{ 0x0050d40c,   1},
+	{ 0x0050d500,   1},
+	{ 0x0050d508,   2},
+	{ 0x0050d608,   1},
+	{ 0x0050d664,   1},
+	{ 0x0050d680,   8},
+	{ 0x0050d6a8,   5},
+	{ 0x0050d700,   8},
+	{ 0x0050d728,   5},
+	{ 0x0050d780,   8},
+	{ 0x0050d7a8,   5},
+	{ 0x0050d854,   1},
+	{ 0x0050d980,   8},
+	{ 0x0050d9a4,   1},
+	{ 0x0050d9ac,   1},
+	{ 0x0050d9c0,   8},
+	{ 0x0050d9e4,   1},
+	{ 0x0050dab0,   1},
+	{ 0x0050db04,   1},
+	{ 0x0050db3c,   1},
+	{ 0x0050db48,   1},
+	{ 0x0050db50,   1},
+	{ 0x0050dba0,   2},
+	{ 0x0050dbb0,   1},
+	{ 0x0050dbdc,   1},
+	{ 0x0050dc0c,   1},
+	{ 0x0050dd00,   1},
+	{ 0x0050dd08,   2},
+	{ 0x0050de08,   1},
+	{ 0x0050de64,   1},
+	{ 0x0050de80,   8},
+	{ 0x0050dea8,   5},
+	{ 0x0050df00,   8},
+	{ 0x0050df28,   5},
+	{ 0x0050df80,   8},
+	{ 0x0050dfa8,   5},
+	{ 0x00581a00,  19},
+	{ 0x00581b00,  50},
+	{ 0x00581e00,  50},
+	{ 0x00581f00,  50},
+	{ 0x00584200,  19},
+	{ 0x00584300,  50},
+	{ 0x00584600,  50},
+	{ 0x00584700,  50},
+	{ 0x00584a00,  19},
+	{ 0x00584b00,  50},
+	{ 0x00584e00,  50},
+	{ 0x00584f00,  50},
+	{ 0x00585200,  19},
+	{ 0x00585300,  50},
+	{ 0x00585600,  50},
+	{ 0x00585700,  50},
+	{ 0x00585a00,  19},
+	{ 0x00585b00,  50},
+	{ 0x00585e00,  50},
+	{ 0x00585f00,  50},
+	{ 0x00589a00,  19},
+	{ 0x00589b00,  50},
+	{ 0x00589e00,  50},
+	{ 0x00589f00,  50},
+	{ 0x0058c200,  19},
+	{ 0x0058c300,  50},
+	{ 0x0058c600,  50},
+	{ 0x0058c700,  50},
+	{ 0x0058ca00,  19},
+	{ 0x0058cb00,  50},
+	{ 0x0058ce00,  50},
+	{ 0x0058cf00,  50},
+	{ 0x0058d200,  19},
+	{ 0x0058d300,  50},
+	{ 0x0058d600,  50},
+	{ 0x0058d700,  50},
+	{ 0x0058da00,  19},
+	{ 0x0058db00,  50},
+	{ 0x0058de00,  50},
+	{ 0x0058df00,  50},
+	{ 0x00820c04,   2},
+	{ 0x00820c14,   1},
+	{ 0x00820c1c,   1},
+	{ 0x00820c24,  37},
+	{ 0x00820d38,   1},
+	{ 0x00820d68,  18},
+	{ 0x00820dbc,  16},
+	{ 0x00822880,  16},
+	{ 0x008400a8,   1},
+	{ 0x009a0100,   1},
+	{ 0x009a01e0,   2},
+	{ 0x00b668b0,  24},
+};
+
+static const u64 ga10b_global_whitelist_ranges_count =
+	ARRAY_SIZE(ga10b_global_whitelist_ranges);
+
+/* context */
+
+/* runcontrol */
+static const u32 ga10b_runcontrol_whitelist[] = {
+};
+static const u64 ga10b_runcontrol_whitelist_count =
+	ARRAY_SIZE(ga10b_runcontrol_whitelist);
+
+const struct regop_offset_range *ga10b_get_global_whitelist_ranges(void)
+{
+	return ga10b_global_whitelist_ranges;
+}
+
+u64 ga10b_get_global_whitelist_ranges_count(void)
+{
+	return ga10b_global_whitelist_ranges_count;
+}
+
+const struct regop_offset_range *ga10b_get_context_whitelist_ranges(void)
+{
+	return ga10b_global_whitelist_ranges;
+}
+
+u64 ga10b_get_context_whitelist_ranges_count(void)
+{
+	return ga10b_global_whitelist_ranges_count;
+}
+
+const u32 *ga10b_get_runcontrol_whitelist(void)
+{
+	return ga10b_runcontrol_whitelist;
+}
+
+u64 ga10b_get_runcontrol_whitelist_count(void)
+{
+	return ga10b_runcontrol_whitelist_count;
+}
diff --git a/drivers/gpu/nvgpu/hal/regops/regops_ga10b.h b/drivers/gpu/nvgpu/hal/regops/regops_ga10b.h
new file mode 100644
index 000000000..ea701a8d4
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/regops/regops_ga10b.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_REGOPS_GA10B_H
+#define NVGPU_REGOPS_GA10B_H
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+
+const struct regop_offset_range *ga10b_get_global_whitelist_ranges(void);
+u64 ga10b_get_global_whitelist_ranges_count(void);
+const struct regop_offset_range *ga10b_get_context_whitelist_ranges(void);
+u64 ga10b_get_context_whitelist_ranges_count(void);
+const u32 *ga10b_get_runcontrol_whitelist(void);
+u64 ga10b_get_runcontrol_whitelist_count(void);
+const struct regop_offset_range *ga10b_get_runcontrol_whitelist_ranges(void);
+u64 ga10b_get_runcontrol_whitelist_ranges_count(void);
+
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#endif /* NVGPU_REGOPS_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/therm/therm_ga10b.h b/drivers/gpu/nvgpu/hal/therm/therm_ga10b.h
new file mode 100644
index 000000000..aca47a667
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/therm/therm_ga10b.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef THERM_GA10B_H
+#define THERM_GA10B_H
+
+struct gk20a;
+
+u32 ga10b_therm_max_fpdiv_factor(void);
+int ga10b_elcg_init_idle_filters(struct gk20a *g);
+
+#endif /* THERM_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/therm/therm_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/therm/therm_ga10b_fusa.c
new file mode 100644
index 000000000..739f9ed14
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/therm/therm_ga10b_fusa.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <nvgpu/soc.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/device.h>
+
+#include <nvgpu/power_features/cg.h>
+
+#include "therm_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_therm_ga10b.h>
+
+u32 ga10b_therm_max_fpdiv_factor(void)
+{
+	return therm_grad_stepping_table_slowdown_factor0_fpdiv_by31_f();
+}
+
+int ga10b_elcg_init_idle_filters(struct gk20a *g)
+{
+	u32 gate_ctrl, idle_filter;
+	u32 i;
+	const struct nvgpu_device *dev;
+	struct nvgpu_fifo *f = &g->fifo;
+
+	if (nvgpu_platform_is_simulation(g)) {
+		return 0;
+	}
+
+	nvgpu_log_info(g, "init clock/power gate reg");
+
+	for (i = 0U; i < f->num_engines; i++) {
+		dev = f->active_engines[i];
+
+		gate_ctrl = nvgpu_readl(g, therm_gate_ctrl_r(dev->engine_id));
+		gate_ctrl = set_field(gate_ctrl,
+			therm_gate_ctrl_eng_idle_filt_exp_m(),
+			therm_gate_ctrl_eng_idle_filt_exp__prod_f());
+		gate_ctrl = set_field(gate_ctrl,
+			therm_gate_ctrl_eng_idle_filt_mant_m(),
+			therm_gate_ctrl_eng_idle_filt_mant__prod_f());
+		gate_ctrl = set_field(gate_ctrl,
+			therm_gate_ctrl_eng_delay_before_m(),
+			therm_gate_ctrl_eng_delay_before__prod_f());
+		gate_ctrl = set_field(gate_ctrl,
+				therm_gate_ctrl_eng_delay_after_m(),
+				therm_gate_ctrl_eng_delay_after__prod_f());
+		nvgpu_writel(g, therm_gate_ctrl_r(dev->engine_id), gate_ctrl);
+	}
+
+	idle_filter = nvgpu_readl(g, therm_fecs_idle_filter_r());
+	idle_filter = set_field(idle_filter,
+			therm_fecs_idle_filter_value_m(),
+			therm_fecs_idle_filter_value__prod_f());
+	nvgpu_writel(g, therm_fecs_idle_filter_r(), idle_filter);
+
+	idle_filter = nvgpu_readl(g, therm_hubmmu_idle_filter_r());
+	idle_filter = set_field(idle_filter,
+			therm_hubmmu_idle_filter_value_m(),
+			therm_hubmmu_idle_filter_value__prod_f());
+	nvgpu_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
+
+	return 0;
+}
diff --git a/drivers/gpu/nvgpu/hal/top/top_ga10b.h b/drivers/gpu/nvgpu/hal/top/top_ga10b.h
new file mode 100644
index 000000000..43527b672
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/top/top_ga10b.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_TOP_GA10B_H
+#define NVGPU_TOP_GA10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+u32 ga10b_get_num_engine_type_entries(struct gk20a *g, u32 engine_type);
+bool ga10b_is_engine_gr(struct gk20a *g, u32 engine_type);
+bool ga10b_is_engine_ce(struct gk20a *g, u32 engine_type);
+
+struct nvgpu_device *ga10b_top_parse_next_dev(struct gk20a *g, u32 *i);
+
+#endif /* NVGPU_TOP_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/top/top_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/top/top_ga10b_fusa.c
new file mode 100644
index 000000000..9179b6ad6
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/top/top_ga10b_fusa.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/device.h>
+#include <nvgpu/log.h>
+
+#include "top_ga10b.h"
+
+#include <nvgpu/hw/ga10b/hw_top_ga10b.h>
+
+u32 ga10b_get_num_engine_type_entries(struct gk20a *g, u32 engine_type)
+{
+	/*
+	 * Will be replaced by core code function in next patch!
+	 */
+	return 0U;
+}
+
+static struct nvgpu_device *ga10b_top_parse_device(struct gk20a *g,
+						   u32 *rows, u32 num_rows)
+{
+	bool valid_device_info = false;
+	struct nvgpu_device *dev;
+
+	/*
+	 * ga10b  device info structure
+	 * 31           24 23           16 15       10   8 7             0
+	 * .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
+	 * |1|  type_enum  |  instance_id  |0 0 0 0 0|     fault_id        |
+	 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+	 * |1|E|0 0 0 0|        device_pri_base            |   reset_id    |
+	 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+	 * |0|0|0 0 0 0|       runlist_pri_base        |0 0 0 0 0 0 0 0|rle|
+	 * `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
+	 */
+
+	/*
+	 * Ensure we have at least 2 entries by checking row 0's chain bit. Not
+	 * all devices (e.g GSP) have 3 rows populated.
+	 */
+	valid_device_info = (top_device_info2_row_chain_v(rows[0]) ==
+			     top_device_info2_row_chain_more_v());
+
+	/* Check for valid device info */
+	if (!valid_device_info) {
+		nvgpu_warn(g, "Parsed broken device from device table!");
+		return NULL;
+	}
+
+	dev = nvgpu_kzalloc(g, sizeof(*dev));
+	if (dev == NULL) {
+		nvgpu_err(g, "OOM allocating device!");
+		return NULL;
+	}
+
+	/*
+	 * Many of the below fields are not valid for non-engine devices. That's
+	 * ok - we can still parse the fields; they'll just be 0s.
+	 */
+	dev->type = top_device_info2_dev_type_enum_v(rows[0]);
+	dev->inst_id = top_device_info2_dev_instance_id_v(rows[0]);
+	dev->fault_id = top_device_info2_dev_fault_id_v(rows[0]);
+	dev->reset_id = top_device_info2_dev_reset_id_v(rows[1]);
+	dev->pri_base = top_device_info2_dev_device_pri_base_v(rows[1]) <<
+		top_device_info2_dev_device_pri_base_b();
+
+	dev->next.engine = top_device_info2_dev_is_engine_v(rows[1]) ==
+		top_device_info2_dev_is_engine_true_v();
+	dev->next.rleng_id = top_device_info2_dev_rleng_id_v(rows[2]);
+	dev->next.rl_pri_base =
+		top_device_info2_dev_runlist_pri_base_v(rows[2]) <<
+		top_device_info2_dev_runlist_pri_base_b();
+
+	if (dev->next.engine) {
+		dev->engine_id = g->ops.runlist.get_engine_id_from_rleng_id(g,
+								dev->next.rleng_id,
+								dev->next.rl_pri_base);
+		dev->runlist_id = g->ops.runlist.get_runlist_id(g,
+								dev->next.rl_pri_base);
+		dev->intr_id = g->ops.runlist.get_engine_intr_id(g,
+								 dev->next.rl_pri_base,
+								 dev->next.rleng_id);
+		g->ops.runlist.get_pbdma_info(g,
+					      dev->next.rl_pri_base,
+					      &dev->next.pbdma_info);
+
+	}
+
+	return dev;
+}
+
+static u32 ga10b_top_table_size(struct gk20a *g)
+{
+	u32 cfg = nvgpu_readl(g, top_device_info_cfg_r());
+
+	return top_device_info_cfg_num_rows_v(cfg);
+}
+
+/*
+ * On Ampere there are 3 rows per device. Although the HW does leave open the
+ * option for adding rows in the future, for now, let's just hard code to row
+ * reads. We have to use specific rows for specific fields
+ */
+struct nvgpu_device *ga10b_top_parse_next_dev(struct gk20a *g, u32 *token)
+{
+	/*
+	 * FIXME: HW define for this exists.
+	 */
+	#define MAX_ROWS 3
+
+	u32 j, cfg;
+	u32 rows[MAX_ROWS] = { 0 };
+
+	cfg = nvgpu_readl(g, top_device_info_cfg_r());
+	if (top_device_info_cfg_version_v(cfg) !=
+			top_device_info_cfg_version_init_v()) {
+		nvgpu_err(g, "device info cfg mismatch");
+		return NULL;
+	}
+
+	/*
+	 * Skip any empty rows. We can assume that this function won't have been
+	 * called mid row, so if we see a 0U row value, then its before we've
+	 * started parsing a device. Thus we can just skip it. But be careful
+	 * not to run past the end of the device register array!
+	 */
+	while (*token < ga10b_top_table_size(g)) {
+		rows[0] = nvgpu_readl(g, top_device_info2_r(*token));
+		(*token)++;
+
+		if (rows[0] != 0U) {
+			break;
+		}
+	}
+
+	if (*token >= ga10b_top_table_size(g)) {
+		return NULL;
+	}
+
+	/*
+	 * Use the *token value to index the actual table; but keep a local j
+	 * index counter to limit ourselves to the max number or rows in a
+	 * table. We can skip the first entry since that got read in the
+	 * while-loop above.
+	 */
+	for (j = 1U; j < MAX_ROWS; j++) {
+		rows[j] = nvgpu_readl(g, top_device_info2_r(*token));
+		(*token)++;
+
+		if (top_device_info2_row_chain_v(rows[j]) ==
+		    top_device_info2_row_chain_last_v()) {
+			break;
+		}
+	}
+
+	return ga10b_top_parse_device(g, rows, MAX_ROWS);
+}
diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
new file mode 100644
index 000000000..d350caac5
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
@@ -0,0 +1,1206 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "hal/bus/bus_gk20a.h"
+#include "hal/bus/bus_gm20b.h"
+#include "hal/mm/mm_gm20b.h"
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
+#include "hal/mm/gmmu/gmmu_gk20a.h"
+#include "hal/mm/gmmu/gmmu_gm20b.h"
+#include "hal/mm/gmmu/gmmu_gp10b.h"
+#include "hal/mm/gmmu/gmmu_gv11b.h"
+#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
+#include "hal/mm/gmmu/gmmu_ga10b.h"
+#include "hal/regops/regops_gv11b.h"
+#include "hal/class/class_ga10b.h"
+#include "hal/fifo/fifo_gv11b.h"
+#include "hal/fifo/preempt_gv11b.h"
+#include "hal/fifo/engines_gp10b.h"
+#include "hal/fifo/engines_gv11b.h"
+#include "hal/fifo/pbdma_gm20b.h"
+#include "hal/fifo/pbdma_gp10b.h"
+#include "hal/fifo/pbdma_gv11b.h"
+#include "hal/fifo/ramin_gk20a.h"
+#include "hal/fifo/ramin_gm20b.h"
+#include "hal/fifo/ramin_gv11b.h"
+#include "hal/fifo/runlist_ram_gv11b.h"
+#include "hal/fifo/runlist_fifo_gv11b.h"
+#include "hal/fifo/runlist_fifo_ga10b.h"
+#include "hal/fifo/tsg_gv11b.h"
+#include "hal/fifo/userd_gk20a.h"
+#include "hal/fifo/userd_gv11b.h"
+#include "hal/fifo/userd_ga10b.h"
+#include "hal/fifo/usermode_gv11b.h"
+#include "hal/fifo/usermode_tu104.h"
+#include "hal/fifo/usermode_ga10b.h"
+#include "hal/fifo/fifo_intr_gv11b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h"
+#include "hal/gr/gr/gr_ga10b.h"
+#include "hal/gr/init/gr_init_ga10b.h"
+#include "hal/gr/intr/gr_intr_ga10b.h"
+#include "hal/init/hal_ga10b_litter.h"
+#include "hal/netlist/netlist_gv11b.h"
+#include "hal/netlist/netlist_ga10b.h"
+#include "hal/ptimer/ptimer_gv11b.h"
+#include "hal/ptimer/ptimer_ga10b.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
+#include "hal/regops/regops_ga10b.h"
+#include "hal/regops/allowlist_ga10b.h"
+#endif
+#include "hal/perf/perf_ga10b.h"
+#include "hal/therm/therm_gm20b.h"
+#include "hal/therm/therm_gp10b.h"
+#include "hal/therm/therm_gv11b.h"
+#include "hal/gr/fecs_trace/fecs_trace_gv11b.h"
+#ifdef CONFIG_NVGPU_GRAPHICS
+#include "hal/gr/zbc/zbc_gv11b.h"
+#endif
+#include "hal/gr/hwpm_map/hwpm_map_gv100.h"
+#include "hal/gr/init/gr_init_gv11b.h"
+#include "hal/ltc/ltc_gm20b.h"
+#include "hal/ltc/ltc_gp10b.h"
+#include "hal/ltc/ltc_gv11b.h"
+#include "hal/fb/fb_gm20b.h"
+#include "hal/fb/fb_gp10b.h"
+#include "hal/fb/fb_gv11b.h"
+#include "hal/fb/fb_mmu_fault_gv11b.h"
+#include "hal/fb/intr/fb_intr_gv11b.h"
+#include "hal/gr/init/gr_init_gm20b.h"
+#include "hal/gr/init/gr_init_gp10b.h"
+#include "hal/gr/init/gr_init_gv11b.h"
+#include "hal/gr/init/gr_init_tu104.h"
+#include "hal/gr/intr/gr_intr_gm20b.h"
+#include "hal/gr/intr/gr_intr_gv11b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h"
+#include "hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h"
+#include "hal/gr/gr/gr_gk20a.h"
+#include "hal/gr/gr/gr_gm20b.h"
+#include "hal/gr/gr/gr_gp10b.h"
+#include "hal/gr/gr/gr_gv11b.h"
+#include "hal/gr/gr/gr_gv100.h"
+#include "hal/perf/perf_gv11b.h"
+#include "hal/sync/syncpt_cmdbuf_gv11b.h"
+#include "hal/sync/sema_cmdbuf_gv11b.h"
+#include "hal/init/hal_gv11b.h"
+#include "hal/init/hal_gv11b_litter.h"
+#include "hal/fifo/channel_gv11b.h"
+
+#include "hal/vgpu/fifo/fifo_gv11b_vgpu.h"
+#include "hal/vgpu/sync/syncpt_cmdbuf_gv11b_vgpu.h"
+
+#include "common/clk_arb/clk_arb_gp10b.h"
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/errata.h>
+#include <nvgpu/gr/gr.h>
+#include <nvgpu/gr/gr_intr.h>
+#include <nvgpu/vgpu/vgpu.h>
+#include <nvgpu/error_notifier.h>
+#include <nvgpu/acr.h>
+#include <nvgpu/ce.h>
+#include <nvgpu/ce_app.h>
+#include <nvgpu/pmu.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/nvhost.h>
+#ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/pmu_pstate.h>
+#endif
+#include <nvgpu/fbp.h>
+#include <nvgpu/therm.h>
+#include <nvgpu/clk_arb.h>
+#include <nvgpu/grmgr.h>
+#include <nvgpu/perfbuf.h>
+
+#include "common/vgpu/init/init_vgpu.h"
+#include "common/vgpu/fb/fb_vgpu.h"
+#include "common/vgpu/top/top_vgpu.h"
+#include "common/vgpu/fifo/fifo_vgpu.h"
+#include "common/vgpu/fifo/channel_vgpu.h"
+#include "common/vgpu/fifo/tsg_vgpu.h"
+#include "common/vgpu/fifo/preempt_vgpu.h"
+#include "common/vgpu/fifo/runlist_vgpu.h"
+#include "common/vgpu/fifo/ramfc_vgpu.h"
+#include "common/vgpu/fifo/userd_vgpu.h"
+#include "common/vgpu/gr/gr_vgpu.h"
+#include "common/vgpu/gr/ctx_vgpu.h"
+#include "common/vgpu/gr/subctx_vgpu.h"
+#include "common/vgpu/ltc/ltc_vgpu.h"
+#include "common/vgpu/mm/mm_vgpu.h"
+#include "common/vgpu/cbc/cbc_vgpu.h"
+#include "common/vgpu/debugger_vgpu.h"
+#include "common/vgpu/pm_reservation_vgpu.h"
+#include "common/vgpu/perf/perf_vgpu.h"
+#include "common/vgpu/gr/fecs_trace_vgpu.h"
+#include "common/vgpu/perf/cyclestats_snapshot_vgpu.h"
+#include "common/vgpu/ptimer/ptimer_vgpu.h"
+#include "common/vgpu/profiler/profiler_vgpu.h"
+#include "vgpu_hal_ga10b.h"
+
+#include <nvgpu/debugger.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/channel.h>
+
+#include <nvgpu/vgpu/ce_vgpu.h>
+#include <nvgpu/vgpu/vm_vgpu.h>
+#ifdef CONFIG_NVGPU_GRAPHICS
+#include <nvgpu/gr/zbc.h>
+#endif
+#include <nvgpu/gr/setup.h>
+
+#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
+
+static int vgpu_ga10b_init_gpu_characteristics(struct gk20a *g)
+{
+	int err;
+
+	nvgpu_log_fn(g, " ");
+
+	err = vgpu_init_gpu_characteristics(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init GPU characteristics");
+		return err;
+	}
+
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
+	nvgpu_set_enabled(g, NVGPU_USE_COHERENT_SYSMEM, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true);
+	if (nvgpu_has_syncpoints(g)) {
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
+	}
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
+#ifdef CONFIG_NVGPU_GRAPHICS
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true);
+#endif
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true);
+#ifdef CONFIG_NVGPU_FECS_TRACE
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true);
+#endif
+#ifdef CONFIG_NVGPU_PROFILER
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PROFILER_V2_DEVICE, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PROFILER_V2_CONTEXT, false);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SMPC_GLOBAL_MODE, true);
+#endif
+
+	return 0;
+}
+
+static const struct gops_acr vgpu_ga10b_ops_acr = {
+	.acr_init = nvgpu_acr_init,
+	.acr_construct_execute = nvgpu_acr_construct_execute,
+};
+
+#ifdef CONFIG_NVGPU_DGPU
+static const struct gops_bios vgpu_ga10b_ops_bios = {
+	.bios_sw_init = nvgpu_bios_sw_init,
+};
+#endif
+
+static const struct gops_ltc_intr vgpu_ga10b_ops_ltc_intr = {
+	.configure = NULL,
+	.isr = NULL,
+	.en_illegal_compstat = NULL,
+};
+
+static const struct gops_ltc vgpu_ga10b_ops_ltc = {
+	.init_ltc_support = nvgpu_init_ltc_support,
+	.ltc_remove_support = nvgpu_ltc_remove_support,
+	.determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
+	.init_fs_state = vgpu_ltc_init_fs_state,
+	.flush = NULL,
+	.set_enabled = NULL,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.set_zbc_s_entry = NULL,
+	.set_zbc_color_entry = NULL,
+	.set_zbc_depth_entry = NULL,
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
+	.is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
+	.is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
+	.split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
+	.split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
+	.set_l2_max_ways_evict_last = vgpu_ltc_set_max_ways_evict_last,
+	.get_l2_max_ways_evict_last = vgpu_ltc_get_max_ways_evict_last,
+#endif /* CONFIG_NVGPU_DEBUGGER */
+};
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+static const struct gops_cbc vgpu_ga10b_ops_cbc = {
+	.cbc_init_support = nvgpu_cbc_init_support,
+	.cbc_remove_support = nvgpu_cbc_remove_support,
+	.init = NULL,
+	.ctrl = NULL,
+	.alloc_comptags = vgpu_cbc_alloc_comptags,
+};
+#endif
+
+static const struct gops_ce vgpu_ga10b_ops_ce = {
+	.ce_init_support = nvgpu_ce_init_support,
+#ifdef CONFIG_NVGPU_DGPU
+	.ce_app_init_support = NULL,
+	.ce_app_suspend = NULL,
+	.ce_app_destroy = NULL,
+#endif
+	.isr_stall = NULL,
+	.isr_nonstall = NULL,
+	.get_num_pce = vgpu_ce_get_num_pce,
+};
+
+static const struct gops_gr_ctxsw_prog vgpu_ga10b_ops_gr_ctxsw_prog = {
+	.hw_get_fecs_header_size = ga10b_ctxsw_prog_hw_get_fecs_header_size,
+	.get_patch_count = gm20b_ctxsw_prog_get_patch_count,
+	.set_patch_count = gm20b_ctxsw_prog_set_patch_count,
+	.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
+	.init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data,
+	.set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
+	.set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode,
+	.set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr,
+	.disable_verif_features = gm20b_ctxsw_prog_disable_verif_features,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr,
+	.set_zcull = gm20b_ctxsw_prog_set_zcull,
+	.set_zcull_mode_no_ctxsw = gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw,
+	.is_zcull_mode_separate_buffer = gm20b_ctxsw_prog_is_zcull_mode_separate_buffer,
+	.set_graphics_preemption_mode_gfxp = gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp,
+	.set_pmu_options_boost_clock_frequencies = NULL,
+	.set_full_preemption_ptr = gv11b_ctxsw_prog_set_full_preemption_ptr,
+	.set_full_preemption_ptr_veid0 = gv11b_ctxsw_prog_set_full_preemption_ptr_veid0,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+#ifdef CONFIG_NVGPU_CILP
+	.set_compute_preemption_mode_cilp = gp10b_ctxsw_prog_set_compute_preemption_mode_cilp,
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.hw_get_gpccs_header_size = ga10b_ctxsw_prog_hw_get_gpccs_header_size,
+	.hw_get_extended_buffer_segments_size_in_bytes = gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes,
+	.hw_extended_marker_size_in_bytes = gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes,
+	.hw_get_perf_counter_control_register_stride = gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride,
+	.get_main_image_ctx_id = gm20b_ctxsw_prog_get_main_image_ctx_id,
+	.set_pm_ptr = gv11b_ctxsw_prog_set_pm_ptr,
+	.set_pm_mode = gm20b_ctxsw_prog_set_pm_mode,
+	.set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode,
+	.hw_get_pm_mode_no_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw,
+	.hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw,
+	.hw_get_pm_mode_stream_out_ctxsw = gv11b_ctxsw_prog_hw_get_pm_mode_stream_out_ctxsw,
+	.set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled,
+	.set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling,
+	.check_main_image_header_magic = ga10b_ctxsw_prog_check_main_image_header_magic,
+	.check_local_header_magic = ga10b_ctxsw_prog_check_local_header_magic,
+	.get_num_gpcs = gm20b_ctxsw_prog_get_num_gpcs,
+	.get_num_tpcs = gm20b_ctxsw_prog_get_num_tpcs,
+	.get_extended_buffer_size_offset = gm20b_ctxsw_prog_get_extended_buffer_size_offset,
+	.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
+	.get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#ifdef CONFIG_NVGPU_FECS_TRACE
+	.hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,
+	.hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag,
+	.hw_record_ts_timestamp = gm20b_ctxsw_prog_hw_record_ts_timestamp,
+	.hw_get_ts_record_size_in_bytes = gm20b_ctxsw_prog_hw_get_ts_record_size_in_bytes,
+	.is_ts_valid_record = gm20b_ctxsw_prog_is_ts_valid_record,
+	.get_ts_buffer_aperture_mask = gm20b_ctxsw_prog_get_ts_buffer_aperture_mask,
+	.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
+	.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
+#endif
+	.hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride,
+	.set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr,
+	.set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header,
+#ifdef CONFIG_DEBUG_FS
+	.dump_ctxsw_stats = NULL,
+#endif
+};
+
+static const struct gops_gr_config vgpu_ga10b_ops_gr_config = {
+	.get_gpc_mask = vgpu_gr_get_gpc_mask,
+	.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
+	.init_sm_id_table = vgpu_gr_init_sm_id_table,
+};
+
+static const struct gops_gr_setup vgpu_ga10b_ops_gr_setup = {
+	.alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
+	.free_gr_ctx = vgpu_gr_free_gr_ctx,
+	.free_subctx = vgpu_gr_setup_free_subctx,
+	.set_preemption_mode = vgpu_gr_set_preemption_mode,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
+#endif
+};
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+static const struct gops_gr_zbc vgpu_ga10b_ops_gr_zbc = {
+	.add_color = NULL,
+	.add_depth = NULL,
+	.set_table = vgpu_gr_add_zbc,
+	.query_table = vgpu_gr_query_zbc,
+	.add_stencil = gv11b_gr_zbc_add_stencil,
+	.get_gpcs_swdx_dss_zbc_c_format_reg = NULL,
+	.get_gpcs_swdx_dss_zbc_z_format_reg = NULL,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+static const struct gops_gr_zcull vgpu_ga10b_ops_gr_zcull = {
+	.get_zcull_info = vgpu_gr_get_zcull_info,
+	.program_zcull_mapping = NULL,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_gr_hwpm_map vgpu_ga10b_ops_gr_hwpm_map = {
+	.align_regs_perf_pma = gv100_gr_hwpm_map_align_regs_perf_pma,
+};
+#endif
+
+static const struct gops_gr_falcon vgpu_ga10b_ops_gr_falcon = {
+	.init_ctx_state = vgpu_gr_init_ctx_state,
+	.load_ctxsw_ucode = NULL,
+};
+
+#ifdef CONFIG_NVGPU_FECS_TRACE
+static const struct gops_gr_fecs_trace vgpu_ga10b_ops_gr_fecs_trace = {
+	.alloc_user_buffer = vgpu_alloc_user_buffer,
+	.free_user_buffer = vgpu_free_user_buffer,
+	.get_mmap_user_buffer_info = vgpu_get_mmap_user_buffer_info,
+	.init = vgpu_fecs_trace_init,
+	.deinit = vgpu_fecs_trace_deinit,
+	.enable = vgpu_fecs_trace_enable,
+	.disable = vgpu_fecs_trace_disable,
+	.is_enabled = vgpu_fecs_trace_is_enabled,
+	.reset = NULL,
+	.flush = NULL,
+	.poll = vgpu_fecs_trace_poll,
+	.bind_channel = NULL,
+	.unbind_channel = NULL,
+	.max_entries = vgpu_fecs_trace_max_entries,
+	.set_filter = vgpu_fecs_trace_set_filter,
+	.get_buffer_full_mailbox_val = gv11b_fecs_trace_get_buffer_full_mailbox_val,
+};
+#endif
+
+static const struct gops_gr_init vgpu_ga10b_ops_gr_init = {
+	.get_no_of_sm = nvgpu_gr_get_no_of_sm,
+	.get_nonpes_aware_tpc = gv11b_gr_init_get_nonpes_aware_tpc,
+	.get_rtv_cb_size = tu104_gr_init_get_rtv_cb_size,
+	.get_bundle_cb_default_size = gv11b_gr_init_get_bundle_cb_default_size,
+	.get_min_gpm_fifo_depth = ga10b_gr_init_get_min_gpm_fifo_depth,
+	.get_bundle_cb_token_limit = ga10b_gr_init_get_bundle_cb_token_limit,
+	.get_attrib_cb_default_size = ga10b_gr_init_get_attrib_cb_default_size,
+	.get_alpha_cb_default_size = gv11b_gr_init_get_alpha_cb_default_size,
+	.get_attrib_cb_size = gv11b_gr_init_get_attrib_cb_size,
+	.get_alpha_cb_size = gv11b_gr_init_get_alpha_cb_size,
+	.get_global_attr_cb_size = gv11b_gr_init_get_global_attr_cb_size,
+	.get_global_ctx_cb_buffer_size = gm20b_gr_init_get_global_ctx_cb_buffer_size,
+	.get_global_ctx_pagepool_buffer_size = gm20b_gr_init_get_global_ctx_pagepool_buffer_size,
+	.commit_global_bundle_cb = ga10b_gr_init_commit_global_bundle_cb,
+	.pagepool_default_size = gp10b_gr_init_pagepool_default_size,
+	.commit_global_pagepool = gp10b_gr_init_commit_global_pagepool,
+	.commit_global_attrib_cb = gv11b_gr_init_commit_global_attrib_cb,
+	.commit_global_cb_manager = gp10b_gr_init_commit_global_cb_manager,
+	.get_ctx_attrib_cb_size = gp10b_gr_init_get_ctx_attrib_cb_size,
+	.commit_cbes_reserve = gv11b_gr_init_commit_cbes_reserve,
+	.detect_sm_arch = vgpu_gr_detect_sm_arch,
+	.get_supported__preemption_modes = gp10b_gr_init_get_supported_preemption_modes,
+	.get_default_preemption_modes = gp10b_gr_init_get_default_preemption_modes,
+#ifdef CONFIG_NVGPU_GRAPHICS
+	.get_attrib_cb_gfxp_default_size = ga10b_gr_init_get_attrib_cb_gfxp_default_size,
+	.get_attrib_cb_gfxp_size = ga10b_gr_init_get_attrib_cb_gfxp_size,
+	.get_gfxp_rtv_cb_size = tu104_gr_init_get_gfxp_rtv_cb_size,
+	.get_ctx_spill_size = ga10b_gr_init_get_ctx_spill_size,
+	.get_ctx_pagepool_size = gp10b_gr_init_get_ctx_pagepool_size,
+	.get_ctx_betacb_size = ga10b_gr_init_get_ctx_betacb_size,
+	.commit_ctxsw_spill = gv11b_gr_init_commit_ctxsw_spill,
+	.gfxp_wfi_timeout = gv11b_gr_init_commit_gfxp_wfi_timeout,
+#endif /* CONFIG_NVGPU_GRAPHICS */
+};
+
+static const struct gops_gr_intr vgpu_ga10b_ops_gr_intr = {
+	.handle_gcc_exception = NULL,
+	.handle_gpc_gpcmmu_exception = NULL,
+	.handle_gpc_gpccs_exception = NULL,
+	.get_tpc_exception = ga10b_gr_intr_get_tpc_exception,
+	.handle_tpc_mpc_exception = NULL,
+	.handle_tex_exception = NULL,
+	.flush_channel_tlb = nvgpu_gr_intr_flush_channel_tlb,
+	.get_sm_no_lock_down_hww_global_esr_mask = gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.tpc_enabled_exceptions = vgpu_gr_gk20a_tpc_enabled_exceptions,
+#endif
+};
+
+static const struct gops_gr vgpu_ga10b_ops_gr = {
+	.gr_init_support = nvgpu_gr_init_support,
+	.gr_suspend = nvgpu_gr_suspend,
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.set_alpha_circular_buffer_size = NULL,
+	.set_circular_buffer_size = NULL,
+	.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
+	.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
+#ifdef CONFIG_NVGPU_TEGRA_FUSE
+	.set_gpc_tpc_mask = NULL,
+#endif
+	.dump_gr_regs = NULL,
+	.update_pc_sampling = vgpu_gr_update_pc_sampling,
+	.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
+	.init_cyclestats = vgpu_gr_init_cyclestats,
+	.set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
+	.bpt_reg_info = NULL,
+	.update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
+	.update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
+	.clear_sm_error_state = vgpu_gr_clear_sm_error_state,
+	.suspend_contexts = vgpu_gr_suspend_contexts,
+	.resume_contexts = vgpu_gr_resume_contexts,
+	.trigger_suspend = NULL,
+	.wait_for_pause = gr_gk20a_wait_for_pause,
+	.resume_from_pause = NULL,
+	.clear_sm_errors = NULL,
+	.sm_debugger_attached = NULL,
+	.suspend_single_sm = NULL,
+	.suspend_all_sms = NULL,
+	.resume_single_sm = NULL,
+	.resume_all_sms = NULL,
+	.lock_down_sm = NULL,
+	.wait_for_sm_lock_down = NULL,
+	.init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf,
+	.get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs,
+	.set_boosted_ctx = NULL,
+	.pre_process_sm_exception = NULL,
+	.set_bes_crop_debug3 = NULL,
+	.set_bes_crop_debug4 = NULL,
+	.is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
+	.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
+	.get_egpc_base = gv11b_gr_get_egpc_base,
+	.get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
+	.is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
+	.decode_egpc_addr = gv11b_gr_decode_egpc_addr,
+	.decode_priv_addr = gr_ga10b_decode_priv_addr,
+	.create_priv_addr_table = gr_ga10b_create_priv_addr_table,
+	.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
+	.get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment,
+	.set_debug_mode = gm20b_gr_set_debug_mode,
+	.set_mmu_debug_mode = vgpu_gr_set_mmu_debug_mode,
+#endif
+};
+
+static const struct gops_class vgpu_ga10b_ops_gpu_class = {
+	.is_valid = ga10b_class_is_valid,
+	.is_valid_compute = ga10b_class_is_valid_compute,
+	.is_valid_gfx = ga10b_class_is_valid_gfx,
+};
+
+static const struct gops_fb_intr vgpu_ga10b_ops_fb_intr = {
+	.enable = NULL,
+	.disable = NULL,
+	.isr = NULL,
+	.is_mmu_fault_pending = NULL,
+};
+
+static const struct gops_fb vgpu_ga10b_ops_fb = {
+	.init_hw = NULL,
+	.init_fs_state = NULL,
+	.set_mmu_page_size = NULL,
+#ifdef CONFIG_NVGPU_COMPRESSION
+	.set_use_full_comp_tag_line = NULL,
+	.compression_page_size = gp10b_fb_compression_page_size,
+	.compressible_page_size = gp10b_fb_compressible_page_size,
+	.compression_align_mask = gm20b_fb_compression_align_mask,
+#endif
+	.vpr_info_fetch = NULL,
+	.dump_vpr_info = NULL,
+	.dump_wpr_info = NULL,
+	.read_wpr_info = NULL,
+#ifdef CONFIG_NVGPU_DEBUGGER
+	.is_debug_mode_enabled = NULL,
+	.set_debug_mode = vgpu_mm_mmu_set_debug_mode,
+	.set_mmu_debug_mode = vgpu_fb_set_mmu_debug_mode,
+#endif
+	.tlb_invalidate = vgpu_mm_tlb_invalidate,
+	.write_mmu_fault_buffer_lo_hi = gv11b_fb_write_mmu_fault_buffer_lo_hi,
+	.write_mmu_fault_buffer_get = fb_gv11b_write_mmu_fault_buffer_get,
+	.write_mmu_fault_buffer_size = gv11b_fb_write_mmu_fault_buffer_size,
+	.write_mmu_fault_status = gv11b_fb_write_mmu_fault_status,
+	.read_mmu_fault_buffer_get = gv11b_fb_read_mmu_fault_buffer_get,
+	.read_mmu_fault_buffer_put = gv11b_fb_read_mmu_fault_buffer_put,
+	.read_mmu_fault_buffer_size = gv11b_fb_read_mmu_fault_buffer_size,
+	.read_mmu_fault_addr_lo_hi = gv11b_fb_read_mmu_fault_addr_lo_hi,
+	.read_mmu_fault_inst_lo_hi = gv11b_fb_read_mmu_fault_inst_lo_hi,
+	.read_mmu_fault_info = gv11b_fb_read_mmu_fault_info,
+	.read_mmu_fault_status = gv11b_fb_read_mmu_fault_status,
+};
+
+static const struct gops_cg vgpu_ga10b_ops_cg = {
+	.slcg_bus_load_gating_prod = NULL,
+	.slcg_ce2_load_gating_prod = NULL,
+	.slcg_chiplet_load_gating_prod = NULL,
+	.slcg_fb_load_gating_prod = NULL,
+	.slcg_fifo_load_gating_prod = NULL,
+	.slcg_gr_load_gating_prod = NULL,
+	.slcg_ltc_load_gating_prod = NULL,
+	.slcg_perf_load_gating_prod = NULL,
+	.slcg_priring_load_gating_prod = NULL,
+	.slcg_pmu_load_gating_prod = NULL,
+	.slcg_therm_load_gating_prod = NULL,
+	.slcg_xbar_load_gating_prod = NULL,
+	.blcg_bus_load_gating_prod = NULL,
+	.blcg_ce_load_gating_prod = NULL,
+	.blcg_fb_load_gating_prod = NULL,
+	.blcg_fifo_load_gating_prod = NULL,
+	.blcg_gr_load_gating_prod = NULL,
+	.blcg_ltc_load_gating_prod = NULL,
+	.blcg_pmu_load_gating_prod = NULL,
+	.blcg_xbar_load_gating_prod = NULL,
+};
+
+static const struct gops_fifo vgpu_ga10b_ops_fifo = {
+	.fifo_init_support = nvgpu_fifo_init_support,
+	.fifo_suspend = nvgpu_fifo_suspend,
+	.init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw,
+	.preempt_channel = vgpu_fifo_preempt_channel,
+	.preempt_tsg = vgpu_fifo_preempt_tsg,
+	.is_preempt_pending = gv11b_fifo_is_preempt_pending,
+	.reset_enable_hw = NULL,
+#ifdef CONFIG_NVGPU_RECOVERY
+	.recover = NULL,
+#endif
+	.setup_sw = vgpu_fifo_setup_sw,
+	.cleanup_sw = vgpu_fifo_cleanup_sw,
+	.set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask,
+	.intr_0_enable = NULL,
+	.intr_1_enable = NULL,
+	.intr_0_isr = NULL,
+	.intr_1_isr = NULL,
+	.handle_sched_error = NULL,
+	.handle_ctxsw_timeout = NULL,
+	.ctxsw_timeout_enable = NULL,
+	.trigger_mmu_fault = NULL,
+	.get_mmu_fault_info = NULL,
+	.get_mmu_fault_desc = NULL,
+	.get_mmu_fault_client_desc = NULL,
+	.get_mmu_fault_gpc_desc = NULL,
+	.mmu_fault_id_to_pbdma_id = NULL,
+};
+
+static const struct gops_engine vgpu_ga10b_ops_engine = {
+	.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
+	.init_ce_info = gp10b_engine_init_ce_info,
+};
+
+static const struct gops_pbdma vgpu_ga10b_ops_pbdma = {
+	.setup_sw = NULL,
+	.cleanup_sw = NULL,
+	.setup_hw = NULL,
+	.intr_enable = NULL,
+	.acquire_val = gm20b_pbdma_acquire_val,
+	.get_signature = gp10b_pbdma_get_signature,
+	.dump_status = NULL,
+	.handle_intr_0 = NULL,
+	.handle_intr_1 = gv11b_pbdma_handle_intr_1,
+	.handle_intr = gm20b_pbdma_handle_intr,
+	.read_data = NULL,
+	.reset_header = NULL,
+	.device_fatal_0_intr_descs = NULL,
+	.channel_fatal_0_intr_descs = NULL,
+	.restartable_0_intr_descs = NULL,
+	.format_gpfifo_entry = gm20b_pbdma_format_gpfifo_entry,
+};
+
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+static const struct gops_sync_syncpt vgpu_ga10b_ops_sync_syncpt = {
+	.get_sync_ro_map = vgpu_gv11b_syncpt_get_sync_ro_map,
+	.alloc_buf = vgpu_gv11b_syncpt_alloc_buf,
+	.free_buf = vgpu_gv11b_syncpt_free_buf,
+#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
+	.add_wait_cmd = gv11b_syncpt_add_wait_cmd,
+	.get_wait_cmd_size = gv11b_syncpt_get_wait_cmd_size,
+	.add_incr_cmd = gv11b_syncpt_add_incr_cmd,
+	.get_incr_cmd_size = gv11b_syncpt_get_incr_cmd_size,
+	.get_incr_per_release = gv11b_syncpt_get_incr_per_release,
+#endif
+};
+#endif
+
+#if defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT) && \
+	defined(CONFIG_NVGPU_SW_SEMAPHORE)
+static const struct gops_sync_sema vgpu_ga10b_ops_sync_sema = {
+	.add_wait_cmd = gv11b_sema_add_wait_cmd,
+	.get_wait_cmd_size = gv11b_sema_get_wait_cmd_size,
+	.add_incr_cmd = gv11b_sema_add_incr_cmd,
+	.get_incr_cmd_size = gv11b_sema_get_incr_cmd_size,
+};
+#endif
+
+static const struct gops_sync vgpu_ga10b_ops_sync = {
+};
+
+static const struct gops_engine_status vgpu_ga10b_ops_engine_status = {
+	.read_engine_status_info = NULL,
+	.dump_engine_status = NULL,
+};
+
+static const struct gops_pbdma_status vgpu_ga10b_ops_pbdma_status = {
+	.read_pbdma_status_info = NULL,
+};
+
+static const struct gops_ramfc vgpu_ga10b_ops_ramfc = {
+	.setup = vgpu_ramfc_setup,
+	.capture_ram_dump = NULL,
+	.commit_userd = NULL,
+	.get_syncpt = NULL,
+	.set_syncpt = NULL,
+};
+
+static const struct gops_ramin vgpu_ga10b_ops_ramin = {
+	.set_gr_ptr = NULL,
+	.set_big_page_size = gm20b_ramin_set_big_page_size,
+	.init_pdb = gv11b_ramin_init_pdb,
+	.init_subctx_pdb = gv11b_ramin_init_subctx_pdb,
+	.set_adr_limit = NULL,
+	.base_shift = gk20a_ramin_base_shift,
+	.alloc_size = gk20a_ramin_alloc_size,
+	.set_eng_method_buffer = NULL,
+};
+
+static const struct gops_runlist vgpu_ga10b_ops_runlist = {
+	.reschedule = NULL,
+	.update = vgpu_runlist_update,
+	.reload = vgpu_runlist_reload,
+	.count_max = ga10b_runlist_count_max,
+	.entry_size = vgpu_runlist_entry_size,
+	.length_max = vgpu_runlist_length_max,
+	.get_tsg_entry = gv11b_runlist_get_tsg_entry,
+	.get_ch_entry = gv11b_runlist_get_ch_entry,
+	.hw_submit = NULL,
+	.wait_pending = NULL,
+	.init_enginfo = nvgpu_next_runlist_init_enginfo,
+};
+
+static const struct gops_userd vgpu_ga10b_ops_userd = {
+#ifdef CONFIG_NVGPU_USERD
+	.setup_sw = vgpu_userd_setup_sw,
+	.cleanup_sw = vgpu_userd_cleanup_sw,
+	.init_mem = ga10b_userd_init_mem,
+	.gp_get = gv11b_userd_gp_get,
+	.gp_put = gv11b_userd_gp_put,
+	.pb_get = gv11b_userd_pb_get,
+#endif
+	.entry_size = gk20a_userd_entry_size,
+};
+
+static const struct gops_channel vgpu_ga10b_ops_channel = {
+	.alloc_inst = vgpu_channel_alloc_inst,
+	.free_inst = vgpu_channel_free_inst,
+	.bind = vgpu_channel_bind,
+	.unbind = vgpu_channel_unbind,
+	.enable = vgpu_channel_enable,
+	.disable = vgpu_channel_disable,
+	.count = vgpu_channel_count,
+	.abort_clean_up = nvgpu_channel_abort_clean_up,
+	.suspend_all_serviceable_ch = nvgpu_channel_suspend_all_serviceable_ch,
+	.resume_all_serviceable_ch = nvgpu_channel_resume_all_serviceable_ch,
+	.set_error_notifier = nvgpu_set_err_notifier,
+};
+
+static const struct gops_tsg vgpu_ga10b_ops_tsg = {
+	.open = vgpu_tsg_open,
+	.release = vgpu_tsg_release,
+	.init_eng_method_buffers = NULL,
+	.deinit_eng_method_buffers = NULL,
+	.enable = gv11b_tsg_enable,
+	.disable = nvgpu_tsg_disable,
+	.bind_channel = vgpu_tsg_bind_channel,
+	.bind_channel_eng_method_buffers = NULL,
+	.unbind_channel = vgpu_tsg_unbind_channel,
+	.unbind_channel_check_hw_state = NULL,
+	.unbind_channel_check_ctx_reload = NULL,
+	.unbind_channel_check_eng_faulted = NULL,
+#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
+	.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
+#endif
+	.force_reset = vgpu_tsg_force_reset_ch,
+	.post_event_id = nvgpu_tsg_post_event_id,
+	.set_timeslice = vgpu_tsg_set_timeslice,
+	.default_timeslice_us = vgpu_tsg_default_timeslice_us,
+	.set_interleave = vgpu_tsg_set_interleave,
+};
+
+static const struct gops_usermode vgpu_ga10b_ops_usermode = {
+	.setup_hw = NULL,
+	.base = tu104_usermode_base,
+	.bus_base = tu104_usermode_bus_base,
+	.ring_doorbell = tu104_usermode_ring_doorbell,
+	.doorbell_token = tu104_usermode_doorbell_token,
+};
+
+static const struct gops_netlist vgpu_ga10b_ops_netlist = {
+	.get_netlist_name = ga10b_netlist_get_name,
+	.is_fw_defined = ga10b_netlist_is_firmware_defined,
+};
+
+static const struct gops_mm_mmu_fault vgpu_ga10b_ops_mm_mmu_fault = {
+	.info_mem_destroy = gv11b_mm_mmu_fault_info_mem_destroy,
+};
+
+static const struct gops_mm_cache vgpu_ga10b_ops_mm_cache = {
+	.fb_flush = vgpu_mm_fb_flush,
+	.l2_invalidate = vgpu_mm_l2_invalidate,
+	.l2_flush = vgpu_mm_l2_flush,
+#ifdef CONFIG_NVGPU_COMPRESSION
+	.cbc_clean = NULL,
+#endif
+};
+
+static const struct gops_mm_gmmu vgpu_ga10b_ops_mm_gmmu = {
+	.map = vgpu_locked_gmmu_map,
+	.unmap = vgpu_locked_gmmu_unmap,
+	.get_big_page_sizes = gm20b_mm_get_big_page_sizes,
+	.get_default_big_page_size = nvgpu_gmmu_default_big_page_size,
+	.gpu_phys_addr = gv11b_gpu_phys_addr,
+	.get_iommu_bit = ga10b_mm_get_iommu_bit,
+	.get_mmu_levels = ga10b_mm_get_mmu_levels,
+	.get_max_page_table_levels = ga10b_get_max_page_table_levels,
+};
+
+static const struct gops_mm vgpu_ga10b_ops_mm = {
+	.init_mm_support = nvgpu_init_mm_support,
+	.pd_cache_init = nvgpu_pd_cache_init,
+	.mm_suspend = nvgpu_mm_suspend,
+	.vm_bind_channel = vgpu_vm_bind_channel,
+	.setup_hw = NULL,
+	.is_bar1_supported = gv11b_mm_is_bar1_supported,
+	.init_inst_block = gv11b_mm_init_inst_block,
+	.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
+	.init_bar2_vm = gp10b_mm_init_bar2_vm,
+	.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
+	.vm_as_alloc_share = vgpu_vm_as_alloc_share,
+	.vm_as_free_share = vgpu_vm_as_free_share,
+	.get_default_va_sizes = gp10b_mm_get_default_va_sizes,
+};
+
+static const struct gops_therm vgpu_ga10b_ops_therm = {
+	.init_therm_support = nvgpu_init_therm_support,
+	.init_therm_setup_hw = NULL,
+	.init_elcg_mode = NULL,
+	.init_blcg_mode = NULL,
+	.elcg_init_idle_filters = NULL,
+};
+
+#ifdef CONFIG_NVGPU_LS_PMU
+static const struct gops_pmu vgpu_ga10b_ops_pmu = {
+	.pmu_early_init = NULL,
+	.pmu_rtos_init = NULL,
+	.pmu_pstate_sw_setup = NULL,
+	.pmu_pstate_pmu_setup = NULL,
+	.pmu_destroy = NULL,
+	.pmu_setup_elpg = NULL,
+	.pmu_get_queue_head = NULL,
+	.pmu_get_queue_head_size = NULL,
+	.pmu_get_queue_tail = NULL,
+	.pmu_get_queue_tail_size = NULL,
+	.pmu_reset = NULL,
+	.pmu_queue_head = NULL,
+	.pmu_queue_tail = NULL,
+	.pmu_msgq_tail = NULL,
+	.pmu_mutex_size = NULL,
+	.pmu_mutex_acquire = NULL,
+	.pmu_mutex_release = NULL,
+	.pmu_is_interrupted = NULL,
+	.pmu_isr = NULL,
+	.pmu_init_perfmon_counter = NULL,
+	.pmu_pg_idle_counter_config = NULL,
+	.pmu_read_idle_counter = NULL,
+	.pmu_reset_idle_counter = NULL,
+	.pmu_read_idle_intr_status = NULL,
+	.pmu_clear_idle_intr_status = NULL,
+	.pmu_dump_elpg_stats = NULL,
+	.pmu_dump_falcon_stats = NULL,
+	.pmu_enable_irq = NULL,
+	.write_dmatrfbase = NULL,
+	.dump_secure_fuses = NULL,
+	.reset_engine = NULL,
+	.is_engine_in_reset = NULL,
+	.pmu_ns_bootstrap = NULL,
+	.is_pmu_supported = NULL,
+};
+#endif
+
+static const struct gops_clk_arb vgpu_ga10b_ops_clk_arb = {
+	.clk_arb_init_arbiter = nvgpu_clk_arb_init_arbiter,
+	.check_clk_arb_support = gp10b_check_clk_arb_support,
+	.get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
+	.get_arbiter_f_points = gp10b_get_arbiter_f_points,
+	.get_arbiter_clk_range = gp10b_get_arbiter_clk_range,
+	.get_arbiter_clk_default = gp10b_get_arbiter_clk_default,
+	.arbiter_clk_init = gp10b_init_clk_arbiter,
+	.clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
+	.clk_arb_cleanup = gp10b_clk_arb_cleanup,
+};
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_regops vgpu_ga10b_ops_regops = {
+	.exec_regops = vgpu_exec_regops,
+	.get_global_whitelist_ranges = ga10b_get_global_whitelist_ranges,
+	.get_global_whitelist_ranges_count = ga10b_get_global_whitelist_ranges_count,
+	.get_context_whitelist_ranges = ga10b_get_context_whitelist_ranges,
+	.get_context_whitelist_ranges_count = ga10b_get_context_whitelist_ranges_count,
+	.get_runcontrol_whitelist = ga10b_get_runcontrol_whitelist,
+	.get_runcontrol_whitelist_count = ga10b_get_runcontrol_whitelist_count,
+	.get_hwpm_router_register_stride = ga10b_get_hwpm_router_register_stride,
+	.get_hwpm_perfmon_register_stride = ga10b_get_hwpm_perfmon_register_stride,
+	.get_hwpm_pma_channel_register_stride = ga10b_get_hwpm_pma_channel_register_stride,
+	.get_hwpm_pma_trigger_register_stride = ga10b_get_hwpm_pma_trigger_register_stride,
+	.get_smpc_register_stride = ga10b_get_smpc_register_stride,
+	.get_cau_register_stride = ga10b_get_cau_register_stride,
+	.get_hwpm_perfmon_register_offset_allowlist =
+		ga10b_get_hwpm_perfmon_register_offset_allowlist,
+	.get_hwpm_router_register_offset_allowlist =
+		ga10b_get_hwpm_router_register_offset_allowlist,
+	.get_hwpm_pma_channel_register_offset_allowlist =
+		ga10b_get_hwpm_pma_channel_register_offset_allowlist,
+	.get_hwpm_pma_trigger_register_offset_allowlist =
+		ga10b_get_hwpm_pma_trigger_register_offset_allowlist,
+	.get_smpc_register_offset_allowlist = ga10b_get_smpc_register_offset_allowlist,
+	.get_cau_register_offset_allowlist = ga10b_get_cau_register_offset_allowlist,
+	.get_hwpm_perfmon_register_ranges = ga10b_get_hwpm_perfmon_register_ranges,
+	.get_hwpm_router_register_ranges = ga10b_get_hwpm_router_register_ranges,
+	.get_hwpm_pma_channel_register_ranges = ga10b_get_hwpm_pma_channel_register_ranges,
+	.get_hwpm_pma_trigger_register_ranges = ga10b_get_hwpm_pma_trigger_register_ranges,
+	.get_smpc_register_ranges = ga10b_get_smpc_register_ranges,
+	.get_cau_register_ranges = ga10b_get_cau_register_ranges,
+	.get_hwpm_perfmux_register_ranges = ga10b_get_hwpm_perfmux_register_ranges,
+};
+#endif
+
+static const struct gops_mc vgpu_ga10b_ops_mc = {
+	.get_chip_details = NULL,
+	.intr_mask = NULL,
+	.intr_enable = NULL,
+	.intr_stall_unit_config = NULL,
+	.intr_nonstall_unit_config = NULL,
+	.isr_stall = NULL,
+	.intr_stall = NULL,
+	.intr_stall_pause = NULL,
+	.intr_stall_resume = NULL,
+	.intr_nonstall = NULL,
+	.intr_nonstall_pause = NULL,
+	.intr_nonstall_resume = NULL,
+	.isr_nonstall = NULL,
+	.is_intr1_pending = NULL,
+	.is_intr_hub_pending = NULL,
+	.log_pending_intrs = NULL,
+	.is_enabled = NULL,
+	.fb_reset = NULL,
+	.is_mmu_fault_pending = NULL,
+	.enable_units = NULL,
+	.enable_dev = NULL,
+	.enable_devtype = NULL,
+};
+
+static const struct gops_debug vgpu_ga10b_ops_debug = {
+	.show_dump = NULL,
+};
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_debugger vgpu_ga10b_ops_debugger = {
+	.post_events = nvgpu_dbg_gpu_post_events,
+	.dbg_set_powergate = vgpu_dbg_set_powergate,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_perf vgpu_ga10b_ops_perf = {
+	.get_pmmsys_per_chiplet_offset = ga10b_perf_get_pmmsys_per_chiplet_offset,
+	.get_pmmgpc_per_chiplet_offset = ga10b_perf_get_pmmgpc_per_chiplet_offset,
+	.get_pmmfbp_per_chiplet_offset = ga10b_perf_get_pmmfbp_per_chiplet_offset,
+	.update_get_put = vgpu_perf_update_get_put,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+static const struct gops_perfbuf vgpu_ga10b_ops_perfbuf = {
+	.perfbuf_enable = vgpu_perfbuffer_enable,
+	.perfbuf_disable = vgpu_perfbuffer_disable,
+	.init_inst_block = vgpu_perfbuffer_init_inst_block,
+	.deinit_inst_block = vgpu_perfbuffer_deinit_inst_block,
+	.update_get_put = nvgpu_perfbuf_update_get_put,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_PROFILER
+static const struct gops_pm_reservation vgpu_ga10b_ops_pm_reservation = {
+	.acquire = vgpu_pm_reservation_acquire,
+	.release = vgpu_pm_reservation_release,
+	.release_all_per_vmid = NULL,
+};
+#endif
+
+#ifdef CONFIG_NVGPU_PROFILER
+static const struct gops_profiler vgpu_ga10b_ops_profiler = {
+	.bind_hwpm = vgpu_profiler_bind_hwpm,
+	.unbind_hwpm = vgpu_profiler_unbind_hwpm,
+	.bind_hwpm_streamout = vgpu_profiler_bind_hwpm_streamout,
+	.unbind_hwpm_streamout = vgpu_profiler_unbind_hwpm_streamout,
+	.bind_smpc = vgpu_profiler_bind_smpc,
+	.unbind_smpc = vgpu_profiler_unbind_smpc,
+};
+#endif
+
+static const struct gops_bus vgpu_ga10b_ops_bus = {
+	.init_hw = NULL,
+	.isr = NULL,
+	.bar1_bind = NULL,
+	.bar2_bind = NULL,
+#ifdef CONFIG_NVGPU_DGPU
+	.set_bar0_window = NULL,
+#endif
+};
+
+static const struct gops_ptimer vgpu_ga10b_ops_ptimer = {
+	.isr = NULL,
+	.read_ptimer = vgpu_read_ptimer,
+#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
+	.get_timestamps_zipper = vgpu_get_timestamps_zipper,
+#endif
+#ifdef CONFIG_NVGPU_PROFILER
+	.get_timer_reg_offsets = gv11b_ptimer_get_timer_reg_offsets,
+#endif
+};
+
+#if defined(CONFIG_NVGPU_CYCLESTATS)
+static const struct gops_css vgpu_ga10b_ops_css = {
+	.enable_snapshot = vgpu_css_enable_snapshot_buffer,
+	.disable_snapshot = vgpu_css_release_snapshot_buffer,
+	.check_data_available = vgpu_css_flush_snapshots,
+	.detach_snapshot = vgpu_css_detach,
+	.set_handled_snapshots = NULL,
+	.allocate_perfmon_ids = NULL,
+	.release_perfmon_ids = NULL,
+	.get_max_buffer_size = vgpu_css_get_buffer_size,
+};
+#endif
+
+static const struct gops_falcon vgpu_ga10b_ops_falcon = {
+	.falcon_sw_init = nvgpu_falcon_sw_init,
+	.falcon_sw_free = nvgpu_falcon_sw_free,
+};
+
+static const struct gops_fbp vgpu_ga10b_ops_fbp = {
+	.fbp_init_support = nvgpu_fbp_init_support,
+};
+
+static const struct gops_priv_ring vgpu_ga10b_ops_priv_ring = {
+	.enable_priv_ring = NULL,
+	.isr = NULL,
+	.set_ppriv_timeout_settings = NULL,
+	.enum_ltc = NULL,
+	.get_gpc_count = vgpu_gr_get_gpc_count,
+};
+
+static const struct gops_fuse vgpu_ga10b_ops_fuse = {
+	.is_opt_ecc_enable = NULL,
+	.is_opt_feature_override_disable = NULL,
+	.fuse_status_opt_fbio = NULL,
+	.fuse_status_opt_fbp = NULL,
+	.fuse_status_opt_rop_l2_fbp = NULL,
+	.fuse_status_opt_tpc_gpc = NULL,
+	.fuse_ctrl_opt_tpc_gpc = NULL,
+	.fuse_opt_sec_debug_en = NULL,
+	.fuse_opt_priv_sec_en = NULL,
+	.read_vin_cal_fuse_rev = NULL,
+	.read_vin_cal_slope_intercept_fuse = NULL,
+	.read_vin_cal_gain_offset_fuse = NULL,
+};
+
+static const struct gops_top vgpu_ga10b_ops_top = {
+	.get_max_gpc_count = vgpu_gr_get_max_gpc_count,
+	.get_max_fbps_count = vgpu_gr_get_max_fbps_count,
+	.get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
+	.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
+	.parse_next_device = vgpu_top_parse_next_dev,
+};
+
+static const struct gops_grmgr vgpu_ga10b_ops_grmgr = {
+	.init_gr_manager = nvgpu_init_gr_manager,
+};
+
+int vgpu_ga10b_init_hal(struct gk20a *g)
+{
+	struct gpu_ops *gops = &g->ops;
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
+
+	gops->acr = vgpu_ga10b_ops_acr;
+#ifdef CONFIG_NVGPU_DGPU
+	gops->bios = vgpu_ga10b_ops_bios;
+#endif /* CONFIG_NVGPU_DGPU */
+	gops->ltc = vgpu_ga10b_ops_ltc;
+	gops->ltc.intr = vgpu_ga10b_ops_ltc_intr;
+#ifdef CONFIG_NVGPU_COMPRESSION
+	gops->cbc = vgpu_ga10b_ops_cbc;
+#endif
+	gops->ce = vgpu_ga10b_ops_ce;
+	gops->gr = vgpu_ga10b_ops_gr;
+	gops->gr.ctxsw_prog = vgpu_ga10b_ops_gr_ctxsw_prog;
+	gops->gr.config = vgpu_ga10b_ops_gr_config;
+	gops->gr.setup = vgpu_ga10b_ops_gr_setup;
+#ifdef CONFIG_NVGPU_GRAPHICS
+	gops->gr.zbc = vgpu_ga10b_ops_gr_zbc;
+	gops->gr.zcull = vgpu_ga10b_ops_gr_zcull;
+#endif /* CONFIG_NVGPU_GRAPHICS */
+#ifdef CONFIG_NVGPU_DEBUGGER
+	gops->gr.hwpm_map = vgpu_ga10b_ops_gr_hwpm_map;
+#endif
+	gops->gr.falcon = vgpu_ga10b_ops_gr_falcon;
+#ifdef CONFIG_NVGPU_FECS_TRACE
+	gops->gr.fecs_trace = vgpu_ga10b_ops_gr_fecs_trace;
+#endif /* CONFIG_NVGPU_FECS_TRACE */
+	gops->gr.init = vgpu_ga10b_ops_gr_init;
+	gops->gr.intr = vgpu_ga10b_ops_gr_intr;
+	gops->gpu_class = vgpu_ga10b_ops_gpu_class;
+	gops->fb = vgpu_ga10b_ops_fb;
+	gops->fb.intr = vgpu_ga10b_ops_fb_intr;
+	gops->cg = vgpu_ga10b_ops_cg;
+	gops->fifo = vgpu_ga10b_ops_fifo;
+	gops->engine = vgpu_ga10b_ops_engine;
+	gops->pbdma = vgpu_ga10b_ops_pbdma;
+	gops->sync = vgpu_ga10b_ops_sync;
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+	gops->sync.syncpt = vgpu_ga10b_ops_sync_syncpt;
+#endif /* CONFIG_TEGRA_GK20A_NVHOST */
+#if defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT) && \
+	defined(CONFIG_NVGPU_SW_SEMAPHORE)
+	gops->sync.sema = vgpu_ga10b_ops_sync_sema;
+#endif
+	gops->engine_status = vgpu_ga10b_ops_engine_status;
+	gops->pbdma_status = vgpu_ga10b_ops_pbdma_status;
+	gops->ramfc = vgpu_ga10b_ops_ramfc;
+	gops->ramin = vgpu_ga10b_ops_ramin;
+	gops->runlist = vgpu_ga10b_ops_runlist;
+	gops->userd = vgpu_ga10b_ops_userd;
+	gops->channel = vgpu_ga10b_ops_channel;
+	gops->tsg = vgpu_ga10b_ops_tsg;
+	gops->usermode = vgpu_ga10b_ops_usermode;
+	gops->netlist = vgpu_ga10b_ops_netlist;
+	gops->mm = vgpu_ga10b_ops_mm;
+	gops->mm.mmu_fault = vgpu_ga10b_ops_mm_mmu_fault;
+	gops->mm.cache = vgpu_ga10b_ops_mm_cache;
+	gops->mm.gmmu = vgpu_ga10b_ops_mm_gmmu;
+	gops->therm = vgpu_ga10b_ops_therm;
+#ifdef CONFIG_NVGPU_LS_PMU
+	gops->pmu = vgpu_ga10b_ops_pmu;
+#endif
+	gops->clk_arb = vgpu_ga10b_ops_clk_arb;
+#ifdef CONFIG_NVGPU_DEBUGGER
+	gops->regops = vgpu_ga10b_ops_regops;
+#endif
+	gops->mc = vgpu_ga10b_ops_mc;
+	gops->debug = vgpu_ga10b_ops_debug;
+#ifdef CONFIG_NVGPU_DEBUGGER
+	gops->debugger = vgpu_ga10b_ops_debugger;
+	gops->perf = vgpu_ga10b_ops_perf;
+	gops->perfbuf = vgpu_ga10b_ops_perfbuf;
+#endif
+#ifdef CONFIG_NVGPU_PROFILER
+	gops->pm_reservation = vgpu_ga10b_ops_pm_reservation;
+	gops->profiler = vgpu_ga10b_ops_profiler;
+#endif
+	gops->bus = vgpu_ga10b_ops_bus;
+	gops->ptimer = vgpu_ga10b_ops_ptimer;
+#if defined(CONFIG_NVGPU_CYCLESTATS)
+	gops->css = vgpu_ga10b_ops_css;
+#endif
+	gops->falcon = vgpu_ga10b_ops_falcon;
+	gops->fbp = vgpu_ga10b_ops_fbp;
+	gops->priv_ring = vgpu_ga10b_ops_priv_ring;
+	gops->fuse = vgpu_ga10b_ops_fuse;
+	gops->top = vgpu_ga10b_ops_top;
+	gops->grmgr = vgpu_ga10b_ops_grmgr;
+
+	/* Lone functions */
+	gops->chip_init_gpu_characteristics = vgpu_ga10b_init_gpu_characteristics;
+	gops->get_litter_value = ga10b_get_litter_value;
+	gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;
+
+	if (!priv->constants.can_set_clkrate) {
+		gops->clk_arb.get_arbiter_clk_domains = NULL;
+	}
+
+	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)){
+		nvgpu_set_errata(g, NVGPU_ERRATA_2969956, true);
+	}
+	nvgpu_set_errata(g, NVGPU_ERRATA_200601972, true);
+	nvgpu_set_errata(g, NVGPU_ERRATA_200391931, true);
+	nvgpu_set_errata(g, NVGPU_ERRATA_SYNCPT_INVALID_ID_0, true);
+
+#ifdef CONFIG_NVGPU_SM_DIVERSITY
+	/*
+	 * To achieve permanent fault coverage, the CTAs launched by each kernel
+	 * in the mission and redundant contexts must execute on different
+	 * hardware resources. This feature proposes modifications in the
+	 * software to modify the virtual SM id to TPC mapping across the
+	 * mission and redundant contexts.
+	 *
+	 * The virtual SM identifier to TPC mapping is done by the nvgpu
+	 * when setting up the golden context. Once the table with this mapping
+	 * is initialized, it is used by all subsequent contexts created.
+	 * The proposal is for setting up the virtual SM identifier to TPC
+	 * mapping on a per-context basis and initializing this virtual SM
+	 * identifier to TPC mapping differently for the mission and
+	 * redundant contexts.
+	 *
+	 * The recommendation for the redundant setting is to offset the
+	 * assignment by 1 (TPC). This will ensure both GPC and TPC diversity.
+	 * The SM and Quadrant diversity will happen naturally.
+	 *
+	 * For kernels with few CTAs, the diversity is guaranteed to be 100%.
+	 * In case of completely random CTA allocation, e.g. large number of
+	 * CTAs in the waiting queue, the diversity is 1 - 1/#SM,
+	 * or 87.5% for GV11B.
+	 */
+	if (priv->constants.max_sm_diversity_config_count > 1U) {
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_SM_DIVERSITY, true);
+	}
+#else
+	priv->constants.max_sm_diversity_config_count =
+		NVGPU_DEFAULT_SM_DIVERSITY_CONFIG_COUNT;
+#endif
+	g->max_sm_diversity_config_count =
+		priv->constants.max_sm_diversity_config_count;
+
+#ifdef CONFIG_NVGPU_COMPRESSION
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_COMPRESSION, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_POST_L2_COMPRESSION, true);
+#endif
+
+#ifdef CONFIG_NVGPU_RECOVERY
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_FAULT_RECOVERY, true);
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+	nvgpu_set_enabled(g, NVGPU_L2_MAX_WAYS_EVICT_LAST_ENABLED, true);
+#endif
+
+	g->name = "ga10b";
+
+	return 0;
+}
diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.h b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.h
new file mode 100644
index 000000000..330874512
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VGPU_HAL_GV11B_H
+#define VGPU_HAL_GV11B_H
+
+struct gk20a;
+
+int vgpu_ga10b_init_hal(struct gk20a *g);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_fs_state.h b/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_fs_state.h
new file mode 100644
index 000000000..94ee10a76
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_fs_state.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_FS_STATE_H
+#define NVGPU_NEXT_FS_STATE_H
+
+struct gk20a;
+struct nvgpu_gr_config;
+
+int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr.h b/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr.h
new file mode 100644
index 000000000..636172302
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_GR_H
+#define NVGPU_NEXT_GR_H
+
+/**
+ * @file
+ *
+ */
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct netlist_av_list;
+
+void nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g);
+void nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g);
+#endif /* NVGPU_NEXT_GR_H */
\ No newline at end of file
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr_ecc.h b/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr_ecc.h
new file mode 100644
index 000000000..73ab1d188
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr_ecc.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GR_ECC_H
+#define NVGPU_NEXT_GR_ECC_H
+
+		/** SM RAMS corrected error count. */
+		struct nvgpu_ecc_stat **sm_rams_ecc_corrected_err_count;
+		/** SM RAMS uncorrected error count. */
+		struct nvgpu_ecc_stat **sm_rams_ecc_uncorrected_err_count;
+
+#endif /* NVGPU_NEXT_GR_ECC_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_bus_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_bus_ga100.h
new file mode 100644
index 000000000..2913fccf4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_bus_ga100.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_BUS_GA100_H
+#define NVGPU_HW_BUS_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define bus_sw_scratch_r(i)\
+		(nvgpu_safe_add_u32(0x00001400U, nvgpu_safe_mult_u32((i), 4U)))
+#define bus_bar0_window_r()                                        (0x00001700U)
+#define bus_bar0_window_base_f(v)                   ((U32(v) & 0xffffffU) << 0U)
+#define bus_bar0_window_target_vid_mem_f()                                (0x0U)
+#define bus_bar0_window_target_sys_mem_coherent_f()                 (0x2000000U)
+#define bus_bar0_window_target_sys_mem_noncoherent_f()              (0x3000000U)
+#define bus_bar0_window_target_bar0_window_base_shift_v()          (0x00000010U)
+#define bus_bar1_block_r()                                         (0x00001704U)
+#define bus_bar1_block_ptr_f(v)                    ((U32(v) & 0xfffffffU) << 0U)
+#define bus_bar1_block_target_vid_mem_f()                                 (0x0U)
+#define bus_bar1_block_target_sys_mem_coh_f()                      (0x20000000U)
+#define bus_bar1_block_target_sys_mem_ncoh_f()                     (0x30000000U)
+#define bus_bar1_block_mode_virtual_f()                            (0x80000000U)
+#define bus_bar2_block_r()                                         (0x00001714U)
+#define bus_bar2_block_ptr_f(v)                    ((U32(v) & 0xfffffffU) << 0U)
+#define bus_bar2_block_target_vid_mem_f()                                 (0x0U)
+#define bus_bar2_block_target_sys_mem_coh_f()                      (0x20000000U)
+#define bus_bar2_block_target_sys_mem_ncoh_f()                     (0x30000000U)
+#define bus_bar2_block_mode_virtual_f()                            (0x80000000U)
+#define bus_bar1_block_ptr_shift_v()                               (0x0000000cU)
+#define bus_bar2_block_ptr_shift_v()                               (0x0000000cU)
+#define bus_bind_status_r()                                        (0x00001710U)
+#define bus_bind_status_bar1_pending_v(r)                   (((r) >> 0U) & 0x1U)
+#define bus_bind_status_bar1_pending_empty_f()                            (0x0U)
+#define bus_bind_status_bar1_outstanding_v(r)               (((r) >> 1U) & 0x1U)
+#define bus_bind_status_bar1_outstanding_false_f()                        (0x0U)
+#define bus_bind_status_bar2_pending_v(r)                   (((r) >> 2U) & 0x1U)
+#define bus_bind_status_bar2_pending_empty_f()                            (0x0U)
+#define bus_bind_status_bar2_pending_busy_v()                      (0x00000001U)
+#define bus_bind_status_bar2_outstanding_v(r)               (((r) >> 3U) & 0x1U)
+#define bus_bind_status_bar2_outstanding_false_f()                        (0x0U)
+#define bus_bind_status_bar2_outstanding_true_v()                  (0x00000001U)
+#define bus_intr_0_r()                                             (0x00001100U)
+#define bus_intr_0_pri_fecserr_m()                             (U32(0x1U) << 2U)
+#define bus_intr_0_pri_timeout_m()                             (U32(0x1U) << 3U)
+#define bus_intr_0_sw_m()                                     (U32(0x1U) << 26U)
+#define bus_intr_0_posted_deadlock_timeout_m()                (U32(0x1U) << 27U)
+#define bus_intr_0_mpmu_m()                                   (U32(0x1U) << 28U)
+#define bus_intr_0_access_timeout_m()                         (U32(0x1U) << 31U)
+#define bus_intr_en_0_r()                                          (0x00001140U)
+#define bus_intr_en_0_pri_fecserr_m()                          (U32(0x1U) << 2U)
+#define bus_intr_en_0_pri_timeout_m()                          (U32(0x1U) << 3U)
+#define bus_intr_en_0_fb_req_timeout_m()                       (U32(0x1U) << 4U)
+#define bus_intr_en_0_fb_ack_timeout_m()                       (U32(0x1U) << 5U)
+#define bus_intr_en_0_fb_ack_extra_m()                         (U32(0x1U) << 6U)
+#define bus_intr_en_0_fb_rdata_timeout_m()                     (U32(0x1U) << 7U)
+#define bus_intr_en_0_fb_rdata_extra_m()                       (U32(0x1U) << 8U)
+#define bus_intr_en_0_sw_m()                                  (U32(0x1U) << 26U)
+#define bus_intr_en_0_posted_deadlock_timeout_m()             (U32(0x1U) << 27U)
+#define bus_intr_en_0_mpmu_m()                                (U32(0x1U) << 28U)
+#define bus_intr_en_0_access_timeout_m()                      (U32(0x1U) << 31U)
+#define bus_fb_timeout_r()                                         (0x00001538U)
+#define bus_fb_timeout_period_v(r)                   (((r) >> 0U) & 0x3fffffffU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ce_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ce_ga100.h
new file mode 100644
index 000000000..8ca9a1802
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ce_ga100.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_CE_GA100_H
+#define NVGPU_HW_CE_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define ce_intr_status_r(i)\
+		(nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32((i), 128U)))
+#define ce_intr_status_blockpipe_pending_f()                              (0x1U)
+#define ce_intr_status_nonblockpipe_pending_f()                           (0x2U)
+#define ce_intr_status_launcherr_pending_f()                              (0x4U)
+#define ce_intr_status_invalid_config_pending_f()                         (0x8U)
+#define ce_intr_status_invalid_config_reset_f()                           (0x8U)
+#define ce_intr_status_mthd_buffer_fault_pending_f()                     (0x10U)
+#define ce_intr_status_mthd_buffer_fault_reset_f()                       (0x10U)
+#define ce_intr_retrigger_r(i)\
+		(nvgpu_safe_add_u32(0x00104434U, nvgpu_safe_mult_u32((i), 128U)))
+#define ce_intr_retrigger_trigger_true_f()                                (0x1U)
+#define ce_pce_map_r()                                             (0x00104028U)
+#define ce_lce_opt_r(i)\
+		(nvgpu_safe_add_u32(0x00104414U, nvgpu_safe_mult_u32((i), 128U)))
+#define ce_lce_opt_force_barriers_npl__prod_f()                           (0x8U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ctrl_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ctrl_ga100.h
new file mode 100644
index 000000000..96c9ddf0d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ctrl_ga100.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_CTRL_GA100_H
+#define NVGPU_HW_CTRL_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define ctrl_doorbell_r(i)\
+		(nvgpu_safe_add_u32(0x00b64000U, nvgpu_safe_mult_u32((i), 8U)))
+#define ctrl_doorbell_vector_f(v)                      ((U32(v) & 0xfffU) << 0U)
+#define ctrl_doorbell_runlist_id_f(v)                  ((U32(v) & 0x7fU) << 16U)
+#define ctrl_legacy_engine_nonstall_intr_base_vectorid_r()         (0x00b66884U)
+#define ctrl_legacy_engine_nonstall_intr_base_vectorid_vector_v(r)\
+				(((r) >> 0U) & 0xfffU)
+#define ctrl_legacy_engine_stall_intr_base_vectorid_r()            (0x00b66880U)
+#define ctrl_legacy_engine_stall_intr_base_vectorid_vector_v(r)\
+				(((r) >> 0U) & 0xfffU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h
new file mode 100644
index 000000000..baa333a2c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_CTXSW_PROG_GA100_H
+#define NVGPU_HW_CTXSW_PROG_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define ctxsw_prog_fecs_header_v()                                 (0x00000200U)
+#define ctxsw_prog_gpccs_header_stride_v()                         (0x00000200U)
+#define ctxsw_prog_main_image_num_gpcs_o()                         (0x00000008U)
+#define ctxsw_prog_main_image_ctl_o()                              (0x0000000cU)
+#define ctxsw_prog_main_image_ctl_type_per_veid_header_v()         (0x00000021U)
+#define ctxsw_prog_main_image_patch_count_o()                      (0x00000010U)
+#define ctxsw_prog_main_image_context_id_o()                       (0x000000f0U)
+#define ctxsw_prog_main_image_patch_adr_lo_o()                     (0x00000014U)
+#define ctxsw_prog_main_image_patch_adr_hi_o()                     (0x00000018U)
+#define ctxsw_prog_main_image_zcull_o()                            (0x0000001cU)
+#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v()              (0x00000001U)
+#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v()       (0x00000002U)
+#define ctxsw_prog_main_image_zcull_ptr_o()                        (0x00000020U)
+#define ctxsw_prog_main_image_pm_o()                               (0x00000028U)
+#define ctxsw_prog_main_image_pm_mode_m()                      (U32(0x7U) << 0U)
+#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f()                        (0x0U)
+#define ctxsw_prog_main_image_pm_mode_ctxsw_f()                           (0x1U)
+#define ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f()                (0x2U)
+#define ctxsw_prog_main_image_pm_smpc_mode_m()                 (U32(0x7U) << 3U)
+#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f()                   (0x0U)
+#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f()                      (0x8U)
+#define ctxsw_prog_main_image_pm_ptr_o()                           (0x0000002cU)
+#define ctxsw_prog_main_image_num_save_ops_o()                     (0x000000f4U)
+#define ctxsw_prog_main_image_num_wfi_save_ops_o()                 (0x000000d0U)
+#define ctxsw_prog_main_image_num_cta_save_ops_o()                 (0x000000d4U)
+#define ctxsw_prog_main_image_num_gfxp_save_ops_o()                (0x000000d8U)
+#define ctxsw_prog_main_image_num_cilp_save_ops_o()                (0x000000dcU)
+#define ctxsw_prog_main_image_num_restore_ops_o()                  (0x000000f8U)
+#define ctxsw_prog_main_image_magic_value_1_o()                    (0x000000fcU)
+#define ctxsw_prog_main_image_magic_value_1_v_value_v()            (0x600dc0deU)
+#define ctxsw_prog_main_image_magic_value_2_o()                    (0x00000100U)
+#define ctxsw_prog_main_image_magic_value_2_v_value_v()            (0xdeadce11U)
+#define ctxsw_prog_main_image_magic_value_3_o()                    (0x000001fcU)
+#define ctxsw_prog_main_image_magic_value_3_v_value_v()            (0xfaceb00cU)
+#define ctxsw_prog_main_image_zcull_ptr_hi_o()                     (0x00000060U)
+#define ctxsw_prog_main_image_pm_ptr_hi_o()                        (0x00000094U)
+#define ctxsw_prog_main_image_full_preemption_ptr_hi_o()           (0x00000064U)
+#define ctxsw_prog_main_image_full_preemption_ptr_o()              (0x00000068U)
+#define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o()     (0x00000070U)
+#define ctxsw_prog_main_image_full_preemption_ptr_veid0_o()        (0x00000074U)
+#define ctxsw_prog_main_image_context_buffer_ptr_hi_o()            (0x00000078U)
+#define ctxsw_prog_main_image_context_buffer_ptr_o()               (0x0000007cU)
+#define ctxsw_prog_local_priv_register_ctl_o()                     (0x0000000cU)
+#define ctxsw_prog_local_priv_register_ctl_offset_v(r)   (((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_local_image_ppc_info_o()                        (0x000000f4U)
+#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r)    (((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r)   (((r) >> 16U) & 0xffffU)
+#define ctxsw_prog_local_image_num_tpcs_o()                        (0x000000f8U)
+#define ctxsw_prog_local_magic_value_1_o()                         (0x000000fcU)
+#define ctxsw_prog_local_magic_value_1_v_value_v()                 (0xad0becabU)
+#define ctxsw_prog_local_magic_value_2_o()                         (0x00000100U)
+#define ctxsw_prog_local_magic_value_2_v_value_v()                 (0x1ceb00daU)
+#define ctxsw_prog_local_magic_value_3_o()                         (0x000001fcU)
+#define ctxsw_prog_local_magic_value_3_v_value_v()                 (0xf00dbeefU)
+#define ctxsw_prog_main_extended_buffer_ctl_o()                    (0x000000ecU)
+#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r)  (((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_main_extended_buffer_ctl_size_v(r)     (((r) >> 16U) & 0xffU)
+#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v()      (0x00000100U)
+#define ctxsw_prog_extended_marker_size_in_bytes_v()               (0x00000004U)
+#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\
+				(0x00000000U)
+#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\
+				(0x00000002U)
+#define ctxsw_prog_main_image_priv_access_map_config_o()           (0x000000a0U)
+#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f()   (0x0U)
+#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f()     (0x2U)
+#define ctxsw_prog_main_image_priv_access_map_addr_lo_o()          (0x000000a4U)
+#define ctxsw_prog_main_image_priv_access_map_addr_hi_o()          (0x000000a8U)
+#define ctxsw_prog_main_image_misc_options_o()                     (0x0000003cU)
+#define ctxsw_prog_main_image_misc_options_verif_features_m()  (U32(0x1U) << 3U)
+#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f()    (0x0U)
+#define ctxsw_prog_main_image_graphics_preemption_options_o()      (0x00000080U)
+#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\
+				(0x1U)
+#define ctxsw_prog_main_image_compute_preemption_options_o()       (0x00000084U)
+#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f()  (0x1U)
+#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U)
+#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU)
+#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\
+				((U32(v) & 0xffffU) << 0U)
+#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o()  (0x000000b0U)
+#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o()     (0x000000b4U)
+#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define ctxsw_prog_record_timestamp_record_size_in_bytes_v()       (0x00000080U)
+#define ctxsw_prog_record_timestamp_magic_value_hi_o()             (0x00000004U)
+#define ctxsw_prog_record_timestamp_magic_value_hi_v_value_v()     (0x600dbeefU)
+#define ctxsw_prog_record_timestamp_timestamp_hi_o()               (0x0000001cU)
+#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m()     (U32(0xffU) << 24U)
+#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU)
+#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v()\
+				(0x000000ffU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_falcon_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_falcon_ga100.h
new file mode 100644
index 000000000..4703c43db
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_falcon_ga100.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_FALCON_GA100_H
+#define NVGPU_HW_FALCON_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define falcon_falcon_irqsclr_r()                                  (0x00000004U)
+#define falcon_falcon_irqstat_r()                                  (0x00000008U)
+#define falcon_falcon_irqstat_halt_true_f()                              (0x10U)
+#define falcon_falcon_irqmode_r()                                  (0x0000000cU)
+#define falcon_falcon_irqmset_r()                                  (0x00000010U)
+#define falcon_falcon_irqmclr_r()                                  (0x00000014U)
+#define falcon_falcon_irqmask_r()                                  (0x00000018U)
+#define falcon_falcon_irqdest_r()                                  (0x0000001cU)
+#define falcon_falcon_curctx_r()                                   (0x00000050U)
+#define falcon_falcon_nxtctx_r()                                   (0x00000054U)
+#define falcon_falcon_mailbox0_r()                                 (0x00000040U)
+#define falcon_falcon_mailbox1_r()                                 (0x00000044U)
+#define falcon_falcon_idlestate_r()                                (0x0000004cU)
+#define falcon_falcon_idlestate_falcon_busy_v(r)            (((r) >> 0U) & 0x1U)
+#define falcon_falcon_idlestate_ext_busy_v(r)            (((r) >> 1U) & 0x7fffU)
+#define falcon_falcon_os_r()                                       (0x00000080U)
+#define falcon_falcon_engctl_r()                                   (0x000000a4U)
+#define falcon_falcon_cpuctl_r()                                   (0x00000100U)
+#define falcon_falcon_cpuctl_startcpu_f(v)               ((U32(v) & 0x1U) << 1U)
+#define falcon_falcon_cpuctl_hreset_f(v)                 ((U32(v) & 0x1U) << 3U)
+#define falcon_falcon_cpuctl_halt_intr_m()                     (U32(0x1U) << 4U)
+#define falcon_falcon_imemc_r(i)\
+		(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U)))
+#define falcon_falcon_imemc_offs_f(v)                   ((U32(v) & 0x3fU) << 2U)
+#define falcon_falcon_imemc_blk_f(v)                  ((U32(v) & 0xffffU) << 8U)
+#define falcon_falcon_imemc_aincw_f(v)                  ((U32(v) & 0x1U) << 24U)
+#define falcon_falcon_imemc_secure_f(v)                 ((U32(v) & 0x1U) << 28U)
+#define falcon_falcon_imemd_r(i)\
+		(nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U)))
+#define falcon_falcon_imemt_r(i)\
+		(nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U)))
+#define falcon_falcon_sctl_r()                                     (0x00000240U)
+#define falcon_falcon_bootvec_r()                                  (0x00000104U)
+#define falcon_falcon_bootvec_vec_f(v)            ((U32(v) & 0xffffffffU) << 0U)
+#define falcon_falcon_dmactl_r()                                   (0x0000010cU)
+#define falcon_falcon_dmactl_dmem_scrubbing_m()                (U32(0x1U) << 1U)
+#define falcon_falcon_dmactl_imem_scrubbing_m()                (U32(0x1U) << 2U)
+#define falcon_falcon_dmactl_require_ctx_f(v)            ((U32(v) & 0x1U) << 0U)
+#define falcon_falcon_hwcfg_r()                                    (0x00000108U)
+#define falcon_falcon_hwcfg_imem_size_v(r)                (((r) >> 0U) & 0x1ffU)
+#define falcon_falcon_hwcfg_dmem_size_v(r)                (((r) >> 9U) & 0x1ffU)
+#define falcon_falcon_imctl_debug_r()                              (0x0000015cU)
+#define falcon_falcon_imctl_debug_addr_blk_f(v)     ((U32(v) & 0xffffffU) << 0U)
+#define falcon_falcon_imctl_debug_cmd_f(v)              ((U32(v) & 0x7U) << 24U)
+#define falcon_falcon_imstat_r()                                   (0x00000144U)
+#define falcon_falcon_traceidx_r()                                 (0x00000148U)
+#define falcon_falcon_traceidx_maxidx_v(r)                (((r) >> 16U) & 0xffU)
+#define falcon_falcon_traceidx_idx_f(v)                 ((U32(v) & 0xffU) << 0U)
+#define falcon_falcon_tracepc_r()                                  (0x0000014cU)
+#define falcon_falcon_tracepc_pc_v(r)                  (((r) >> 0U) & 0xffffffU)
+#define falcon_falcon_exterraddr_r()                               (0x0010a168U)
+#define falcon_falcon_exterrstat_r()                               (0x0010a16cU)
+#define falcon_falcon_icd_cmd_r()                                  (0x00000200U)
+#define falcon_falcon_icd_cmd_opc_rreg_f()                                (0x8U)
+#define falcon_falcon_icd_cmd_opc_rstat_f()                               (0xeU)
+#define falcon_falcon_icd_cmd_idx_f(v)                  ((U32(v) & 0x1fU) << 8U)
+#define falcon_falcon_icd_rdata_r()                                (0x0000020cU)
+#define falcon_falcon_dmemc_r(i)\
+		(nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U)))
+#define falcon_falcon_dmemc_offs_m()                          (U32(0x3fU) << 2U)
+#define falcon_falcon_dmemc_blk_m()                         (U32(0xffffU) << 8U)
+#define falcon_falcon_dmemc_aincw_f(v)                  ((U32(v) & 0x1U) << 24U)
+#define falcon_falcon_dmemc_aincr_f(v)                  ((U32(v) & 0x1U) << 25U)
+#define falcon_falcon_dmemd_r(i)\
+		(nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U)))
+#define falcon_falcon_debug1_r()                                   (0x00000090U)
+#define falcon_falcon_debuginfo_r()                                (0x00000094U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fb_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fb_ga100.h
new file mode 100644
index 000000000..3cb53577a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fb_ga100.h
@@ -0,0 +1,359 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_FB_GA100_H
+#define NVGPU_HW_FB_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define fb_fbhub_num_active_ltcs_r()                               (0x00100800U)
+#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m()      (U32(0x1U) << 25U)
+#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f()    (0x2000000U)
+#define fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m() (U32(0x1U) << 26U)
+#define fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f()    (0x0U)
+#define fb_fbhub_num_active_ltcs_count_f(v)             ((U32(v) & 0x1fU) << 0U)
+#define fb_fbhub_num_active_ltcs_count_m()                    (U32(0x1fU) << 0U)
+#define fb_fbhub_num_active_ltcs_count_v(r)                (((r) >> 0U) & 0x1fU)
+#define fb_mmu_hypervisor_ctl_r()                                  (0x00100ed0U)
+#define fb_mmu_hypervisor_ctl_force_cbc_raw_mode_v(r)       (((r) >> 5U) & 0x1U)
+#define fb_mmu_hypervisor_ctl_force_cbc_raw_mode_disable_v()       (0x00000000U)
+#define fb_mmu_ctrl_r()                                            (0x00100c80U)
+#define fb_mmu_ctrl_pri_fifo_empty_v(r)                    (((r) >> 15U) & 0x1U)
+#define fb_mmu_ctrl_pri_fifo_empty_false_f()                              (0x0U)
+#define fb_mmu_ctrl_pri_fifo_space_v(r)                   (((r) >> 16U) & 0xffU)
+#define fb_mmu_ctrl_atomic_capability_mode_m()                (U32(0x3U) << 24U)
+#define fb_mmu_ctrl_atomic_capability_mode_rmw_f()                  (0x2000000U)
+#define fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m()       (U32(0x1U) << 27U)
+#define fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f()                (0x0U)
+#define fb_mmu_bind_imb_r()                                        (0x00100cacU)
+#define fb_mmu_bind_imb_aperture_f(v)                    ((U32(v) & 0x3U) << 0U)
+#define fb_mmu_bind_imb_aperture_vid_mem_f()                              (0x0U)
+#define fb_mmu_bind_imb_aperture_sys_mem_c_f()                            (0x2U)
+#define fb_mmu_bind_imb_aperture_sys_mem_nc_f()                           (0x3U)
+#define fb_mmu_bind_imb_addr_f(v)                  ((U32(v) & 0xfffffffU) << 4U)
+#define fb_mmu_bind_imb_addr_alignment_v()                         (0x0000000cU)
+#define fb_mmu_bind_r()                                            (0x00100cb0U)
+#define fb_mmu_bind_engine_id_f(v)                      ((U32(v) & 0xffU) << 0U)
+#define fb_mmu_bind_trigger_true_f()                               (0x80000000U)
+#define fb_priv_mmu_phy_secure_r()                                 (0x00100ce4U)
+#define fb_mmu_invalidate_pdb_r()                                  (0x00100cb8U)
+#define fb_mmu_invalidate_pdb_aperture_vid_mem_f()                        (0x0U)
+#define fb_mmu_invalidate_pdb_aperture_sys_mem_f()                        (0x2U)
+#define fb_mmu_invalidate_pdb_addr_f(v)            ((U32(v) & 0xfffffffU) << 4U)
+#define fb_mmu_invalidate_r()                                      (0x00100cbcU)
+#define fb_mmu_invalidate_all_va_true_f()                                 (0x1U)
+#define fb_mmu_invalidate_all_pdb_true_f()                                (0x2U)
+#define fb_mmu_invalidate_replay_s()                                        (3U)
+#define fb_mmu_invalidate_replay_start_ack_all_f()                       (0x10U)
+#define fb_mmu_invalidate_replay_cancel_global_f()                       (0x20U)
+#define fb_mmu_invalidate_trigger_v(r)                     (((r) >> 31U) & 0x1U)
+#define fb_mmu_invalidate_trigger_true_v()                         (0x00000001U)
+#define fb_mmu_invalidate_trigger_true_f()                         (0x80000000U)
+#define fb_mmu_debug_wr_r()                                        (0x00100cc8U)
+#define fb_mmu_debug_wr_aperture_s()                                        (2U)
+#define fb_mmu_debug_wr_aperture_v(r)                       (((r) >> 0U) & 0x3U)
+#define fb_mmu_debug_wr_aperture_vid_mem_f()                              (0x0U)
+#define fb_mmu_debug_wr_aperture_sys_mem_coh_f()                          (0x2U)
+#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f()                         (0x3U)
+#define fb_mmu_debug_wr_vol_false_f()                                     (0x0U)
+#define fb_mmu_debug_wr_addr_f(v)                  ((U32(v) & 0xfffffffU) << 4U)
+#define fb_mmu_debug_wr_addr_alignment_v()                         (0x0000000cU)
+#define fb_mmu_debug_rd_r()                                        (0x00100cccU)
+#define fb_mmu_debug_rd_aperture_vid_mem_f()                              (0x0U)
+#define fb_mmu_debug_rd_vol_false_f()                                     (0x0U)
+#define fb_mmu_debug_rd_addr_f(v)                  ((U32(v) & 0xfffffffU) << 4U)
+#define fb_mmu_debug_rd_addr_alignment_v()                         (0x0000000cU)
+#define fb_mmu_debug_ctrl_r()                                      (0x00100cc4U)
+#define fb_mmu_debug_ctrl_debug_v(r)                       (((r) >> 16U) & 0x1U)
+#define fb_mmu_debug_ctrl_debug_m()                           (U32(0x1U) << 16U)
+#define fb_mmu_debug_ctrl_debug_enabled_v()                        (0x00000001U)
+#define fb_mmu_debug_ctrl_debug_enabled_f()                           (0x10000U)
+#define fb_mmu_debug_ctrl_debug_disabled_f()                              (0x0U)
+#define fb_mmu_l2tlb_ecc_status_r()                                (0x00100e70U)
+#define fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()\
+				(U32(0x1U) << 0U)
+#define fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m()\
+				(U32(0x1U) << 1U)
+#define fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 16U)
+#define fb_mmu_l2tlb_ecc_status_corrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 17U)
+#define fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 18U)
+#define fb_mmu_l2tlb_ecc_status_uncorrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 19U)
+#define fb_mmu_l2tlb_ecc_status_reset_clear_f()                    (0x40000000U)
+#define fb_mmu_l2tlb_ecc_corrected_err_count_r()                   (0x00100e74U)
+#define fb_mmu_l2tlb_ecc_corrected_err_count_total_s()                     (16U)
+#define fb_mmu_l2tlb_ecc_corrected_err_count_total_v(r)  (((r) >> 0U) & 0xffffU)
+#define fb_mmu_l2tlb_ecc_corrected_err_count_unique_s()                    (16U)
+#define fb_mmu_l2tlb_ecc_corrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_l2tlb_ecc_uncorrected_err_count_r()                 (0x00100e78U)
+#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s()                   (16U)
+#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define fb_mmu_l2tlb_ecc_uncorrected_err_count_unique_s()                  (16U)
+#define fb_mmu_l2tlb_ecc_uncorrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_l2tlb_ecc_address_r()                               (0x00100e7cU)
+#define fb_mmu_hubtlb_ecc_status_r()                               (0x00100e84U)
+#define fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()     (U32(0x1U) << 0U)
+#define fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m()   (U32(0x1U) << 1U)
+#define fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 16U)
+#define fb_mmu_hubtlb_ecc_status_corrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 17U)
+#define fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 18U)
+#define fb_mmu_hubtlb_ecc_status_uncorrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 19U)
+#define fb_mmu_hubtlb_ecc_status_reset_clear_f()                   (0x40000000U)
+#define fb_mmu_hubtlb_ecc_corrected_err_count_r()                  (0x00100e88U)
+#define fb_mmu_hubtlb_ecc_corrected_err_count_total_s()                    (16U)
+#define fb_mmu_hubtlb_ecc_corrected_err_count_total_v(r) (((r) >> 0U) & 0xffffU)
+#define fb_mmu_hubtlb_ecc_corrected_err_count_unique_s()                   (16U)
+#define fb_mmu_hubtlb_ecc_corrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_hubtlb_ecc_uncorrected_err_count_r()                (0x00100e8cU)
+#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s()                  (16U)
+#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define fb_mmu_hubtlb_ecc_uncorrected_err_count_unique_s()                 (16U)
+#define fb_mmu_hubtlb_ecc_uncorrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_hubtlb_ecc_address_r()                              (0x00100e90U)
+#define fb_mmu_fillunit_ecc_status_r()                             (0x00100e98U)
+#define fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()  (U32(0x1U) << 0U)
+#define fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m()\
+				(U32(0x1U) << 1U)
+#define fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m() (U32(0x1U) << 2U)
+#define fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m()\
+				(U32(0x1U) << 3U)
+#define fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 16U)
+#define fb_mmu_fillunit_ecc_status_corrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 17U)
+#define fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 18U)
+#define fb_mmu_fillunit_ecc_status_uncorrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 19U)
+#define fb_mmu_fillunit_ecc_status_reset_clear_f()                 (0x40000000U)
+#define fb_mmu_fillunit_ecc_corrected_err_count_r()                (0x00100e9cU)
+#define fb_mmu_fillunit_ecc_corrected_err_count_total_s()                  (16U)
+#define fb_mmu_fillunit_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define fb_mmu_fillunit_ecc_corrected_err_count_unique_s()                 (16U)
+#define fb_mmu_fillunit_ecc_corrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_fillunit_ecc_uncorrected_err_count_r()              (0x00100ea0U)
+#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_s()                (16U)
+#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define fb_mmu_fillunit_ecc_uncorrected_err_count_unique_s()               (16U)
+#define fb_mmu_fillunit_ecc_uncorrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_fillunit_ecc_address_r()                            (0x00100ea4U)
+#define fb_niso_cfg1_r()                                           (0x00100c14U)
+#define fb_niso_cfg1_sysmem_nvlink_m()                        (U32(0x1U) << 17U)
+#define fb_niso_cfg1_sysmem_nvlink_enabled_f()                        (0x20000U)
+#define fb_niso_flush_sysmem_addr_r()                              (0x00100c10U)
+#define fb_mmu_fault_buffer_lo_r(i)\
+		(nvgpu_safe_add_u32(0x00100e24U, nvgpu_safe_mult_u32((i), 20U)))
+#define fb_mmu_fault_buffer_lo_addr_f(v)            ((U32(v) & 0xfffffU) << 12U)
+#define fb_mmu_fault_buffer_hi_r(i)\
+		(nvgpu_safe_add_u32(0x00100e28U, nvgpu_safe_mult_u32((i), 20U)))
+#define fb_mmu_fault_buffer_hi_addr_f(v)          ((U32(v) & 0xffffffffU) << 0U)
+#define fb_mmu_fault_buffer_get_r(i)\
+		(nvgpu_safe_add_u32(0x00100e2cU, nvgpu_safe_mult_u32((i), 20U)))
+#define fb_mmu_fault_buffer_get_ptr_f(v)             ((U32(v) & 0xfffffU) << 0U)
+#define fb_mmu_fault_buffer_get_ptr_m()                    (U32(0xfffffU) << 0U)
+#define fb_mmu_fault_buffer_get_ptr_v(r)                (((r) >> 0U) & 0xfffffU)
+#define fb_mmu_fault_buffer_get_getptr_corrupted_m()          (U32(0x1U) << 30U)
+#define fb_mmu_fault_buffer_get_getptr_corrupted_clear_f()         (0x40000000U)
+#define fb_mmu_fault_buffer_get_overflow_m()                  (U32(0x1U) << 31U)
+#define fb_mmu_fault_buffer_get_overflow_clear_f()                 (0x80000000U)
+#define fb_mmu_fault_buffer_put_r(i)\
+		(nvgpu_safe_add_u32(0x00100e30U, nvgpu_safe_mult_u32((i), 20U)))
+#define fb_mmu_fault_buffer_put_ptr_v(r)                (((r) >> 0U) & 0xfffffU)
+#define fb_mmu_fault_buffer_size_r(i)\
+		(nvgpu_safe_add_u32(0x00100e34U, nvgpu_safe_mult_u32((i), 20U)))
+#define fb_mmu_fault_buffer_size_val_f(v)            ((U32(v) & 0xfffffU) << 0U)
+#define fb_mmu_fault_buffer_size_val_v(r)               (((r) >> 0U) & 0xfffffU)
+#define fb_mmu_fault_buffer_size_overflow_intr_enable_f()          (0x20000000U)
+#define fb_mmu_fault_buffer_size_enable_m()                   (U32(0x1U) << 31U)
+#define fb_mmu_fault_buffer_size_enable_v(r)               (((r) >> 31U) & 0x1U)
+#define fb_mmu_fault_buffer_size_enable_true_f()                   (0x80000000U)
+#define fb_mmu_fault_addr_lo_r()                                   (0x00100e4cU)
+#define fb_mmu_fault_addr_lo_phys_aperture_v(r)             (((r) >> 0U) & 0x3U)
+#define fb_mmu_fault_addr_lo_addr_v(r)                 (((r) >> 12U) & 0xfffffU)
+#define fb_mmu_fault_addr_hi_r()                                   (0x00100e50U)
+#define fb_mmu_fault_addr_hi_addr_v(r)               (((r) >> 0U) & 0xffffffffU)
+#define fb_mmu_fault_inst_lo_r()                                   (0x00100e54U)
+#define fb_mmu_fault_inst_lo_engine_id_v(r)               (((r) >> 0U) & 0x1ffU)
+#define fb_mmu_fault_inst_lo_aperture_v(r)                 (((r) >> 10U) & 0x3U)
+#define fb_mmu_fault_inst_lo_addr_v(r)                 (((r) >> 12U) & 0xfffffU)
+#define fb_mmu_fault_inst_hi_r()                                   (0x00100e58U)
+#define fb_mmu_fault_inst_hi_addr_v(r)               (((r) >> 0U) & 0xffffffffU)
+#define fb_mmu_fault_info_r()                                      (0x00100e5cU)
+#define fb_mmu_fault_info_fault_type_v(r)                  (((r) >> 0U) & 0x1fU)
+#define fb_mmu_fault_info_replayable_fault_v(r)             (((r) >> 7U) & 0x1U)
+#define fb_mmu_fault_info_client_v(r)                      (((r) >> 8U) & 0x7fU)
+#define fb_mmu_fault_info_access_type_v(r)                 (((r) >> 16U) & 0xfU)
+#define fb_mmu_fault_info_client_type_v(r)                 (((r) >> 20U) & 0x1U)
+#define fb_mmu_fault_info_gpc_id_v(r)                     (((r) >> 24U) & 0x1fU)
+#define fb_mmu_fault_info_protected_mode_v(r)              (((r) >> 29U) & 0x1U)
+#define fb_mmu_fault_info_replayable_fault_en_v(r)         (((r) >> 30U) & 0x1U)
+#define fb_mmu_fault_info_valid_v(r)                       (((r) >> 31U) & 0x1U)
+#define fb_mmu_fault_status_r()                                    (0x00100e60U)
+#define fb_mmu_fault_status_dropped_bar1_phys_set_f()                     (0x1U)
+#define fb_mmu_fault_status_dropped_bar1_virt_set_f()                     (0x2U)
+#define fb_mmu_fault_status_dropped_bar2_phys_set_f()                     (0x4U)
+#define fb_mmu_fault_status_dropped_bar2_virt_set_f()                     (0x8U)
+#define fb_mmu_fault_status_dropped_ifb_phys_set_f()                     (0x10U)
+#define fb_mmu_fault_status_dropped_ifb_virt_set_f()                     (0x20U)
+#define fb_mmu_fault_status_dropped_other_phys_set_f()                   (0x40U)
+#define fb_mmu_fault_status_dropped_other_virt_set_f()                   (0x80U)
+#define fb_mmu_fault_status_replayable_m()                     (U32(0x1U) << 8U)
+#define fb_mmu_fault_status_replayable_error_m()              (U32(0x1U) << 10U)
+#define fb_mmu_fault_status_non_replayable_error_m()          (U32(0x1U) << 11U)
+#define fb_mmu_fault_status_replayable_overflow_m()           (U32(0x1U) << 12U)
+#define fb_mmu_fault_status_non_replayable_overflow_m()       (U32(0x1U) << 13U)
+#define fb_mmu_fault_status_replayable_getptr_corrupted_m()   (U32(0x1U) << 14U)
+#define fb_mmu_fault_status_non_replayable_getptr_corrupted_m()\
+				(U32(0x1U) << 15U)
+#define fb_mmu_fault_status_busy_true_f()                          (0x40000000U)
+#define fb_mmu_fault_status_valid_m()                         (U32(0x1U) << 31U)
+#define fb_mmu_fault_status_valid_set_f()                          (0x80000000U)
+#define fb_mmu_fault_status_valid_clear_f()                        (0x80000000U)
+#define fb_mmu_local_memory_range_r()                              (0x00100ce0U)
+#define fb_mmu_local_memory_range_lower_scale_v(r)          (((r) >> 0U) & 0xfU)
+#define fb_mmu_local_memory_range_lower_mag_v(r)           (((r) >> 4U) & 0x3fU)
+#define fb_mmu_local_memory_range_ecc_mode_v(r)            (((r) >> 30U) & 0x1U)
+#define fb_niso_scrub_status_r()                                   (0x00100b20U)
+#define fb_niso_scrub_status_flag_v(r)                      (((r) >> 0U) & 0x1U)
+#define fb_mmu_int_vector_info_fault_r()                           (0x00100ee0U)
+#define fb_mmu_int_vector_info_fault_vector_v(r)         (((r) >> 0U) & 0xffffU)
+#define fb_mmu_int_vector_ecc_error_r()                            (0x00100edcU)
+#define fb_mmu_int_vector_ecc_error_vector_v(r)          (((r) >> 0U) & 0xffffU)
+#define fb_mmu_int_vector_fault_r(i)\
+		(nvgpu_safe_add_u32(0x00100ee4U, nvgpu_safe_mult_u32((i), 4U)))
+#define fb_mmu_int_vector_fault_error_v(r)               (((r) >> 0U) & 0xffffU)
+#define fb_mmu_int_vector_fault_notify_v(r)             (((r) >> 16U) & 0xffffU)
+#define fb_mmu_num_active_ltcs_r()                                 (0x00100ec0U)
+#define fb_mmu_num_active_ltcs_count_v(r)                  (((r) >> 0U) & 0x1fU)
+#define fb_mmu_cbc_base_r()                                        (0x00100ec4U)
+#define fb_mmu_cbc_base_address_f(v)               ((U32(v) & 0x3ffffffU) << 0U)
+#define fb_mmu_cbc_base_address_alignment_shift_v()                (0x0000000bU)
+#define fb_mmu_cbc_top_r()                                         (0x00100ec8U)
+#define fb_mmu_cbc_top_size_f(v)                      ((U32(v) & 0x7fffU) << 0U)
+#define fb_mmu_cbc_max_r()                                         (0x00100eccU)
+#define fb_mmu_cbc_max_comptagline_f(v)             ((U32(v) & 0xffffffU) << 0U)
+#define fb_mmu_cbc_max_comptagline_m()                    (U32(0xffffffU) << 0U)
+#define fb_mmu_vpr_mode_r()                                        (0x001fa800U)
+#define fb_mmu_vpr_mode_fetch_f(v)                       ((U32(v) & 0x1U) << 2U)
+#define fb_mmu_vpr_mode_fetch_v(r)                          (((r) >> 2U) & 0x1U)
+#define fb_mmu_vpr_mode_fetch_false_v()                            (0x00000000U)
+#define fb_mmu_vpr_mode_fetch_true_f()                                    (0x4U)
+#define fb_mmu_vpr_addr_lo_r()                                     (0x001fa804U)
+#define fb_mmu_vpr_addr_lo_val_v(r)                   (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_vpr_addr_lo_val_alignment_v()                       (0x0000000cU)
+#define fb_mmu_vpr_addr_hi_r()                                     (0x001fa808U)
+#define fb_mmu_vpr_addr_hi_val_v(r)                   (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_vpr_addr_hi_val_alignment_v()                       (0x0000000cU)
+#define fb_mmu_vpr_cya_lo_r()                                      (0x001fa80cU)
+#define fb_mmu_vpr_cya_hi_r()                                      (0x001fa810U)
+#define fb_mmu_wpr1_addr_lo_r()                                    (0x001fa81cU)
+#define fb_mmu_wpr1_addr_lo_val_v(r)                  (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_wpr1_addr_lo_val_alignment_v()                      (0x0000000cU)
+#define fb_mmu_wpr1_addr_hi_r()                                    (0x001fa820U)
+#define fb_mmu_wpr1_addr_hi_val_v(r)                  (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_wpr1_addr_hi_val_alignment_v()                      (0x0000000cU)
+#define fb_mmu_wpr2_addr_lo_r()                                    (0x001fa824U)
+#define fb_mmu_wpr2_addr_lo_val_v(r)                  (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_wpr2_addr_lo_val_alignment_v()                      (0x0000000cU)
+#define fb_mmu_wpr2_addr_hi_r()                                    (0x001fa828U)
+#define fb_mmu_wpr2_addr_hi_val_v(r)                  (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_wpr2_addr_hi_val_alignment_v()                      (0x0000000cU)
+#define fb_mmu_wpr_allow_read_r()                                  (0x001fa814U)
+#define fb_mmu_wpr_allow_write_r()                                 (0x001fa818U)
+#define fb_mmu_smc_eng_cfg_0_r(i)\
+		(nvgpu_safe_add_u32(0x001f94c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define fb_mmu_smc_eng_cfg_0_remote_swizid_f(v)          ((U32(v) & 0xfU) << 0U)
+#define fb_mmu_smc_eng_cfg_0_remote_swizid_m()                 (U32(0xfU) << 0U)
+#define fb_mmu_smc_eng_cfg_0_mmu_eng_veid_offset_f(v)  ((U32(v) & 0x3fU) << 16U)
+#define fb_mmu_smc_eng_cfg_0_mmu_eng_veid_offset_m()         (U32(0x3fU) << 16U)
+#define fb_mmu_smc_eng_cfg_0_veid_max_f(v)             ((U32(v) & 0x3fU) << 24U)
+#define fb_mmu_smc_eng_cfg_0_veid_max_m()                    (U32(0x3fU) << 24U)
+#define fb_mmu_smc_eng_cfg_1_r(i)\
+		(nvgpu_safe_add_u32(0x001f94e0U, nvgpu_safe_mult_u32((i), 4U)))
+#define fb_mmu_smc_eng_cfg_1_gpc_mask_f(v)            ((U32(v) & 0xffffU) << 0U)
+#define fb_mmu_smc_eng_cfg_1_gpc_mask_m()                   (U32(0xffffU) << 0U)
+#define fb_mmu_mmu_eng_id_cfg_r(i)\
+		(nvgpu_safe_add_u32(0x001f9600U, nvgpu_safe_mult_u32((i), 4U)))
+#define fb_mmu_mmu_eng_id_cfg_remote_swizid_f(v)         ((U32(v) & 0xfU) << 0U)
+#define fb_mmu_mmu_eng_id_cfg_remote_swizid_m()                (U32(0xfU) << 0U)
+#define fb_mmu_hypervisor_ctl_r()                                  (0x00100ed0U)
+#define fb_mmu_hypervisor_ctl_use_smc_veid_tables_f(v)   ((U32(v) & 0x1U) << 3U)
+#define fb_mmu_hypervisor_ctl_use_smc_veid_tables_m()          (U32(0x1U) << 3U)
+#define fb_mmu_hypervisor_ctl_use_smc_veid_tables_enable_v()       (0x00000001U)
+#define fb_mmu_hypervisor_ctl_use_smc_veid_tables_disable_v()      (0x00000000U)
+#define fb_hshub_prg_config_r(i)\
+		(nvgpu_safe_add_u32(0x00004c7cU, nvgpu_safe_mult_u32((i), 8192U)))
+#define fb_hshub_prg_config_num_hshubs_v(r)                 (((r) >> 1U) & 0x3U)
+#define fb_hshub_num_active_ltcs_r(i)\
+		(nvgpu_safe_add_u32(0x00004c20U, nvgpu_safe_mult_u32((i), 8192U)))
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fbpa_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fbpa_ga100.h
new file mode 100644
index 000000000..59d5f0393
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fbpa_ga100.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_FBPA_GA100_H
+#define NVGPU_HW_FBPA_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define fbpa_0_intr_status_r()                                     (0x00900398U)
+#define fbpa_0_intr_status_sec_subp0_pending_f()                          (0x1U)
+#define fbpa_0_intr_status_ded_subp0_pending_f()                          (0x2U)
+#define fbpa_0_intr_status_sec_subp1_pending_f()                      (0x10000U)
+#define fbpa_0_intr_status_ded_subp1_pending_f()                      (0x20000U)
+#define fbpa_ecc_intr_ctrl_r()                                     (0x009a0474U)
+#define fbpa_ecc_intr_ctrl_sec_intr_en_enabled_f()                        (0x1U)
+#define fbpa_ecc_intr_ctrl_ded_intr_en_enabled_f()                        (0x2U)
+#define fbpa_0_ecc_status_r(i)\
+		(nvgpu_safe_add_u32(0x00900478U, nvgpu_safe_mult_u32((i), 4U)))
+#define fbpa_0_ecc_status_sec_intr_pending_f()                            (0x2U)
+#define fbpa_0_ecc_status_ded_intr_pending_f()                            (0x4U)
+#define fbpa_0_ecc_status_sec_counter_overflow_pending_f()            (0x20000U)
+#define fbpa_0_ecc_status_ded_counter_overflow_pending_f()            (0x40000U)
+#define fbpa_0_ecc_sec_count_r(i)\
+		(nvgpu_safe_add_u32(0x00900480U, nvgpu_safe_mult_u32((i), 4U)))
+#define fbpa_0_ecc_ded_count_r(i)\
+		(nvgpu_safe_add_u32(0x00900488U, nvgpu_safe_mult_u32((i), 4U)))
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_flush_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_flush_ga100.h
new file mode 100644
index 000000000..3c49ec9ed
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_flush_ga100.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_FLUSH_GA100_H
+#define NVGPU_HW_FLUSH_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define flush_l2_system_invalidate_r()                             (0x00070004U)
+#define flush_l2_system_invalidate_pending_v(r)             (((r) >> 0U) & 0x1U)
+#define flush_l2_system_invalidate_pending_busy_v()                (0x00000001U)
+#define flush_l2_system_invalidate_pending_busy_f()                       (0x1U)
+#define flush_l2_system_invalidate_outstanding_v(r)         (((r) >> 1U) & 0x1U)
+#define flush_l2_system_invalidate_outstanding_true_v()            (0x00000001U)
+#define flush_l2_flush_dirty_r()                                   (0x00070010U)
+#define flush_l2_flush_dirty_pending_v(r)                   (((r) >> 0U) & 0x1U)
+#define flush_l2_flush_dirty_pending_busy_v()                      (0x00000001U)
+#define flush_l2_flush_dirty_pending_busy_f()                             (0x1U)
+#define flush_l2_flush_dirty_outstanding_v(r)               (((r) >> 1U) & 0x1U)
+#define flush_l2_flush_dirty_outstanding_true_v()                  (0x00000001U)
+#define flush_l2_clean_comptags_r()                                (0x0007000cU)
+#define flush_l2_clean_comptags_pending_v(r)                (((r) >> 0U) & 0x1U)
+#define flush_l2_clean_comptags_pending_busy_v()                   (0x00000001U)
+#define flush_l2_clean_comptags_pending_busy_f()                          (0x1U)
+#define flush_l2_clean_comptags_outstanding_v(r)            (((r) >> 1U) & 0x1U)
+#define flush_l2_clean_comptags_outstanding_true_v()               (0x00000001U)
+#define flush_fb_flush_r()                                         (0x00070000U)
+#define flush_fb_flush_pending_v(r)                         (((r) >> 0U) & 0x1U)
+#define flush_fb_flush_pending_busy_v()                            (0x00000001U)
+#define flush_fb_flush_pending_busy_f()                                   (0x1U)
+#define flush_fb_flush_outstanding_v(r)                     (((r) >> 1U) & 0x1U)
+#define flush_fb_flush_outstanding_true_v()                        (0x00000001U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_func_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_func_ga100.h
new file mode 100644
index 000000000..9c8924c57
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_func_ga100.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_FUNC_GA100_H
+#define NVGPU_HW_FUNC_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define func_full_phys_offset_v()                                  (0x00b80000U)
+#define func_doorbell_r()                                          (0x00030090U)
+#define func_cfg0_r()                                              (0x00030000U)
+#define func_priv_cpu_intr_top_en_set_r(i)\
+		(nvgpu_safe_add_u32(0x00001608U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_top_en_clear_r(i)\
+		(nvgpu_safe_add_u32(0x00001610U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_top_en_clear__size_1_v()                (0x00000001U)
+#define func_priv_cpu_intr_top_en_set_r(i)\
+		(nvgpu_safe_add_u32(0x00001608U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_leaf_en_set_r(i)\
+		(nvgpu_safe_add_u32(0x00001200U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_leaf_en_clear_r(i)\
+		(nvgpu_safe_add_u32(0x00001400U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_top_r(i)\
+		(nvgpu_safe_add_u32(0x00001600U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_top__size_1_v()                         (0x00000001U)
+#define func_priv_cpu_intr_leaf_r(i)\
+		(nvgpu_safe_add_u32(0x00001000U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_leaf__size_1_v()                        (0x00000008U)
+#define func_priv_mmu_fault_buffer_lo_r(i)\
+		(nvgpu_safe_add_u32(0x00003000U, nvgpu_safe_mult_u32((i), 32U)))
+#define func_priv_mmu_fault_buffer_hi_r(i)\
+		(nvgpu_safe_add_u32(0x00003004U, nvgpu_safe_mult_u32((i), 32U)))
+#define func_priv_mmu_fault_buffer_get_r(i)\
+		(nvgpu_safe_add_u32(0x00003008U, nvgpu_safe_mult_u32((i), 32U)))
+#define func_priv_mmu_fault_buffer_put_r(i)\
+		(nvgpu_safe_add_u32(0x0000300cU, nvgpu_safe_mult_u32((i), 32U)))
+#define func_priv_mmu_fault_buffer_size_r(i)\
+		(nvgpu_safe_add_u32(0x00003010U, nvgpu_safe_mult_u32((i), 32U)))
+#define func_priv_mmu_fault_addr_lo_r()                            (0x00003080U)
+#define func_priv_mmu_fault_addr_hi_r()                            (0x00003084U)
+#define func_priv_mmu_fault_inst_lo_r()                            (0x00003088U)
+#define func_priv_mmu_fault_inst_hi_r()                            (0x0000308cU)
+#define func_priv_mmu_fault_info_r()                               (0x00003090U)
+#define func_priv_mmu_fault_status_r()                             (0x00003094U)
+#define func_priv_bar2_block_r()                                   (0x00000f48U)
+#define func_priv_bind_status_r()                                  (0x00000f50U)
+#define func_priv_mmu_invalidate_pdb_r()                           (0x000030a0U)
+#define func_priv_mmu_invalidate_r()                               (0x000030b0U)
+#define func_priv_cpu_intr_pfb_vector_v()                          (0x0000008dU)
+#define func_priv_cpu_intr_pmu_vector_v()                          (0x00000098U)
+#define func_priv_cpu_intr_ltc_all_vector_v()                      (0x00000099U)
+#define func_priv_cpu_intr_pbus_vector_v()                         (0x0000009cU)
+#define func_priv_cpu_intr_priv_ring_vector_v()                    (0x0000009eU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fuse_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fuse_ga100.h
new file mode 100644
index 000000000..65b6e5a81
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_fuse_ga100.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_FUSE_GA100_H
+#define NVGPU_HW_FUSE_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define fuse_status_opt_gpc_r()                                    (0x00820c1cU)
+#define fuse_status_opt_tpc_gpc_r(i)\
+		(nvgpu_safe_add_u32(0x00820c38U, nvgpu_safe_mult_u32((i), 4U)))
+#define fuse_ctrl_opt_tpc_gpc_r(i)\
+		(nvgpu_safe_add_u32(0x00820838U, nvgpu_safe_mult_u32((i), 4U)))
+#define fuse_status_opt_fbio_r()                                   (0x00820c14U)
+#define fuse_status_opt_rop_l2_fbp_r(i)\
+		(nvgpu_safe_add_u32(0x00820d70U, nvgpu_safe_mult_u32((i), 4U)))
+#define fuse_status_opt_fbp_r()                                    (0x00820d38U)
+#define fuse_opt_ecc_en_r()                                        (0x00820228U)
+#define fuse_opt_feature_fuses_override_disable_r()                (0x008203f0U)
+#define fuse_opt_priv_sec_en_r()                                   (0x00820434U)
+#define fuse_opt_sm_ttu_en_r()                                     (0x00820168U)
+#define fuse_feature_override_ecc_r()                              (0x0082380cU)
+#define fuse_feature_override_ecc_sm_lrf_v(r)               (((r) >> 0U) & 0x1U)
+#define fuse_feature_override_ecc_sm_lrf_enabled_v()               (0x00000001U)
+#define fuse_feature_override_ecc_sm_lrf_override_v(r)      (((r) >> 3U) & 0x1U)
+#define fuse_feature_override_ecc_sm_lrf_override_true_v()         (0x00000001U)
+#define fuse_feature_override_ecc_sm_l1_data_v(r)           (((r) >> 4U) & 0x1U)
+#define fuse_feature_override_ecc_sm_l1_data_enabled_v()           (0x00000001U)
+#define fuse_feature_override_ecc_sm_l1_data_override_v(r)  (((r) >> 7U) & 0x1U)
+#define fuse_feature_override_ecc_sm_l1_data_override_true_v()     (0x00000001U)
+#define fuse_feature_override_ecc_sm_l1_tag_v(r)            (((r) >> 8U) & 0x1U)
+#define fuse_feature_override_ecc_sm_l1_tag_enabled_v()            (0x00000001U)
+#define fuse_feature_override_ecc_sm_l1_tag_override_v(r)  (((r) >> 11U) & 0x1U)
+#define fuse_feature_override_ecc_sm_l1_tag_override_true_v()      (0x00000001U)
+#define fuse_feature_override_ecc_ltc_v(r)                 (((r) >> 12U) & 0x1U)
+#define fuse_feature_override_ecc_ltc_enabled_v()                  (0x00000001U)
+#define fuse_feature_override_ecc_ltc_override_v(r)        (((r) >> 15U) & 0x1U)
+#define fuse_feature_override_ecc_ltc_override_true_v()            (0x00000001U)
+#define fuse_feature_override_ecc_dram_v(r)                (((r) >> 16U) & 0x1U)
+#define fuse_feature_override_ecc_dram_enabled_v()                 (0x00000001U)
+#define fuse_feature_override_ecc_dram_override_v(r)       (((r) >> 19U) & 0x1U)
+#define fuse_feature_override_ecc_dram_override_true_v()           (0x00000001U)
+#define fuse_feature_override_ecc_sm_cbu_v(r)              (((r) >> 20U) & 0x1U)
+#define fuse_feature_override_ecc_sm_cbu_enabled_v()               (0x00000001U)
+#define fuse_feature_override_ecc_sm_cbu_override_v(r)     (((r) >> 23U) & 0x1U)
+#define fuse_feature_override_ecc_sm_cbu_override_true_v()         (0x00000001U)
+#define fuse_feature_override_ecc_1_r()                            (0x00823810U)
+#define fuse_feature_override_ecc_1_sm_l0_icache_v(r)       (((r) >> 0U) & 0x1U)
+#define fuse_feature_override_ecc_1_sm_l0_icache_enabled_v()       (0x00000001U)
+#define fuse_feature_override_ecc_1_sm_l0_icache_override_v(r)\
+				(((r) >> 1U) & 0x1U)
+#define fuse_feature_override_ecc_1_sm_l0_icache_override_true_v() (0x00000001U)
+#define fuse_feature_override_ecc_1_sm_l1_icache_v(r)       (((r) >> 2U) & 0x1U)
+#define fuse_feature_override_ecc_1_sm_l1_icache_enabled_v()       (0x00000001U)
+#define fuse_feature_override_ecc_1_sm_l1_icache_override_v(r)\
+				(((r) >> 3U) & 0x1U)
+#define fuse_feature_override_ecc_1_sm_l1_icache_override_true_v() (0x00000001U)
+#define fuse_opt_pdi_0_r()                                         (0x00820344U)
+#define fuse_opt_pdi_1_r()                                         (0x00820348U)
+#define fuse_sec2_ucode1_version_r()                               (0x00824140U)
+#define fuse_gsp_ucode1_version_r()                                (0x008241c0U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gc6_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gc6_ga100.h
new file mode 100644
index 000000000..e84868340
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gc6_ga100.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_GC6_GA100_H
+#define NVGPU_HW_GC6_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define gc6_aon_secure_scratch_group_05_r(i)\
+		(nvgpu_safe_add_u32(0x00118234U, nvgpu_safe_mult_u32((i), 4U)))
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gmmu_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gmmu_ga100.h
new file mode 100644
index 000000000..86ef80555
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gmmu_ga100.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_GMMU_GA100_H
+#define NVGPU_HW_GMMU_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define gmmu_new_pde_aperture_video_memory_f()                            (0x2U)
+#define gmmu_new_pde_aperture_sys_mem_coh_f()                             (0x4U)
+#define gmmu_new_pde_aperture_sys_mem_ncoh_f()                            (0x6U)
+#define gmmu_new_pde_address_sys_f(v)               ((U32(v) & 0xffffffU) << 8U)
+#define gmmu_new_pde_vol_true_f()                                         (0x8U)
+#define gmmu_new_pde_address_shift_v()                             (0x0000000cU)
+#define gmmu_new_dual_pde_aperture_big_video_memory_f()                   (0x2U)
+#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f()                    (0x4U)
+#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f()                   (0x6U)
+#define gmmu_new_dual_pde_address_big_sys_f(v)     ((U32(v) & 0xfffffffU) << 4U)
+#define gmmu_new_dual_pde_aperture_small_video_memory_f()                 (0x2U)
+#define gmmu_new_dual_pde_aperture_small_sys_mem_coh_f()                  (0x4U)
+#define gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f()                 (0x6U)
+#define gmmu_new_dual_pde_vol_small_true_f()                              (0x8U)
+#define gmmu_new_dual_pde_vol_big_true_f()                                (0x8U)
+#define gmmu_new_dual_pde_address_small_sys_f(v)    ((U32(v) & 0xffffffU) << 8U)
+#define gmmu_new_dual_pde_address_shift_v()                        (0x0000000cU)
+#define gmmu_new_dual_pde_address_big_shift_v()                    (0x00000008U)
+#define gmmu_new_pte_valid_true_f()                                       (0x1U)
+#define gmmu_new_pte_valid_false_f()                                      (0x0U)
+#define gmmu_new_pte_privilege_true_f()                                  (0x20U)
+#define gmmu_new_pte_address_sys_f(v)               ((U32(v) & 0xffffffU) << 8U)
+#define gmmu_new_pte_address_vid_f(v)               ((U32(v) & 0xffffffU) << 8U)
+#define gmmu_new_pte_vol_true_f()                                         (0x8U)
+#define gmmu_new_pte_aperture_video_memory_f()                            (0x0U)
+#define gmmu_new_pte_aperture_sys_mem_coh_f()                             (0x4U)
+#define gmmu_new_pte_aperture_sys_mem_ncoh_f()                            (0x6U)
+#define gmmu_new_pte_read_only_true_f()                                  (0x40U)
+#define gmmu_new_pte_comptagline_f(v)                ((U32(v) & 0xfffffU) << 4U)
+#define gmmu_new_pte_kind_f(v)                         ((U32(v) & 0xffU) << 24U)
+#define gmmu_new_pte_address_shift_v()                             (0x0000000cU)
+#define gmmu_pte_kind_f(v)                              ((U32(v) & 0xffU) << 4U)
+#define gmmu_fault_fault_type_atomic_violation_v()                 (0x0000000fU)
+#define gmmu_fault_client_gpc_rop_3_v()                            (0x00000073U)
+#define gmmu_fault_client_hub_esc_v()                              (0x00000063U)
+#define gmmu_fault_client_type_gpc_v()                             (0x00000000U)
+#define gmmu_fault_client_type_hub_v()                             (0x00000001U)
+#define gmmu_fault_type_unbound_inst_block_v()                     (0x00000004U)
+#define gmmu_fault_type_pte_v()                                    (0x00000002U)
+#define gmmu_fault_mmu_eng_id_bar2_v()                             (0x000000c0U)
+#define gmmu_fault_mmu_eng_id_physical_v()                         (0x0000001fU)
+#define gmmu_fault_mmu_eng_id_ce0_v()                              (0x0000000fU)
+#define gmmu_fault_buf_size_v()                                    (0x00000020U)
+#define gmmu_fault_buf_entry_inst_aperture_v(r)             (((r) >> 8U) & 0x3U)
+#define gmmu_fault_buf_entry_inst_lo_v(r)              (((r) >> 12U) & 0xfffffU)
+#define gmmu_fault_buf_entry_inst_lo_b()                                   (12U)
+#define gmmu_fault_buf_entry_inst_lo_w()                                    (0U)
+#define gmmu_fault_buf_entry_inst_hi_v(r)            (((r) >> 0U) & 0xffffffffU)
+#define gmmu_fault_buf_entry_inst_hi_w()                                    (1U)
+#define gmmu_fault_buf_entry_addr_phys_aperture_v(r)        (((r) >> 0U) & 0x3U)
+#define gmmu_fault_buf_entry_addr_lo_v(r)              (((r) >> 12U) & 0xfffffU)
+#define gmmu_fault_buf_entry_addr_lo_b()                                   (12U)
+#define gmmu_fault_buf_entry_addr_lo_w()                                    (2U)
+#define gmmu_fault_buf_entry_addr_hi_v(r)            (((r) >> 0U) & 0xffffffffU)
+#define gmmu_fault_buf_entry_addr_hi_w()                                    (3U)
+#define gmmu_fault_buf_entry_timestamp_lo_v(r)       (((r) >> 0U) & 0xffffffffU)
+#define gmmu_fault_buf_entry_timestamp_lo_w()                               (4U)
+#define gmmu_fault_buf_entry_timestamp_hi_v(r)       (((r) >> 0U) & 0xffffffffU)
+#define gmmu_fault_buf_entry_timestamp_hi_w()                               (5U)
+#define gmmu_fault_buf_entry_engine_id_v(r)               (((r) >> 0U) & 0x1ffU)
+#define gmmu_fault_buf_entry_engine_id_w()                                  (6U)
+#define gmmu_fault_buf_entry_fault_type_v(r)               (((r) >> 0U) & 0x1fU)
+#define gmmu_fault_buf_entry_fault_type_w()                                 (7U)
+#define gmmu_fault_buf_entry_replayable_fault_v(r)          (((r) >> 7U) & 0x1U)
+#define gmmu_fault_buf_entry_replayable_fault_true_v()             (0x00000001U)
+#define gmmu_fault_buf_entry_client_v(r)                   (((r) >> 8U) & 0x7fU)
+#define gmmu_fault_buf_entry_access_type_v(r)              (((r) >> 16U) & 0xfU)
+#define gmmu_fault_buf_entry_mmu_client_type_v(r)          (((r) >> 20U) & 0x1U)
+#define gmmu_fault_buf_entry_gpc_id_v(r)                  (((r) >> 24U) & 0x1fU)
+#define gmmu_fault_buf_entry_protected_mode_v(r)           (((r) >> 29U) & 0x1U)
+#define gmmu_fault_buf_entry_replayable_fault_en_v(r)      (((r) >> 30U) & 0x1U)
+#define gmmu_fault_buf_entry_valid_m()                        (U32(0x1U) << 31U)
+#define gmmu_fault_buf_entry_valid_v(r)                    (((r) >> 31U) & 0x1U)
+#define gmmu_fault_buf_entry_valid_w()                                      (7U)
+#define gmmu_fault_buf_entry_valid_true_v()                        (0x00000001U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h
new file mode 100644
index 000000000..d1e5f374c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h
@@ -0,0 +1,1256 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_GR_GA100_H
+#define NVGPU_HW_GR_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define gr_intr_notify_ctrl_r()                                    (0x00400160U)
+#define gr_intr_notify_ctrl_vector_f(v)                ((U32(v) & 0xfffU) << 0U)
+#define gr_intr_notify_ctrl_cpu_enable_f()                         (0x80000000U)
+#define gr_intr_notify_ctrl_gsp_enable_f()                         (0x40000000U)
+#define gr_intr_r()                                                (0x00400100U)
+#define gr_intr_notify_pending_f()                                        (0x1U)
+#define gr_intr_semaphore_pending_f()                                     (0x2U)
+#define gr_intr_illegal_method_pending_f()                               (0x10U)
+#define gr_intr_illegal_class_pending_f()                                (0x20U)
+#define gr_intr_illegal_notify_pending_f()                               (0x40U)
+#define gr_intr_debug_method_pending_f()                                 (0x80U)
+#define gr_intr_firmware_method_pending_f()                             (0x100U)
+#define gr_intr_buffer_notify_pending_f()                             (0x10000U)
+#define gr_intr_fecs_error_pending_f()                                (0x80000U)
+#define gr_intr_class_error_pending_f()                              (0x100000U)
+#define gr_intr_exception_pending_f()                                (0x200000U)
+#define gr_fecs_intr_r()                                           (0x00400144U)
+#define gr_class_error_r()                                         (0x00400110U)
+#define gr_class_error_code_v(r)                         (((r) >> 0U) & 0xffffU)
+#define gr_intr_en_r()                                             (0x0040013cU)
+#define gr_intr_en_notify__prod_f()                                       (0x1U)
+#define gr_intr_en_semaphore__prod_f()                                    (0x2U)
+#define gr_intr_en_illegal_method__prod_f()                              (0x10U)
+#define gr_intr_en_illegal_class__prod_f()                               (0x20U)
+#define gr_intr_en_illegal_notify__prod_f()                              (0x40U)
+#define gr_intr_en_debug_method__prod_f()                                (0x80U)
+#define gr_intr_en_firmware_method__prod_f()                            (0x100U)
+#define gr_intr_en_buffer_notify__prod_f()                            (0x10000U)
+#define gr_intr_en_fecs_error__prod_f()                               (0x80000U)
+#define gr_intr_en_class_error__prod_f()                             (0x100000U)
+#define gr_intr_en_exception__prod_f()                               (0x200000U)
+#define gr_intr_en_fe_debug_intr__prod_f()                           (0x400000U)
+#define gr_intr_retrigger_r()                                      (0x00400158U)
+#define gr_intr_retrigger_trigger_true_f()                                (0x1U)
+#define gr_exception_r()                                           (0x00400108U)
+#define gr_exception_fe_m()                                    (U32(0x1U) << 0U)
+#define gr_exception_gpc_m()                                  (U32(0x1U) << 24U)
+#define gr_exception_memfmt_m()                                (U32(0x1U) << 1U)
+#define gr_exception_ds_m()                                    (U32(0x1U) << 4U)
+#define gr_exception_sked_m()                                  (U32(0x1U) << 8U)
+#define gr_exception_pd_m()                                    (U32(0x1U) << 2U)
+#define gr_exception_scc_m()                                   (U32(0x1U) << 3U)
+#define gr_exception_ssync_m()                                 (U32(0x1U) << 5U)
+#define gr_exception_mme_m()                                   (U32(0x1U) << 7U)
+#define gr_exception1_r()                                          (0x00400118U)
+#define gr_exception1_gpc_0_pending_f()                                   (0x1U)
+#define gr_exception_en_r()                                        (0x00400138U)
+#define gr_exception_en_fe_enabled_f()                                    (0x1U)
+#define gr_exception_en_gpc_enabled_f()                             (0x1000000U)
+#define gr_exception_en_memfmt_enabled_f()                                (0x2U)
+#define gr_exception_en_ds_enabled_f()                                   (0x10U)
+#define gr_exception_en_pd_enabled_f()                                    (0x4U)
+#define gr_exception_en_scc_enabled_f()                                   (0x8U)
+#define gr_exception_en_ssync_enabled_f()                                (0x20U)
+#define gr_exception_en_mme_enabled_f()                                  (0x80U)
+#define gr_exception_en_sked_enabled_f()                                (0x100U)
+#define gr_exception1_en_r()                                       (0x00400130U)
+#define gr_gpfifo_ctl_r()                                          (0x00400500U)
+#define gr_gpfifo_ctl_access_f(v)                        ((U32(v) & 0x1U) << 0U)
+#define gr_gpfifo_ctl_access_enabled_f()                                  (0x1U)
+#define gr_gpfifo_ctl_semaphore_access_f(v)             ((U32(v) & 0x1U) << 16U)
+#define gr_gpfifo_ctl_semaphore_access_enabled_f()                    (0x10000U)
+#define gr_gpfifo_status_r()                                       (0x00400504U)
+#define gr_trapped_addr_r()                                        (0x00400704U)
+#define gr_trapped_addr_mthd_v(r)                         (((r) >> 2U) & 0xfffU)
+#define gr_trapped_addr_subch_v(r)                         (((r) >> 16U) & 0x7U)
+#define gr_trapped_addr_mme_generated_v(r)                 (((r) >> 20U) & 0x1U)
+#define gr_trapped_addr_datahigh_v(r)                      (((r) >> 24U) & 0x1U)
+#define gr_trapped_addr_priv_v(r)                          (((r) >> 28U) & 0x1U)
+#define gr_trapped_data_lo_r()                                     (0x00400708U)
+#define gr_trapped_data_hi_r()                                     (0x0040070cU)
+#define gr_trapped_data_mme_r()                                    (0x00400710U)
+#define gr_trapped_data_mme_pc_v(r)                       (((r) >> 0U) & 0xfffU)
+#define gr_status_r()                                              (0x00400700U)
+#define gr_status_state_v(r)                                (((r) >> 0U) & 0x1U)
+#define gr_status_state_busy_v()                                   (0x00000001U)
+#define gr_status_fe_method_upper_v(r)                      (((r) >> 1U) & 0x1U)
+#define gr_status_fe_method_upper_busy_v()                         (0x00000001U)
+#define gr_status_fe_method_lower_v(r)                      (((r) >> 2U) & 0x1U)
+#define gr_status_fe_method_lower_busy_v()                         (0x00000001U)
+#define gr_status_1_r()                                            (0x00400604U)
+#define gr_engine_config_r()                                       (0x00400614U)
+#define gr_engine_config_supported_3d_true_f()                            (0x1U)
+#define gr_engine_config_supported_compute_true_f()                       (0x2U)
+#define gr_engine_config_supported_i2m_true_f()                           (0x4U)
+#define gr_engine_config_supported_2d_true_f()                            (0x8U)
+#define gr_engine_status_r()                                       (0x0040060cU)
+#define gr_engine_status_value_busy_f()                                   (0x1U)
+#define gr_pri_gpc0_gpccs_gpc_exception_r()                        (0x00502c90U)
+#define gr_pri_gpc0_gpccs_gpc_exception_en_r()                     (0x00502c94U)
+#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_r()                   (0x00504508U)
+#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r()                (0x0050450cU)
+#define gr_activity_0_r()                                          (0x00400380U)
+#define gr_activity_1_r()                                          (0x00400384U)
+#define gr_activity_1_memfmt_b()                                            (6U)
+#define gr_activity_4_r()                                          (0x00400390U)
+#define gr_activity_4_gpc0_s()                                              (3U)
+#define gr_activity_4_gpc0_v(r)                             (((r) >> 0U) & 0x7U)
+#define gr_activity_4_gpc0_empty_v()                               (0x00000000U)
+#define gr_activity_4_gpc0_preempted_v()                           (0x00000004U)
+#define gr_pri_sked_activity_r()                                   (0x00407054U)
+#define gr_pri_gpc0_gpccs_gpc_activity0_r()                        (0x00502c80U)
+#define gr_pri_gpc0_gpccs_gpc_activity1_r()                        (0x00502c84U)
+#define gr_pri_gpc0_gpccs_gpc_activity2_r()                        (0x00502c88U)
+#define gr_pri_gpc0_gpccs_gpc_activity3_r()                        (0x00502c8cU)
+#define gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r()                  (0x00504500U)
+#define gr_pri_gpcs_gpccs_gpc_activity_0_r()                       (0x0041ac80U)
+#define gr_pri_gpcs_gpccs_gpc_activity_1_r()                       (0x0041ac84U)
+#define gr_pri_gpcs_gpccs_gpc_activity_2_r()                       (0x0041ac88U)
+#define gr_pri_gpcs_gpccs_gpc_activity_3_r()                       (0x0041ac8cU)
+#define gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r()                  (0x00419d00U)
+#define gr_pri_ds_mpipe_status_r()                                 (0x00405858U)
+#define gr_pri_fe_go_idle_info_r()                                 (0x00404194U)
+#define gr_pri_fe_chip_def_info_r()                                (0x00404030U)
+#define gr_pri_fe_chip_def_info_max_veid_count_init_v()            (0x00000040U)
+#define gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r()             (0x00504238U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r()                     (0x00504358U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m()\
+				(U32(0x1U) << 0U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m()\
+				(U32(0x1U) << 1U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m()\
+				(U32(0x1U) << 3U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m()\
+				(U32(0x1U) << 8U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m()\
+				(U32(0x1U) << 9U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m()\
+				(U32(0x1U) << 10U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m()\
+				(U32(0x1U) << 11U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 24U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 26U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f()          (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r()        (0x0050435cU)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r()      (0x00504360U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s()        (16U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r()                 (0x0050436cU)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m()\
+				(U32(0x1U) << 0U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 8U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 10U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f()      (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r()    (0x00504370U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r()  (0x00504374U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s()    (16U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r()                     (0x00504638U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m()\
+				(U32(0x1U) << 0U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m()\
+				(U32(0x1U) << 4U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m()\
+				(U32(0x1U) << 6U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 16U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 18U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f()          (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r()        (0x0050463cU)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r()      (0x00504640U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s()        (16U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r()                  (0x00504624U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m()\
+				(U32(0x1U) << 0U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m()\
+				(U32(0x1U) << 4U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m()\
+				(U32(0x1U) << 5U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m()\
+				(U32(0x1U) << 6U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m()\
+				(U32(0x1U) << 7U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 8U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 10U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f()       (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r()     (0x00504628U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s()       (16U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r()   (0x0050462cU)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s()     (16U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_r()                  (0x0050464cU)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m()\
+				(U32(0x1U) << 6U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 16U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 18U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f()       (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r()     (0x00504650U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s()       (16U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r()   (0x00504654U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s()     (16U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_r()                    (0x00504388U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_l0ic_data_m()\
+				(U32(0x1U) << 0U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_l0ic_data_m()\
+				(U32(0x1U) << 8U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_l0ic_predecode_m()\
+				(U32(0x1U) << 1U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_l0ic_predecode_m()\
+				(U32(0x1U) << 9U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_urf_data_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_urf_data_m()\
+				(U32(0x1U) << 10U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 24U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 26U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_reset_task_f()         (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_corrected_err_count_r()       (0x0050438cU)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_corrected_err_count_total_s()         (16U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_uncorrected_err_count_r()     (0x00504390U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_uncorrected_err_count_total_s()       (16U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_r()                    (0x00419b54U)
+#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_task_f()         (0x1U)
+#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_task_f()         (0x2U)
+#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_task_f()         (0x4U)
+#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_task_f()         (0x8U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_r()                    (0x00504354U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_init_f()         (0x0U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_init_f()         (0x0U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_init_f()         (0x0U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_init_f()         (0x0U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 9U)
+#define gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_r()                (0x00419b68U)
+#define gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_task_f()      (0x1U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_r()                (0x00504368U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_init_f()      (0x0U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 3U)
+#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_r()                 (0x00419e20U)
+#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_task_f()       (0x1U)
+#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_pixprf_task_f()     (0x10U)
+#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_miss_fifo_task_f()  (0x20U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r()                 (0x00504620U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_init_f()       (0x0U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_inject_corrected_err_f(v)\
+				((U32(v) & 0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 3U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_pixprf_init_f()      (0x0U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_miss_fifo_init_f()   (0x0U)
+#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_r()                    (0x00419e34U)
+#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_task_f()       (0x1U)
+#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_task_f()    (0x4U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_r()                    (0x00504634U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_init_f()       (0x0U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_init_f()    (0x0U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 5U)
+#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_r()                 (0x00419e48U)
+#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_task_f()     (0x4U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_r()                 (0x00504648U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_init_f()     (0x0U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 5U)
+#define gr_pri_gpcs_tpcs_sm_rams_ecc_control_r()                   (0x00419b84U)
+#define gr_pri_gpcs_tpcs_sm_rams_ecc_control_scrub_l0ic_data_task_f()     (0x1U)
+#define gr_pri_gpcs_tpcs_sm_rams_ecc_control_scrub_l0ic_predecode_task_f()\
+				(0x2U)
+#define gr_pri_gpcs_tpcs_sm_rams_ecc_control_scrub_urf_data_task_f()      (0x4U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_control_r()                   (0x00504384U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_control_scrub_l0ic_data_init_f()     (0x0U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_control_scrub_l0ic_predecode_init_f()\
+				(0x0U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_control_scrub_urf_data_init_f()      (0x0U)
+#define gr_pri_gpc0_tpc0_tex_m_routing_r()                         (0x005042c4U)
+#define gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()                    (0x0U)
+#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()                      (0x1U)
+#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()                      (0x2U)
+#define gr_pipe_bundle_address_r()                                 (0x00400200U)
+#define gr_pipe_bundle_address_value_v(r)                (((r) >> 0U) & 0xffffU)
+#define gr_pipe_bundle_address_veid_f(v)               ((U32(v) & 0x3fU) << 20U)
+#define gr_pipe_bundle_data_r()                                    (0x00400204U)
+#define gr_pipe_bundle_data_hi_r()                                 (0x0040020cU)
+#define gr_pipe_bundle_config_r()                                  (0x00400208U)
+#define gr_pipe_bundle_config_override_pipe_mode_disabled_f()             (0x0U)
+#define gr_pipe_bundle_config_override_pipe_mode_enabled_f()       (0x80000000U)
+#define gr_gpc0_tpc0_mpc_hww_esr_r()                               (0x00504430U)
+#define gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f()                 (0x40000000U)
+#define gr_gpc0_tpc0_mpc_hww_esr_info_r()                          (0x00504434U)
+#define gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(r)            (((r) >> 0U) & 0x3fU)
+#define gr_gpc0_tpc0_pe_hww_esr_r()                                (0x00504084U)
+#define gr_gpc0_tpc0_pe_hww_esr_reset_task_f()                     (0x40000000U)
+#define gr_gpc0_prop_hww_esr_r()                                   (0x00500420U)
+#define gr_gpc0_prop_hww_esr_reset_active_f()                      (0x40000000U)
+#define gr_gpc0_prop_hww_esr_coord_r()                             (0x00500434U)
+#define gr_gpc0_prop_hww_esr_format_r()                            (0x00500438U)
+#define gr_gpc0_prop_hww_esr_state_r()                             (0x0050043cU)
+#define gr_gpc0_prop_hww_esr_state2_r()                            (0x00500440U)
+#define gr_gpc0_prop_hww_esr_offset_r()                            (0x00500444U)
+#define gr_gpc0_zcull_hww_esr_r()                                  (0x00500900U)
+#define gr_gpc0_zcull_hww_esr_reset_active_f()                     (0x40000000U)
+#define gr_gpc0_setup_hww_esr_r()                                  (0x00500824U)
+#define gr_gpc0_setup_hww_esr_reset_active_f()                     (0x40000000U)
+#define gr_gpc0_ppc0_pes_hww_esr_r()                               (0x00503038U)
+#define gr_gpc0_ppc0_pes_hww_esr_reset_task_f()                    (0x40000000U)
+#define gr_gpc0_gpccs_hww_esr_r()                                  (0x00502c98U)
+#define gr_gpc0_gpccs_hww_esr_ecc_corrected_m()                (U32(0x1U) << 0U)
+#define gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m()              (U32(0x1U) << 1U)
+#define gr_gpccs_falcon_ecc_control_r()                            (0x0050268cU)
+#define gr_gpccs_falcon_ecc_control_inject_corrected_err_f(v)\
+				((U32(v) & 0x1U) << 0U)
+#define gr_gpccs_falcon_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 1U)
+#define gr_fe_hww_esr_r()                                          (0x00404000U)
+#define gr_fe_hww_esr_reset_active_f()                             (0x40000000U)
+#define gr_fe_hww_esr_en_enable_f()                                (0x80000000U)
+#define gr_fe_hww_esr_info_r()                                     (0x004041b0U)
+#define gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r()            (0x00419eacU)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r()            (0x0050472cU)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()\
+				(0x4U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f()   (0x10U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f() (0x20U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f()\
+				(0x40U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f()\
+				(0x100U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_poison_data_report_f()\
+				(0x1000U)
+#define gr_gpcs_tpcs_sms_hww_global_esr_r()                        (0x00419eb4U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_r()                        (0x00504734U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()              (0x10U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f()            (0x20U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f() (0x40U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f()  (0x4U)
+#define gr_fe_go_idle_timeout_r()                                  (0x00404154U)
+#define gr_fe_go_idle_timeout_count_disabled_f()                          (0x0U)
+#define gr_fe_go_idle_timeout_count_prod_f()                           (0x1800U)
+#define gr_fe_compute_go_idle_timeout_r()                          (0x00404160U)
+#define gr_fe_compute_go_idle_timeout_count_disabled_f()                  (0x0U)
+#define gr_fe_compute_go_idle_timeout_count_init_f()                     (0x40U)
+#define gr_fe_object_table_r(i)\
+		(nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_fe_object_table_nvclass_v(r)                  (((r) >> 0U) & 0xffffU)
+#define gr_fe_tpc_fs_r(i)\
+		(nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_pri_mme_shadow_ram_index_r()                            (0x00404488U)
+#define gr_pri_mme_shadow_ram_index_nvclass_f(v)      ((U32(v) & 0xffffU) << 0U)
+#define gr_pri_mme_shadow_ram_index_method_address_f(v)\
+				((U32(v) & 0xfffU) << 16U)
+#define gr_pri_mme_shadow_ram_index_fepipe_f(v)         ((U32(v) & 0x1U) << 29U)
+#define gr_pri_mme_shadow_ram_index_fepipe_fe0_f()                        (0x0U)
+#define gr_pri_mme_shadow_ram_index_write_trigger_f()              (0x80000000U)
+#define gr_pri_mme_shadow_ram_data_r()                             (0x0040448cU)
+#define gr_mme_hww_esr_r()                                         (0x00404490U)
+#define gr_mme_hww_esr_missing_macro_data_pending_f()                     (0x1U)
+#define gr_mme_hww_esr_illegal_opcode_pending_f()                         (0x4U)
+#define gr_mme_hww_esr_branch_in_delay_pending_f()                        (0x8U)
+#define gr_mme_hww_esr_inst_ram_acess_pending_f()                        (0x20U)
+#define gr_mme_hww_esr_data_ram_access_pending_f()                       (0x40U)
+#define gr_mme_hww_esr_illegal_mme_method_pending_f()                    (0x80U)
+#define gr_mme_hww_esr_dma_dram_access_pending_f()                    (0x10000U)
+#define gr_mme_hww_esr_dma_read_pb_pending_f()                        (0x20000U)
+#define gr_mme_hww_esr_dma_illegal_fifo_pending_f()                   (0x40000U)
+#define gr_mme_hww_esr_dma_read_overflow_pending_f()                  (0x80000U)
+#define gr_mme_hww_esr_dma_fifo_resized_pending_f()                  (0x100000U)
+#define gr_mme_hww_esr_reset_active_f()                            (0x40000000U)
+#define gr_mme_hww_esr_en_enable_f()                               (0x80000000U)
+#define gr_mme_hww_esr_info_r()                                    (0x00404494U)
+#define gr_mme_hww_esr_info_pc_valid_v(r)                  (((r) >> 28U) & 0x1U)
+#define gr_mme_hww_esr_info2_r()                                   (0x0040449cU)
+#define gr_mme_hww_esr_info3_r()                                   (0x004044a8U)
+#define gr_mme_hww_esr_info4_r()                                   (0x004044acU)
+#define gr_memfmt_hww_esr_r()                                      (0x00404600U)
+#define gr_memfmt_hww_esr_reset_active_f()                         (0x40000000U)
+#define gr_memfmt_hww_esr_en_enable_f()                            (0x80000000U)
+#define gr_fecs_cpuctl_r()                                         (0x00409100U)
+#define gr_fecs_cpuctl_startcpu_f(v)                     ((U32(v) & 0x1U) << 1U)
+#define gr_fecs_cpuctl_alias_r()                                   (0x00409130U)
+#define gr_fecs_dmactl_r()                                         (0x0040910cU)
+#define gr_fecs_dmactl_require_ctx_f(v)                  ((U32(v) & 0x1U) << 0U)
+#define gr_fecs_dmactl_dmem_scrubbing_m()                      (U32(0x1U) << 1U)
+#define gr_fecs_dmactl_imem_scrubbing_m()                      (U32(0x1U) << 2U)
+#define gr_fecs_mailbox0_r()                                       (0x00409040U)
+#define gr_fecs_mailbox1_r()                                       (0x00409044U)
+#define gr_fecs_imemc_r(i)\
+		(nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_fecs_imemc_offs_f(v)                         ((U32(v) & 0x3fU) << 2U)
+#define gr_fecs_imemc_blk_f(v)                        ((U32(v) & 0xffffU) << 8U)
+#define gr_fecs_imemc_aincw_f(v)                        ((U32(v) & 0x1U) << 24U)
+#define gr_fecs_imemd_r(i)\
+		(nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_fecs_imemt_r(i)\
+		(nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_fecs_imemt_tag_f(v)                        ((U32(v) & 0xffffU) << 0U)
+#define gr_fecs_dmemc_r(i)\
+		(nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U)))
+#define gr_fecs_dmemc_offs_f(v)                         ((U32(v) & 0x3fU) << 2U)
+#define gr_fecs_dmemc_blk_f(v)                        ((U32(v) & 0xffffU) << 8U)
+#define gr_fecs_dmemc_aincw_f(v)                        ((U32(v) & 0x1U) << 24U)
+#define gr_fecs_dmemd_r(i)\
+		(nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U)))
+#define gr_fecs_dmatrfbase_r()                                     (0x00409110U)
+#define gr_fecs_dmatrfmoffs_r()                                    (0x00409114U)
+#define gr_fecs_dmatrffboffs_r()                                   (0x0040911cU)
+#define gr_fecs_dmatrfcmd_r()                                      (0x00409118U)
+#define gr_fecs_dmatrfcmd_imem_f(v)                      ((U32(v) & 0x1U) << 4U)
+#define gr_fecs_dmatrfcmd_write_f(v)                     ((U32(v) & 0x1U) << 5U)
+#define gr_fecs_dmatrfcmd_size_f(v)                      ((U32(v) & 0x7U) << 8U)
+#define gr_fecs_dmatrfcmd_ctxdma_f(v)                   ((U32(v) & 0x7U) << 12U)
+#define gr_fecs_bootvec_r()                                        (0x00409104U)
+#define gr_fecs_bootvec_vec_f(v)                  ((U32(v) & 0xffffffffU) << 0U)
+#define gr_fecs_irqsset_r()                                        (0x00409000U)
+#define gr_fecs_falcon_hwcfg_r()                                   (0x00409108U)
+#define gr_gpcs_gpccs_irqsset_r()                                  (0x0041a000U)
+#define gr_gpcs_gpccs_falcon_hwcfg_r()                             (0x0041a108U)
+#define gr_fecs_current_ctx_r()                                    (0x00409b00U)
+#define gr_fecs_current_ctx_ptr_f(v)               ((U32(v) & 0xfffffffU) << 0U)
+#define gr_fecs_current_ctx_ptr_v(r)                  (((r) >> 0U) & 0xfffffffU)
+#define gr_fecs_current_ctx_target_s()                                      (2U)
+#define gr_fecs_current_ctx_target_m()                        (U32(0x3U) << 28U)
+#define gr_fecs_current_ctx_target_v(r)                    (((r) >> 28U) & 0x3U)
+#define gr_fecs_current_ctx_target_vid_mem_f()                            (0x0U)
+#define gr_fecs_current_ctx_target_sys_mem_coh_f()                 (0x20000000U)
+#define gr_fecs_current_ctx_target_sys_mem_ncoh_f()                (0x30000000U)
+#define gr_fecs_current_ctx_valid_f(v)                  ((U32(v) & 0x1U) << 31U)
+#define gr_fecs_current_ctx_valid_m()                         (U32(0x1U) << 31U)
+#define gr_fecs_current_ctx_valid_v(r)                     (((r) >> 31U) & 0x1U)
+#define gr_fecs_current_ctx_valid_false_f()                               (0x0U)
+#define gr_fecs_method_data_r()                                    (0x00409500U)
+#define gr_fecs_method_push_r()                                    (0x00409504U)
+#define gr_fecs_method_push_adr_f(v)                   ((U32(v) & 0xfffU) << 0U)
+#define gr_fecs_method_push_adr_bind_pointer_v()                   (0x00000003U)
+#define gr_fecs_method_push_adr_discover_image_size_v()            (0x00000010U)
+#define gr_fecs_method_push_adr_wfi_golden_save_v()                (0x00000009U)
+#define gr_fecs_method_push_adr_discover_zcull_image_size_v()      (0x00000016U)
+#define gr_fecs_method_push_adr_discover_pm_image_size_v()         (0x00000025U)
+#define gr_fecs_method_push_adr_discover_reglist_image_size_v()    (0x00000030U)
+#define gr_fecs_method_push_adr_set_reglist_bind_instance_v()      (0x00000031U)
+#define gr_fecs_method_push_adr_set_reglist_virtual_address_v()    (0x00000032U)
+#define gr_fecs_method_push_adr_stop_ctxsw_v()                     (0x00000038U)
+#define gr_fecs_method_push_adr_start_ctxsw_v()                    (0x00000039U)
+#define gr_fecs_method_push_adr_set_watchdog_timeout_f()                 (0x21U)
+#define gr_fecs_method_push_adr_discover_preemption_image_size_v() (0x0000001aU)
+#define gr_fecs_method_push_adr_halt_pipeline_v()                  (0x00000004U)
+#define gr_fecs_method_push_adr_configure_interrupt_completion_option_v()\
+				(0x0000003aU)
+#define gr_fecs_method_push_adr_smpc_global_mode_start_v()         (0x00000069U)
+#define gr_fecs_method_push_adr_smpc_global_mode_stop_v()          (0x0000006aU)
+#define gr_fecs_host_int_status_r()                                (0x00409c18U)
+#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) ((U32(v) & 0x1U) << 16U)
+#define gr_fecs_host_int_status_umimp_firmware_method_f(v)\
+				((U32(v) & 0x1U) << 17U)
+#define gr_fecs_host_int_status_watchdog_active_f()                   (0x80000U)
+#define gr_fecs_host_int_status_ctxsw_intr_f(v)       ((U32(v) & 0xffffU) << 0U)
+#define gr_fecs_host_int_status_ecc_corrected_m()             (U32(0x1U) << 21U)
+#define gr_fecs_host_int_status_ecc_uncorrected_m()           (U32(0x1U) << 22U)
+#define gr_fecs_host_int_clear_r()                                 (0x00409c20U)
+#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f()                      (0x2U)
+#define gr_fecs_host_int_enable_r()                                (0x00409c24U)
+#define gr_fecs_host_int_enable_ctxsw_intr0_enable_f()                    (0x1U)
+#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f()                    (0x2U)
+#define gr_fecs_host_int_enable_fault_during_ctxsw_enable_f()         (0x10000U)
+#define gr_fecs_host_int_enable_umimp_firmware_method_enable_f()      (0x20000U)
+#define gr_fecs_host_int_enable_umimp_illegal_method_enable_f()       (0x40000U)
+#define gr_fecs_host_int_enable_watchdog_enable_f()                   (0x80000U)
+#define gr_fecs_host_int_enable_flush_when_busy_enable_f()           (0x100000U)
+#define gr_fecs_host_int_enable_ecc_corrected_enable_f()             (0x200000U)
+#define gr_fecs_host_int_enable_ecc_uncorrected_enable_f()           (0x400000U)
+#define gr_fecs_ctxsw_reset_ctl_r()                                (0x00409614U)
+#define gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f()                     (0x0U)
+#define gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f()            (0x10U)
+#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f()             (0x0U)
+#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f()          (0x100U)
+#define gr_gpccs_ctxsw_reset_ctl_r()                               (0x0041a614U)
+#define gr_gpccs_ctxsw_reset_ctl_gpc_halt_disabled_f()                    (0x0U)
+#define gr_gpccs_ctxsw_reset_ctl_gpc_reset_disabled_f()                  (0x20U)
+#define gr_gpccs_ctxsw_reset_ctl_gpc_context_reset_disabled_f()         (0x200U)
+#define gr_gpccs_ctxsw_reset_ctl_gpc_context_reset_enabled_f()            (0x0U)
+#define gr_gpccs_ctxsw_reset_ctl_zcull_reset_disabled_f()               (0x800U)
+#define gr_gpccs_ctxsw_reset_ctl_zcull_reset_enabled_f()                  (0x0U)
+#define gr_bes_becs_ctxsw_be_reset_ctl_r()                         (0x00408a10U)
+#define gr_bes_becs_ctxsw_be_reset_ctl_be_halt_disabled_f()               (0x0U)
+#define gr_bes_becs_ctxsw_be_reset_ctl_be_engine_reset_disabled_f()      (0x40U)
+#define gr_bes_becs_ctxsw_be_reset_ctl_be_context_reset_enabled_f()       (0x0U)
+#define gr_bes_becs_ctxsw_be_reset_ctl_be_context_reset_disabled_f()    (0x400U)
+#define gr_fecs_ctx_state_store_major_rev_id_r()                   (0x0040960cU)
+#define gr_fecs_ctxsw_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_fecs_ctxsw_mailbox__size_1_v()                          (0x00000012U)
+#define gr_fecs_ctxsw_mailbox_value_f(v)          ((U32(v) & 0xffffffffU) << 0U)
+#define gr_fecs_ctxsw_mailbox_value_pass_v()                       (0x00000001U)
+#define gr_fecs_ctxsw_mailbox_value_fail_v()                       (0x00000002U)
+#define gr_fecs_ctxsw_mailbox_value_ctxsw_checksum_mismatch_v()    (0x00000021U)
+#define gr_fecs_ctxsw_func_tracing_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_fecs_ctxsw_func_tracing_mailbox__size_1_v()             (0x00000006U)
+#define gr_fecs_cfg_r()                                            (0x00409620U)
+#define gr_fecs_cfg_imem_sz_v(r)                           (((r) >> 0U) & 0xffU)
+#define gr_fecs_ctxsw_status_1_r()                                 (0x00409400U)
+#define gr_fecs_ctxsw_status_1_arb_busy_m()                   (U32(0x1U) << 12U)
+#define gr_fecs_arb_ctx_adr_r()                                    (0x00409a24U)
+#define gr_fecs_new_ctx_r()                                        (0x00409b04U)
+#define gr_fecs_new_ctx_ptr_f(v)                   ((U32(v) & 0xfffffffU) << 0U)
+#define gr_fecs_new_ctx_target_s()                                          (2U)
+#define gr_fecs_new_ctx_target_v(r)                        (((r) >> 28U) & 0x3U)
+#define gr_fecs_new_ctx_target_vid_mem_f()                                (0x0U)
+#define gr_fecs_new_ctx_target_sys_mem_ncoh_f()                    (0x30000000U)
+#define gr_fecs_new_ctx_target_sys_mem_coh_f()                     (0x20000000U)
+#define gr_fecs_new_ctx_valid_m()                             (U32(0x1U) << 31U)
+#define gr_fecs_arb_ctx_ptr_r()                                    (0x00409a0cU)
+#define gr_fecs_arb_ctx_ptr_ptr_f(v)               ((U32(v) & 0xfffffffU) << 0U)
+#define gr_fecs_arb_ctx_ptr_target_s()                                      (2U)
+#define gr_fecs_arb_ctx_ptr_target_v(r)                    (((r) >> 28U) & 0x3U)
+#define gr_fecs_arb_ctx_ptr_target_vid_mem_f()                            (0x0U)
+#define gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f()                (0x30000000U)
+#define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f()                 (0x20000000U)
+#define gr_fecs_arb_ctx_cmd_r()                                    (0x00409a10U)
+#define gr_fecs_arb_ctx_cmd_cmd_s()                                         (5U)
+#define gr_fecs_arb_ctx_cmd_cmd_v(r)                       (((r) >> 0U) & 0x1fU)
+#define gr_fecs_ctxsw_status_fe_0_r()                              (0x00409c00U)
+#define gr_gpc0_gpccs_ctxsw_status_gpc_0_r()                       (0x00502c04U)
+#define gr_gpc0_gpccs_ctxsw_status_1_r()                           (0x00502400U)
+#define gr_fecs_ctxsw_idlestate_r()                                (0x00409420U)
+#define gr_gpc0_gpccs_ctxsw_idlestate_r()                          (0x00502420U)
+#define gr_rstr2d_gpc_map_r(i)\
+		(nvgpu_safe_add_u32(0x0040780cU, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_rstr2d_map_table_cfg_r()                                (0x004078bcU)
+#define gr_rstr2d_map_table_cfg_row_offset_f(v)         ((U32(v) & 0xffU) << 0U)
+#define gr_rstr2d_map_table_cfg_num_entries_f(v)        ((U32(v) & 0xffU) << 8U)
+#define gr_pd_hww_esr_r()                                          (0x00406018U)
+#define gr_pd_hww_esr_reset_active_f()                             (0x40000000U)
+#define gr_pd_hww_esr_en_enable_f()                                (0x80000000U)
+#define gr_pd_num_tpc_per_gpc_r(i)\
+		(nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_pd_num_tpc_per_gpc__size_1_v()                          (0x00000004U)
+#define gr_pd_num_tpc_per_gpc_count0_f(v)                ((U32(v) & 0xfU) << 0U)
+#define gr_pd_num_tpc_per_gpc_count1_f(v)                ((U32(v) & 0xfU) << 4U)
+#define gr_pd_num_tpc_per_gpc_count2_f(v)                ((U32(v) & 0xfU) << 8U)
+#define gr_pd_num_tpc_per_gpc_count3_f(v)               ((U32(v) & 0xfU) << 12U)
+#define gr_pd_num_tpc_per_gpc_count4_f(v)               ((U32(v) & 0xfU) << 16U)
+#define gr_pd_num_tpc_per_gpc_count5_f(v)               ((U32(v) & 0xfU) << 20U)
+#define gr_pd_num_tpc_per_gpc_count6_f(v)               ((U32(v) & 0xfU) << 24U)
+#define gr_pd_num_tpc_per_gpc_count7_f(v)               ((U32(v) & 0xfU) << 28U)
+#define gr_pd_ab_dist_cfg0_r()                                     (0x004064c0U)
+#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f()                 (0x80000000U)
+#define gr_pd_ab_dist_cfg1_r()                                     (0x004064c4U)
+#define gr_pd_ab_dist_cfg1_max_batches_init_f()                        (0xffffU)
+#define gr_pd_ab_dist_cfg1_max_output_f(v)           ((U32(v) & 0xffffU) << 16U)
+#define gr_pd_ab_dist_cfg1_max_output_granularity_v()              (0x00000080U)
+#define gr_pd_ab_dist_cfg2_r()                                     (0x004064c8U)
+#define gr_pd_ab_dist_cfg2_token_limit_f(v)           ((U32(v) & 0x3fffU) << 0U)
+#define gr_pd_ab_dist_cfg2_token_limit_init_v()                    (0x00002180U)
+#define gr_pd_ab_dist_cfg2_state_limit_f(v)          ((U32(v) & 0x3fffU) << 16U)
+#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v()  (0x00000020U)
+#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v()     (0x00002180U)
+#define gr_pd_dist_skip_table_r(i)\
+		(nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_pd_dist_skip_table__size_1_v()                          (0x00000008U)
+#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v)         ((U32(v) & 0xffU) << 0U)
+#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v)         ((U32(v) & 0xffU) << 8U)
+#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v)        ((U32(v) & 0xffU) << 16U)
+#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v)        ((U32(v) & 0xffU) << 24U)
+#define gr_ds_debug_r()                                            (0x00405800U)
+#define gr_ds_tga_constraintlogic_beta_r()                         (0x00405830U)
+#define gr_ds_tga_constraintlogic_beta_cbsize_f(v)  ((U32(v) & 0x3fffffU) << 0U)
+#define gr_ds_tga_constraintlogic_alpha_r()                        (0x0040585cU)
+#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v)   ((U32(v) & 0xffffU) << 0U)
+#define gr_ds_hww_esr_r()                                          (0x00405840U)
+#define gr_ds_hww_esr_reset_task_f()                               (0x40000000U)
+#define gr_ds_hww_esr_en_enabled_f()                               (0x80000000U)
+#define gr_ds_num_tpc_per_gpc_r(i)\
+		(nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_scc_debug_r()                                           (0x00408000U)
+#define gr_scc_debug_pagepool_invalidates_m()                  (U32(0x1U) << 9U)
+#define gr_scc_debug_pagepool_invalidates_disable_f()                   (0x200U)
+#define gr_scc_bundle_cb_base_r()                                  (0x00408004U)
+#define gr_scc_bundle_cb_base_addr_39_8_f(v)      ((U32(v) & 0xffffffffU) << 0U)
+#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v()             (0x00000008U)
+#define gr_scc_bundle_cb_size_r()                                  (0x00408008U)
+#define gr_scc_bundle_cb_size_div_256b_f(v)            ((U32(v) & 0x7ffU) << 0U)
+#define gr_scc_bundle_cb_size_div_256b__prod_v()                   (0x00000030U)
+#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v()        (0x00000100U)
+#define gr_scc_bundle_cb_size_valid_true_f()                       (0x80000000U)
+#define gr_scc_pagepool_base_r()                                   (0x0040800cU)
+#define gr_scc_pagepool_base_addr_39_8_f(v)       ((U32(v) & 0xffffffffU) << 0U)
+#define gr_scc_pagepool_base_addr_39_8_align_bits_v()              (0x00000008U)
+#define gr_scc_pagepool_r()                                        (0x00408010U)
+#define gr_scc_pagepool_total_pages_f(v)               ((U32(v) & 0x3ffU) << 0U)
+#define gr_scc_pagepool_total_pages_hwmax_v()                      (0x00000000U)
+#define gr_scc_pagepool_total_pages_hwmax_value_v()                (0x00000200U)
+#define gr_scc_pagepool_total_pages_byte_granularity_v()           (0x00000100U)
+#define gr_scc_pagepool_valid_true_f()                             (0x80000000U)
+#define gr_scc_rm_rtv_cb_base_r()                                  (0x00408070U)
+#define gr_scc_rm_rtv_cb_base_addr_39_8_f(v)      ((U32(v) & 0xffffffffU) << 0U)
+#define gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f()                    (0x8U)
+#define gr_scc_rm_rtv_cb_size_r()                                  (0x00408074U)
+#define gr_scc_rm_rtv_cb_size_div_256b_f(v)           ((U32(v) & 0x7fffU) << 0U)
+#define gr_scc_rm_rtv_cb_size_div_256b_byte_granularity_v()        (0x00000100U)
+#define gr_scc_rm_rtv_cb_size_div_256b_default_f()                      (0x800U)
+#define gr_scc_rm_rtv_cb_size_div_256b_db_adder_f()                       (0x0U)
+#define gr_scc_rm_rtv_cb_size_div_256b_gfxp_adder_f()                    (0x20U)
+#define gr_gpcs_gcc_rm_rtv_cb_base_r()                             (0x00419034U)
+#define gr_gpcs_gcc_rm_rtv_cb_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
+#define gr_scc_rm_gfxp_reserve_r()                                 (0x00408078U)
+#define gr_scc_rm_gfxp_reserve_rtv_cb_size_div_256b_f(v)\
+				((U32(v) & 0x1ffU) << 0U)
+#define gr_scc_hww_esr_r()                                         (0x00408030U)
+#define gr_scc_hww_esr_reset_active_f()                            (0x40000000U)
+#define gr_scc_hww_esr_en_enable_f()                               (0x80000000U)
+#define gr_ssync_hww_esr_r()                                       (0x00405a14U)
+#define gr_ssync_hww_esr_reset_active_f()                          (0x40000000U)
+#define gr_ssync_hww_esr_en_enable_f()                             (0x80000000U)
+#define gr_sked_hww_esr_r()                                        (0x00407020U)
+#define gr_sked_hww_esr_reset_active_f()                           (0x40000000U)
+#define gr_sked_hww_esr_en_r()                                     (0x00407024U)
+#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m()\
+				(U32(0x1U) << 25U)
+#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f()   (0x0U)
+#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f()\
+				(0x2000000U)
+#define gr_cwd_fs_r()                                              (0x00405b00U)
+#define gr_cwd_fs_num_gpcs_f(v)                         ((U32(v) & 0xffU) << 0U)
+#define gr_cwd_fs_num_tpcs_f(v)                         ((U32(v) & 0xffU) << 8U)
+#define gr_cwd_gpc_tpc_id_r(i)\
+		(nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_cwd_gpc_tpc_id_tpc0_s()                                          (4U)
+#define gr_cwd_gpc_tpc_id_tpc0_f(v)                      ((U32(v) & 0xfU) << 0U)
+#define gr_cwd_gpc_tpc_id_gpc0_s()                                          (4U)
+#define gr_cwd_gpc_tpc_id_gpc0_f(v)                      ((U32(v) & 0xfU) << 4U)
+#define gr_cwd_sm_id_r(i)\
+		(nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_cwd_sm_id__size_1_v()                                   (0x00000010U)
+#define gr_gpc0_fs_gpc_r()                                         (0x00502608U)
+#define gr_gpc0_fs_gpc_num_available_tpcs_v(r)             (((r) >> 0U) & 0x1fU)
+#define gr_gpc0_fs_gpc_num_available_zculls_v(r)          (((r) >> 16U) & 0x1fU)
+#define gr_gpc0_cfg_r()                                            (0x00502620U)
+#define gr_gpc0_cfg_imem_sz_v(r)                           (((r) >> 0U) & 0xffU)
+#define gr_gpc0_zcull_fs_r()                                       (0x00500910U)
+#define gr_gpc0_zcull_fs_num_sms_f(v)                  ((U32(v) & 0x1ffU) << 0U)
+#define gr_gpc0_zcull_fs_num_active_banks_f(v)          ((U32(v) & 0xfU) << 16U)
+#define gr_gpc0_zcull_ram_addr_r()                                 (0x00500914U)
+#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\
+				((U32(v) & 0xfU) << 0U)
+#define gr_gpc0_zcull_ram_addr_row_offset_f(v)           ((U32(v) & 0xfU) << 8U)
+#define gr_gpc0_zcull_sm_num_rcp_r()                               (0x00500918U)
+#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v)  ((U32(v) & 0xffffffU) << 0U)
+#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v()             (0x00800000U)
+#define gr_gpc0_zcull_total_ram_size_r()                           (0x00500920U)
+#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v)\
+				((U32(v) & 0xffffU) << 0U)
+#define gr_gpc0_zcull_zcsize_r(i)\
+		(nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U)))
+#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v()        (0x00000040U)
+#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v()         (0x00000010U)
+#define gr_gpc0_gpm_pd_sm_id_r(i)\
+		(nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpc0_gpm_pd_sm_id_id_f(v)                    ((U32(v) & 0xffU) << 0U)
+#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\
+		(nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r)           (((r) >> 0U) & 0xffU)
+#define gr_gpc0_tpc0_sm_cfg_r()                                    (0x00504608U)
+#define gr_gpc0_tpc0_sm_cfg_tpc_id_f(v)               ((U32(v) & 0xffffU) << 0U)
+#define gr_gpc0_tpc0_sm_arch_r()                                   (0x00504330U)
+#define gr_gpc0_tpc0_sm_arch_warp_count_v(r)               (((r) >> 0U) & 0xffU)
+#define gr_gpc0_tpc0_sm_arch_spa_version_v(r)             (((r) >> 8U) & 0xfffU)
+#define gr_gpc0_tpc0_sm_arch_sm_version_v(r)             (((r) >> 20U) & 0xfffU)
+#define gr_gpc0_ppc0_pes_vsc_strem_r()                             (0x00503018U)
+#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m()               (U32(0x1U) << 0U)
+#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f()                     (0x1U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_r()                          (0x005030c0U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v)        ((U32(v) & 0x3fffffU) << 0U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m()               (U32(0x3fffffU) << 0U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()                (0x00001800U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v()                   (0x00002080U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v()            (0x00000020U)
+#define gr_gpc0_ppc0_cbm_beta_cb_offset_r()                        (0x005030f4U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_size_r()                         (0x005030e4U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v)         ((U32(v) & 0xffffU) << 0U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m()                (U32(0xffffU) << 0U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v()               (0x00000800U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v()           (0x00000020U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r()                       (0x005030f8U)
+#define gr_gpcs_tpcs_tex_m_dbg2_r()                                (0x00419a3cU)
+#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r()             (0x005030f0U)
+#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\
+				((U32(v) & 0x3fffffU) << 0U)
+#define gr_gpcs_tpcs_tex_rm_cb_0_r()                               (0x00419e00U)
+#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpcs_tpcs_tex_rm_cb_1_r()                               (0x00419e04U)
+#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) ((U32(v) & 0x1fffffU) << 0U)
+#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f()           (0x80U)
+#define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f()                    (0x80000000U)
+#define gr_gpccs_cpuctl_r()                                        (0x0041a100U)
+#define gr_gpccs_cpuctl_startcpu_f(v)                    ((U32(v) & 0x1U) << 1U)
+#define gr_gpccs_dmactl_r()                                        (0x0041a10cU)
+#define gr_gpccs_dmactl_require_ctx_f(v)                 ((U32(v) & 0x1U) << 0U)
+#define gr_gpccs_dmactl_imem_scrubbing_m()                     (U32(0x1U) << 2U)
+#define gr_gpccs_imemc_r(i)\
+		(nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_gpccs_imemc_offs_f(v)                        ((U32(v) & 0x3fU) << 2U)
+#define gr_gpccs_imemc_blk_f(v)                       ((U32(v) & 0xffffU) << 8U)
+#define gr_gpccs_imemc_aincw_f(v)                       ((U32(v) & 0x1U) << 24U)
+#define gr_gpccs_imemd_r(i)\
+		(nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_gpccs_imemt_r(i)\
+		(nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_gpccs_imemt_tag_f(v)                       ((U32(v) & 0xffffU) << 0U)
+#define gr_gpccs_dmemc_r(i)\
+		(nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U)))
+#define gr_gpccs_dmemc_offs_f(v)                        ((U32(v) & 0x3fU) << 2U)
+#define gr_gpccs_dmemc_blk_f(v)                       ((U32(v) & 0xffffU) << 8U)
+#define gr_gpccs_dmemc_aincw_f(v)                       ((U32(v) & 0x1U) << 24U)
+#define gr_gpccs_dmemd_r(i)\
+		(nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U)))
+#define gr_gpccs_ctxsw_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpccs_ctxsw_mailbox__size_1_v()                         (0x00000012U)
+#define gr_gpccs_ctxsw_mailbox_value_f(v)         ((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpc0_gpccs_ctxsw_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x00502800U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpc0_gpccs_ctxsw_func_tracing_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x005028c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpc0_gpccs_ctxsw_func_tracing_mailbox__size_1_v()       (0x00000006U)
+#define gr_gpcs_swdx_bundle_cb_base_r()                            (0x00418e24U)
+#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpcs_swdx_bundle_cb_size_r()                            (0x00418e28U)
+#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v)      ((U32(v) & 0x7ffU) << 0U)
+#define gr_gpcs_swdx_bundle_cb_size_valid_true_f()                 (0x80000000U)
+#define gr_gpc0_swdx_rm_spill_buffer_size_r()                      (0x005001dcU)
+#define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v)   ((U32(v) & 0xffffU) << 0U)
+#define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v()         (0x000004e0U)
+#define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\
+				(0x00000100U)
+#define gr_gpc0_swdx_rm_spill_buffer_addr_r()                      (0x005001d8U)
+#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()      (0x00000008U)
+#define gr_gpcs_swdx_beta_cb_ctrl_r()                              (0x004181e4U)
+#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v)    ((U32(v) & 0xfffU) << 0U)
+#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v()            (0x00000100U)
+#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r()                          (0x0041befcU)
+#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v)\
+				((U32(v) & 0xfffU) << 0U)
+#define gr_gpcs_ppcs_cbm_debug_r()                                 (0x0041bec4U)
+#define gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m()            (U32(0x1U) << 0U)
+#define gr_gpcs_ppcs_cbm_debug_invalidate_alpha_disable_f()               (0x0U)
+#define gr_gpcs_ppcs_cbm_debug_invalidate_beta_m()             (U32(0x1U) << 1U)
+#define gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f()                (0x0U)
+#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\
+		(nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v)         ((U32(v) & 0x3fffffU) << 0U)
+#define gr_gpcs_swdx_tc_beta_cb_size_v_m()                (U32(0x3fffffU) << 0U)
+#define gr_gpcs_swdx_dss_zbc_color_r_r(i)\
+		(nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_swdx_dss_zbc_color_r__size_1_v()                   (0x0000000fU)
+#define gr_gpcs_swdx_dss_zbc_color_g_r(i)\
+		(nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_swdx_dss_zbc_color_b_r(i)\
+		(nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_swdx_dss_zbc_color_a_r(i)\
+		(nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r()                 (0x00418100U)
+#define gr_gpcs_swdx_dss_zbc_z_r(i)\
+		(nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_swdx_dss_zbc_z__size_1_v()                         (0x0000000fU)
+#define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r()                 (0x0041814cU)
+#define gr_gpcs_swdx_dss_zbc_s_r(i)\
+		(nvgpu_safe_add_u32(0x0041815cU, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_swdx_dss_zbc_s__size_1_v()                         (0x0000000fU)
+#define gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r()                 (0x00418198U)
+#define gr_gpcs_swdx_spill_unit_r()                                (0x00418e9cU)
+#define gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_m()\
+				(U32(0x1U) << 16U)
+#define gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_disabled_f() (0x0U)
+#define gr_gpcs_setup_attrib_cb_base_r()                           (0x00418810U)
+#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v)\
+				((U32(v) & 0xfffffffU) << 0U)
+#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()     (0x0000000cU)
+#define gr_gpcs_setup_attrib_cb_base_valid_true_f()                (0x80000000U)
+#define gr_crstr_gpc_map_r(i)\
+		(nvgpu_safe_add_u32(0x00418b08U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_crstr_gpc_map_tile0_f(v)                     ((U32(v) & 0x1fU) << 0U)
+#define gr_crstr_gpc_map_tile1_f(v)                     ((U32(v) & 0x1fU) << 5U)
+#define gr_crstr_gpc_map_tile2_f(v)                    ((U32(v) & 0x1fU) << 10U)
+#define gr_crstr_gpc_map_tile3_f(v)                    ((U32(v) & 0x1fU) << 15U)
+#define gr_crstr_gpc_map_tile4_f(v)                    ((U32(v) & 0x1fU) << 20U)
+#define gr_crstr_gpc_map_tile5_f(v)                    ((U32(v) & 0x1fU) << 25U)
+#define gr_crstr_map_table_cfg_r()                                 (0x00418bb8U)
+#define gr_crstr_map_table_cfg_row_offset_f(v)          ((U32(v) & 0xffU) << 0U)
+#define gr_crstr_map_table_cfg_num_entries_f(v)         ((U32(v) & 0xffU) << 8U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_r(i)\
+		(nvgpu_safe_add_u32(0x00418980U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(v)   ((U32(v) & 0x7U) << 0U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(v)   ((U32(v) & 0x7U) << 4U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(v)   ((U32(v) & 0x7U) << 8U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(v)  ((U32(v) & 0x7U) << 12U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(v)  ((U32(v) & 0x7U) << 16U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(v)  ((U32(v) & 0x7U) << 20U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(v)  ((U32(v) & 0x7U) << 24U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(v)  ((U32(v) & 0x7U) << 28U)
+#define gr_gpcs_gpm_pd_cfg_r()                                     (0x00418c6cU)
+#define gr_gpcs_gcc_pagepool_base_r()                              (0x00419004U)
+#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v)  ((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpcs_gcc_pagepool_r()                                   (0x00419008U)
+#define gr_gpcs_gcc_pagepool_total_pages_f(v)          ((U32(v) & 0x3ffU) << 0U)
+#define gr_gpcs_tpcs_pe_vaf_r()                                    (0x0041980cU)
+#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f()                    (0x10U)
+#define gr_gpcs_tpcs_mpc_pix_debug_r()                             (0x00419c04U)
+#define gr_gpcs_tpcs_mpc_pix_debug_cta_subpartition_skew_m()  (U32(0x1U) << 13U)
+#define gr_gpcs_tpcs_mpc_pix_debug_cta_subpartition_skew_disable_f()      (0x0U)
+#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r()                (0x00419848U)
+#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v)\
+				((U32(v) & 0xfffffffU) << 0U)
+#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f()     (0x10000000U)
+#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r()               (0x00419c2cU)
+#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v)\
+				((U32(v) & 0xfffffffU) << 0U)
+#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f()    (0x10000000U)
+#define gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r()              (0x00419ea8U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r()              (0x00504728U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f()\
+				(0x4U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f()\
+				(0x20U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f() (0x40U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f()\
+				(0x100U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f()\
+				(0x200U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f()\
+				(0x800U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f()   (0x2000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f()  (0x4000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f()\
+				(0x8000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f()\
+				(0x10000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f()\
+				(0x40000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f()\
+				(0x800000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_tex_format_report_f()\
+				(0x1000000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_tex_layout_report_f()\
+				(0x2000000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f()\
+				(0x4000000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_arrive_report_f() (0x8000000U)
+#define gr_gpcs_tpcs_tpccs_tpc_exception_en_r()                    (0x00419d0cU)
+#define gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()                (0x2U)
+#define gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f()              (0x10U)
+#define gr_gpcs_tpcs_tpccs_tpc_exception_en_pe_enabled_f()                (0x4U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_en_r()                    (0x0050450cU)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r)         (((r) >> 1U) & 0x1U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f()                (0x2U)
+#define gr_gpcs_gpccs_gpc_exception_en_r()                         (0x0041ac94U)
+#define gr_gpcs_gpccs_gpc_exception_en_gcc_enabled_f()                    (0x4U)
+#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v)        ((U32(v) & 0xffU) << 16U)
+#define gr_gpcs_gpccs_gpc_exception_en_gpccs_enabled_f()               (0x4000U)
+#define gr_gpcs_gpccs_gpc_exception_en_gpcmmu0_enabled_f()             (0x2000U)
+#define gr_gpc0_gpccs_gpc_exception_r()                            (0x00502c90U)
+#define gr_gpc0_gpccs_gpc_exception_prop_m()                   (U32(0x1U) << 0U)
+#define gr_gpc0_gpccs_gpc_exception_zcull_m()                  (U32(0x1U) << 1U)
+#define gr_gpc0_gpccs_gpc_exception_setup_m()                  (U32(0x1U) << 3U)
+#define gr_gpc0_gpccs_gpc_exception_pes0_m()                   (U32(0x1U) << 4U)
+#define gr_gpc0_gpccs_gpc_exception_pes1_m()                   (U32(0x1U) << 5U)
+#define gr_gpc0_gpccs_gpc_exception_gcc_v(r)                (((r) >> 2U) & 0x1U)
+#define gr_gpc0_gpccs_gpc_exception_tpc_v(r)              (((r) >> 16U) & 0xffU)
+#define gr_gpc0_gpccs_gpc_exception_gpccs_m()                 (U32(0x1U) << 14U)
+#define gr_gpc0_gpccs_gpc_exception_gpcmmu0_m()               (U32(0x1U) << 13U)
+#define gr_pri_gpc0_gcc_l15_ecc_control_r()                        (0x00501044U)
+#define gr_pri_gpc0_gcc_l15_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 1U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_r()                       (0x00504508U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(r)            (((r) >> 1U) & 0x1U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v()            (0x00000001U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m()               (U32(0x1U) << 4U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_pe_m()                (U32(0x1U) << 2U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_r()                         (0x00504704U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m()       (U32(0x1U) << 0U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(r)   (((r) >> 0U) & 0x1U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v()        (0x00000001U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f()               (0x1U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f()              (0x0U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m()       (U32(0x1U) << 31U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f()     (0x80000000U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f()           (0x0U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m()    (U32(0x1U) << 3U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f()        (0x8U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f()       (0x0U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f()        (0x40000000U)
+#define gr_gpc0_tpc0_sm0_warp_valid_mask_0_r()                     (0x00504708U)
+#define gr_gpc0_tpc0_sm0_warp_valid_mask_1_r()                     (0x0050470cU)
+#define gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r()                 (0x00504710U)
+#define gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r()                 (0x00504714U)
+#define gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r()                  (0x00504718U)
+#define gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r()                  (0x0050471cU)
+#define gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r()                 (0x00419e90U)
+#define gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r()                 (0x00419e94U)
+#define gr_gpcs_tpcs_sms_dbgr_status0_r()                          (0x00419e80U)
+#define gr_gpc0_tpc0_sm0_dbgr_status0_r()                          (0x00504700U)
+#define gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(r)      (((r) >> 4U) & 0x1U)
+#define gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v()         (0x00000001U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_r()                          (0x00504730U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(r)         (((r) >> 0U) & 0xffffU)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v()               (0x00000000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f()           (0x2U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f()             (0x5U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f()               (0x6U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f()            (0x8U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f()    (0x9U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f()       (0xbU)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f()                   (0xdU)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f()                  (0xeU)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f()           (0xfU)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f()       (0x10U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f()   (0x12U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f()                (0x17U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f()               (0x18U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f()               (0x19U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f()                 (0x20U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_arrive_f()                   (0x21U)
+#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r()                         (0x0050460cU)
+#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(r)       (((r) >> 0U) & 0x1U)
+#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(r)       (((r) >> 1U) & 0x1U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r()                       (0x00504738U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r()                    (0x0050473cU)
+#define gr_gpcs_tpcs_pes_vsc_vpc_r()                               (0x0041be08U)
+#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f()                (0x4U)
+#define gr_ppcs_wwdx_map_gpc_map_r(i)\
+		(nvgpu_safe_add_u32(0x0041bf00U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_ppcs_wwdx_map_table_cfg_r()                             (0x0041bfd0U)
+#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v)      ((U32(v) & 0xffU) << 0U)
+#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v)     ((U32(v) & 0xffU) << 8U)
+#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\
+				((U32(v) & 0x1fU) << 16U)
+#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\
+				((U32(v) & 0x7U) << 21U)
+#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r()                           (0x0041bfd4U)
+#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v)\
+				((U32(v) & 0xffffffU) << 0U)
+#define gr_ppcs_wwdx_map_table_cfg_coeff_r(i)\
+		(nvgpu_safe_add_u32(0x0041bfb0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v()               (0x00000005U)
+#define gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(v)\
+				((U32(v) & 0xffU) << 0U)
+#define gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(v)\
+				((U32(v) & 0xffU) << 8U)
+#define gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(v)\
+				((U32(v) & 0xffU) << 16U)
+#define gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(v)\
+				((U32(v) & 0xffU) << 24U)
+#define gr_bes_zrop_settings_r()                                   (0x00408850U)
+#define gr_bes_zrop_settings_num_active_ltcs_f(v)        ((U32(v) & 0xfU) << 0U)
+#define gr_bes_crop_debug3_r()                                     (0x00408908U)
+#define gr_bes_crop_debug3_comp_vdc_4to2_disable_m()          (U32(0x1U) << 31U)
+#define gr_bes_crop_debug3_blendopt_read_suppress_m()          (U32(0x1U) << 1U)
+#define gr_bes_crop_debug3_blendopt_read_suppress_disabled_f()            (0x0U)
+#define gr_bes_crop_debug3_blendopt_read_suppress_enabled_f()             (0x2U)
+#define gr_bes_crop_debug3_blendopt_fill_override_m()          (U32(0x1U) << 2U)
+#define gr_bes_crop_debug3_blendopt_fill_override_disabled_f()            (0x0U)
+#define gr_bes_crop_debug3_blendopt_fill_override_enabled_f()             (0x4U)
+#define gr_bes_crop_debug4_r()                                     (0x0040894cU)
+#define gr_bes_crop_debug4_clamp_fp_blend_m()                 (U32(0x1U) << 18U)
+#define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f()                      (0x0U)
+#define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f()               (0x40000U)
+#define gr_bes_crop_settings_r()                                   (0x00408958U)
+#define gr_bes_crop_settings_num_active_ltcs_f(v)        ((U32(v) & 0xfU) << 0U)
+#define gr_zcull_bytes_per_aliquot_per_gpu_v()                     (0x00000020U)
+#define gr_zcull_save_restore_header_bytes_per_gpc_v()             (0x00000020U)
+#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v()   (0x000000c0U)
+#define gr_zcull_subregion_qty_v()                                 (0x00000010U)
+#define gr_gpcs_tpcs_tex_in_dbg_r()                                (0x00419a00U)
+#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(v)\
+				((U32(v) & 0x1U) << 19U)
+#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m()      (U32(0x1U) << 19U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_r()                             (0x00419bf0U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(v) ((U32(v) & 0x1U) << 5U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m()        (U32(0x1U) << 5U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(v)\
+				((U32(v) & 0x1U) << 10U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m()       (U32(0x1U) << 10U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m()   (U32(0x1U) << 28U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f()       (0x0U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f() (0x10000000U)
+#define gr_fe_pwr_mode_r()                                         (0x00404170U)
+#define gr_fe_pwr_mode_mode_auto_f()                                      (0x0U)
+#define gr_fe_pwr_mode_mode_force_on_f()                                  (0x2U)
+#define gr_fe_pwr_mode_req_v(r)                             (((r) >> 4U) & 0x1U)
+#define gr_fe_pwr_mode_req_send_f()                                      (0x10U)
+#define gr_fe_pwr_mode_req_done_v()                                (0x00000000U)
+#define gr_gpcs_pri_mmu_ctrl_r()                                   (0x00418880U)
+#define gr_gpcs_pri_mmu_ctrl_vm_pg_size_m()                    (U32(0x1U) << 0U)
+#define gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m()        (U32(0x1U) << 11U)
+#define gr_gpcs_pri_mmu_ctrl_comp_fault_m()                    (U32(0x1U) << 2U)
+#define gr_gpcs_pri_mmu_ctrl_miss_gran_m()                     (U32(0x3U) << 3U)
+#define gr_gpcs_pri_mmu_ctrl_cache_mode_m()                    (U32(0x3U) << 5U)
+#define gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m()       (U32(0x3U) << 24U)
+#define gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m()\
+				(U32(0x1U) << 27U)
+#define gr_gpcs_pri_mmu_pm_unit_mask_r()                           (0x00418890U)
+#define gr_gpcs_pri_mmu_pm_req_mask_r()                            (0x00418894U)
+#define gr_gpcs_pri_mmu_debug_ctrl_r()                             (0x004188b0U)
+#define gr_gpcs_pri_mmu_debug_ctrl_debug_m()                  (U32(0x1U) << 16U)
+#define gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f()                  (0x10000U)
+#define gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f()                     (0x0U)
+#define gr_gpcs_pri_mmu_debug_wr_r()                               (0x004188b4U)
+#define gr_gpcs_pri_mmu_debug_rd_r()                               (0x004188b8U)
+#define gr_gpcs_mmu_num_active_ltcs_r()                            (0x004188acU)
+#define gr_gpcs_tpcs_sms_dbgr_control0_r()                         (0x00419e84U)
+#define gr_fe_gfxp_wfi_timeout_r()                                 (0x004041c0U)
+#define gr_fe_gfxp_wfi_timeout_count_f(v)         ((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpcs_tpcs_sm_texio_control_r()                          (0x00419bd8U)
+#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m()  (U32(0x7U) << 8U)
+#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\
+				(0x100U)
+#define gr_gpcs_tpcs_sm_disp_ctrl_r()                              (0x00419ba4U)
+#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m()             (U32(0x3U) << 11U)
+#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()              (0x1000U)
+#define gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m()     (U32(0x1U) << 21U)
+#define gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_enable_f()     (0x200000U)
+#define gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_disable_f()         (0x0U)
+#define gr_gpcs_tc_debug0_r()                                      (0x00418708U)
+#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v)\
+				((U32(v) & 0x1ffU) << 0U)
+#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m()     (U32(0x1ffU) << 0U)
+#define gr_debug_0_r()                                             (0x00400080U)
+#define gr_debug_0_scg_force_slow_drain_tpc_m()               (U32(0x1U) << 11U)
+#define gr_debug_0_scg_force_slow_drain_tpc_enabled_f()                 (0x800U)
+#define gr_debug_2_r()                                             (0x00400088U)
+#define gr_debug_2_gfxp_wfi_timeout_unit_m()                  (U32(0x1U) << 27U)
+#define gr_debug_2_gfxp_wfi_timeout_unit_usec_f()                         (0x0U)
+#define gr_debug_2_graphics_auto_go_idle_m()                  (U32(0x1U) << 17U)
+#define gr_debug_2_graphics_auto_go_idle_disabled_f()                     (0x0U)
+#define gr_debug_2_graphics_auto_go_idle_enabled_f()                  (0x20000U)
+#define gr_debug_2_compute_auto_go_idle_m()                   (U32(0x1U) << 18U)
+#define gr_debug_2_compute_auto_go_idle_disabled_f()                      (0x0U)
+#define gr_debug_2_compute_auto_go_idle_enabled_f()                   (0x40000U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r()        (0x00584200U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r()        (0x00584204U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r()            (0x00584208U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r()            (0x00584210U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r()            (0x00584214U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r()            (0x00584218U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r()            (0x0058421cU)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r()            (0x0058420cU)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r()            (0x00584220U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r()            (0x00584224U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r()            (0x00584228U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r()            (0x0058422cU)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r()            (0x00584230U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r()            (0x00584234U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r()            (0x00584238U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r()            (0x0058423cU)
+#define gr_egpc0_etpc0_sm0_dsm_perf_counter4_r()                   (0x00584614U)
+#define gr_egpc0_etpc0_sm0_dsm_perf_counter5_r()                   (0x00584618U)
+#define gr_egpc0_etpc0_sm0_dsm_perf_counter6_r()                   (0x0058461cU)
+#define gr_egpc0_etpc0_sm0_dsm_perf_counter7_r()                   (0x00584620U)
+#define gr_gpc0_gpccs_falcon_ecc_status_r()                        (0x00502678U)
+#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m() (U32(0x1U) << 0U)
+#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m() (U32(0x1U) << 1U)
+#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m()\
+				(U32(0x1U) << 4U)
+#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m()\
+				(U32(0x1U) << 5U)
+#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 10U)
+#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 8U)
+#define gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()             (0x80000000U)
+#define gr_gpc0_gpccs_falcon_ecc_address_r()                       (0x00502684U)
+#define gr_gpc0_gpccs_falcon_ecc_address_row_address_v(r)\
+				(((r) >> 0U) & 0xfffffU)
+#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r()           (0x0050267cU)
+#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r()         (0x00502680U)
+#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_fecs_falcon_ecc_control_r()                             (0x0040968cU)
+#define gr_fecs_falcon_ecc_control_inject_corrected_err_f(v)\
+				((U32(v) & 0x1U) << 0U)
+#define gr_fecs_falcon_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 1U)
+#define gr_fecs_falcon_ecc_status_r()                              (0x00409678U)
+#define gr_fecs_falcon_ecc_status_corrected_err_imem_m()       (U32(0x1U) << 0U)
+#define gr_fecs_falcon_ecc_status_corrected_err_dmem_m()       (U32(0x1U) << 1U)
+#define gr_fecs_falcon_ecc_status_uncorrected_err_imem_m()     (U32(0x1U) << 4U)
+#define gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m()     (U32(0x1U) << 5U)
+#define gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 10U)
+#define gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 8U)
+#define gr_fecs_falcon_ecc_status_reset_task_f()                   (0x80000000U)
+#define gr_fecs_falcon_ecc_address_r()                             (0x00409684U)
+#define gr_fecs_falcon_ecc_address_row_address_v(r)     (((r) >> 0U) & 0xfffffU)
+#define gr_fecs_falcon_ecc_corrected_err_count_r()                 (0x0040967cU)
+#define gr_fecs_falcon_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_fecs_falcon_ecc_uncorrected_err_count_r()               (0x00409680U)
+#define gr_fecs_falcon_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_gcc_l15_ecc_status_r()                         (0x00501048U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m() (U32(0x1U) << 0U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m() (U32(0x1U) << 1U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m()\
+				(U32(0x1U) << 4U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m()\
+				(U32(0x1U) << 5U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 8U) & 0x1U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 10U) & 0x1U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f()              (0x40000000U)
+#define gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r()            (0x0050104cU)
+#define gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r()          (0x00501054U)
+#define gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s()            (16U)
+#define gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_gpc0_mmu0_l1tlb_ecc_control_r()                         (0x00501410U)
+#define gr_gpc0_mmu0_l1tlb_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 5U)
+#define gr_gpc0_mmu0_gpcmmu_global_esr_r()                         (0x00501424U)
+#define gr_gpc0_mmu0_gpcmmu_global_esr_ecc_corrected_m()       (U32(0x1U) << 0U)
+#define gr_gpc0_mmu0_gpcmmu_global_esr_ecc_uncorrected_m()     (U32(0x1U) << 1U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_r()                          (0x00501414U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m()\
+				(U32(0x1U) << 0U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m()\
+				(U32(0x1U) << 2U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m()\
+				(U32(0x1U) << 1U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m()\
+				(U32(0x1U) << 3U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 18U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 16U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_reset_task_f()               (0x40000000U)
+#define gr_gpc0_mmu0_l1tlb_ecc_address_r()                         (0x00501420U)
+#define gr_gpc0_mmu0_l1tlb_ecc_corrected_err_count_r()             (0x00501418U)
+#define gr_gpc0_mmu0_l1tlb_ecc_corrected_err_count_total_s()               (16U)
+#define gr_gpc0_mmu0_l1tlb_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_gpc0_mmu0_l1tlb_ecc_uncorrected_err_count_r()           (0x0050141cU)
+#define gr_gpc0_mmu0_l1tlb_ecc_uncorrected_err_count_total_s()             (16U)
+#define gr_gpc0_mmu0_l1tlb_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_gpcs_gpccs_engine_reset_ctl_r()                         (0x0041a610U)
+#define gr_gpcs_gpccs_engine_reset_ctl_gpc_engine_reset_enabled_f()       (0x0U)
+#define gr_gpcs_gpccs_engine_reset_ctl_gpc_engine_reset_disabled_f()      (0x1U)
+#define gr_gpc0_gpccs_engine_reset_ctl_r()                         (0x00502610U)
+#define gr_gpc0_gpccs_engine_reset_ctl_gpc_engine_reset_v(r)\
+				(((r) >> 0U) & 0x1U)
+#define gr_gpc0_gpccs_engine_reset_ctl_gpc_engine_reset_disabled_v()\
+				(0x00000001U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ltc_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ltc_ga100.h
new file mode 100644
index 000000000..412b6afce
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ltc_ga100.h
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_LTC_GA100_H
+#define NVGPU_HW_LTC_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define ltc_pltcg_base_v()                                         (0x00140000U)
+#define ltc_pltcg_extent_v()                                       (0x0017ffffU)
+#define ltc_ltc0_ltss_v()                                          (0x00140200U)
+#define ltc_ltc0_lts0_v()                                          (0x00140400U)
+#define ltc_ltcs_ltss_v()                                          (0x0017e200U)
+#define ltc_ltc0_lts0_dstg_cfg0_r()                                (0x00140518U)
+#define ltc_ltcs_ltss_dstg_cfg0_r()                                (0x0017e318U)
+#define ltc_ltc0_lts0_tstg_cfg1_r()                                (0x00140494U)
+#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r)         (((r) >> 0U) & 0xffffU)
+#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r)           (((r) >> 16U) & 0x3U)
+#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v()                (0x00000000U)
+#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v()               (0x00000001U)
+#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v()            (0x00000002U)
+#define ltc_ltcs_ltss_cbc_ctrl1_r()                                (0x0017e26cU)
+#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f()                          (0x1U)
+#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f()                     (0x2U)
+#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f()                          (0x4U)
+#define ltc_ltcs_ltss_tstg_set_mgmt0_r()                           (0x0017e2acU)
+#define ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_f(v)\
+				((U32(v) & 0x1fU) << 16U)
+#define ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_m()      (U32(0x1fU) << 16U)
+#define ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_v(r)  (((r) >> 16U) & 0x1fU)
+#define ltc_ltc0_lts0_cbc_ctrl1_r()                                (0x0014046cU)
+#define ltc_ltcs_ltss_cbc_ctrl2_r()                                (0x0017e270U)
+#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v)\
+				((U32(v) & 0xfffffU) << 0U)
+#define ltc_ltcs_ltss_cbc_ctrl3_r()                                (0x0017e274U)
+#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v)\
+				((U32(v) & 0xfffffU) << 0U)
+#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v()         (0x000fffffU)
+#define ltc_ltcs_ltss_cbc_base_r()                                 (0x0017e278U)
+#define ltc_ltcs_ltss_cbc_base_alignment_shift_v()                 (0x0000000bU)
+#define ltc_ltcs_ltss_cbc_num_active_ltcs_r()                      (0x0017e27cU)
+#define ltc_ltcs_misc_ltc_num_active_ltcs_r()                      (0x0017e000U)
+#define ltc_ltcs_ltss_cbc_param_r()                                (0x0017e280U)
+#define ltc_ltcs_ltss_cbc_param_bytes_per_comptagline_per_slice_v(r)\
+				(((r) >> 0U) & 0x3ffU)
+#define ltc_ltcs_ltss_cbc_param_amap_divide_rounding_v(r)  (((r) >> 10U) & 0x3U)
+#define ltc_ltcs_ltss_cbc_param_amap_swizzle_rounding_v(r) (((r) >> 12U) & 0x3U)
+#define ltc_ltcs_ltss_cbc_param2_r()                               (0x0017e3f4U)
+#define ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define ltc_ltcs_ltss_cbc_param2_cache_line_size_v(r)      (((r) >> 24U) & 0xfU)
+#define ltc_ltcs_ltss_cbc_param2_slices_per_ltc_v(r)       (((r) >> 28U) & 0xfU)
+#define ltc_ltcs_ltss_tstg_set_mgmt_3_r()                          (0x0017e2b4U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_ce_imm_m()\
+				(U32(0x1U) << 23U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_ce_imm_enabled_f()\
+				(0x800000U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_fclr_imm_m()\
+				(U32(0x1U) << 21U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_fclr_imm_enabled_f()\
+				(0x200000U)
+#define ltc_ltcs_ltss_dstg_zbc_index_r()                           (0x0017e338U)
+#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v)        ((U32(v) & 0xfU) << 0U)
+#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
+		(nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U)))
+#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v()       (0x00000004U)
+#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r()               (0x0017e34cU)
+#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r()             (0x0017e204U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_2_r()                          (0x0017e2b0U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f()   (0x10000000U)
+#define ltc_ltcs_ltss_intr_r()                                     (0x0017e20cU)
+#define ltc_ltcs_ltss_intr_idle_error_cbc_m()                  (U32(0x1U) << 1U)
+#define ltc_ltcs_ltss_intr_idle_error_cbc_reset_f()                       (0x2U)
+#define ltc_ltcs_ltss_intr_en_idle_error_cbc_m()              (U32(0x1U) << 17U)
+#define ltc_ltcs_ltss_intr_en_idle_error_cbc_enabled_f()              (0x20000U)
+#define ltc_ltcs_ltss_intr_idle_error_tstg_m()                 (U32(0x1U) << 2U)
+#define ltc_ltcs_ltss_intr_idle_error_tstg_reset_f()                      (0x4U)
+#define ltc_ltcs_ltss_intr_en_idle_error_tstg_m()             (U32(0x1U) << 18U)
+#define ltc_ltcs_ltss_intr_en_idle_error_tstg_enabled_f()             (0x40000U)
+#define ltc_ltcs_ltss_intr_idle_error_dstg_m()                 (U32(0x1U) << 3U)
+#define ltc_ltcs_ltss_intr_idle_error_dstg_reset_f()                      (0x8U)
+#define ltc_ltcs_ltss_intr_en_idle_error_dstg_m()             (U32(0x1U) << 19U)
+#define ltc_ltcs_ltss_intr_en_idle_error_dstg_enabled_f()             (0x80000U)
+#define ltc_ltcs_ltss_intr_evicted_cb_m()                      (U32(0x1U) << 4U)
+#define ltc_ltcs_ltss_intr_evicted_cb_reset_f()                          (0x10U)
+#define ltc_ltcs_ltss_intr_en_evicted_cb_m()                  (U32(0x1U) << 20U)
+#define ltc_ltcs_ltss_intr_en_evicted_cb_enabled_f()                 (0x100000U)
+#define ltc_ltcs_ltss_intr_illegal_compstat_m()                (U32(0x1U) << 5U)
+#define ltc_ltcs_ltss_intr_illegal_compstat_reset_f()                    (0x20U)
+#define ltc_ltcs_ltss_intr_en_illegal_compstat_m()            (U32(0x1U) << 21U)
+#define ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f()           (0x200000U)
+#define ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f()               (0x0U)
+#define ltc_ltcs_ltss_intr_illegal_atomic_m()                 (U32(0x1U) << 12U)
+#define ltc_ltcs_ltss_intr_illegal_atomic_reset_f()                    (0x1000U)
+#define ltc_ltcs_ltss_intr_en_illegal_atomic_m()              (U32(0x1U) << 28U)
+#define ltc_ltcs_ltss_intr_en_illegal_atomic_enabled_f()           (0x10000000U)
+#define ltc_ltcs_ltss_intr_blkactivity_err_m()                (U32(0x1U) << 13U)
+#define ltc_ltcs_ltss_intr_blkactivity_err_reset_f()                   (0x2000U)
+#define ltc_ltcs_ltss_intr_en_blkactivity_err_m()             (U32(0x1U) << 29U)
+#define ltc_ltcs_ltss_intr_en_blkactivity_err_enabled_f()          (0x20000000U)
+#define ltc_ltcs_ltss_intr_illegal_compstat_access_m()        (U32(0x1U) << 14U)
+#define ltc_ltcs_ltss_intr_illegal_compstat_access_reset_f()           (0x4000U)
+#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_m()     (U32(0x1U) << 30U)
+#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_enabled_f()  (0x40000000U)
+#define ltc_ltcs_ltss_intr2_r()                                    (0x0017e208U)
+#define ltc_ltcs_ltss_intr2_trdone_invalid_tdtag_m()           (U32(0x1U) << 0U)
+#define ltc_ltcs_ltss_intr2_trdone_invalid_tdtag_reset_f()                (0x1U)
+#define ltc_ltcs_ltss_intr2_en_trdone_invalid_tdtag_m()       (U32(0x1U) << 16U)
+#define ltc_ltcs_ltss_intr2_en_trdone_invalid_tdtag_enabled_f()       (0x10000U)
+#define ltc_ltcs_ltss_intr2_unexpected_trdone_m()              (U32(0x1U) << 1U)
+#define ltc_ltcs_ltss_intr2_unexpected_trdone_reset_f()                   (0x2U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_trdone_m()          (U32(0x1U) << 17U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_trdone_enabled_f()          (0x20000U)
+#define ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_data_m() (U32(0x1U) << 2U)
+#define ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_data_reset_f()      (0x4U)
+#define ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_data_m()\
+				(U32(0x1U) << 18U)
+#define ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_data_enabled_f()\
+				(0x40000U)
+#define ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_cancel_m()\
+				(U32(0x1U) << 3U)
+#define ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_cancel_reset_f()    (0x8U)
+#define ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_cancel_m()\
+				(U32(0x1U) << 19U)
+#define ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_cancel_enabled_f()\
+				(0x80000U)
+#define ltc_ltcs_ltss_intr2_prbrs_invalid_subid_m()            (U32(0x1U) << 4U)
+#define ltc_ltcs_ltss_intr2_prbrs_invalid_subid_reset_f()                (0x10U)
+#define ltc_ltcs_ltss_intr2_en_prbrs_invalid_subid_m()        (U32(0x1U) << 20U)
+#define ltc_ltcs_ltss_intr2_en_prbrs_invalid_subid_enabled_f()       (0x100000U)
+#define ltc_ltcs_ltss_intr2_unexpected_prbrs_m()               (U32(0x1U) << 5U)
+#define ltc_ltcs_ltss_intr2_unexpected_prbrs_reset_f()                   (0x20U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_prbrs_m()           (U32(0x1U) << 21U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_prbrs_enabled_f()          (0x200000U)
+#define ltc_ltcs_ltss_intr2_prbin_unexpected_prbrs_m()         (U32(0x1U) << 6U)
+#define ltc_ltcs_ltss_intr2_prbin_unexpected_prbrs_reset_f()             (0x40U)
+#define ltc_ltcs_ltss_intr2_en_prbin_unexpected_prbrs_m()     (U32(0x1U) << 22U)
+#define ltc_ltcs_ltss_intr2_en_prbin_unexpected_prbrs_enabled_f()    (0x400000U)
+#define ltc_ltcs_ltss_intr2_prbimo_unexpected_prbrs_m()        (U32(0x1U) << 7U)
+#define ltc_ltcs_ltss_intr2_prbimo_unexpected_prbrs_reset_f()            (0x80U)
+#define ltc_ltcs_ltss_intr2_en_prbimo_unexpected_prbrs_m()    (U32(0x1U) << 23U)
+#define ltc_ltcs_ltss_intr2_en_prbimo_unexpected_prbrs_enabled_f()   (0x800000U)
+#define ltc_ltcs_ltss_intr2_prbx_missing_data_m()              (U32(0x1U) << 8U)
+#define ltc_ltcs_ltss_intr2_prbx_missing_data_reset_f()                 (0x100U)
+#define ltc_ltcs_ltss_intr2_en_prbx_missing_data_m()          (U32(0x1U) << 24U)
+#define ltc_ltcs_ltss_intr2_en_prbx_missing_data_enabled_f()        (0x1000000U)
+#define ltc_ltcs_ltss_intr2_prbx_unexpected_data_m()           (U32(0x1U) << 9U)
+#define ltc_ltcs_ltss_intr2_prbx_unexpected_data_reset_f()              (0x200U)
+#define ltc_ltcs_ltss_intr2_en_prbx_unexpected_data_m()       (U32(0x1U) << 25U)
+#define ltc_ltcs_ltss_intr2_en_prbx_unexpected_data_enabled_f()     (0x2000000U)
+#define ltc_ltcs_ltss_intr2_prbrs_unexpected_pa7_m()          (U32(0x1U) << 10U)
+#define ltc_ltcs_ltss_intr2_prbrs_unexpected_pa7_reset_f()              (0x400U)
+#define ltc_ltcs_ltss_intr2_en_prbrs_unexpected_pa7_m()       (U32(0x1U) << 26U)
+#define ltc_ltcs_ltss_intr2_en_prbrs_unexpected_pa7_enabled_f()     (0x4000000U)
+#define ltc_ltcs_ltss_intr2_trdone_unexpected_pa7_m()         (U32(0x1U) << 11U)
+#define ltc_ltcs_ltss_intr2_trdone_unexpected_pa7_reset_f()             (0x800U)
+#define ltc_ltcs_ltss_intr2_en_trdone_unexpected_pa7_m()      (U32(0x1U) << 27U)
+#define ltc_ltcs_ltss_intr2_en_trdone_unexpected_pa7_enabled_f()    (0x8000000U)
+#define ltc_ltcs_ltss_intr2_sysfill_bypass_invalid_subid_m()  (U32(0x1U) << 12U)
+#define ltc_ltcs_ltss_intr2_sysfill_bypass_invalid_subid_reset_f()     (0x1000U)
+#define ltc_ltcs_ltss_intr2_en_sysfill_bypass_invalid_subid_m()\
+				(U32(0x1U) << 28U)
+#define ltc_ltcs_ltss_intr2_en_sysfill_bypass_invalid_subid_enabled_f()\
+				(0x10000000U)
+#define ltc_ltcs_ltss_intr2_unexpected_sysfill_bypass_m()     (U32(0x1U) << 13U)
+#define ltc_ltcs_ltss_intr2_unexpected_sysfill_bypass_reset_f()        (0x2000U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_sysfill_bypass_m()  (U32(0x1U) << 29U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_sysfill_bypass_enabled_f()\
+				(0x20000000U)
+#define ltc_ltcs_ltss_intr2_checkedin_unexpected_prbrs_m()    (U32(0x1U) << 14U)
+#define ltc_ltcs_ltss_intr2_checkedin_unexpected_prbrs_reset_f()       (0x4000U)
+#define ltc_ltcs_ltss_intr2_en_checkedin_unexpected_prbrs_m() (U32(0x1U) << 30U)
+#define ltc_ltcs_ltss_intr2_en_checkedin_unexpected_prbrs_enabled_f()\
+				(0x40000000U)
+#define ltc_ltcs_ltss_intr2_checkedin_unexpected_trdone_m()   (U32(0x1U) << 15U)
+#define ltc_ltcs_ltss_intr2_checkedin_unexpected_trdone_reset_f()      (0x8000U)
+#define ltc_ltcs_ltss_intr2_en_checkedin_unexpected_trdone_m()\
+				(U32(0x1U) << 31U)
+#define ltc_ltcs_ltss_intr2_en_checkedin_unexpected_trdone_enabled_f()\
+				(0x80000000U)
+#define ltc_ltcs_ltss_intr3_r()                                    (0x0017e388U)
+#define ltc_ltcs_ltss_intr3_checkedout_rwc_upg_unexpected_nvport_m()\
+				(U32(0x1U) << 0U)
+#define ltc_ltcs_ltss_intr3_checkedout_rwc_upg_unexpected_nvport_reset_f()\
+				(0x1U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_rwc_upg_unexpected_nvport_m()\
+				(U32(0x1U) << 16U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_rwc_upg_unexpected_nvport_enabled_f()\
+				(0x10000U)
+#define ltc_ltcs_ltss_intr3_checkedout_trdone_unexpected_nvport_m()\
+				(U32(0x1U) << 1U)
+#define ltc_ltcs_ltss_intr3_checkedout_trdone_unexpected_nvport_reset_f() (0x2U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_trdone_unexpected_nvport_m()\
+				(U32(0x1U) << 17U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_trdone_unexpected_nvport_enabled_f()\
+				(0x20000U)
+#define ltc_ltcs_ltss_intr3_checkedout_prbrs_unexpected_nvport_m()\
+				(U32(0x1U) << 2U)
+#define ltc_ltcs_ltss_intr3_checkedout_prbrs_unexpected_nvport_reset_f()  (0x4U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_prbrs_unexpected_nvport_m()\
+				(U32(0x1U) << 18U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_prbrs_unexpected_nvport_enabled_f()\
+				(0x40000U)
+#define ltc_ltcs_ltss_intr3_checkedout_ninb_ncnp_req_m()       (U32(0x1U) << 3U)
+#define ltc_ltcs_ltss_intr3_checkedout_ninb_ncnp_req_reset_f()            (0x8U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_ninb_ncnp_req_m()   (U32(0x1U) << 19U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_ninb_ncnp_req_enabled_f()   (0x80000U)
+#define ltc_ltcs_ltss_intr3_checkedout_creq_ncnp_req_m()       (U32(0x1U) << 4U)
+#define ltc_ltcs_ltss_intr3_checkedout_creq_ncnp_req_reset_f()           (0x10U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_creq_ncnp_req_m()   (U32(0x1U) << 20U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_creq_ncnp_req_enabled_f()  (0x100000U)
+#define ltc_ltcs_ltss_intr3_rmwrs_invalid_subid_m()            (U32(0x1U) << 5U)
+#define ltc_ltcs_ltss_intr3_rmwrs_invalid_subid_reset_f()                (0x20U)
+#define ltc_ltcs_ltss_intr3_en_rmwrs_invalid_subid_m()        (U32(0x1U) << 21U)
+#define ltc_ltcs_ltss_intr3_en_rmwrs_invalid_subid_enabled_f()       (0x200000U)
+#define ltc_ltcs_ltss_intr3_unexpected_rmwrs_m()               (U32(0x1U) << 6U)
+#define ltc_ltcs_ltss_intr3_unexpected_rmwrs_reset_f()                   (0x40U)
+#define ltc_ltcs_ltss_intr3_en_unexpected_rmwrs_m()           (U32(0x1U) << 22U)
+#define ltc_ltcs_ltss_intr3_en_unexpected_rmwrs_enabled_f()          (0x400000U)
+#define ltc_ltcs_ltss_intr3_ecc_corrected_m()                  (U32(0x1U) << 7U)
+#define ltc_ltcs_ltss_intr3_ecc_uncorrected_m()                (U32(0x1U) << 8U)
+#define ltc_ltcs_ltss_intr3_illegal_access_kind_type1_m()     (U32(0x1U) << 10U)
+#define ltc_ltcs_ltss_intr3_illegal_access_kind_type1_reset_f()         (0x400U)
+#define ltc_ltcs_ltss_intr3_en_illegal_access_kind_type1_m()  (U32(0x1U) << 26U)
+#define ltc_ltcs_ltss_intr3_en_illegal_access_kind_type1_enabled_f()\
+				(0x4000000U)
+#define ltc_ltcs_ltss_intr3_illegal_access_kind_type2_m()     (U32(0x1U) << 11U)
+#define ltc_ltcs_ltss_intr3_illegal_access_kind_type2_reset_f()         (0x800U)
+#define ltc_ltcs_ltss_intr3_en_illegal_access_kind_type2_m()  (U32(0x1U) << 27U)
+#define ltc_ltcs_ltss_intr3_en_illegal_access_kind_type2_enabled_f()\
+				(0x8000000U)
+#define ltc_ltc0_lts0_intr_r()                                     (0x0014040cU)
+#define ltc_ltc0_lts0_intr2_r()                                    (0x00140408U)
+#define ltc_ltc0_lts0_dstg_ecc_report_r()                          (0x0014051cU)
+#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()           (U32(0xffU) << 0U)
+#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(r)       (((r) >> 0U) & 0xffU)
+#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()          (U32(0xffU) << 16U)
+#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(r)      (((r) >> 16U) & 0xffU)
+#define ltc_ltcs_ltss_tstg_cmgmt0_r()                              (0x0017e2a0U)
+#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f()                  (0x1U)
+#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f()  (0x300U)
+#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\
+				(0x10000000U)
+#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\
+				(0x20000000U)
+#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\
+				(0x40000000U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_r()                              (0x0017e2a4U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f()                       (0x1U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f()       (0x300U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f()  (0x10000U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f()  (0x10000000U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\
+				(0x20000000U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U)
+#define ltc_ltc0_ltss_tstg_cmgmt0_r()                              (0x001402a0U)
+#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f()                  (0x1U)
+#define ltc_ltc0_ltss_tstg_cmgmt1_r()                              (0x001402a4U)
+#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f()                       (0x1U)
+#define ltc_ltc0_lts0_tstg_info_1_r()                              (0x0014058cU)
+#define ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(r)  (((r) >> 0U) & 0xffffU)
+#define ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(r)      (((r) >> 16U) & 0x1fU)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_r()                          (0x0017e39cU)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_m()   (U32(0x1U) << 7U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_disabled_f()     (0x0U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_enabled_f()     (0x80U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_m()  (U32(0x1U) << 29U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_disabled_f()     (0x0U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_enabled_f()\
+				(0x20000000U)
+#define ltc_ltc0_lts0_dstg_ecc_address_r()                         (0x00140520U)
+#define ltc_ltc0_lts0_dstg_ecc_address_info_ram_m()           (U32(0x1U) << 22U)
+#define ltc_ltc0_lts0_l2_cache_ecc_address_r()                     (0x001404fcU)
+#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r()         (0x001404f4U)
+#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s()           (16U)
+#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m()\
+				(U32(0xffffU) << 0U)
+#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r()       (0x001404f8U)
+#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s()         (16U)
+#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m()\
+				(U32(0xffffU) << 0U)
+#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_r()                      (0x001404f0U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()\
+				(U32(0x1U) << 0U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m()\
+				(U32(0x1U) << 1U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m()\
+				(U32(0x1U) << 2U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m()\
+				(U32(0x1U) << 3U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m()\
+				(U32(0x1U) << 4U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m()\
+				(U32(0x1U) << 5U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 16U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 18U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f()           (0x40000000U)
+#define ltc_ltc0_lts0_intr3_r()                                    (0x00140588U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_mc_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_mc_ga100.h
new file mode 100644
index 000000000..96307a83f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_mc_ga100.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_MC_GA100_H
+#define NVGPU_HW_MC_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define mc_boot_0_r()                                              (0x00000000U)
+#define mc_boot_0_architecture_v(r)                       (((r) >> 24U) & 0x1fU)
+#define mc_boot_0_implementation_v(r)                      (((r) >> 20U) & 0xfU)
+#define mc_boot_0_major_revision_v(r)                       (((r) >> 4U) & 0xfU)
+#define mc_boot_0_minor_revision_v(r)                       (((r) >> 0U) & 0xfU)
+#define mc_enable_r()                                              (0x00000200U)
+#define mc_enable_perfmon_m()                                 (U32(0x1U) << 28U)
+#define mc_enable_perfmon_enabled_f()                              (0x10000000U)
+#define mc_device_enable_r(i)\
+		(nvgpu_safe_add_u32(0x00000600U, nvgpu_safe_mult_u32((i), 4U)))
+#define mc_device_enable__size_1_v()                               (0x00000001U)
+#define mc_intr_ltc_r()                                            (0x000001c0U)
+#define mc_intr_fbpa_r()                                           (0x000001d0U)
+#define mc_intr_fbpa_part_mask_v(r)                  (((r) >> 0U) & 0x3fffffffU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pbdma_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pbdma_ga100.h
new file mode 100644
index 000000000..5553252f9
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pbdma_ga100.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PBDMA_GA100_H
+#define NVGPU_HW_PBDMA_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pbdma_gp_entry1_r()                                        (0x10000004U)
+#define pbdma_gp_entry1_get_hi_v(r)                        (((r) >> 0U) & 0xffU)
+#define pbdma_gp_entry1_length_f(v)                ((U32(v) & 0x1fffffU) << 10U)
+#define pbdma_gp_entry1_length_v(r)                   (((r) >> 10U) & 0x1fffffU)
+#define pbdma_gp_base_r(i)\
+		(nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_base_offset_f(v)                 ((U32(v) & 0x1fffffffU) << 3U)
+#define pbdma_gp_base_rsvd_s()                                              (3U)
+#define pbdma_gp_base_hi_r(i)\
+		(nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_base_hi_offset_f(v)                    ((U32(v) & 0xffU) << 0U)
+#define pbdma_gp_base_hi_limit2_f(v)                   ((U32(v) & 0x1fU) << 16U)
+#define pbdma_gp_fetch_r(i)\
+		(nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_get_r(i)\
+		(nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_put_r(i)\
+		(nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_get_r(i)\
+		(nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_get_hi_r(i)\
+		(nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_put_r(i)\
+		(nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_put_hi_r(i)\
+		(nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_pb_header_r(i)\
+		(nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_pb_header_method_zero_f()                                   (0x0U)
+#define pbdma_pb_header_subchannel_zero_f()                               (0x0U)
+#define pbdma_pb_header_level_main_f()                                    (0x0U)
+#define pbdma_pb_header_first_true_f()                               (0x400000U)
+#define pbdma_pb_header_type_inc_f()                               (0x20000000U)
+#define pbdma_pb_header_type_non_inc_f()                           (0x60000000U)
+#define pbdma_hdr_shadow_r(i)\
+		(nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_shadow_0_r(i)\
+		(nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_shadow_1_r(i)\
+		(nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_secure_config_r(i)\
+		(nvgpu_safe_add_u32(0x00040134U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_secure_config_force_ce_split_m()                 (U32(0x1U) << 0U)
+#define pbdma_secure_config_force_ce_split_true_f()                       (0x1U)
+#define pbdma_subdevice_r(i)\
+		(nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_subdevice_id_f(v)                        ((U32(v) & 0xfffU) << 0U)
+#define pbdma_subdevice_status_active_f()                          (0x10000000U)
+#define pbdma_subdevice_channel_dma_enable_f()                     (0x20000000U)
+#define pbdma_method0_r(i)\
+		(nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_method0_addr_f(v)                        ((U32(v) & 0xfffU) << 2U)
+#define pbdma_method0_subch_v(r)                           (((r) >> 16U) & 0x7U)
+#define pbdma_method0_first_true_f()                                 (0x400000U)
+#define pbdma_method0_valid_true_f()                               (0x80000000U)
+#define pbdma_method1_r(i)\
+		(nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_method2_r(i)\
+		(nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_method3_r(i)\
+		(nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_data0_r(i)\
+		(nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_acquire_r(i)\
+		(nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_acquire_retry_man_2_f()                                     (0x2U)
+#define pbdma_acquire_retry_exp_2_f()                                   (0x100U)
+#define pbdma_acquire_timeout_exp_f(v)                  ((U32(v) & 0xfU) << 11U)
+#define pbdma_acquire_timeout_exp_max_v()                          (0x0000000fU)
+#define pbdma_acquire_timeout_exp_max_f()                              (0x7800U)
+#define pbdma_acquire_timeout_man_f(v)               ((U32(v) & 0xffffU) << 15U)
+#define pbdma_acquire_timeout_man_max_v()                          (0x0000ffffU)
+#define pbdma_acquire_timeout_man_max_f()                          (0x7fff8000U)
+#define pbdma_acquire_timeout_en_enable_f()                        (0x80000000U)
+#define pbdma_status_r(i)\
+		(nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_signature_r(i)\
+		(nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_signature_hw_valid_f()                                   (0xfaceU)
+#define pbdma_signature_sw_zero_f()                                       (0x0U)
+#define pbdma_config_r(i)\
+		(nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_config_auth_level_privileged_f()                          (0x100U)
+#define pbdma_config_userd_writeback_m()                      (U32(0x1U) << 12U)
+#define pbdma_config_userd_writeback_enable_f()                        (0x1000U)
+#define pbdma_hce_ctrl_r(i)\
+		(nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_hce_ctrl_hce_priv_mode_yes_f()                             (0x20U)
+#define pbdma_intr_0_r(i)\
+		(nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_intr_0__size_1_v()                                   (0x00000020U)
+#define pbdma_intr_0_gpfifo_pending_f()                                (0x2000U)
+#define pbdma_intr_0_gpptr_pending_f()                                 (0x4000U)
+#define pbdma_intr_0_gpentry_pending_f()                               (0x8000U)
+#define pbdma_intr_0_gpcrc_pending_f()                                (0x10000U)
+#define pbdma_intr_0_pbptr_pending_f()                                (0x20000U)
+#define pbdma_intr_0_pbentry_pending_f()                              (0x40000U)
+#define pbdma_intr_0_pbcrc_pending_f()                                (0x80000U)
+#define pbdma_intr_0_method_pending_f()                              (0x200000U)
+#define pbdma_intr_0_device_pending_f()                              (0x800000U)
+#define pbdma_intr_0_eng_reset_pending_f()                          (0x1000000U)
+#define pbdma_intr_0_semaphore_pending_f()                          (0x2000000U)
+#define pbdma_intr_0_acquire_pending_f()                            (0x4000000U)
+#define pbdma_intr_0_pri_pending_f()                                (0x8000000U)
+#define pbdma_intr_0_pbseg_pending_f()                             (0x40000000U)
+#define pbdma_intr_0_signature_pending_f()                         (0x80000000U)
+#define pbdma_intr_1_r(i)\
+		(nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_intr_1_ctxnotvalid_pending_f()                       (0x80000000U)
+#define pbdma_intr_0_en_set_tree_r(i,j)\
+		(nvgpu_safe_add_u32(nvgpu_safe_add_u32(0x00040170U, \
+		nvgpu_safe_mult_u32((i), 2048U)), nvgpu_safe_mult_u32((j), 4U)))
+#define pbdma_intr_0_en_set_tree__size_1_v()                       (0x00000020U)
+#define pbdma_intr_0_en_set_tree_gpfifo_enabled_f()                    (0x2000U)
+#define pbdma_intr_0_en_set_tree_gpptr_enabled_f()                     (0x4000U)
+#define pbdma_intr_0_en_set_tree_gpentry_enabled_f()                   (0x8000U)
+#define pbdma_intr_0_en_set_tree_gpcrc_enabled_f()                    (0x10000U)
+#define pbdma_intr_0_en_set_tree_pbptr_enabled_f()                    (0x20000U)
+#define pbdma_intr_0_en_set_tree_pbentry_enabled_f()                  (0x40000U)
+#define pbdma_intr_0_en_set_tree_pbcrc_enabled_f()                    (0x80000U)
+#define pbdma_intr_0_en_set_tree_method_enabled_f()                  (0x200000U)
+#define pbdma_intr_0_en_set_tree_device_enabled_f()                  (0x800000U)
+#define pbdma_intr_0_en_set_tree_eng_reset_enabled_f()              (0x1000000U)
+#define pbdma_intr_0_en_set_tree_semaphore_enabled_f()              (0x2000000U)
+#define pbdma_intr_0_en_set_tree_acquire_enabled_f()                (0x4000000U)
+#define pbdma_intr_0_en_set_tree_pri_enabled_f()                    (0x8000000U)
+#define pbdma_intr_0_en_set_tree_pbseg_enabled_f()                 (0x40000000U)
+#define pbdma_intr_0_en_set_tree_signature_enabled_f()             (0x80000000U)
+#define pbdma_intr_0_en_clear_tree_r(i,j)\
+		(nvgpu_safe_add_u32(nvgpu_safe_add_u32(0x00040190U, \
+		nvgpu_safe_mult_u32((i), 2048U)), nvgpu_safe_mult_u32((j), 4U)))
+#define pbdma_intr_0_en_clear_tree__size_1_v()                     (0x00000020U)
+#define pbdma_intr_0_en_clear_tree__size_2_v()                     (0x00000002U)
+#define pbdma_intr_0_en_clear_tree_gpfifo_enabled_f()                  (0x2000U)
+#define pbdma_intr_0_en_clear_tree_gpptr_enabled_f()                   (0x4000U)
+#define pbdma_intr_0_en_clear_tree_gpentry_enabled_f()                 (0x8000U)
+#define pbdma_intr_0_en_clear_tree_gpcrc_enabled_f()                  (0x10000U)
+#define pbdma_intr_0_en_clear_tree_pbptr_enabled_f()                  (0x20000U)
+#define pbdma_intr_0_en_clear_tree_pbentry_enabled_f()                (0x40000U)
+#define pbdma_intr_0_en_clear_tree_pbcrc_enabled_f()                  (0x80000U)
+#define pbdma_intr_0_en_clear_tree_method_enabled_f()                (0x200000U)
+#define pbdma_intr_0_en_clear_tree_device_enabled_f()                (0x800000U)
+#define pbdma_intr_0_en_clear_tree_eng_reset_enabled_f()            (0x1000000U)
+#define pbdma_intr_0_en_clear_tree_semaphore_enabled_f()            (0x2000000U)
+#define pbdma_intr_0_en_clear_tree_acquire_enabled_f()              (0x4000000U)
+#define pbdma_intr_0_en_clear_tree_pri_enabled_f()                  (0x8000000U)
+#define pbdma_intr_0_en_clear_tree_pbseg_enabled_f()               (0x40000000U)
+#define pbdma_intr_0_en_clear_tree_signature_enabled_f()           (0x80000000U)
+#define pbdma_intr_1_en_set_tree_r(i,j)\
+		(nvgpu_safe_add_u32(nvgpu_safe_add_u32(0x00040180U, \
+		nvgpu_safe_mult_u32((i), 2048U)), nvgpu_safe_mult_u32((j), 4U)))
+#define pbdma_intr_1_en_set_tree_hce_re_illegal_op_enabled_f()            (0x1U)
+#define pbdma_intr_1_en_set_tree_hce_re_alignb_enabled_f()                (0x2U)
+#define pbdma_intr_1_en_set_tree_hce_priv_enabled_f()                     (0x4U)
+#define pbdma_intr_1_en_set_tree_hce_illegal_mthd_enabled_f()             (0x8U)
+#define pbdma_intr_1_en_set_tree_hce_illegal_class_enabled_f()           (0x10U)
+#define pbdma_intr_1_en_set_tree_ctxnotvalid_enabled_f()           (0x80000000U)
+#define pbdma_intr_1_en_clear_tree_r(i,j)\
+		(nvgpu_safe_add_u32(nvgpu_safe_add_u32(0x000401a0U, \
+		nvgpu_safe_mult_u32((i), 2048U)), nvgpu_safe_mult_u32((j), 4U)))
+#define pbdma_intr_1_en_clear_tree_hce_re_illegal_op_enabled_f()          (0x1U)
+#define pbdma_intr_1_en_clear_tree_hce_re_alignb_enabled_f()              (0x2U)
+#define pbdma_intr_1_en_clear_tree_hce_priv_enabled_f()                   (0x4U)
+#define pbdma_intr_1_en_clear_tree_hce_illegal_mthd_enabled_f()           (0x8U)
+#define pbdma_intr_1_en_clear_tree_hce_illegal_class_enabled_f()         (0x10U)
+#define pbdma_intr_1_en_clear_tree_ctxnotvalid_enabled_f()         (0x80000000U)
+#define pbdma_udma_nop_r()                                         (0x00000008U)
+#define pbdma_target_r(i)\
+		(nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_target_engine_f(v)                        ((U32(v) & 0x1fU) << 0U)
+#define pbdma_target_engine_sw_f()                                       (0x1fU)
+#define pbdma_target_eng_ctx_valid_true_f()                           (0x10000U)
+#define pbdma_target_ce_ctx_valid_true_f()                            (0x20000U)
+#define pbdma_set_channel_info_r(i)\
+		(nvgpu_safe_add_u32(0x000400fcU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_set_channel_info_veid_f(v)                ((U32(v) & 0x3fU) << 8U)
+#define pbdma_set_channel_info_chid_f(v)              ((U32(v) & 0xfffU) << 16U)
+#define pbdma_status_sched_r(i)\
+		(nvgpu_safe_add_u32(0x0004015cU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_status_sched_tsgid_v(r)                     (((r) >> 0U) & 0xfffU)
+#define pbdma_status_sched_chan_status_v(r)                (((r) >> 13U) & 0x7U)
+#define pbdma_status_sched_chan_status_valid_v()                   (0x00000001U)
+#define pbdma_status_sched_chan_status_chsw_save_v()               (0x00000005U)
+#define pbdma_status_sched_chan_status_chsw_load_v()               (0x00000006U)
+#define pbdma_status_sched_chan_status_chsw_switch_v()             (0x00000007U)
+#define pbdma_status_sched_next_tsgid_v(r)               (((r) >> 16U) & 0xfffU)
+#define pbdma_intr_notify_r(i)\
+		(nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_intr_notify_vector_f(v)                  ((U32(v) & 0xfffU) << 0U)
+#define pbdma_intr_notify_ctrl_gsp_disable_f()                            (0x0U)
+#define pbdma_intr_notify_ctrl_cpu_enable_f()                      (0x80000000U)
+#define pbdma_cfg0_r(i)\
+		(nvgpu_safe_add_u32(0x00040104U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_cfg0__size_1_v()                                     (0x00000020U)
+#define pbdma_cfg0_pbdma_fault_id_v(r)                    (((r) >> 0U) & 0x3ffU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_perf_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_perf_ga100.h
new file mode 100644
index 000000000..cc49baaac
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_perf_ga100.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PERF_GA100_H
+#define NVGPU_HW_PERF_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define perf_pmmgpc_perdomain_offset_v()                           (0x00000200U)
+#define perf_pmmsys_perdomain_offset_v()                           (0x00000200U)
+#define perf_pmmgpc_base_v()                                       (0x00180000U)
+#define perf_pmmgpc_extent_v()                                     (0x00183fffU)
+#define perf_pmmsys_base_v()                                       (0x00260000U)
+#define perf_pmmsys_extent_v()                                     (0x00267fffU)
+#define perf_pmmfbp_base_v()                                       (0x00200000U)
+#define perf_pmmfbp_extent_v()                                     (0x00203fffU)
+#define perf_pmasys_control_r()                                    (0x0024a000U)
+#define perf_pmasys_channel_control_r(i)\
+		(nvgpu_safe_add_u32(0x0024a730U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_control__size_1_v()                    (0x00000001U)
+#define perf_pmasys_channel_control_membuf_status_overflowed_f()         (0x10U)
+#define perf_pmasys_channel_control_membuf_clear_status_doit_f()         (0x20U)
+#define perf_pmasys_channel_mem_block_r(i)\
+		(nvgpu_safe_add_u32(0x0024a638U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_mem_block__size_1_v()                  (0x00000001U)
+#define perf_pmasys_channel_mem_block_base_f(v)    ((U32(v) & 0xfffffffU) << 0U)
+#define perf_pmasys_channel_mem_block_target_f(v)       ((U32(v) & 0x3U) << 28U)
+#define perf_pmasys_channel_mem_block_target_lfb_f()                      (0x0U)
+#define perf_pmasys_channel_mem_block_target_sys_coh_f()           (0x20000000U)
+#define perf_pmasys_channel_mem_block_target_sys_ncoh_f()          (0x30000000U)
+#define perf_pmasys_channel_mem_block_valid_true_f()               (0x80000000U)
+#define perf_pmasys_channel_mem_block_valid_false_f()                     (0x0U)
+#define perf_pmasys_channel_outbase_r(i)\
+		(nvgpu_safe_add_u32(0x0024a644U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_outbase__size_1_v()                    (0x00000001U)
+#define perf_pmasys_channel_outbaseupper_r(i)\
+		(nvgpu_safe_add_u32(0x0024a648U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_outbaseupper__size_1_v()               (0x00000001U)
+#define perf_pmasys_channel_outbaseupper_ptr_f(v)       ((U32(v) & 0xffU) << 0U)
+#define perf_pmasys_channel_outsize_r(i)\
+		(nvgpu_safe_add_u32(0x0024a64cU, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_outsize__size_1_v()                    (0x00000001U)
+#define perf_pmasys_channel_mem_bytes_r(i)\
+		(nvgpu_safe_add_u32(0x0024a654U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_mem_bytes__size_1_v()                  (0x00000001U)
+#define perf_pmasys_channel_mem_bump_r(i)\
+		(nvgpu_safe_add_u32(0x0024a624U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_mem_bump__size_1_v()                   (0x00000001U)
+#define perf_pmasys_enginestatus_r()                               (0x0024a75cU)
+#define perf_pmasys_enginestatus_rbufempty_empty_v()               (0x00000001U)
+#define perf_pmasys_enginestatus_rbufempty_empty_f()                     (0x10U)
+#define perf_pmasys_controlreg_r()                                 (0x0024a03cU)
+#define perf_pmasys_controlreg_legacy_mode_m()                 (U32(0x1U) << 0U)
+#define perf_pmasys_controlreg_legacy_mode_enable_f()                     (0x0U)
+#define perf_pmasys_controlreg_legacy_mode_disable_f()                    (0x1U)
+#define perf_pmmsys_engine_sel_r(i)\
+		(nvgpu_safe_add_u32(0x0026006cU, nvgpu_safe_mult_u32((i), 512U)))
+#define perf_pmmsys_engine_sel__size_1_v()                         (0x0000003aU)
+#define perf_pmmfbp_engine_sel_r(i)\
+		(nvgpu_safe_add_u32(0x0020006cU, nvgpu_safe_mult_u32((i), 512U)))
+#define perf_pmmfbp_engine_sel__size_1_v()                         (0x00000011U)
+#define perf_pmmgpc_engine_sel_r(i)\
+		(nvgpu_safe_add_u32(0x0018006cU, nvgpu_safe_mult_u32((i), 512U)))
+#define perf_pmmgpc_engine_sel__size_1_v()                         (0x0000001aU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pgsp_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pgsp_ga100.h
new file mode 100644
index 000000000..95372d2ef
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pgsp_ga100.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PGSP_GA100_H
+#define NVGPU_HW_PGSP_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pgsp_falcon_irqsset_r()                                    (0x00110000U)
+#define pgsp_falcon_nxtctx_r()                                     (0x00110054U)
+#define pgsp_falcon_nxtctx_ctxptr_f(v)             ((U32(v) & 0xfffffffU) << 0U)
+#define pgsp_falcon_nxtctx_ctxtgt_fb_f()                                  (0x0U)
+#define pgsp_falcon_nxtctx_ctxtgt_sys_coh_f()                      (0x20000000U)
+#define pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f()                     (0x30000000U)
+#define pgsp_falcon_nxtctx_ctxvalid_f(v)                ((U32(v) & 0x1U) << 30U)
+#define pgsp_falcon_itfen_r()                                      (0x00110048U)
+#define pgsp_falcon_itfen_ctxen_enable_f()                                (0x1U)
+#define pgsp_falcon_engctl_r()                                     (0x001100a4U)
+#define pgsp_falcon_engctl_switch_context_true_f()                        (0x8U)
+#define pgsp_falcon_debug1_r()                                     (0x00110090U)
+#define pgsp_falcon_debug1_ctxsw_mode_m()                     (U32(0x1U) << 16U)
+#define pgsp_fbif_transcfg_r(i)\
+		(nvgpu_safe_add_u32(0x00110600U, nvgpu_safe_mult_u32((i), 4U)))
+#define pgsp_fbif_transcfg_target_local_fb_f()                            (0x0U)
+#define pgsp_fbif_transcfg_target_coherent_sysmem_f()                     (0x1U)
+#define pgsp_fbif_transcfg_target_noncoherent_sysmem_f()                  (0x2U)
+#define pgsp_fbif_transcfg_mem_type_v(r)                    (((r) >> 2U) & 0x1U)
+#define pgsp_fbif_transcfg_mem_type_virtual_f()                           (0x0U)
+#define pgsp_fbif_transcfg_mem_type_physical_f()                          (0x4U)
+#define pgsp_falcon_engine_r()                                     (0x001103c0U)
+#define pgsp_falcon_engine_reset_true_f()                                 (0x1U)
+#define pgsp_falcon_engine_reset_false_f()                                (0x0U)
+#define pgsp_fbif_ctl_r()                                          (0x00110624U)
+#define pgsp_fbif_ctl_allow_phys_no_ctx_allow_f()                        (0x80U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pnvdec_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pnvdec_ga100.h
new file mode 100644
index 000000000..6832dc277
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pnvdec_ga100.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PNVDEC_GA100_H
+#define NVGPU_HW_PNVDEC_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pnvdec_falcon_irqsset_r(i)\
+		(nvgpu_safe_add_u32(0x00848000U, nvgpu_safe_mult_u32((i), 16384U)))
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pram_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pram_ga100.h
new file mode 100644
index 000000000..bb52ef6f4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pram_ga100.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRAM_GA100_H
+#define NVGPU_HW_PRAM_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pram_data032_r(i)\
+		(nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U)))
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_fbp_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_fbp_ga100.h
new file mode 100644
index 000000000..5a48e7445
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_fbp_ga100.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRI_FBP_GA100_H
+#define NVGPU_HW_PRI_FBP_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pri_fbp_fbp0_priv_error_adr_r()                            (0x00128120U)
+#define pri_fbp_fbp0_priv_error_wrdat_r()                          (0x00128124U)
+#define pri_fbp_fbp0_priv_error_info_r()                           (0x00128128U)
+#define pri_fbp_fbp0_priv_error_info_subid_v(r)           (((r) >> 24U) & 0xffU)
+#define pri_fbp_fbp0_priv_error_info_local_ordering_v(r)   (((r) >> 22U) & 0x1U)
+#define pri_fbp_fbp0_priv_error_info_priv_level_v(r)       (((r) >> 20U) & 0x3U)
+#define pri_fbp_fbp0_priv_error_info_priv_master_v(r)      (((r) >> 0U) & 0xffU)
+#define pri_fbp_fbp0_priv_error_code_r()                           (0x0012812cU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_gpc_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_gpc_ga100.h
new file mode 100644
index 000000000..abd53f41e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_gpc_ga100.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRI_GPC_GA100_H
+#define NVGPU_HW_PRI_GPC_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pri_gpc_gpc0_priv_error_adr_r()                            (0x00124120U)
+#define pri_gpc_gpc0_priv_error_wrdat_r()                          (0x00124124U)
+#define pri_gpc_gpc0_priv_error_info_r()                           (0x00124128U)
+#define pri_gpc_gpc0_priv_error_info_subid_v(r)           (((r) >> 24U) & 0xffU)
+#define pri_gpc_gpc0_priv_error_info_local_ordering_v(r)   (((r) >> 22U) & 0x1U)
+#define pri_gpc_gpc0_priv_error_info_priv_level_v(r)       (((r) >> 20U) & 0x3U)
+#define pri_gpc_gpc0_priv_error_info_priv_master_v(r)      (((r) >> 0U) & 0xffU)
+#define pri_gpc_gpc0_priv_error_code_r()                           (0x0012412cU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_ringmaster_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_ringmaster_ga100.h
new file mode 100644
index 000000000..a8c467c18
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_ringmaster_ga100.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRI_RINGMASTER_GA100_H
+#define NVGPU_HW_PRI_RINGMASTER_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pri_ringmaster_command_r()                                 (0x0012004cU)
+#define pri_ringmaster_command_cmd_m()                        (U32(0x3fU) << 0U)
+#define pri_ringmaster_command_cmd_v(r)                    (((r) >> 0U) & 0x3fU)
+#define pri_ringmaster_command_cmd_no_cmd_v()                      (0x00000000U)
+#define pri_ringmaster_command_cmd_ack_interrupt_f()                      (0x2U)
+#define pri_ringmaster_command_cmd_enumerate_and_start_ring_f()           (0x4U)
+#define pri_ringmaster_master_ring_start_results_r()               (0x00120050U)
+#define pri_ringmaster_master_ring_start_results_connectivity_pass_f()    (0x1U)
+#define pri_ringmaster_intr_status0_r()                            (0x00120058U)
+#define pri_ringmaster_intr_status0_ring_start_conn_fault_v(r)\
+				(((r) >> 0U) & 0x1U)
+#define pri_ringmaster_intr_status0_disconnect_fault_v(r)   (((r) >> 1U) & 0x1U)
+#define pri_ringmaster_intr_status0_overflow_fault_v(r)     (((r) >> 2U) & 0x1U)
+#define pri_ringmaster_intr_status0_ring_enum_fault_v(r)    (((r) >> 3U) & 0x1U)
+#define pri_ringmaster_intr_status0_gpc_rs_map_config_fault_v(r)\
+				(((r) >> 4U) & 0x1U)
+#define pri_ringmaster_intr_status0_gbl_write_error_fbp_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define pri_ringmaster_intr_status0_gbl_write_error_sys_v(r)\
+				(((r) >> 8U) & 0x1U)
+#define pri_ringmaster_intr_status1_r()                            (0x0012005cU)
+#define pri_ringmaster_enum_fbp_r()                                (0x00120074U)
+#define pri_ringmaster_enum_fbp_count_v(r)                 (((r) >> 0U) & 0x1fU)
+#define pri_ringmaster_enum_gpc_r()                                (0x00120078U)
+#define pri_ringmaster_enum_gpc_count_v(r)                 (((r) >> 0U) & 0x1fU)
+#define pri_ringmaster_enum_ltc_r()                                (0x0012006cU)
+#define pri_ringmaster_gpc_rs_map_r(i)\
+		(nvgpu_safe_add_u32(0x001200c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define pri_ringmaster_gpc_rs_map_smc_valid_f(v)        ((U32(v) & 0x1U) << 31U)
+#define pri_ringmaster_gpc_rs_map_smc_valid_m()               (U32(0x1U) << 31U)
+#define pri_ringmaster_gpc_rs_map_smc_valid_true_v()               (0x00000001U)
+#define pri_ringmaster_gpc_rs_map_smc_valid_false_v()              (0x00000000U)
+#define pri_ringmaster_gpc_rs_map_smc_engine_id_f(v)     ((U32(v) & 0x7U) << 8U)
+#define pri_ringmaster_gpc_rs_map_smc_engine_id_m()            (U32(0x7U) << 8U)
+#define pri_ringmaster_gpc_rs_map_smc_engine_local_cluster_id_f(v)\
+				((U32(v) & 0x7U) << 0U)
+#define pri_ringmaster_gpc_rs_map_smc_engine_local_cluster_id_m()\
+				(U32(0x7U) << 0U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_ringstation_sys_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_ringstation_sys_ga100.h
new file mode 100644
index 000000000..93a9ed22e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_ringstation_sys_ga100.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRI_RINGSTATION_SYS_GA100_H
+#define NVGPU_HW_PRI_RINGSTATION_SYS_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pri_ringstation_sys_master_ring_start_results_r()          (0x00120050U)
+#define pri_ringstation_sys_master_ring_start_results_connectivity_pass_f()\
+				(0x1U)
+#define pri_ringstation_sys_bar0_to_pri_window_r()                 (0x00122144U)
+#define pri_ringstation_sys_bar0_to_pri_window_index_f(v)\
+				((U32(v) & 0x3fU) << 0U)
+#define pri_ringstation_sys_bar0_to_pri_window_index_m()      (U32(0x3fU) << 0U)
+#define pri_ringstation_sys_bar0_to_pri_window_enable_f(v)\
+				((U32(v) & 0x1U) << 31U)
+#define pri_ringstation_sys_bar0_to_pri_window_enable_m()     (U32(0x1U) << 31U)
+#define pri_ringstation_sys_bar0_to_pri_window_enable_enable_v()   (0x00000001U)
+#define pri_ringstation_sys_bar0_to_pri_window_enable_disable_v()  (0x00000000U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_sys_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_sys_ga100.h
new file mode 100644
index 000000000..5c81ec978
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pri_sys_ga100.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRI_SYS_GA100_H
+#define NVGPU_HW_PRI_SYS_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pri_sys_priv_error_adr_r()                                 (0x00122120U)
+#define pri_sys_priv_error_wrdat_r()                               (0x00122124U)
+#define pri_sys_priv_error_info_r()                                (0x00122128U)
+#define pri_sys_priv_error_info_subid_v(r)                (((r) >> 24U) & 0xffU)
+#define pri_sys_priv_error_info_local_ordering_v(r)        (((r) >> 22U) & 0x1U)
+#define pri_sys_priv_error_info_priv_level_v(r)            (((r) >> 20U) & 0x3U)
+#define pri_sys_priv_error_info_priv_master_v(r)           (((r) >> 0U) & 0xffU)
+#define pri_sys_priv_error_code_r()                                (0x0012212cU)
+#define pri_sys_pri_error_r()                                      (0x00000000U)
+#define pri_sys_pri_error_code_f(v)                 ((U32(v) & 0xffffffU) << 8U)
+#define pri_sys_pri_error_code_v(r)                    (((r) >> 8U) & 0xffffffU)
+#define pri_sys_pri_error_code_host_fecs_err_v()                   (0x00bad00fU)
+#define pri_sys_pri_error_code_host_pri_timeout_v()                (0x00bad001U)
+#define pri_sys_pri_error_code_host_fb_ack_timeout_v()             (0x00bad0b0U)
+#define pri_sys_pri_error_code_fecs_pri_timeout_v()                (0x00badf10U)
+#define pri_sys_pri_error_code_fecs_pri_orphan_v()                 (0x00badf20U)
+#define pri_sys_pri_error_code_fecs_dead_ring_v()                  (0x00badf30U)
+#define pri_sys_pri_error_code_fecs_trap_v()                       (0x00badf40U)
+#define pri_sys_pri_error_code_fecs_pri_client_err_v()             (0x00badf50U)
+#define pri_sys_pri_error_extra_v(r)                       (((r) >> 0U) & 0xffU)
+#define pri_sys_pri_error_extra_async_idle_v()                     (0x00000001U)
+#define pri_sys_pri_error_extra_extra_sync_req_v()                 (0x00000020U)
+#define pri_sys_pri_error_extra_no_such_address_v()                (0x00000040U)
+#define pri_sys_pri_error_fecs_pri_route_err_extra_write_only_v()  (0x00000045U)
+#define pri_sys_pri_error_local_priv_ring_extra_no_such_target_v() (0x00000080U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_proj_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_proj_ga100.h
new file mode 100644
index 000000000..8ce754d86
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_proj_ga100.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PROJ_GA100_H
+#define NVGPU_HW_PROJ_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define proj_gpc_base_v()                                          (0x00500000U)
+#define proj_gpc_shared_base_v()                                   (0x00418000U)
+#define proj_gpc_stride_v()                                        (0x00008000U)
+#define proj_gpc_priv_stride_v()                                   (0x00000800U)
+#define proj_gpc_addr_width_v()                                    (0x0000000fU)
+#define proj_fbp_priv_stride_v()                                   (0x00000800U)
+#define proj_ltc_stride_v()                                        (0x00002000U)
+#define proj_lts_stride_v()                                        (0x00000200U)
+#define proj_fbpa_base_v()                                         (0x00900000U)
+#define proj_fbpa_shared_base_v()                                  (0x009a0000U)
+#define proj_fbpa_stride_v()                                       (0x00004000U)
+#define proj_ppc_in_gpc_base_v()                                   (0x00003000U)
+#define proj_ppc_in_gpc_shared_base_v()                            (0x00003e00U)
+#define proj_ppc_in_gpc_stride_v()                                 (0x00000200U)
+#define proj_rop_base_v()                                          (0x00410000U)
+#define proj_rop_shared_base_v()                                   (0x00408800U)
+#define proj_rop_stride_v()                                        (0x00000400U)
+#define proj_tpc_in_gpc_base_v()                                   (0x00004000U)
+#define proj_tpc_in_gpc_stride_v()                                 (0x00000800U)
+#define proj_tpc_in_gpc_shared_base_v()                            (0x00001800U)
+#define proj_tpc_addr_width_v()                                    (0x0000000bU)
+#define proj_smpc_base_v()                                         (0x00000200U)
+#define proj_smpc_shared_base_v()                                  (0x00000300U)
+#define proj_smpc_unique_base_v()                                  (0x00000600U)
+#define proj_smpc_stride_v()                                       (0x00000100U)
+#define proj_host_num_engines_v()                                  (0x0000001aU)
+#define proj_host_num_pbdma_v()                                    (0x00000020U)
+#define proj_scal_litter_num_tpc_per_gpc_v()                       (0x00000008U)
+#define proj_scal_litter_num_fbps_v()                              (0x0000000cU)
+#define proj_scal_litter_num_fbpas_v()                             (0x00000018U)
+#define proj_scal_litter_num_gpcs_v()                              (0x00000008U)
+#define proj_scal_litter_num_pes_per_gpc_v()                       (0x00000003U)
+#define proj_scal_litter_num_zcull_banks_v()                       (0x00000004U)
+#define proj_scal_litter_num_sm_per_tpc_v()                        (0x00000002U)
+#define proj_scal_litter_num_ltc_lts_sets_v()                      (0x00000100U)
+#define proj_scal_litter_num_ltc_lts_ways_v()                      (0x00000010U)
+#define proj_sm_unique_base_v()                                    (0x00000700U)
+#define proj_sm_shared_base_v()                                    (0x00000680U)
+#define proj_sm_stride_v()                                         (0x00000080U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_psec_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_psec_ga100.h
new file mode 100644
index 000000000..9740a1791
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_psec_ga100.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PSEC_GA100_H
+#define NVGPU_HW_PSEC_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define psec_falcon_irqsset_r()                                    (0x00840000U)
+#define psec_falcon_irqsset_swgen0_set_f()                               (0x40U)
+#define psec_falcon_irqsclr_r()                                    (0x00840004U)
+#define psec_falcon_irqstat_r()                                    (0x00840008U)
+#define psec_falcon_irqstat_halt_true_f()                                (0x10U)
+#define psec_falcon_irqstat_exterr_true_f()                              (0x20U)
+#define psec_falcon_irqstat_swgen0_true_f()                              (0x40U)
+#define psec_falcon_irqmset_r()                                    (0x00840010U)
+#define psec_falcon_irqmset_gptmr_f(v)                   ((U32(v) & 0x1U) << 0U)
+#define psec_falcon_irqmset_wdtmr_f(v)                   ((U32(v) & 0x1U) << 1U)
+#define psec_falcon_irqmset_mthd_f(v)                    ((U32(v) & 0x1U) << 2U)
+#define psec_falcon_irqmset_ctxsw_f(v)                   ((U32(v) & 0x1U) << 3U)
+#define psec_falcon_irqmset_halt_f(v)                    ((U32(v) & 0x1U) << 4U)
+#define psec_falcon_irqmset_exterr_f(v)                  ((U32(v) & 0x1U) << 5U)
+#define psec_falcon_irqmset_swgen0_f(v)                  ((U32(v) & 0x1U) << 6U)
+#define psec_falcon_irqmset_swgen1_f(v)                  ((U32(v) & 0x1U) << 7U)
+#define psec_falcon_irqmask_r()                                    (0x00840018U)
+#define psec_falcon_irqdest_r()                                    (0x0084001cU)
+#define psec_falcon_irqdest_host_gptmr_f(v)              ((U32(v) & 0x1U) << 0U)
+#define psec_falcon_irqdest_host_wdtmr_f(v)              ((U32(v) & 0x1U) << 1U)
+#define psec_falcon_irqdest_host_mthd_f(v)               ((U32(v) & 0x1U) << 2U)
+#define psec_falcon_irqdest_host_ctxsw_f(v)              ((U32(v) & 0x1U) << 3U)
+#define psec_falcon_irqdest_host_halt_f(v)               ((U32(v) & 0x1U) << 4U)
+#define psec_falcon_irqdest_host_exterr_f(v)             ((U32(v) & 0x1U) << 5U)
+#define psec_falcon_irqdest_host_swgen0_f(v)             ((U32(v) & 0x1U) << 6U)
+#define psec_falcon_irqdest_host_swgen1_f(v)             ((U32(v) & 0x1U) << 7U)
+#define psec_falcon_irqdest_host_ext_f(v)               ((U32(v) & 0xffU) << 8U)
+#define psec_falcon_irqdest_target_gptmr_f(v)           ((U32(v) & 0x1U) << 16U)
+#define psec_falcon_irqdest_target_wdtmr_f(v)           ((U32(v) & 0x1U) << 17U)
+#define psec_falcon_irqdest_target_mthd_f(v)            ((U32(v) & 0x1U) << 18U)
+#define psec_falcon_irqdest_target_ctxsw_f(v)           ((U32(v) & 0x1U) << 19U)
+#define psec_falcon_irqdest_target_halt_f(v)            ((U32(v) & 0x1U) << 20U)
+#define psec_falcon_irqdest_target_exterr_f(v)          ((U32(v) & 0x1U) << 21U)
+#define psec_falcon_irqdest_target_swgen0_f(v)          ((U32(v) & 0x1U) << 22U)
+#define psec_falcon_irqdest_target_swgen1_f(v)          ((U32(v) & 0x1U) << 23U)
+#define psec_falcon_irqdest_target_ext_f(v)            ((U32(v) & 0xffU) << 24U)
+#define psec_falcon_nxtctx_r()                                     (0x00840054U)
+#define psec_falcon_itfen_r()                                      (0x00840048U)
+#define psec_falcon_itfen_ctxen_enable_f()                                (0x1U)
+#define psec_falcon_engctl_r()                                     (0x008400a4U)
+#define psec_falcon_cpuctl_alias_r()                               (0x00840130U)
+#define psec_falcon_cpuctl_alias_startcpu_f(v)           ((U32(v) & 0x1U) << 1U)
+#define psec_falcon_exterrstat_r()                                 (0x0084016cU)
+#define psec_falcon_exterrstat_valid_m()                      (U32(0x1U) << 31U)
+#define psec_falcon_debug1_r()                                     (0x00840090U)
+#define psec_falcon_debug1_ctxsw_mode_m()                     (U32(0x1U) << 16U)
+#define psec_fbif_transcfg_r(i)\
+		(nvgpu_safe_add_u32(0x00840600U, nvgpu_safe_mult_u32((i), 4U)))
+#define psec_fbif_transcfg_target_local_fb_f()                            (0x0U)
+#define psec_fbif_transcfg_target_coherent_sysmem_f()                     (0x1U)
+#define psec_fbif_transcfg_target_noncoherent_sysmem_f()                  (0x2U)
+#define psec_fbif_transcfg_mem_type_v(r)                    (((r) >> 2U) & 0x1U)
+#define psec_fbif_transcfg_mem_type_virtual_f()                           (0x0U)
+#define psec_fbif_transcfg_mem_type_physical_f()                          (0x4U)
+#define psec_falcon_engine_r()                                     (0x008403c0U)
+#define psec_falcon_engine_reset_true_f()                                 (0x1U)
+#define psec_falcon_engine_reset_false_f()                                (0x0U)
+#define psec_fbif_ctl_r()                                          (0x00840624U)
+#define psec_fbif_ctl_allow_phys_no_ctx_allow_f()                        (0x80U)
+#define psec_hwcfg_r()                                             (0x00840abcU)
+#define psec_hwcfg_emem_size_f(v)                      ((U32(v) & 0x1ffU) << 0U)
+#define psec_falcon_hwcfg1_r()                                     (0x0084012cU)
+#define psec_falcon_hwcfg1_dmem_tag_width_v(r)            (((r) >> 21U) & 0x1fU)
+#define psec_ememc_r(i)\
+		(nvgpu_safe_add_u32(0x00840ac0U, nvgpu_safe_mult_u32((i), 8U)))
+#define psec_ememc__size_1_v()                                     (0x00000004U)
+#define psec_ememc_blk_m()                                    (U32(0xffU) << 8U)
+#define psec_ememc_offs_m()                                   (U32(0x3fU) << 2U)
+#define psec_ememc_aincw_m()                                  (U32(0x1U) << 24U)
+#define psec_ememc_aincr_m()                                  (U32(0x1U) << 25U)
+#define psec_ememd_r(i)\
+		(nvgpu_safe_add_u32(0x00840ac4U, nvgpu_safe_mult_u32((i), 8U)))
+#define psec_msgq_head_r(i)\
+		(nvgpu_safe_add_u32(0x00840c80U, nvgpu_safe_mult_u32((i), 8U)))
+#define psec_msgq_head_val_f(v)                   ((U32(v) & 0xffffffffU) << 0U)
+#define psec_msgq_head_val_v(r)                      (((r) >> 0U) & 0xffffffffU)
+#define psec_msgq_tail_r(i)\
+		(nvgpu_safe_add_u32(0x00840c84U, nvgpu_safe_mult_u32((i), 8U)))
+#define psec_msgq_tail_val_f(v)                   ((U32(v) & 0xffffffffU) << 0U)
+#define psec_msgq_tail_val_v(r)                      (((r) >> 0U) & 0xffffffffU)
+#define psec_queue_head_r(i)\
+		(nvgpu_safe_add_u32(0x00840c00U, nvgpu_safe_mult_u32((i), 8U)))
+#define psec_queue_head_address_f(v)              ((U32(v) & 0xffffffffU) << 0U)
+#define psec_queue_head_address_v(r)                 (((r) >> 0U) & 0xffffffffU)
+#define psec_queue_tail_r(i)\
+		(nvgpu_safe_add_u32(0x00840c04U, nvgpu_safe_mult_u32((i), 8U)))
+#define psec_queue_tail_address_f(v)              ((U32(v) & 0xffffffffU) << 0U)
+#define psec_queue_tail_address_v(r)                 (((r) >> 0U) & 0xffffffffU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pwr_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pwr_ga100.h
new file mode 100644
index 000000000..1a53a1435
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_pwr_ga100.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PWR_GA100_H
+#define NVGPU_HW_PWR_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pwr_falcon_irqsset_r()                                     (0x0010a000U)
+#define pwr_falcon_irqsset_swgen0_set_f()                                (0x40U)
+#define pwr_falcon_irqsclr_r()                                     (0x0010a004U)
+#define pwr_falcon_irqstat_r()                                     (0x0010a008U)
+#define pwr_falcon_irqstat_halt_true_f()                                 (0x10U)
+#define pwr_falcon_irqstat_exterr_true_f()                               (0x20U)
+#define pwr_falcon_irqstat_swgen0_true_f()                               (0x40U)
+#define pwr_falcon_irqstat_ext_ecc_parity_true_f()                      (0x400U)
+#define pwr_falcon_irqmset_r()                                     (0x0010a010U)
+#define pwr_falcon_irqmset_gptmr_f(v)                    ((U32(v) & 0x1U) << 0U)
+#define pwr_falcon_irqmset_wdtmr_f(v)                    ((U32(v) & 0x1U) << 1U)
+#define pwr_falcon_irqmset_mthd_f(v)                     ((U32(v) & 0x1U) << 2U)
+#define pwr_falcon_irqmset_ctxsw_f(v)                    ((U32(v) & 0x1U) << 3U)
+#define pwr_falcon_irqmset_halt_f(v)                     ((U32(v) & 0x1U) << 4U)
+#define pwr_falcon_irqmset_exterr_f(v)                   ((U32(v) & 0x1U) << 5U)
+#define pwr_falcon_irqmset_swgen0_f(v)                   ((U32(v) & 0x1U) << 6U)
+#define pwr_falcon_irqmset_swgen1_f(v)                   ((U32(v) & 0x1U) << 7U)
+#define pwr_falcon_irqmset_ext_ecc_parity_f(v)          ((U32(v) & 0x1U) << 10U)
+#define pwr_falcon_irqmask_r()                                     (0x0010a018U)
+#define pwr_falcon_irqdest_r()                                     (0x0010a01cU)
+#define pwr_falcon_irqdest_host_gptmr_f(v)               ((U32(v) & 0x1U) << 0U)
+#define pwr_falcon_irqdest_host_wdtmr_f(v)               ((U32(v) & 0x1U) << 1U)
+#define pwr_falcon_irqdest_host_mthd_f(v)                ((U32(v) & 0x1U) << 2U)
+#define pwr_falcon_irqdest_host_ctxsw_f(v)               ((U32(v) & 0x1U) << 3U)
+#define pwr_falcon_irqdest_host_halt_f(v)                ((U32(v) & 0x1U) << 4U)
+#define pwr_falcon_irqdest_host_exterr_f(v)              ((U32(v) & 0x1U) << 5U)
+#define pwr_falcon_irqdest_host_swgen0_f(v)              ((U32(v) & 0x1U) << 6U)
+#define pwr_falcon_irqdest_host_swgen1_f(v)              ((U32(v) & 0x1U) << 7U)
+#define pwr_falcon_irqdest_host_ext_f(v)                ((U32(v) & 0xffU) << 8U)
+#define pwr_falcon_irqdest_host_ext_ecc_parity_f(v)     ((U32(v) & 0x1U) << 10U)
+#define pwr_falcon_irqdest_target_gptmr_f(v)            ((U32(v) & 0x1U) << 16U)
+#define pwr_falcon_irqdest_target_wdtmr_f(v)            ((U32(v) & 0x1U) << 17U)
+#define pwr_falcon_irqdest_target_mthd_f(v)             ((U32(v) & 0x1U) << 18U)
+#define pwr_falcon_irqdest_target_ctxsw_f(v)            ((U32(v) & 0x1U) << 19U)
+#define pwr_falcon_irqdest_target_halt_f(v)             ((U32(v) & 0x1U) << 20U)
+#define pwr_falcon_irqdest_target_exterr_f(v)           ((U32(v) & 0x1U) << 21U)
+#define pwr_falcon_irqdest_target_swgen0_f(v)           ((U32(v) & 0x1U) << 22U)
+#define pwr_falcon_irqdest_target_swgen1_f(v)           ((U32(v) & 0x1U) << 23U)
+#define pwr_falcon_irqdest_target_ext_f(v)             ((U32(v) & 0xffU) << 24U)
+#define pwr_falcon_irqdest_target_ext_ecc_parity_f(v)   ((U32(v) & 0x1U) << 26U)
+#define pwr_falcon_mailbox1_r()                                    (0x0010a044U)
+#define pwr_falcon_itfen_r()                                       (0x0010a048U)
+#define pwr_falcon_itfen_ctxen_enable_f()                                 (0x1U)
+#define pwr_falcon_os_r()                                          (0x0010a080U)
+#define pwr_falcon_cpuctl_r()                                      (0x0010a100U)
+#define pwr_falcon_cpuctl_startcpu_f(v)                  ((U32(v) & 0x1U) << 1U)
+#define pwr_falcon_cpuctl_alias_r()                                (0x0010a130U)
+#define pwr_pmu_scpctl_stat_r()                                    (0x0010ac08U)
+#define pwr_pmu_scpctl_stat_debug_mode_m()                    (U32(0x1U) << 20U)
+#define pwr_pmu_scpctl_stat_debug_mode_v(r)                (((r) >> 20U) & 0x1U)
+#define pwr_falcon_dmatrfbase_r()                                  (0x0010a110U)
+#define pwr_falcon_dmatrfbase1_r()                                 (0x0010a128U)
+#define pwr_falcon_dmatrfmoffs_r()                                 (0x0010a114U)
+#define pwr_falcon_dmatrfcmd_r()                                   (0x0010a118U)
+#define pwr_falcon_dmatrfcmd_imem_f(v)                   ((U32(v) & 0x1U) << 4U)
+#define pwr_falcon_dmatrfcmd_write_f(v)                  ((U32(v) & 0x1U) << 5U)
+#define pwr_falcon_dmatrfcmd_size_f(v)                   ((U32(v) & 0x7U) << 8U)
+#define pwr_falcon_dmatrfcmd_ctxdma_f(v)                ((U32(v) & 0x7U) << 12U)
+#define pwr_falcon_dmatrffboffs_r()                                (0x0010a11cU)
+#define pwr_falcon_exterraddr_r()                                  (0x0010a168U)
+#define pwr_falcon_exterrstat_r()                                  (0x0010a16cU)
+#define pwr_falcon_exterrstat_valid_m()                       (U32(0x1U) << 31U)
+#define pwr_falcon_exterrstat_valid_v(r)                   (((r) >> 31U) & 0x1U)
+#define pwr_falcon_exterrstat_valid_true_v()                       (0x00000001U)
+#define pwr_falcon_dmemc_r(i)\
+		(nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U)))
+#define pwr_falcon_dmemc_offs_f(v)                      ((U32(v) & 0x3fU) << 2U)
+#define pwr_falcon_dmemc_blk_f(v)                     ((U32(v) & 0xffffU) << 8U)
+#define pwr_falcon_dmemc_aincw_f(v)                     ((U32(v) & 0x1U) << 24U)
+#define pwr_falcon_dmemd_r(i)\
+		(nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U)))
+#define pwr_pmu_new_instblk_r()                                    (0x0010a480U)
+#define pwr_pmu_new_instblk_ptr_f(v)               ((U32(v) & 0xfffffffU) << 0U)
+#define pwr_pmu_new_instblk_target_fb_f()                                 (0x0U)
+#define pwr_pmu_new_instblk_target_sys_coh_f()                     (0x20000000U)
+#define pwr_pmu_new_instblk_target_sys_ncoh_f()                    (0x30000000U)
+#define pwr_pmu_new_instblk_valid_f(v)                  ((U32(v) & 0x1U) << 30U)
+#define pwr_pmu_mutex_id_r()                                       (0x0010a488U)
+#define pwr_pmu_mutex_id_value_v(r)                        (((r) >> 0U) & 0xffU)
+#define pwr_pmu_mutex_id_value_init_v()                            (0x00000000U)
+#define pwr_pmu_mutex_id_value_not_avail_v()                       (0x000000ffU)
+#define pwr_pmu_mutex_id_release_r()                               (0x0010a48cU)
+#define pwr_pmu_mutex_id_release_value_f(v)             ((U32(v) & 0xffU) << 0U)
+#define pwr_pmu_mutex_id_release_value_m()                    (U32(0xffU) << 0U)
+#define pwr_pmu_mutex_r(i)\
+		(nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_mutex__size_1_v()                                  (0x00000010U)
+#define pwr_pmu_mutex_value_f(v)                        ((U32(v) & 0xffU) << 0U)
+#define pwr_pmu_mutex_value_v(r)                           (((r) >> 0U) & 0xffU)
+#define pwr_pmu_mutex_value_initial_lock_f()                              (0x0U)
+#define pwr_pmu_queue_head_r(i)\
+		(nvgpu_safe_add_u32(0x0010a800U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_queue_head__size_1_v()                             (0x00000008U)
+#define pwr_pmu_queue_head_address_f(v)           ((U32(v) & 0xffffffffU) << 0U)
+#define pwr_pmu_queue_head_address_v(r)              (((r) >> 0U) & 0xffffffffU)
+#define pwr_pmu_queue_tail_r(i)\
+		(nvgpu_safe_add_u32(0x0010a820U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_queue_tail__size_1_v()                             (0x00000008U)
+#define pwr_pmu_queue_tail_address_f(v)           ((U32(v) & 0xffffffffU) << 0U)
+#define pwr_pmu_queue_tail_address_v(r)              (((r) >> 0U) & 0xffffffffU)
+#define pwr_pmu_msgq_head_r()                                      (0x0010a4c8U)
+#define pwr_pmu_msgq_head_val_f(v)                ((U32(v) & 0xffffffffU) << 0U)
+#define pwr_pmu_msgq_head_val_v(r)                   (((r) >> 0U) & 0xffffffffU)
+#define pwr_pmu_msgq_tail_r()                                      (0x0010a4ccU)
+#define pwr_pmu_msgq_tail_val_f(v)                ((U32(v) & 0xffffffffU) << 0U)
+#define pwr_pmu_msgq_tail_val_v(r)                   (((r) >> 0U) & 0xffffffffU)
+#define pwr_pmu_idle_mask_r(i)\
+		(nvgpu_safe_add_u32(0x0010be40U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_idle_mask_gr_enabled_f()                                  (0x1U)
+#define pwr_pmu_idle_mask_ce_2_enabled_f()                           (0x200000U)
+#define pwr_pmu_idle_count_r(i)\
+		(nvgpu_safe_add_u32(0x0010bf80U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_idle_count_value_v(r)                (((r) >> 0U) & 0x7fffffffU)
+#define pwr_pmu_idle_count_reset_f(v)                   ((U32(v) & 0x1U) << 31U)
+#define pwr_pmu_idle_ctrl_r(i)\
+		(nvgpu_safe_add_u32(0x0010bfc0U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_idle_ctrl_value_m()                            (U32(0x3U) << 0U)
+#define pwr_pmu_idle_ctrl_value_busy_f()                                  (0x2U)
+#define pwr_pmu_idle_ctrl_value_always_f()                                (0x3U)
+#define pwr_pmu_idle_ctrl_filter_m()                           (U32(0x1U) << 2U)
+#define pwr_pmu_idle_ctrl_filter_disabled_f()                             (0x0U)
+#define pwr_pmu_idle_mask_supp_r(i)\
+		(nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32((i), 8U)))
+#define pwr_pmu_idle_threshold_r(i)\
+		(nvgpu_safe_add_u32(0x0010be00U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_idle_threshold_value_f(v)         ((U32(v) & 0x7fffffffU) << 0U)
+#define pwr_pmu_idle_intr_r()                                      (0x0010a9e8U)
+#define pwr_pmu_idle_intr_en_f(v)                        ((U32(v) & 0x1U) << 0U)
+#define pwr_pmu_idle_intr_status_r()                               (0x0010a9ecU)
+#define pwr_pmu_idle_intr_status_intr_f(v)               ((U32(v) & 0x1U) << 0U)
+#define pwr_pmu_idle_intr_status_intr_v(r)                  (((r) >> 0U) & 0x1U)
+#define pwr_pmu_idle_mask_1_supp_r(i)\
+		(nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32((i), 8U)))
+#define pwr_pmu_idle_ctrl_supp_r(i)\
+		(nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32((i), 8U)))
+#define pwr_pmu_debug_r(i)\
+		(nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_debug__size_1_v()                                  (0x00000004U)
+#define pwr_pmu_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_mailbox__size_1_v()                                (0x0000000cU)
+#define pwr_pmu_bar0_addr_r()                                      (0x0010a7a0U)
+#define pwr_pmu_bar0_data_r()                                      (0x0010a7a4U)
+#define pwr_pmu_bar0_ctl_r()                                       (0x0010a7acU)
+#define pwr_pmu_bar0_timeout_r()                                   (0x0010a7a8U)
+#define pwr_pmu_bar0_fecs_error_r()                                (0x0010a988U)
+#define pwr_pmu_bar0_host_error_r()                                (0x0010a990U)
+#define pwr_pmu_bar0_error_status_r()                              (0x0010a7b0U)
+#define pwr_pmu_bar0_error_status_timeout_host_m()             (U32(0x1U) << 0U)
+#define pwr_pmu_bar0_error_status_timeout_fecs_m()             (U32(0x1U) << 1U)
+#define pwr_pmu_bar0_error_status_cmd_hwerr_m()                (U32(0x1U) << 2U)
+#define pwr_pmu_bar0_error_status_err_cmd_m()                  (U32(0x1U) << 3U)
+#define pwr_pmu_bar0_error_status_hosterr_m()                 (U32(0x1U) << 30U)
+#define pwr_pmu_bar0_error_status_fecserr_m()                 (U32(0x1U) << 31U)
+#define pwr_pmu_pg_idlefilth_r(i)\
+		(nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_pg_ppuidlefilth_r(i)\
+		(nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_pg_idle_cnt_r(i)\
+		(nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_pg_intren_r(i)\
+		(nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_fbif_transcfg_r(i)\
+		(nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_fbif_transcfg_target_local_fb_f()                             (0x0U)
+#define pwr_fbif_transcfg_target_coherent_sysmem_f()                      (0x1U)
+#define pwr_fbif_transcfg_target_noncoherent_sysmem_f()                   (0x2U)
+#define pwr_fbif_transcfg_mem_type_v(r)                     (((r) >> 2U) & 0x1U)
+#define pwr_fbif_transcfg_mem_type_virtual_f()                            (0x0U)
+#define pwr_fbif_transcfg_mem_type_physical_f()                           (0x4U)
+#define pwr_falcon_engine_r()                                      (0x0010a3c0U)
+#define pwr_falcon_engine_reset_true_f()                                  (0x1U)
+#define pwr_falcon_engine_reset_false_f()                                 (0x0U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ram_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ram_ga100.h
new file mode 100644
index 000000000..62f2cde5c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_ram_ga100.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_RAM_GA100_H
+#define NVGPU_HW_RAM_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define ram_in_ramfc_s()                                                 (4096U)
+#define ram_in_ramfc_w()                                                    (0U)
+#define ram_in_page_dir_base_target_vid_mem_f()                           (0x0U)
+#define ram_in_page_dir_base_target_sys_mem_coh_f()                       (0x2U)
+#define ram_in_page_dir_base_target_sys_mem_ncoh_f()                      (0x3U)
+#define ram_in_page_dir_base_vol_true_f()                                 (0x4U)
+#define ram_in_use_ver2_pt_format_true_f()                              (0x400U)
+#define ram_in_big_page_size_m()                              (U32(0x1U) << 11U)
+#define ram_in_big_page_size_w()                                          (128U)
+#define ram_in_big_page_size_128kb_f()                                    (0x0U)
+#define ram_in_big_page_size_64kb_f()                                   (0x800U)
+#define ram_in_page_dir_base_lo_f(v)                ((U32(v) & 0xfffffU) << 12U)
+#define ram_in_page_dir_base_lo_w()                                       (128U)
+#define ram_in_page_dir_base_hi_f(v)              ((U32(v) & 0xffffffffU) << 0U)
+#define ram_in_page_dir_base_hi_w()                                       (129U)
+#define ram_in_engine_cs_w()                                              (132U)
+#define ram_in_engine_cs_wfi_v()                                   (0x00000000U)
+#define ram_in_engine_wfi_mode_f(v)                      ((U32(v) & 0x1U) << 2U)
+#define ram_in_engine_wfi_mode_virtual_v()                         (0x00000001U)
+#define ram_in_engine_wfi_target_w()                                      (132U)
+#define ram_in_engine_wfi_ptr_lo_f(v)               ((U32(v) & 0xfffffU) << 12U)
+#define ram_in_engine_wfi_ptr_hi_f(v)                   ((U32(v) & 0xffU) << 0U)
+#define ram_in_engine_wfi_ptr_hi_w()                                      (133U)
+#define ram_in_engine_wfi_veid_f(v)                     ((U32(v) & 0x3fU) << 0U)
+#define ram_in_engine_wfi_veid_w()                                        (134U)
+#define ram_in_eng_method_buffer_addr_lo_w()                              (136U)
+#define ram_in_eng_method_buffer_addr_hi_w()                              (137U)
+#define ram_in_sc_pdb_valid_long_w(i)\
+		(166ULL + (((i)*1ULL)/32ULL))
+#define ram_in_sc_pdb_valid__size_1_v()                            (0x00000040U)
+#define ram_in_sc_page_dir_base_target_f(v, i)\
+		((U32(v) & 0x3U) << (0U + (i)*0U))
+#define ram_in_sc_page_dir_base_target__size_1_v()                 (0x00000040U)
+#define ram_in_sc_page_dir_base_target_vid_mem_v()                 (0x00000000U)
+#define ram_in_sc_page_dir_base_target_sys_mem_coh_v()             (0x00000002U)
+#define ram_in_sc_page_dir_base_target_sys_mem_ncoh_v()            (0x00000003U)
+#define ram_in_sc_page_dir_base_vol_f(v, i)\
+		((U32(v) & 0x1U) << (2U + (i)*0U))
+#define ram_in_sc_page_dir_base_vol_w(i)\
+		(168U + (((i)*128U)/32U))
+#define ram_in_sc_page_dir_base_vol_true_v()                       (0x00000001U)
+#define ram_in_sc_page_dir_base_fault_replay_tex_f(v, i)\
+		((U32(v) & 0x1U) << (4U + (i)*0U))
+#define ram_in_sc_page_dir_base_fault_replay_gcc_f(v, i)\
+		((U32(v) & 0x1U) << (5U + (i)*0U))
+#define ram_in_sc_use_ver2_pt_format_f(v, i)\
+		((U32(v) & 0x1U) << (10U + (i)*0U))
+#define ram_in_sc_big_page_size_f(v, i)\
+		((U32(v) & 0x1U) << (11U + (i)*0U))
+#define ram_in_sc_page_dir_base_hi_w(i)\
+		(169U + (((i)*128U)/32U))
+#define ram_in_sc_page_dir_base_lo_0_f(v)           ((U32(v) & 0xfffffU) << 12U)
+#define ram_in_base_shift_v()                                      (0x0000000cU)
+#define ram_in_alloc_size_v()                                      (0x00001000U)
+#define ram_fc_size_val_v()                                        (0x00000200U)
+#define ram_fc_signature_w()                                                (4U)
+#define ram_fc_pb_get_w()                                                   (6U)
+#define ram_fc_pb_get_hi_w()                                                (7U)
+#define ram_fc_pb_top_level_get_w()                                         (8U)
+#define ram_fc_pb_top_level_get_hi_w()                                      (9U)
+#define ram_fc_acquire_w()                                                 (12U)
+#define ram_fc_sem_addr_hi_w()                                             (14U)
+#define ram_fc_sem_addr_lo_w()                                             (15U)
+#define ram_fc_sem_payload_lo_w()                                          (16U)
+#define ram_fc_sem_payload_hi_w()                                          (39U)
+#define ram_fc_sem_execute_w()                                             (17U)
+#define ram_fc_gp_base_w()                                                 (18U)
+#define ram_fc_gp_base_hi_w()                                              (19U)
+#define ram_fc_pb_put_w()                                                  (23U)
+#define ram_fc_pb_put_hi_w()                                               (24U)
+#define ram_fc_pb_header_w()                                               (33U)
+#define ram_fc_pb_count_w()                                                (34U)
+#define ram_fc_subdevice_w()                                               (37U)
+#define ram_fc_target_w()                                                  (43U)
+#define ram_fc_hce_ctrl_w()                                                (57U)
+#define ram_fc_config_w()                                                  (61U)
+#define ram_fc_set_channel_info_w()                                        (63U)
+#define ram_fc_intr_notify_w()                                             (62U)
+#define ram_userd_base_shift_v()                                   (0x00000009U)
+#define ram_userd_chan_size_v()                                    (0x00000200U)
+#define ram_userd_put_w()                                                  (16U)
+#define ram_userd_get_w()                                                  (17U)
+#define ram_userd_ref_w()                                                  (18U)
+#define ram_userd_put_hi_w()                                               (19U)
+#define ram_userd_top_level_get_w()                                        (22U)
+#define ram_userd_top_level_get_hi_w()                                     (23U)
+#define ram_userd_get_hi_w()                                               (24U)
+#define ram_userd_gp_get_w()                                               (34U)
+#define ram_userd_gp_put_w()                                               (35U)
+#define ram_rl_entry_size_v()                                      (0x00000010U)
+#define ram_rl_entry_type_channel_v()                              (0x00000000U)
+#define ram_rl_entry_type_tsg_v()                                  (0x00000001U)
+#define ram_rl_entry_id_f(v)                           ((U32(v) & 0xfffU) << 0U)
+#define ram_rl_entry_chan_runqueue_selector_f(v)         ((U32(v) & 0x1U) << 1U)
+#define ram_rl_entry_chan_inst_target_f(v)               ((U32(v) & 0x3U) << 4U)
+#define ram_rl_entry_chan_inst_target_sys_mem_ncoh_v()             (0x00000003U)
+#define ram_rl_entry_chan_inst_target_sys_mem_coh_v()              (0x00000002U)
+#define ram_rl_entry_chan_inst_target_vid_mem_v()                  (0x00000000U)
+#define ram_rl_entry_chan_userd_target_f(v)              ((U32(v) & 0x3U) << 6U)
+#define ram_rl_entry_chan_userd_target_vid_mem_v()                 (0x00000000U)
+#define ram_rl_entry_chan_userd_target_sys_mem_coh_v()             (0x00000002U)
+#define ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()            (0x00000003U)
+#define ram_rl_entry_chan_userd_ptr_lo_f(v)         ((U32(v) & 0xffffffU) << 8U)
+#define ram_rl_entry_chan_userd_ptr_hi_f(v)       ((U32(v) & 0xffffffffU) << 0U)
+#define ram_rl_entry_chid_f(v)                         ((U32(v) & 0xfffU) << 0U)
+#define ram_rl_entry_chan_inst_ptr_lo_f(v)          ((U32(v) & 0xfffffU) << 12U)
+#define ram_rl_entry_chan_inst_ptr_hi_f(v)        ((U32(v) & 0xffffffffU) << 0U)
+#define ram_rl_entry_tsg_timeslice_scale_f(v)           ((U32(v) & 0xfU) << 16U)
+#define ram_rl_entry_tsg_timeslice_timeout_f(v)        ((U32(v) & 0xffU) << 24U)
+#define ram_rl_entry_tsg_length_f(v)                    ((U32(v) & 0xffU) << 0U)
+#define ram_rl_entry_tsg_tsgid_f(v)                    ((U32(v) & 0xfffU) << 0U)
+#define ram_rl_entry_chan_userd_ptr_align_shift_v()                (0x00000008U)
+#define ram_rl_entry_chan_inst_ptr_align_shift_v()                 (0x0000000cU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_runlist_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_runlist_ga100.h
new file mode 100644
index 000000000..95e8793f6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_runlist_ga100.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_RUNLIST_GA100_H
+#define NVGPU_HW_RUNLIST_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define runlist_channel_config_r()                                 (0x00000004U)
+#define runlist_channel_config_num_channels_log2_2k_v()            (0x0000000bU)
+#define runlist_channel_config_chram_bar0_offset_v(r) (((r) >> 4U) & 0xfffffffU)
+#define runlist_channel_config_chram_bar0_offset_b()                        (4U)
+#define runlist_doorbell_config_r()                                (0x00000008U)
+#define runlist_doorbell_config_id_v(r)                 (((r) >> 16U) & 0xffffU)
+#define runlist_fb_config_r()                                      (0x0000000cU)
+#define runlist_fb_config_fb_thread_id_v(r)                (((r) >> 0U) & 0xffU)
+#define runlist_pbdma_config_r(i)\
+		(nvgpu_safe_add_u32(0x00000010U, nvgpu_safe_mult_u32((i), 4U)))
+#define runlist_pbdma_config__size_1_v()                           (0x00000002U)
+#define runlist_pbdma_config_id_v(r)                       (((r) >> 0U) & 0xffU)
+#define runlist_pbdma_config_pbdma_bar0_offset_v(r)     (((r) >> 10U) & 0xffffU)
+#define runlist_pbdma_config_valid_v(r)                    (((r) >> 31U) & 0x1U)
+#define runlist_pbdma_config_valid_true_v()                        (0x00000001U)
+#define runlist_userd_writeback_r()                                (0x00000028U)
+#define runlist_userd_writeback_timer_100us_f()                          (0x64U)
+#define runlist_userd_writeback_timescale_0_f()                           (0x0U)
+#define runlist_engine_status0_r(i)\
+		(nvgpu_safe_add_u32(0x00000200U, nvgpu_safe_mult_u32((i), 64U)))
+#define runlist_engine_status0_tsgid_v(r)                 (((r) >> 0U) & 0xfffU)
+#define runlist_engine_status0_ctx_status_v(r)             (((r) >> 13U) & 0x7U)
+#define runlist_engine_status0_ctx_status_valid_v()                (0x00000001U)
+#define runlist_engine_status0_ctx_status_save_v()                 (0x00000005U)
+#define runlist_engine_status0_ctx_status_load_v()                 (0x00000006U)
+#define runlist_engine_status0_ctx_status_switch_v()               (0x00000007U)
+#define runlist_engine_status0_ctxsw_in_progress_f()                   (0x8000U)
+#define runlist_engine_status0_next_tsgid_v(r)           (((r) >> 16U) & 0xfffU)
+#define runlist_engine_status0_faulted_v(r)                (((r) >> 30U) & 0x1U)
+#define runlist_engine_status0_faulted_true_v()                    (0x00000001U)
+#define runlist_engine_status0_engine_v(r)                 (((r) >> 31U) & 0x1U)
+#define runlist_engine_status0_engine_busy_v()                     (0x00000001U)
+#define runlist_engine_status1_r(i)\
+		(nvgpu_safe_add_u32(0x00000204U, nvgpu_safe_mult_u32((i), 64U)))
+#define runlist_engine_status1_intr_id_v(r)               (((r) >> 16U) & 0x1fU)
+#define runlist_engine_status_debug_r(i)\
+		(nvgpu_safe_add_u32(0x00000228U, nvgpu_safe_mult_u32((i), 64U)))
+#define runlist_engine_status_debug_engine_id_v(r)        (((r) >> 24U) & 0x3fU)
+#define runlist_chram_channel_r(i)\
+		(nvgpu_safe_add_u32(0x00000000U, nvgpu_safe_mult_u32((i), 4U)))
+#define runlist_chram_channel_enable_v(r)                   (((r) >> 1U) & 0x1U)
+#define runlist_chram_channel_enable_in_use_v()                    (0x00000001U)
+#define runlist_chram_channel_next_v(r)                     (((r) >> 2U) & 0x1U)
+#define runlist_chram_channel_next_true_v()                        (0x00000001U)
+#define runlist_chram_channel_busy_v(r)                     (((r) >> 3U) & 0x1U)
+#define runlist_chram_channel_busy_true_v()                        (0x00000001U)
+#define runlist_chram_channel_eng_faulted_v(r)              (((r) >> 5U) & 0x1U)
+#define runlist_chram_channel_eng_faulted_true_v()                 (0x00000001U)
+#define runlist_chram_channel_ctx_reload_v(r)               (((r) >> 9U) & 0x1U)
+#define runlist_chram_channel_ctx_reload_true_v()                  (0x00000001U)
+#define runlist_chram_channel_status_v(r)                  (((r) >> 8U) & 0x1fU)
+#define runlist_chram_channel_status_idle_v()                      (0x00000000U)
+#define runlist_chram_channel_status_pending_v()                   (0x00000001U)
+#define runlist_chram_channel_status_pending_ctx_reload_v()        (0x00000003U)
+#define runlist_chram_channel_status_pending_acquire_fail_v()      (0x00000011U)
+#define runlist_chram_channel_status_pending_acquire_fail_ctx_reload_v()\
+				(0x00000013U)
+#define runlist_chram_channel_status_pbdma_busy_v()                (0x00000004U)
+#define runlist_chram_channel_status_pbdma_busy_and_eng_busy_v()   (0x0000000cU)
+#define runlist_chram_channel_status_eng_busy_v()                  (0x00000008U)
+#define runlist_chram_channel_status_eng_busy_pending_acquire_fail_v()\
+				(0x00000019U)
+#define runlist_chram_channel_status_eng_busy_pending_v()          (0x00000009U)
+#define runlist_chram_channel_status_pbdma_busy_ctx_reload_v()     (0x00000006U)
+#define runlist_chram_channel_status_pbdma_busy_eng_busy_ctx_reload_v()\
+				(0x0000000eU)
+#define runlist_chram_channel_status_busy_ctx_reload_v()           (0x0000000aU)
+#define runlist_chram_channel_status_eng_busy_pending_ctx_reload_v()\
+				(0x0000000bU)
+#define runlist_chram_channel_status_eng_busy_pending_acquire_fail_ctx_reload_v()\
+				(0x0000001bU)
+#define runlist_chram_channel_update_f(v)         ((U32(v) & 0xffffffffU) << 0U)
+#define runlist_chram_channel_update_enable_channel_v()            (0x00000002U)
+#define runlist_chram_channel_update_disable_channel_v()           (0x00000003U)
+#define runlist_chram_channel_update_force_ctx_reload_v()          (0x00000200U)
+#define runlist_chram_channel_update_reset_pbdma_faulted_v()       (0x00000011U)
+#define runlist_chram_channel_update_reset_eng_faulted_v()         (0x00000021U)
+#define runlist_chram_channel_update_clear_channel_v()             (0xffffffffU)
+#define runlist_submit_base_lo_r()                                 (0x00000080U)
+#define runlist_submit_base_lo_ptr_align_shift_v()                 (0x0000000cU)
+#define runlist_submit_base_lo_ptr_lo_f(v)          ((U32(v) & 0xfffffU) << 12U)
+#define runlist_submit_base_lo_target_vid_mem_f()                         (0x0U)
+#define runlist_submit_base_lo_target_sys_mem_coherent_f()                (0x2U)
+#define runlist_submit_base_lo_target_sys_mem_noncoherent_f()             (0x3U)
+#define runlist_submit_base_hi_r()                                 (0x00000084U)
+#define runlist_submit_base_hi_ptr_hi_f(v)              ((U32(v) & 0xffU) << 0U)
+#define runlist_submit_r()                                         (0x00000088U)
+#define runlist_submit_length_f(v)                    ((U32(v) & 0xffffU) << 0U)
+#define runlist_submit_length_max_v()                              (0x0000ffffU)
+#define runlist_submit_offset_f(v)                   ((U32(v) & 0xffffU) << 16U)
+#define runlist_submit_info_r()                                    (0x0000008cU)
+#define runlist_submit_info_pending_true_f()                           (0x8000U)
+#define runlist_sched_disable_r()                                  (0x00000094U)
+#define runlist_sched_disable_runlist_enabled_v()                  (0x00000000U)
+#define runlist_sched_disable_runlist_disabled_v()                 (0x00000001U)
+#define runlist_preempt_r()                                        (0x00000098U)
+#define runlist_preempt_id_f(v)                        ((U32(v) & 0xfffU) << 0U)
+#define runlist_preempt_tsg_preempt_pending_true_f()                 (0x100000U)
+#define runlist_preempt_runlist_preempt_pending_true_f()             (0x200000U)
+#define runlist_preempt_type_runlist_f()                                  (0x0U)
+#define runlist_preempt_type_tsg_f()                                (0x1000000U)
+#define runlist_virtual_channel_cfg_r(i)\
+		(nvgpu_safe_add_u32(0x00000300U, nvgpu_safe_mult_u32((i), 4U)))
+#define runlist_virtual_channel_cfg_mask_hw_mask_hw_init_f()            (0x7ffU)
+#define runlist_virtual_channel_cfg_pending_enable_true_f()        (0x80000000U)
+#define runlist_intr_vectorid_r(i)\
+		(nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32((i), 4U)))
+#define runlist_intr_vectorid__size_1_v()                          (0x00000002U)
+#define runlist_intr_vectorid_vector_v(r)                 (((r) >> 0U) & 0xfffU)
+#define runlist_intr_vectorid_gsp_enable_f()                       (0x40000000U)
+#define runlist_intr_vectorid_cpu_enable_f()                       (0x80000000U)
+#define runlist_intr_retrigger_r(i)\
+		(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U)))
+#define runlist_intr_retrigger_trigger_true_f()                           (0x1U)
+#define runlist_intr_0_r()                                         (0x00000100U)
+#define runlist_intr_0_ctxsw_timeout_eng_pending_f(i)\
+		((U32(0x1U) << (0U + ((i)*1U))))
+#define runlist_intr_0_ctxsw_timeout_eng_reset_f(i)\
+		((U32(0x1U) << (0U + ((i)*1U))))
+#define runlist_intr_0_bad_tsg_pending_f()                             (0x1000U)
+#define runlist_intr_0_pbdmai_intr_tree_j_pending_f(i, j)\
+		((U32(0x1U) << (16U + ((i)*1U) + ((j)*2U))))
+#define runlist_intr_0_pbdmai_intr_tree_j__size_1_v()              (0x00000002U)
+#define runlist_intr_bad_tsg_r()                                   (0x00000174U)
+#define runlist_intr_bad_tsg_code_v(r)                      (((r) >> 0U) & 0xfU)
+#define runlist_intr_0_en_set_tree_r(i)\
+		(nvgpu_safe_add_u32(0x00000120U, nvgpu_safe_mult_u32((i), 8U)))
+#define runlist_intr_0_en_set_tree_ctxsw_timeout_eng0_enabled_f()         (0x1U)
+#define runlist_intr_0_en_set_tree_ctxsw_timeout_eng1_enabled_f()         (0x2U)
+#define runlist_intr_0_en_set_tree_ctxsw_timeout_eng2_enabled_f()         (0x4U)
+#define runlist_intr_0_en_set_tree_bad_tsg_enabled_f()                 (0x1000U)
+#define runlist_intr_0_en_set_tree_pbdma0_intr_tree_0_enabled_f()     (0x10000U)
+#define runlist_intr_0_en_set_tree_pbdma1_intr_tree_0_enabled_f()     (0x20000U)
+#define runlist_intr_0_en_clear_tree_r(i)\
+		(nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32((i), 8U)))
+#define runlist_intr_0_en_clear_tree_ctxsw_timeout_eng0_enabled_f()       (0x1U)
+#define runlist_intr_0_en_clear_tree_ctxsw_timeout_eng1_enabled_f()       (0x2U)
+#define runlist_intr_0_en_clear_tree_ctxsw_timeout_eng2_enabled_f()       (0x4U)
+#define runlist_engine_ctxsw_timeout_info_r(i)\
+		(nvgpu_safe_add_u32(0x00000224U, nvgpu_safe_mult_u32((i), 64U)))
+#define runlist_engine_ctxsw_timeout_info__size_1_v()              (0x00000003U)
+#define runlist_engine_ctxsw_timeout_info_prev_tsgid_v(r)\
+				(((r) >> 0U) & 0x3fffU)
+#define runlist_engine_ctxsw_timeout_info_ctxsw_state_v(r) (((r) >> 14U) & 0x3U)
+#define runlist_engine_ctxsw_timeout_info_ctxsw_state_load_v()     (0x00000001U)
+#define runlist_engine_ctxsw_timeout_info_ctxsw_state_save_v()     (0x00000002U)
+#define runlist_engine_ctxsw_timeout_info_ctxsw_state_switch_v()   (0x00000003U)
+#define runlist_engine_ctxsw_timeout_info_next_tsgid_v(r)\
+				(((r) >> 16U) & 0x3fffU)
+#define runlist_engine_ctxsw_timeout_info_status_v(r)      (((r) >> 30U) & 0x3U)
+#define runlist_engine_ctxsw_timeout_info_status_ack_received_v()  (0x00000002U)
+#define runlist_engine_ctxsw_timeout_info_status_dropped_timeout_v()\
+				(0x00000003U)
+#define runlist_engine_ctxsw_timeout_config_r(i)\
+		(nvgpu_safe_add_u32(0x00000220U, nvgpu_safe_mult_u32((i), 64U)))
+#define runlist_engine_ctxsw_timeout_config__size_1_v()            (0x00000003U)
+#define runlist_engine_ctxsw_timeout_config_period_f(v)\
+				((U32(v) & 0x7fffffffU) << 0U)
+#define runlist_engine_ctxsw_timeout_config_period_v(r)\
+				(((r) >> 0U) & 0x7fffffffU)
+#define runlist_engine_ctxsw_timeout_config_period_max_f()         (0x7fffffffU)
+#define runlist_engine_ctxsw_timeout_config_period_f(v)\
+				((U32(v) & 0x7fffffffU) << 0U)
+#define runlist_engine_ctxsw_timeout_config_period_max_f()         (0x7fffffffU)
+#define runlist_engine_ctxsw_timeout_config_detection_disabled_f()        (0x0U)
+#define runlist_engine_ctxsw_timeout_config_detection_enabled_f()  (0x80000000U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_smcarb_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_smcarb_ga100.h
new file mode 100644
index 000000000..4b3c6dce1
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_smcarb_ga100.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_SMCARB_GA100_H
+#define NVGPU_HW_SMCARB_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define smcarb_smc_partition_gpc_map_r(i)\
+		(nvgpu_safe_add_u32(0x0000cc00U, nvgpu_safe_mult_u32((i), 4U)))
+#define smcarb_smc_partition_gpc_map_sys_pipe_local_gpc_id_f(v)\
+				((U32(v) & 0x1fU) << 0U)
+#define smcarb_smc_partition_gpc_map_sys_pipe_local_gpc_id_m()\
+				(U32(0x1fU) << 0U)
+#define smcarb_smc_partition_gpc_map_sys_pipe_id_f(v)   ((U32(v) & 0x1fU) << 8U)
+#define smcarb_smc_partition_gpc_map_sys_pipe_id_m()          (U32(0x1fU) << 8U)
+#define smcarb_smc_partition_gpc_map_physical_gpc_id_v(r) (((r) >> 16U) & 0x1fU)
+#define smcarb_smc_partition_gpc_map_ugpu_id_v(r)          (((r) >> 24U) & 0x1U)
+#define smcarb_smc_partition_gpc_map_valid_f(v)         ((U32(v) & 0x1U) << 31U)
+#define smcarb_smc_partition_gpc_map_valid_m()                (U32(0x1U) << 31U)
+#define smcarb_smc_partition_gpc_map_valid_true_v()                (0x00000001U)
+#define smcarb_smc_partition_gpc_map_valid_false_v()               (0x00000000U)
+#define smcarb_sys_pipe_info_r()                                   (0x0000cc80U)
+#define smcarb_sys_pipe_info_mode_f(v)                   ((U32(v) & 0x1U) << 0U)
+#define smcarb_sys_pipe_info_mode_m()                          (U32(0x1U) << 0U)
+#define smcarb_sys_pipe_info_mode_v(r)                      (((r) >> 0U) & 0x1U)
+#define smcarb_sys_pipe_info_mode_legacy_v()                       (0x00000000U)
+#define smcarb_sys_pipe_info_mode_smc_v()                          (0x00000001U)
+#define smcarb_ugpu_gpc_count_r()                                  (0x0000cc84U)
+#define smcarb_ugpu_gpc_count_ugpu0_v(r)                   (((r) >> 0U) & 0x1fU)
+#define smcarb_ugpu_gpc_count_ugpu1_v(r)                   (((r) >> 8U) & 0x1fU)
+#define smcarb_timestamp_ctrl_r()                                  (0x0000cc8cU)
+#define smcarb_timestamp_ctrl_disable_tick_m()                 (U32(0x1U) << 0U)
+#define smcarb_timestamp_ctrl_disable_tick__prod_f()                      (0x0U)
+#define smcarb_max_partitionable_sys_pipes_v()                     (0x00000008U)
+#define smcarb_allowed_swizzid__size1_v()                          (0x0000000fU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_therm_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_therm_ga100.h
new file mode 100644
index 000000000..ce0239526
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_therm_ga100.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_THERM_GA100_H
+#define NVGPU_HW_THERM_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define therm_config2_r()                                          (0x00020130U)
+#define therm_config2_slowdown_factor_extended_f(v)     ((U32(v) & 0x1U) << 24U)
+#define therm_config2_grad_enable_f(v)                  ((U32(v) & 0x1U) << 31U)
+#define therm_gate_ctrl_r(i)\
+		(nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U)))
+#define therm_gate_ctrl_eng_clk_m()                            (U32(0x3U) << 0U)
+#define therm_gate_ctrl_eng_clk_run_f()                                   (0x0U)
+#define therm_gate_ctrl_eng_clk_auto_f()                                  (0x1U)
+#define therm_gate_ctrl_eng_clk_stop_f()                                  (0x2U)
+#define therm_gate_ctrl_blk_clk_m()                            (U32(0x3U) << 2U)
+#define therm_gate_ctrl_blk_clk_run_f()                                   (0x0U)
+#define therm_gate_ctrl_blk_clk_auto_f()                                  (0x4U)
+#define therm_gate_ctrl_idle_holdoff_m()                       (U32(0x1U) << 4U)
+#define therm_gate_ctrl_idle_holdoff_on_f()                              (0x10U)
+#define therm_gate_ctrl_eng_idle_filt_exp_f(v)          ((U32(v) & 0x1fU) << 8U)
+#define therm_gate_ctrl_eng_idle_filt_exp_m()                 (U32(0x1fU) << 8U)
+#define therm_gate_ctrl_eng_idle_filt_mant_f(v)         ((U32(v) & 0x7U) << 13U)
+#define therm_gate_ctrl_eng_idle_filt_mant_m()                (U32(0x7U) << 13U)
+#define therm_gate_ctrl_eng_delay_before_f(v)           ((U32(v) & 0xfU) << 16U)
+#define therm_gate_ctrl_eng_delay_before_m()                  (U32(0xfU) << 16U)
+#define therm_gate_ctrl_eng_delay_after_f(v)            ((U32(v) & 0xfU) << 20U)
+#define therm_gate_ctrl_eng_delay_after_m()                   (U32(0xfU) << 20U)
+#define therm_fecs_idle_filter_r()                                 (0x00020288U)
+#define therm_fecs_idle_filter_value_m()                (U32(0xffffffffU) << 0U)
+#define therm_hubmmu_idle_filter_r()                               (0x0002028cU)
+#define therm_hubmmu_idle_filter_value_m()              (U32(0xffffffffU) << 0U)
+#define therm_clk_slowdown_r(i)\
+		(nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U)))
+#define therm_clk_slowdown_idle_factor_m()                   (U32(0x3fU) << 16U)
+#define therm_clk_slowdown_idle_factor_disabled_f()                       (0x0U)
+#define therm_grad_stepping_table_r(i)\
+		(nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U)))
+#define therm_grad_stepping_table_slowdown_factor0_f(v) ((U32(v) & 0x3fU) << 0U)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()        (0x1U)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()          (0x2U)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()          (0x6U)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()          (0xeU)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by31_f()        (0x3cU)
+#define therm_grad_stepping_table_slowdown_factor1_f(v) ((U32(v) & 0x3fU) << 6U)
+#define therm_grad_stepping_table_slowdown_factor2_f(v)\
+				((U32(v) & 0x3fU) << 12U)
+#define therm_grad_stepping_table_slowdown_factor3_f(v)\
+				((U32(v) & 0x3fU) << 18U)
+#define therm_grad_stepping_table_slowdown_factor4_f(v)\
+				((U32(v) & 0x3fU) << 24U)
+#define therm_grad_stepping0_r()                                   (0x000202c0U)
+#define therm_grad_stepping0_feature_enable_f()                           (0x1U)
+#define therm_grad_stepping1_r()                                   (0x000202c4U)
+#define therm_grad_stepping1_pdiv_duration_f(v)      ((U32(v) & 0x1ffffU) << 0U)
+#define therm_clk_timing_r(i)\
+		(nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define therm_clk_timing_grad_slowdown_enabled_f()                    (0x10000U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_timer_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_timer_ga100.h
new file mode 100644
index 000000000..238cbffbc
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_timer_ga100.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_TIMER_GA100_H
+#define NVGPU_HW_TIMER_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define timer_pri_timeout_r()                                      (0x00009080U)
+#define timer_pri_timeout_save_0_r()                               (0x00009084U)
+#define timer_pri_timeout_save_0_fecs_tgt_v(r)             (((r) >> 31U) & 0x1U)
+#define timer_pri_timeout_save_0_addr_v(r)             (((r) >> 2U) & 0x3fffffU)
+#define timer_pri_timeout_save_0_write_v(r)                 (((r) >> 1U) & 0x1U)
+#define timer_pri_timeout_save_1_r()                               (0x00009088U)
+#define timer_pri_timeout_fecs_errcode_r()                         (0x0000908cU)
+#define timer_time_0_r()                                           (0x00009400U)
+#define timer_time_1_r()                                           (0x00009410U)
+#define timer_gr_tick_freq_r()                                     (0x00009480U)
+#define timer_gr_tick_freq_select_f(v)                   ((U32(v) & 0x7U) << 0U)
+#define timer_gr_tick_freq_select_max_f()                                 (0x0U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_top_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_top_ga100.h
new file mode 100644
index 000000000..049c43380
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_top_ga100.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_TOP_GA100_H
+#define NVGPU_HW_TOP_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define top_num_gpcs_r()                                           (0x00022430U)
+#define top_num_gpcs_value_v(r)                            (((r) >> 0U) & 0x1fU)
+#define top_tpc_per_gpc_r()                                        (0x00022434U)
+#define top_tpc_per_gpc_value_v(r)                         (((r) >> 0U) & 0x1fU)
+#define top_num_fbps_r()                                           (0x00022438U)
+#define top_num_fbps_value_v(r)                            (((r) >> 0U) & 0x1fU)
+#define top_num_fbpas_r()                                          (0x0002243cU)
+#define top_num_fbpas_value_v(r)                           (((r) >> 0U) & 0x1fU)
+#define top_ltc_per_fbp_r()                                        (0x00022450U)
+#define top_ltc_per_fbp_value_v(r)                         (((r) >> 0U) & 0x1fU)
+#define top_slices_per_ltc_r()                                     (0x0002245cU)
+#define top_slices_per_ltc_value_v(r)                      (((r) >> 0U) & 0x1fU)
+#define top_num_ltcs_r()                                           (0x00022454U)
+#define top_num_ltcs_value_v(r)                            (((r) >> 0U) & 0x1fU)
+#define top_num_ces_r()                                            (0x00022444U)
+#define top_num_ces_value_v(r)                             (((r) >> 0U) & 0x1fU)
+#define top_device_info_cfg_r()                                    (0x000224fcU)
+#define top_device_info_cfg_version_v(r)                    (((r) >> 0U) & 0xfU)
+#define top_device_info_cfg_version_init_v()                       (0x00000002U)
+#define top_device_info_cfg_num_rows_v(r)                (((r) >> 20U) & 0xfffU)
+#define top_device_info2_r(i)\
+		(nvgpu_safe_add_u32(0x00022800U, nvgpu_safe_mult_u32((i), 4U)))
+#define top_device_info2_row_chain_v(r)                    (((r) >> 31U) & 0x1U)
+#define top_device_info2_row_chain_more_v()                        (0x00000001U)
+#define top_device_info2_row_chain_last_v()                        (0x00000000U)
+#define top_device_info2_dev_fault_id_v(r)                (((r) >> 0U) & 0x7ffU)
+#define top_device_info2_dev_instance_id_v(r)             (((r) >> 16U) & 0xffU)
+#define top_device_info2_dev_type_enum_v(r)               (((r) >> 24U) & 0x7fU)
+#define top_device_info2_dev_reset_id_v(r)                 (((r) >> 0U) & 0xffU)
+#define top_device_info2_dev_device_pri_base_v(r)       (((r) >> 8U) & 0x3ffffU)
+#define top_device_info2_dev_device_pri_base_b()                            (8U)
+#define top_device_info2_dev_is_engine_v(r)                (((r) >> 30U) & 0x1U)
+#define top_device_info2_dev_is_engine_true_v()                    (0x00000001U)
+#define top_device_info2_dev_rleng_id_v(r)                  (((r) >> 0U) & 0x3U)
+#define top_device_info2_dev_runlist_pri_base_v(r)      (((r) >> 10U) & 0xffffU)
+#define top_device_info2_dev_runlist_pri_base_b()                          (10U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_trim_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_trim_ga100.h
new file mode 100644
index 000000000..b989f19e7
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_trim_ga100.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_TRIM_GA100_H
+#define NVGPU_HW_TRIM_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define trim_sys_nvlink_uphy_cfg_r()                               (0x00132410U)
+#define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(v)\
+				((U32(v) & 0x1U) << 12U)
+#define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m()     (U32(0x1U) << 12U)
+#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r()                (0x00132a70U)
+#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_update_cycle_init_f()     (0x0U)
+#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_cont_update_enabled_f()\
+				(0x8000000U)
+#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_start_count_disabled_f()  (0x0U)
+#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_start_count_enabled_f()\
+				(0x2000000U)
+#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_reset_m()     (U32(0x1U) << 24U)
+#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_reset_asserted_f()  (0x1000000U)
+#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_reset_deasserted_f()      (0x0U)
+#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_noeg_f()\
+				(0x20000000U)
+#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r()               (0x00132a74U)
+#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r()               (0x00132a78U)
+#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r()                   (0x00136470U)
+#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_update_cycle_init_f()        (0x0U)
+#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_cont_update_enabled_f()\
+				(0x8000000U)
+#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_start_count_disabled_f()     (0x0U)
+#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_start_count_enabled_f()\
+				(0x2000000U)
+#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_reset_m()        (U32(0x1U) << 24U)
+#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_reset_asserted_f()     (0x1000000U)
+#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_reset_deasserted_f()         (0x0U)
+#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_source_xbar_nobg_duplicate_f()\
+				(0x20000000U)
+#define trim_sys_fll_fr_clk_cntr_xbarclk_cntr0_r()                 (0x00136474U)
+#define trim_sys_fll_fr_clk_cntr_xbarclk_cntr1_r()                 (0x00136478U)
+#define trim_sys_fr_clk_cntr_sysclk_cfg_r()                        (0x0013762cU)
+#define trim_sys_fr_clk_cntr_sysclk_cfg_update_cycle_init_f()             (0x0U)
+#define trim_sys_fr_clk_cntr_sysclk_cfg_cont_update_enabled_f()     (0x8000000U)
+#define trim_sys_fr_clk_cntr_sysclk_cfg_start_count_disabled_f()          (0x0U)
+#define trim_sys_fr_clk_cntr_sysclk_cfg_start_count_enabled_f()     (0x2000000U)
+#define trim_sys_fr_clk_cntr_sysclk_cfg_reset_m()             (U32(0x1U) << 24U)
+#define trim_sys_fr_clk_cntr_sysclk_cfg_reset_asserted_f()          (0x1000000U)
+#define trim_sys_fr_clk_cntr_sysclk_cfg_reset_deasserted_f()              (0x0U)
+#define trim_sys_fr_clk_cntr_sysclk_cfg_source_sys_noeg_f()        (0x10000000U)
+#define trim_sys_fr_clk_cntr_sysclk_cntr0_r()                      (0x00137630U)
+#define trim_sys_fr_clk_cntr_sysclk_cntr1_r()                      (0x00137634U)
+#define trim_sys_ind_clk_sys_core_clksrc_r()                       (0x00137c00U)
+#define trim_sys_ind_clk_sys_core_clksrc_hostclk_fll_f()                (0x180U)
+#define trim_fault_threshold_high_r()                              (0x00132af0U)
+#define trim_fault_threshold_high_count_v(r)         (((r) >> 0U) & 0xffffffffU)
+#define trim_fault_threshold_low_r()                               (0x00132af4U)
+#define trim_fault_threshold_low_count_v(r)          (((r) >> 0U) & 0xffffffffU)
+#define trim_fault_status_r()                                      (0x00132b0cU)
+#define trim_fault_status_dc_m()                               (U32(0x1U) << 0U)
+#define trim_fault_status_dc_v(r)                           (((r) >> 0U) & 0x1U)
+#define trim_fault_status_dc_true_v()                              (0x00000001U)
+#define trim_fault_status_lower_threshold_m()                  (U32(0x1U) << 1U)
+#define trim_fault_status_lower_threshold_v(r)              (((r) >> 1U) & 0x1U)
+#define trim_fault_status_lower_threshold_true_v()                 (0x00000001U)
+#define trim_fault_status_higher_threshold_m()                 (U32(0x1U) << 2U)
+#define trim_fault_status_higher_threshold_v(r)             (((r) >> 2U) & 0x1U)
+#define trim_fault_status_higher_threshold_true_v()                (0x00000001U)
+#define trim_fault_status_overflow_m()                         (U32(0x1U) << 3U)
+#define trim_fault_status_overflow_v(r)                     (((r) >> 3U) & 0x1U)
+#define trim_fault_status_overflow_true_v()                        (0x00000001U)
+#define trim_fault_status_fault_out_v(r)                    (((r) >> 4U) & 0x1U)
+#define trim_fault_status_fault_out_true_v()                       (0x00000001U)
+#define trim_gpcclk_fault_priv_level_mask_r()                      (0x00132bb0U)
+#define trim_gpcclk_fault_threshold_high_r()                       (0x00132af0U)
+#define trim_gpcclk_fault_threshold_low_r()                        (0x00132af4U)
+#define trim_gpcclk_fault_status_r()                               (0x00132b0cU)
+#define trim_sysclk_fault_priv_level_mask_r()                      (0x00137b80U)
+#define trim_sysclk_fault_threshold_high_r()                       (0x00137674U)
+#define trim_sysclk_fault_threshold_low_r()                        (0x00137678U)
+#define trim_sysclk_fault_status_r()                               (0x00137690U)
+#define trim_hostclk_fault_priv_level_mask_r()                     (0x00137b80U)
+#define trim_hostclk_fault_threshold_high_r()                      (0x00137774U)
+#define trim_hostclk_fault_threshold_low_r()                       (0x00137778U)
+#define trim_hostclk_fault_status_r()                              (0x00137790U)
+#define trim_xbarclk_fault_priv_level_mask_r()                     (0x00137b80U)
+#define trim_xbarclk_fault_threshold_high_r()                      (0x00137980U)
+#define trim_xbarclk_fault_threshold_low_r()                       (0x00137984U)
+#define trim_xbarclk_fault_status_r()                              (0x0013799cU)
+#define trim_nvdclk_fault_priv_level_mask_r()                      (0x00137b80U)
+#define trim_nvdclk_fault_threshold_high_r()                       (0x001379c0U)
+#define trim_nvdclk_fault_threshold_low_r()                        (0x001379c4U)
+#define trim_nvdclk_fault_status_r()                               (0x001379dcU)
+#define trim_dramclk_fault_priv_level_mask_r()                     (0x001321e4U)
+#define trim_dramclk_fault_threshold_high_r()                      (0x001321a0U)
+#define trim_dramclk_fault_threshold_low_r()                       (0x001321a4U)
+#define trim_dramclk_fault_status_r()                              (0x001321bcU)
+#define trim_pwrclk_fault_priv_level_mask_r()                      (0x00137b80U)
+#define trim_pwrclk_fault_threshold_high_r()                       (0x001376f4U)
+#define trim_pwrclk_fault_threshold_low_r()                        (0x001376f8U)
+#define trim_pwrclk_fault_status_r()                               (0x00137710U)
+#define trim_utilsclk_fault_priv_level_mask_r()                    (0x00137b80U)
+#define trim_utilsclk_fault_threshold_high_r()                     (0x00137734U)
+#define trim_utilsclk_fault_threshold_low_r()                      (0x00137738U)
+#define trim_utilsclk_fault_status_r()                             (0x00137750U)
+#define trim_pex_refclk_fault_priv_level_mask_r()                  (0x00137b80U)
+#define trim_pex_refclk_fault_threshold_high_r()                   (0x001377b4U)
+#define trim_pex_refclk_fault_threshold_low_r()                    (0x001377b8U)
+#define trim_pex_refclk_fault_status_r()                           (0x001377d0U)
+#define trim_nvl_commonclk_fault_priv_level_mask_r()               (0x00137b80U)
+#define trim_nvl_commonclk_fault_threshold_high_r()                (0x00137940U)
+#define trim_nvl_commonclk_fault_threshold_low_r()                 (0x00137944U)
+#define trim_nvl_commonclk_fault_status_r()                        (0x0013795cU)
+#define trim_xclk_fault_priv_level_mask_r()                        (0x00137b00U)
+#define trim_xclk_fault_threshold_high_r()                         (0x00137900U)
+#define trim_xclk_fault_threshold_low_r()                          (0x00137904U)
+#define trim_xclk_fault_status_r()                                 (0x0013791cU)
+#define trim_fmon_master_status_r()                                (0x00137a00U)
+#define trim_fmon_master_status_fault_out_v(r)              (((r) >> 0U) & 0x1U)
+#define trim_fmon_master_status_fault_out_true_v()                 (0x00000001U)
+#define trim_xtal4x_cfg5_r()                                       (0x001370b0U)
+#define trim_xtal4x_cfg_r()                                        (0x00137090U)
+#define trim_xtal4x_cfg_pll_lock_v(r)                      (((r) >> 17U) & 0x1U)
+#define trim_xtal4x_cfg_pll_lock_true_v()                          (0x00000001U)
+#define trim_mem_pll_status_r()                                    (0x00137390U)
+#define trim_mem_pll_status_dram_curr_state_v(r)            (((r) >> 1U) & 0x1U)
+#define trim_mem_pll_status_dram_curr_state_good_v()               (0x00000001U)
+#define trim_mem_pll_status_refm_curr_state_v(r)           (((r) >> 17U) & 0x1U)
+#define trim_mem_pll_status_refm_curr_state_good_v()               (0x00000001U)
+#define trim_sppll0_cfg_r()                                        (0x0000e800U)
+#define trim_sppll0_cfg_curr_state_v(r)                    (((r) >> 17U) & 0x1U)
+#define trim_sppll0_cfg_curr_state_good_v()                        (0x00000001U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xp_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xp_ga100.h
new file mode 100644
index 000000000..9932359b0
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xp_ga100.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_XP_GA100_H
+#define NVGPU_HW_XP_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define xp_dl_mgr_r(i)\
+		(nvgpu_safe_add_u32(0x0008b8c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define xp_dl_mgr_safe_timing_f(v)                       ((U32(v) & 0x1U) << 2U)
+#define xp_pl_link_config_r(i)\
+		(nvgpu_safe_add_u32(0x0008c040U, nvgpu_safe_mult_u32((i), 4U)))
+#define xp_pl_link_config_ltssm_status_f(v)              ((U32(v) & 0x1U) << 4U)
+#define xp_pl_link_config_ltssm_status_idle_v()                    (0x00000000U)
+#define xp_pl_link_config_ltssm_directive_f(v)           ((U32(v) & 0xfU) << 0U)
+#define xp_pl_link_config_ltssm_directive_m()                  (U32(0xfU) << 0U)
+#define xp_pl_link_config_ltssm_directive_normal_operations_v()    (0x00000000U)
+#define xp_pl_link_config_ltssm_directive_change_speed_v()         (0x00000001U)
+#define xp_pl_link_config_max_link_rate_f(v)            ((U32(v) & 0x3U) << 18U)
+#define xp_pl_link_config_max_link_rate_m()                   (U32(0x3U) << 18U)
+#define xp_pl_link_config_max_link_rate_2500_mtps_v()              (0x00000003U)
+#define xp_pl_link_config_max_link_rate_5000_mtps_v()              (0x00000002U)
+#define xp_pl_link_config_max_link_rate_8000_mtps_v()              (0x00000001U)
+#define xp_pl_link_config_target_tx_width_f(v)          ((U32(v) & 0x7U) << 20U)
+#define xp_pl_link_config_target_tx_width_m()                 (U32(0x7U) << 20U)
+#define xp_pl_link_config_target_tx_width_x1_v()                   (0x00000007U)
+#define xp_pl_link_config_target_tx_width_x2_v()                   (0x00000006U)
+#define xp_pl_link_config_target_tx_width_x4_v()                   (0x00000005U)
+#define xp_pl_link_config_target_tx_width_x8_v()                   (0x00000004U)
+#define xp_pl_link_config_target_tx_width_x16_v()                  (0x00000000U)
+#define xp_dl_mgr_timing_r(i)\
+		(nvgpu_safe_add_u32(0x0008b400U, nvgpu_safe_mult_u32((i), 4U)))
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xve_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xve_ga100.h
new file mode 100644
index 000000000..6ae10ca54
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xve_ga100.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_XVE_GA100_H
+#define NVGPU_HW_XVE_GA100_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define xve_rom_ctrl_r()                                           (0x00000050U)
+#define xve_rom_ctrl_rom_shadow_disabled_f()                              (0x0U)
+#define xve_rom_ctrl_rom_shadow_enabled_f()                               (0x1U)
+#define xve_link_control_status_r()                                (0x00000088U)
+#define xve_link_control_status_link_speed_v(r)            (((r) >> 16U) & 0xfU)
+#define xve_link_control_status_link_speed_link_speed_2p5_v()      (0x00000001U)
+#define xve_link_control_status_link_speed_link_speed_5p0_v()      (0x00000002U)
+#define xve_link_control_status_link_speed_link_speed_8p0_v()      (0x00000003U)
+#define xve_link_control_status_link_width_v(r)           (((r) >> 20U) & 0x3fU)
+#define xve_link_control_status_link_width_x1_v()                  (0x00000001U)
+#define xve_link_control_status_link_width_x2_v()                  (0x00000002U)
+#define xve_link_control_status_link_width_x4_v()                  (0x00000004U)
+#define xve_link_control_status_link_width_x8_v()                  (0x00000008U)
+#define xve_link_control_status_link_width_x16_v()                 (0x00000010U)
+#define xve_priv_xv_r()                                            (0x00000150U)
+#define xve_priv_xv_cya_l0s_enable_f(v)                  ((U32(v) & 0x1U) << 7U)
+#define xve_priv_xv_cya_l0s_enable_m()                         (U32(0x1U) << 7U)
+#define xve_priv_xv_cya_l0s_enable_v(r)                     (((r) >> 7U) & 0x1U)
+#define xve_priv_xv_cya_l1_enable_f(v)                   ((U32(v) & 0x1U) << 8U)
+#define xve_priv_xv_cya_l1_enable_m()                          (U32(0x1U) << 8U)
+#define xve_priv_xv_cya_l1_enable_v(r)                      (((r) >> 8U) & 0x1U)
+#define xve_cya_2_r()                                              (0x00000704U)
+#define xve_reset_r()                                              (0x00000718U)
+#define xve_reset_reset_m()                                    (U32(0x1U) << 0U)
+#define xve_reset_gpu_on_sw_reset_m()                          (U32(0x1U) << 1U)
+#define xve_reset_counter_en_m()                               (U32(0x1U) << 2U)
+#define xve_reset_counter_val_f(v)                     ((U32(v) & 0x7ffU) << 4U)
+#define xve_reset_clock_on_sw_reset_m()                       (U32(0x1U) << 15U)
+#define xve_reset_clock_counter_en_m()                        (U32(0x1U) << 16U)
+#define xve_reset_clock_counter_val_f(v)              ((U32(v) & 0x7ffU) << 17U)
+#define xve_pcie_capability_r()                                    (0x00000610U)
+#define xve_pcie_capability_gen2_capable_enable_f()                       (0x1U)
+#define xve_pcie_capability_gen3_capable_enable_f()                    (0x1000U)
+#define xve_high_latency_r()                                       (0x00000a10U)
+#define xve_high_latency_snoop_latency_value_init_f()                    (0xfaU)
+#define xve_high_latency_snoop_latency_scale_init_f()                   (0x400U)
+#define xve_high_latency_no_snoop_latency_value_init_f()             (0xfa0000U)
+#define xve_high_latency_no_snoop_latency_scale_init_f()            (0x4000000U)
+#define xve_ltr_msg_ctrl_r()                                       (0x00000a20U)
+#define xve_ltr_msg_ctrl_trigger_not_pending_f()                          (0x0U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_bus_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_bus_ga10b.h
new file mode 100644
index 000000000..795c2d111
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_bus_ga10b.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_BUS_GA10B_H
+#define NVGPU_HW_BUS_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define bus_bar0_window_r()                                        (0x00001700U)
+#define bus_bar0_window_base_f(v)                   ((U32(v) & 0xffffffU) << 0U)
+#define bus_bar0_window_target_vid_mem_f()                                (0x0U)
+#define bus_bar0_window_target_sys_mem_coherent_f()                 (0x2000000U)
+#define bus_bar0_window_target_sys_mem_noncoherent_f()              (0x3000000U)
+#define bus_bar0_window_target_bar0_window_base_shift_v()          (0x00000010U)
+#define bus_bar1_block_r()                                         (0x00001704U)
+#define bus_bar1_block_ptr_f(v)                    ((U32(v) & 0xfffffffU) << 0U)
+#define bus_bar1_block_target_vid_mem_f()                                 (0x0U)
+#define bus_bar1_block_target_sys_mem_coh_f()                      (0x20000000U)
+#define bus_bar1_block_target_sys_mem_ncoh_f()                     (0x30000000U)
+#define bus_bar1_block_mode_virtual_f()                            (0x80000000U)
+#define bus_bar2_block_r()                                         (0x00001714U)
+#define bus_bar2_block_ptr_f(v)                    ((U32(v) & 0xfffffffU) << 0U)
+#define bus_bar2_block_target_vid_mem_f()                                 (0x0U)
+#define bus_bar2_block_target_sys_mem_coh_f()                      (0x20000000U)
+#define bus_bar2_block_target_sys_mem_ncoh_f()                     (0x30000000U)
+#define bus_bar2_block_mode_virtual_f()                            (0x80000000U)
+#define bus_bar1_block_ptr_shift_v()                               (0x0000000cU)
+#define bus_bar2_block_ptr_shift_v()                               (0x0000000cU)
+#define bus_bind_status_r()                                        (0x00001710U)
+#define bus_bind_status_bar1_pending_v(r)                   (((r) >> 0U) & 0x1U)
+#define bus_bind_status_bar1_outstanding_v(r)               (((r) >> 1U) & 0x1U)
+#define bus_bind_status_bar2_pending_v(r)                   (((r) >> 2U) & 0x1U)
+#define bus_bind_status_bar2_outstanding_v(r)               (((r) >> 3U) & 0x1U)
+#define bus_intr_0_r()                                             (0x00001100U)
+#define bus_intr_0_pri_fecserr_m()                             (U32(0x1U) << 2U)
+#define bus_intr_0_pri_timeout_m()                             (U32(0x1U) << 3U)
+#define bus_intr_0_fb_req_timeout_m()                          (U32(0x1U) << 4U)
+#define bus_intr_0_fb_ack_timeout_m()                          (U32(0x1U) << 5U)
+#define bus_intr_0_fb_ack_extra_m()                            (U32(0x1U) << 6U)
+#define bus_intr_0_fb_rdata_timeout_m()                        (U32(0x1U) << 7U)
+#define bus_intr_0_fb_rdata_extra_m()                          (U32(0x1U) << 8U)
+#define bus_intr_0_sw_m()                                     (U32(0x1U) << 26U)
+#define bus_intr_0_posted_deadlock_timeout_m()                (U32(0x1U) << 27U)
+#define bus_intr_0_mpmu_m()                                   (U32(0x1U) << 28U)
+#define bus_intr_0_access_timeout_m()                         (U32(0x1U) << 31U)
+#define bus_intr_en_0_r()                                          (0x00001140U)
+#define bus_intr_en_0_pri_fecserr_m()                          (U32(0x1U) << 2U)
+#define bus_intr_en_0_pri_timeout_m()                          (U32(0x1U) << 3U)
+#define bus_intr_en_0_fb_req_timeout_m()                       (U32(0x1U) << 4U)
+#define bus_intr_en_0_fb_ack_timeout_m()                       (U32(0x1U) << 5U)
+#define bus_intr_en_0_fb_ack_extra_m()                         (U32(0x1U) << 6U)
+#define bus_intr_en_0_fb_rdata_timeout_m()                     (U32(0x1U) << 7U)
+#define bus_intr_en_0_fb_rdata_extra_m()                       (U32(0x1U) << 8U)
+#define bus_intr_en_0_sw_m()                                  (U32(0x1U) << 26U)
+#define bus_intr_en_0_posted_deadlock_timeout_m()             (U32(0x1U) << 27U)
+#define bus_intr_en_0_mpmu_m()                                (U32(0x1U) << 28U)
+#define bus_intr_en_0_access_timeout_m()                      (U32(0x1U) << 31U)
+#define bus_fb_timeout_r()                                         (0x00001538U)
+#define bus_fb_timeout_period_v(r)                   (((r) >> 0U) & 0x3fffffffU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h
new file mode 100644
index 000000000..ed6753ef9
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_CCSR_GA10B_H
+#define NVGPU_HW_CCSR_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ce_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ce_ga10b.h
new file mode 100644
index 000000000..56ebab665
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ce_ga10b.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_CE_GA10B_H
+#define NVGPU_HW_CE_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define ce_lce_intr_en_r(i)\
+		(nvgpu_safe_add_u32(0x0010440cU, nvgpu_safe_mult_u32((i), 128U)))
+#define ce_lce_intr_en_blockpipe_m()                           (U32(0x1U) << 0U)
+#define ce_lce_intr_en_nonblockpipe_m()                        (U32(0x1U) << 1U)
+#define ce_lce_intr_en_launcherr_m()                           (U32(0x1U) << 2U)
+#define ce_lce_intr_en_invalid_config_m()                      (U32(0x1U) << 3U)
+#define ce_lce_intr_en_mthd_buffer_fault_m()                   (U32(0x1U) << 4U)
+#define ce_lce_intr_en_fbuf_crc_fail_m()                       (U32(0x1U) << 5U)
+#define ce_lce_intr_en_fbuf_magic_chk_fail_m()                 (U32(0x1U) << 6U)
+#define ce_lce_intr_en_poison_error_m()                        (U32(0x1U) << 7U)
+#define ce_lce_intr_en_nonstalling_debug_m()                  (U32(0x1U) << 30U)
+#define ce_lce_intr_en_stalling_debug_m()                     (U32(0x1U) << 31U)
+#define ce_intr_status_r(i)\
+		(nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32((i), 128U)))
+#define ce_intr_status_blockpipe_pending_f()                              (0x1U)
+#define ce_intr_status_launcherr_pending_f()                              (0x4U)
+#define ce_intr_status_invalid_config_pending_f()                         (0x8U)
+#define ce_intr_status_invalid_config_reset_f()                           (0x8U)
+#define ce_intr_status_mthd_buffer_fault_pending_f()                     (0x10U)
+#define ce_intr_status_mthd_buffer_fault_reset_f()                       (0x10U)
+#define ce_intr_status_fbuf_crc_fail_pending_f()                         (0x20U)
+#define ce_intr_status_fbuf_crc_fail_reset_f()                           (0x20U)
+#define ce_intr_status_fbuf_magic_chk_fail_pending_f()                   (0x40U)
+#define ce_intr_status_fbuf_magic_chk_fail_reset_f()                     (0x40U)
+#define ce_intr_status_poison_error_pending_f()                          (0x80U)
+#define ce_intr_status_poison_error_reset_f()                            (0x80U)
+#define ce_intr_status_stalling_debug_pending_f()                  (0x80000000U)
+#define ce_intr_retrigger_r(i)\
+		(nvgpu_safe_add_u32(0x00104434U, nvgpu_safe_mult_u32((i), 128U)))
+#define ce_intr_retrigger_trigger_true_f()                                (0x1U)
+#define ce_pce_map_r()                                             (0x00104028U)
+#define ce_lce_opt_r(i)\
+		(nvgpu_safe_add_u32(0x00104414U, nvgpu_safe_mult_u32((i), 128U)))
+#define ce_lce_opt_force_barriers_npl__prod_f()                           (0x8U)
+#define ce_lce_intr_notify_ctrl_r(i)\
+		(nvgpu_safe_add_u32(0x00104424U, nvgpu_safe_mult_u32((i), 128U)))
+#define ce_lce_intr_notify_ctrl_vector_v(r)               (((r) >> 0U) & 0xfffU)
+#define ce_lce_intr_notify_ctrl_gsp_m()                       (U32(0x1U) << 30U)
+#define ce_lce_intr_notify_ctrl_gsp_disable_f()                           (0x0U)
+#define ce_lce_intr_notify_ctrl_cpu_m()                       (U32(0x1U) << 31U)
+#define ce_lce_intr_notify_ctrl_cpu_enable_f()                     (0x80000000U)
+#define ce_lce_intr_notify_ctrl_cpu_disable_f()                           (0x0U)
+#define ce_lce_intr_ctrl_r(i)\
+		(nvgpu_safe_add_u32(0x0010442cU, nvgpu_safe_mult_u32((i), 128U)))
+#define ce_lce_intr_ctrl_gsp_m()                              (U32(0x1U) << 30U)
+#define ce_lce_intr_ctrl_gsp_disable_f()                                  (0x0U)
+#define ce_lce_intr_ctrl_cpu_m()                              (U32(0x1U) << 31U)
+#define ce_lce_intr_ctrl_cpu_enable_f()                            (0x80000000U)
+#define ce_lce_intr_ctrl_cpu_disable_f()                                  (0x0U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ctrl_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ctrl_ga10b.h
new file mode 100644
index 000000000..f7f7f5d5b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ctrl_ga10b.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_CTRL_GA10B_H
+#define NVGPU_HW_CTRL_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define ctrl_doorbell_r(i)\
+		(nvgpu_safe_add_u32(0x00b64000U, nvgpu_safe_mult_u32((i), 8U)))
+#define ctrl_doorbell_vector_f(v)                      ((U32(v) & 0xfffU) << 0U)
+#define ctrl_doorbell_runlist_id_f(v)                  ((U32(v) & 0x7fU) << 16U)
+#define ctrl_legacy_engine_nonstall_intr_base_vectorid_r()         (0x00b66884U)
+#define ctrl_legacy_engine_nonstall_intr_base_vectorid_vector_v(r)\
+				(((r) >> 0U) & 0xfffU)
+#define ctrl_legacy_engine_stall_intr_base_vectorid_r()            (0x00b66880U)
+#define ctrl_legacy_engine_stall_intr_base_vectorid_vector_v(r)\
+				(((r) >> 0U) & 0xfffU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h
new file mode 100644
index 000000000..849a32e00
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_CTXSW_PROG_GA10B_H
+#define NVGPU_HW_CTXSW_PROG_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define ctxsw_prog_ctxsw_header_size_in_bytes_v()                  (0x00000300U)
+#define ctxsw_prog_fecs_header_size_in_bytes_v()                   (0x00000300U)
+#define ctxsw_prog_gpccs_header_stride_v()                         (0x00000300U)
+#define ctxsw_prog_main_image_num_gpcs_o()                         (0x00000008U)
+#define ctxsw_prog_main_image_ctl_o()                              (0x0000000cU)
+#define ctxsw_prog_main_image_ctl_type_per_veid_header_v()         (0x00000021U)
+#define ctxsw_prog_main_image_patch_count_o()                      (0x00000010U)
+#define ctxsw_prog_main_image_context_id_o()                       (0x000000f0U)
+#define ctxsw_prog_main_image_patch_adr_lo_o()                     (0x00000014U)
+#define ctxsw_prog_main_image_patch_adr_hi_o()                     (0x00000018U)
+#define ctxsw_prog_main_image_zcull_o()                            (0x0000001cU)
+#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v()              (0x00000001U)
+#define ctxsw_prog_main_image_zcull_ptr_o()                        (0x00000020U)
+#define ctxsw_prog_main_image_pm_o()                               (0x00000028U)
+#define ctxsw_prog_main_image_pm_mode_m()                      (U32(0x7U) << 0U)
+#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f()                        (0x0U)
+#define ctxsw_prog_main_image_pm_mode_ctxsw_f()                           (0x1U)
+#define ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f()                (0x2U)
+#define ctxsw_prog_main_image_pm_smpc_mode_m()                 (U32(0x7U) << 3U)
+#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f()                   (0x0U)
+#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f()                      (0x8U)
+#define ctxsw_prog_main_image_pm_ptr_o()                           (0x0000002cU)
+#define ctxsw_prog_main_image_num_save_ops_o()                     (0x000000f4U)
+#define ctxsw_prog_main_image_num_wfi_save_ops_o()                 (0x000000d0U)
+#define ctxsw_prog_main_image_num_cta_save_ops_o()                 (0x000000d4U)
+#define ctxsw_prog_main_image_num_gfxp_save_ops_o()                (0x000000d8U)
+#define ctxsw_prog_main_image_num_cilp_save_ops_o()                (0x000000dcU)
+#define ctxsw_prog_main_image_num_restore_ops_o()                  (0x000000f8U)
+#define ctxsw_prog_main_image_magic_value_1_o()                    (0x000000fcU)
+#define ctxsw_prog_main_image_magic_value_1_v_value_v()            (0x600dc0deU)
+#define ctxsw_prog_main_image_magic_value_2_o()                    (0x00000100U)
+#define ctxsw_prog_main_image_magic_value_2_v_value_v()            (0xdeadce11U)
+#define ctxsw_prog_main_image_magic_value_3_o()                    (0x000001fcU)
+#define ctxsw_prog_main_image_magic_value_3_v_value_v()            (0xfaceb00cU)
+#define ctxsw_prog_main_image_magic_value_4_o()                    (0x00000200U)
+#define ctxsw_prog_main_image_magic_value_4_v_value_v()            (0x0baff1edU)
+#define ctxsw_prog_main_image_magic_value_5_o()                    (0x000002fcU)
+#define ctxsw_prog_main_image_magic_value_5_v_value_v()            (0xca5cadedU)
+#define ctxsw_prog_main_image_zcull_ptr_hi_o()                     (0x00000060U)
+#define ctxsw_prog_main_image_pm_ptr_hi_o()                        (0x00000094U)
+#define ctxsw_prog_main_image_full_preemption_ptr_hi_o()           (0x00000064U)
+#define ctxsw_prog_main_image_full_preemption_ptr_o()              (0x00000068U)
+#define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o()     (0x00000070U)
+#define ctxsw_prog_main_image_full_preemption_ptr_veid0_o()        (0x00000074U)
+#define ctxsw_prog_main_image_context_buffer_ptr_hi_o()            (0x00000078U)
+#define ctxsw_prog_main_image_context_buffer_ptr_o()               (0x0000007cU)
+#define ctxsw_prog_local_priv_register_ctl_o()                     (0x0000000cU)
+#define ctxsw_prog_local_priv_register_ctl_offset_v(r)   (((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_local_sys_reglist_offset_o()                    (0x00000034U)
+#define ctxsw_prog_local_sys_reglist_offset_compute_v(r) (((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_local_sys_reglist_offset_graphics_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define ctxsw_prog_local_gpc_reglist_offset_o()                    (0x00000034U)
+#define ctxsw_prog_local_gpc_reglist_offset_compute_v(r) (((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_local_gpc_reglist_offset_graphics_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define ctxsw_prog_local_lts_reglist_offset_o()                    (0x00000038U)
+#define ctxsw_prog_local_lts_reglist_offset_v_v(r)       (((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_local_ppc_reglist_offset_o()                    (0x00000038U)
+#define ctxsw_prog_local_ppc_reglist_offset_compute_v(r) (((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_local_ppc_reglist_offset_graphics_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define ctxsw_prog_local_ext_tpc_reglist_offset_o()                (0x0000003cU)
+#define ctxsw_prog_local_ext_tpc_reglist_offset_compute_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_local_ext_tpc_reglist_offset_graphics_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define ctxsw_prog_local_tpc_reglist_offset_r(i)\
+		(nvgpu_safe_add_u32(0x00000040U, nvgpu_safe_mult_u32((i), 4U)))
+#define ctxsw_prog_local_tpc_reglist_offset_compute_v(r) (((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_local_tpc_reglist_offset_graphics_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define ctxsw_prog_local_image_ppc_info_o()                        (0x000000f4U)
+#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r)    (((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r)   (((r) >> 16U) & 0xffffU)
+#define ctxsw_prog_local_image_num_tpcs_o()                        (0x000000f8U)
+#define ctxsw_prog_local_magic_value_1_o()                         (0x000000fcU)
+#define ctxsw_prog_local_magic_value_1_v_value_v()                 (0xad0becabU)
+#define ctxsw_prog_local_magic_value_2_o()                         (0x00000100U)
+#define ctxsw_prog_local_magic_value_2_v_value_v()                 (0x1ceb00daU)
+#define ctxsw_prog_local_magic_value_3_o()                         (0x000001fcU)
+#define ctxsw_prog_local_magic_value_3_v_value_v()                 (0xf00dbeefU)
+#define ctxsw_prog_local_magic_value_4_o()                         (0x00000200U)
+#define ctxsw_prog_local_magic_value_4_v_value_v()                 (0x0dec0dedU)
+#define ctxsw_prog_local_magic_value_5_o()                         (0x000002fcU)
+#define ctxsw_prog_local_magic_value_5_v_value_v()                 (0x5caff01dU)
+#define ctxsw_prog_main_extended_buffer_ctl_o()                    (0x000000ecU)
+#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r)  (((r) >> 0U) & 0xffffU)
+#define ctxsw_prog_main_extended_buffer_ctl_size_v(r)     (((r) >> 16U) & 0xffU)
+#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v()      (0x00000100U)
+#define ctxsw_prog_extended_marker_size_in_bytes_v()               (0x00000004U)
+#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\
+				(0x00000000U)
+#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\
+				(0x00000002U)
+#define ctxsw_prog_main_image_priv_access_map_config_o()           (0x000000a0U)
+#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f()   (0x0U)
+#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f()     (0x2U)
+#define ctxsw_prog_main_image_priv_access_map_addr_lo_o()          (0x000000a4U)
+#define ctxsw_prog_main_image_priv_access_map_addr_hi_o()          (0x000000a8U)
+#define ctxsw_prog_main_image_misc_options_o()                     (0x0000003cU)
+#define ctxsw_prog_main_image_misc_options_verif_features_m()  (U32(0x1U) << 3U)
+#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f()    (0x0U)
+#define ctxsw_prog_main_image_graphics_preemption_options_o()      (0x00000080U)
+#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\
+				(0x1U)
+#define ctxsw_prog_main_image_compute_preemption_options_o()       (0x00000084U)
+#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f()  (0x1U)
+#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U)
+#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU)
+#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\
+				((U32(v) & 0xffffU) << 0U)
+#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o()  (0x000000b0U)
+#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o()     (0x000000b4U)
+#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define ctxsw_prog_record_timestamp_record_size_in_bytes_v()       (0x00000080U)
+#define ctxsw_prog_record_timestamp_magic_value_hi_o()             (0x00000004U)
+#define ctxsw_prog_record_timestamp_timestamp_hi_o()               (0x0000001cU)
+#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m()     (U32(0xffU) << 24U)
+#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU)
+#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v()\
+				(0x000000ffU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_falcon_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_falcon_ga10b.h
new file mode 100644
index 000000000..230f04aa8
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_falcon_ga10b.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_FALCON_GA10B_H
+#define NVGPU_HW_FALCON_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define falcon_falcon_irqstat_r()                                  (0x00000008U)
+#define falcon_falcon_irqmode_r()                                  (0x0000000cU)
+#define falcon_falcon_irqmset_r()                                  (0x00000010U)
+#define falcon_falcon_irqmclr_r()                                  (0x00000014U)
+#define falcon_falcon_irqmask_r()                                  (0x00000018U)
+#define falcon_falcon_irqdest_r()                                  (0x0000001cU)
+#define falcon_falcon_curctx_r()                                   (0x00000050U)
+#define falcon_falcon_nxtctx_r()                                   (0x00000054U)
+#define falcon_falcon_mailbox0_r()                                 (0x00000040U)
+#define falcon_falcon_mailbox1_r()                                 (0x00000044U)
+#define falcon_falcon_idlestate_r()                                (0x0000004cU)
+#define falcon_falcon_os_r()                                       (0x00000080U)
+#define falcon_falcon_engctl_r()                                   (0x000000a4U)
+#define falcon_falcon_cpuctl_r()                                   (0x00000100U)
+#define falcon_falcon_cpuctl_startcpu_f(v)               ((U32(v) & 0x1U) << 1U)
+#define falcon_falcon_cpuctl_hreset_f(v)                 ((U32(v) & 0x1U) << 3U)
+#define falcon_falcon_cpuctl_halt_intr_m()                     (U32(0x1U) << 4U)
+#define falcon_falcon_cpuctl_halt_intr_v(r)                 (((r) >> 4U) & 0x1U)
+#define falcon_falcon_imemc_r(i)\
+		(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U)))
+#define falcon_falcon_imemc_offs_f(v)                   ((U32(v) & 0x3fU) << 2U)
+#define falcon_falcon_imemc_blk_f(v)                  ((U32(v) & 0xffffU) << 8U)
+#define falcon_falcon_imemc_aincw_f(v)                  ((U32(v) & 0x1U) << 24U)
+#define falcon_falcon_imemc_secure_f(v)                 ((U32(v) & 0x1U) << 28U)
+#define falcon_falcon_imemd_r(i)\
+		(nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U)))
+#define falcon_falcon_imemt_r(i)\
+		(nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U)))
+#define falcon_falcon_sctl_r()                                     (0x00000240U)
+#define falcon_falcon_bootvec_r()                                  (0x00000104U)
+#define falcon_falcon_bootvec_vec_f(v)            ((U32(v) & 0xffffffffU) << 0U)
+#define falcon_falcon_dmactl_r()                                   (0x0000010cU)
+#define falcon_falcon_dmactl_require_ctx_f(v)            ((U32(v) & 0x1U) << 0U)
+#define falcon_falcon_hwcfg_r()                                    (0x00000108U)
+#define falcon_falcon_hwcfg_imem_size_v(r)                (((r) >> 0U) & 0x1ffU)
+#define falcon_falcon_hwcfg_dmem_size_v(r)                (((r) >> 9U) & 0x1ffU)
+#define falcon_falcon_imstat_r()                                   (0x00000144U)
+#define falcon_falcon_traceidx_r()                                 (0x00000148U)
+#define falcon_falcon_traceidx_maxidx_v(r)                (((r) >> 16U) & 0xffU)
+#define falcon_falcon_tracepc_r()                                  (0x0000014cU)
+#define falcon_falcon_tracepc_pc_v(r)                  (((r) >> 0U) & 0xffffffU)
+#define falcon_falcon_exterraddr_r()                               (0x0010a168U)
+#define falcon_falcon_exterrstat_r()                               (0x0010a16cU)
+#define falcon_falcon_icd_cmd_r()                                  (0x00000200U)
+#define falcon_falcon_icd_cmd_opc_rreg_f()                                (0x8U)
+#define falcon_falcon_icd_cmd_opc_rstat_f()                               (0xeU)
+#define falcon_falcon_icd_cmd_idx_f(v)                  ((U32(v) & 0x1fU) << 8U)
+#define falcon_falcon_icd_rdata_r()                                (0x0000020cU)
+#define falcon_falcon_dmemc_r(i)\
+		(nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U)))
+#define falcon_falcon_dmemc_offs_m()                          (U32(0x3fU) << 2U)
+#define falcon_falcon_dmemc_blk_m()                         (U32(0xffffU) << 8U)
+#define falcon_falcon_dmemc_aincw_f(v)                  ((U32(v) & 0x1U) << 24U)
+#define falcon_falcon_dmemc_aincr_f(v)                  ((U32(v) & 0x1U) << 25U)
+#define falcon_falcon_dmemd_r(i)\
+		(nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U)))
+#define falcon_falcon_debug1_r()                                   (0x00000090U)
+#define falcon_falcon_debuginfo_r()                                (0x00000094U)
+#define falcon_falcon_hwcfg2_r()                                   (0x000000f4U)
+#define falcon_falcon_hwcfg2_mem_scrubbing_v(r)            (((r) >> 12U) & 0x1U)
+#define falcon_falcon_hwcfg2_mem_scrubbing_pending_v()             (0x00000001U)
+#define falcon_falcon_hwcfg2_riscv_br_priv_lockdown_v(r)   (((r) >> 13U) & 0x1U)
+#define falcon_falcon_hwcfg2_riscv_br_priv_lockdown_lock_v()       (0x00000001U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fb_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fb_ga10b.h
new file mode 100644
index 000000000..7424222fc
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fb_ga10b.h
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_FB_GA10B_H
+#define NVGPU_HW_FB_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define fb_fbhub_num_active_ltcs_r()                               (0x00100800U)
+#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m()      (U32(0x1U) << 25U)
+#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f()    (0x2000000U)
+#define fb_fbhub_num_active_ltcs_count_f(v)             ((U32(v) & 0x1fU) << 0U)
+#define fb_fbhub_num_active_ltcs_count_m()                    (U32(0x1fU) << 0U)
+#define fb_fbhub_num_active_ltcs_count_v(r)                (((r) >> 0U) & 0x1fU)
+#define fb_mmu_ctrl_r()                                            (0x00100c80U)
+#define fb_mmu_ctrl_pri_fifo_empty_v(r)                    (((r) >> 15U) & 0x1U)
+#define fb_mmu_ctrl_pri_fifo_empty_false_f()                              (0x0U)
+#define fb_mmu_ctrl_pri_fifo_space_v(r)                   (((r) >> 16U) & 0xffU)
+#define fb_mmu_ctrl_atomic_capability_mode_m()                (U32(0x3U) << 24U)
+#define fb_mmu_ctrl_atomic_capability_mode_rmw_f()                  (0x2000000U)
+#define fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m()       (U32(0x1U) << 27U)
+#define fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f()                (0x0U)
+#define fb_priv_mmu_phy_secure_r()                                 (0x00100ce4U)
+#define fb_mmu_invalidate_pdb_r()                                  (0x00100cb8U)
+#define fb_mmu_invalidate_pdb_aperture_vid_mem_f()                        (0x0U)
+#define fb_mmu_invalidate_pdb_aperture_sys_mem_f()                        (0x2U)
+#define fb_mmu_invalidate_pdb_addr_f(v)            ((U32(v) & 0xfffffffU) << 4U)
+#define fb_mmu_invalidate_r()                                      (0x00100cbcU)
+#define fb_mmu_invalidate_all_va_true_f()                                 (0x1U)
+#define fb_mmu_invalidate_all_pdb_true_f()                                (0x2U)
+#define fb_mmu_invalidate_replay_start_ack_all_f()                       (0x10U)
+#define fb_mmu_invalidate_replay_cancel_global_f()                       (0x20U)
+#define fb_mmu_invalidate_trigger_true_f()                         (0x80000000U)
+#define fb_mmu_debug_wr_r()                                        (0x00100cc8U)
+#define fb_mmu_debug_wr_aperture_vid_mem_f()                              (0x0U)
+#define fb_mmu_debug_wr_aperture_sys_mem_coh_f()                          (0x2U)
+#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f()                         (0x3U)
+#define fb_mmu_debug_wr_vol_false_f()                                     (0x0U)
+#define fb_mmu_debug_wr_addr_f(v)                  ((U32(v) & 0xfffffffU) << 4U)
+#define fb_mmu_debug_wr_addr_alignment_v()                         (0x0000000cU)
+#define fb_mmu_debug_rd_r()                                        (0x00100cccU)
+#define fb_mmu_debug_rd_aperture_vid_mem_f()                              (0x0U)
+#define fb_mmu_debug_rd_vol_false_f()                                     (0x0U)
+#define fb_mmu_debug_rd_addr_f(v)                  ((U32(v) & 0xfffffffU) << 4U)
+#define fb_mmu_debug_rd_addr_alignment_v()                         (0x0000000cU)
+#define fb_mmu_debug_ctrl_r()                                      (0x00100cc4U)
+#define fb_mmu_debug_ctrl_debug_m()                           (U32(0x1U) << 16U)
+#define fb_mmu_debug_ctrl_debug_enabled_v()                        (0x00000001U)
+#define fb_mmu_debug_ctrl_debug_enabled_f()                           (0x10000U)
+#define fb_mmu_debug_ctrl_debug_disabled_f()                              (0x0U)
+#define fb_mmu_l2tlb_ecc_control_r()                               (0x00100e6cU)
+#define fb_mmu_l2tlb_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 5U)
+#define fb_mmu_l2tlb_ecc_status_r()                                (0x00100e70U)
+#define fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()\
+				(U32(0x1U) << 0U)
+#define fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m()\
+				(U32(0x1U) << 1U)
+#define fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb1_sa_data_m()\
+				(U32(0x1U) << 2U)
+#define fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb1_sa_data_m()\
+				(U32(0x1U) << 3U)
+#define fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 16U)
+#define fb_mmu_l2tlb_ecc_status_corrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 17U)
+#define fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 18U)
+#define fb_mmu_l2tlb_ecc_status_uncorrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 19U)
+#define fb_mmu_l2tlb_ecc_status_reset_clear_f()                    (0x40000000U)
+#define fb_mmu_l2tlb_ecc_corrected_err_count_r()                   (0x00100e74U)
+#define fb_mmu_l2tlb_ecc_corrected_err_count_total_s()                     (16U)
+#define fb_mmu_l2tlb_ecc_corrected_err_count_total_v(r)  (((r) >> 0U) & 0xffffU)
+#define fb_mmu_l2tlb_ecc_corrected_err_count_unique_s()                    (16U)
+#define fb_mmu_l2tlb_ecc_corrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_l2tlb_ecc_uncorrected_err_count_r()                 (0x00100e78U)
+#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s()                   (16U)
+#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define fb_mmu_l2tlb_ecc_uncorrected_err_count_unique_s()                  (16U)
+#define fb_mmu_l2tlb_ecc_uncorrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_l2tlb_ecc_address_r()                               (0x00100e7cU)
+#define fb_mmu_hubtlb_ecc_control_r()                              (0x00100e80U)
+#define fb_mmu_hubtlb_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 5U)
+#define fb_mmu_hubtlb_ecc_status_r()                               (0x00100e84U)
+#define fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()     (U32(0x1U) << 0U)
+#define fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m()   (U32(0x1U) << 1U)
+#define fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 16U)
+#define fb_mmu_hubtlb_ecc_status_corrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 17U)
+#define fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 18U)
+#define fb_mmu_hubtlb_ecc_status_uncorrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 19U)
+#define fb_mmu_hubtlb_ecc_status_reset_clear_f()                   (0x40000000U)
+#define fb_mmu_hubtlb_ecc_corrected_err_count_r()                  (0x00100e88U)
+#define fb_mmu_hubtlb_ecc_corrected_err_count_total_s()                    (16U)
+#define fb_mmu_hubtlb_ecc_corrected_err_count_total_v(r) (((r) >> 0U) & 0xffffU)
+#define fb_mmu_hubtlb_ecc_corrected_err_count_unique_s()                   (16U)
+#define fb_mmu_hubtlb_ecc_corrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_hubtlb_ecc_uncorrected_err_count_r()                (0x00100e8cU)
+#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s()                  (16U)
+#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define fb_mmu_hubtlb_ecc_uncorrected_err_count_unique_s()                 (16U)
+#define fb_mmu_hubtlb_ecc_uncorrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_hubtlb_ecc_address_r()                              (0x00100e90U)
+#define fb_mmu_fillunit_ecc_control_r()                            (0x00100e94U)
+#define fb_mmu_fillunit_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 5U)
+#define fb_mmu_fillunit_ecc_status_r()                             (0x00100e98U)
+#define fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()  (U32(0x1U) << 0U)
+#define fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m()\
+				(U32(0x1U) << 1U)
+#define fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m() (U32(0x1U) << 2U)
+#define fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m()\
+				(U32(0x1U) << 3U)
+#define fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 16U)
+#define fb_mmu_fillunit_ecc_status_corrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 17U)
+#define fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 18U)
+#define fb_mmu_fillunit_ecc_status_uncorrected_err_unique_counter_overflow_m()\
+				(U32(0x1U) << 19U)
+#define fb_mmu_fillunit_ecc_status_reset_clear_f()                 (0x40000000U)
+#define fb_mmu_fillunit_ecc_corrected_err_count_r()                (0x00100e9cU)
+#define fb_mmu_fillunit_ecc_corrected_err_count_total_s()                  (16U)
+#define fb_mmu_fillunit_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define fb_mmu_fillunit_ecc_corrected_err_count_unique_s()                 (16U)
+#define fb_mmu_fillunit_ecc_corrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_fillunit_ecc_uncorrected_err_count_r()              (0x00100ea0U)
+#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_s()                (16U)
+#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define fb_mmu_fillunit_ecc_uncorrected_err_count_unique_s()               (16U)
+#define fb_mmu_fillunit_ecc_uncorrected_err_count_unique_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define fb_mmu_fillunit_ecc_address_r()                            (0x00100ea4U)
+#define fb_niso_flush_sysmem_addr_r()                              (0x00100c10U)
+#define fb_mmu_fault_buffer_lo_r(i)\
+		(nvgpu_safe_add_u32(0x00100e24U, nvgpu_safe_mult_u32((i), 20U)))
+#define fb_mmu_fault_buffer_lo_addr_f(v)            ((U32(v) & 0xfffffU) << 12U)
+#define fb_mmu_fault_buffer_hi_r(i)\
+		(nvgpu_safe_add_u32(0x00100e28U, nvgpu_safe_mult_u32((i), 20U)))
+#define fb_mmu_fault_buffer_hi_addr_f(v)          ((U32(v) & 0xffffffffU) << 0U)
+#define fb_mmu_fault_buffer_get_r(i)\
+		(nvgpu_safe_add_u32(0x00100e2cU, nvgpu_safe_mult_u32((i), 20U)))
+#define fb_mmu_fault_buffer_get_ptr_f(v)             ((U32(v) & 0xfffffU) << 0U)
+#define fb_mmu_fault_buffer_get_ptr_m()                    (U32(0xfffffU) << 0U)
+#define fb_mmu_fault_buffer_get_ptr_v(r)                (((r) >> 0U) & 0xfffffU)
+#define fb_mmu_fault_buffer_get_getptr_corrupted_m()          (U32(0x1U) << 30U)
+#define fb_mmu_fault_buffer_get_getptr_corrupted_clear_f()         (0x40000000U)
+#define fb_mmu_fault_buffer_get_overflow_m()                  (U32(0x1U) << 31U)
+#define fb_mmu_fault_buffer_get_overflow_clear_f()                 (0x80000000U)
+#define fb_mmu_fault_buffer_put_r(i)\
+		(nvgpu_safe_add_u32(0x00100e30U, nvgpu_safe_mult_u32((i), 20U)))
+#define fb_mmu_fault_buffer_put_ptr_v(r)                (((r) >> 0U) & 0xfffffU)
+#define fb_mmu_fault_buffer_size_r(i)\
+		(nvgpu_safe_add_u32(0x00100e34U, nvgpu_safe_mult_u32((i), 20U)))
+#define fb_mmu_fault_buffer_size_val_f(v)            ((U32(v) & 0xfffffU) << 0U)
+#define fb_mmu_fault_buffer_size_val_v(r)               (((r) >> 0U) & 0xfffffU)
+#define fb_mmu_fault_buffer_size_overflow_intr_enable_f()          (0x20000000U)
+#define fb_mmu_fault_buffer_size_enable_m()                   (U32(0x1U) << 31U)
+#define fb_mmu_fault_buffer_size_enable_true_f()                   (0x80000000U)
+#define fb_mmu_fault_addr_lo_r()                                   (0x00100e4cU)
+#define fb_mmu_fault_addr_lo_phys_aperture_v(r)             (((r) >> 0U) & 0x3U)
+#define fb_mmu_fault_addr_lo_addr_v(r)                 (((r) >> 12U) & 0xfffffU)
+#define fb_mmu_fault_addr_hi_r()                                   (0x00100e50U)
+#define fb_mmu_fault_addr_hi_addr_v(r)               (((r) >> 0U) & 0xffffffffU)
+#define fb_mmu_fault_inst_lo_r()                                   (0x00100e54U)
+#define fb_mmu_fault_inst_lo_engine_id_v(r)               (((r) >> 0U) & 0x1ffU)
+#define fb_mmu_fault_inst_lo_aperture_v(r)                 (((r) >> 10U) & 0x3U)
+#define fb_mmu_fault_inst_lo_addr_v(r)                 (((r) >> 12U) & 0xfffffU)
+#define fb_mmu_fault_inst_hi_r()                                   (0x00100e58U)
+#define fb_mmu_fault_inst_hi_addr_v(r)               (((r) >> 0U) & 0xffffffffU)
+#define fb_mmu_fault_info_r()                                      (0x00100e5cU)
+#define fb_mmu_fault_info_fault_type_v(r)                  (((r) >> 0U) & 0x1fU)
+#define fb_mmu_fault_info_replayable_fault_v(r)             (((r) >> 7U) & 0x1U)
+#define fb_mmu_fault_info_client_v(r)                      (((r) >> 8U) & 0x7fU)
+#define fb_mmu_fault_info_access_type_v(r)                 (((r) >> 16U) & 0xfU)
+#define fb_mmu_fault_info_client_type_v(r)                 (((r) >> 20U) & 0x1U)
+#define fb_mmu_fault_info_gpc_id_v(r)                     (((r) >> 24U) & 0x1fU)
+#define fb_mmu_fault_info_protected_mode_v(r)              (((r) >> 29U) & 0x1U)
+#define fb_mmu_fault_info_replayable_fault_en_v(r)         (((r) >> 30U) & 0x1U)
+#define fb_mmu_fault_info_valid_v(r)                       (((r) >> 31U) & 0x1U)
+#define fb_mmu_fault_status_r()                                    (0x00100e60U)
+#define fb_mmu_fault_status_dropped_bar1_phys_set_f()                     (0x1U)
+#define fb_mmu_fault_status_dropped_bar1_virt_set_f()                     (0x2U)
+#define fb_mmu_fault_status_dropped_bar2_phys_set_f()                     (0x4U)
+#define fb_mmu_fault_status_dropped_bar2_virt_set_f()                     (0x8U)
+#define fb_mmu_fault_status_dropped_ifb_phys_set_f()                     (0x10U)
+#define fb_mmu_fault_status_dropped_ifb_virt_set_f()                     (0x20U)
+#define fb_mmu_fault_status_dropped_other_phys_set_f()                   (0x40U)
+#define fb_mmu_fault_status_dropped_other_virt_set_f()                   (0x80U)
+#define fb_mmu_fault_status_replayable_m()                     (U32(0x1U) << 8U)
+#define fb_mmu_fault_status_replayable_error_m()              (U32(0x1U) << 10U)
+#define fb_mmu_fault_status_non_replayable_error_m()          (U32(0x1U) << 11U)
+#define fb_mmu_fault_status_replayable_overflow_m()           (U32(0x1U) << 12U)
+#define fb_mmu_fault_status_non_replayable_overflow_m()       (U32(0x1U) << 13U)
+#define fb_mmu_fault_status_replayable_getptr_corrupted_m()   (U32(0x1U) << 14U)
+#define fb_mmu_fault_status_non_replayable_getptr_corrupted_m()\
+				(U32(0x1U) << 15U)
+#define fb_mmu_fault_status_busy_true_f()                          (0x40000000U)
+#define fb_mmu_fault_status_valid_m()                         (U32(0x1U) << 31U)
+#define fb_mmu_fault_status_valid_set_f()                          (0x80000000U)
+#define fb_mmu_fault_status_valid_clear_f()                        (0x80000000U)
+#define fb_niso_scrub_status_r()                                   (0x00100b20U)
+#define fb_mmu_int_vector_info_fault_r()                           (0x00100ee0U)
+#define fb_mmu_int_vector_info_fault_vector_v(r)         (((r) >> 0U) & 0xffffU)
+#define fb_mmu_int_vector_ecc_error_r()                            (0x00100edcU)
+#define fb_mmu_int_vector_ecc_error_vector_v(r)          (((r) >> 0U) & 0xffffU)
+#define fb_mmu_int_vector_fault_r(i)\
+		(nvgpu_safe_add_u32(0x00100ee4U, nvgpu_safe_mult_u32((i), 4U)))
+#define fb_mmu_int_vector_fault_error_v(r)               (((r) >> 0U) & 0xffffU)
+#define fb_mmu_int_vector_fault_notify_v(r)             (((r) >> 16U) & 0xffffU)
+#define fb_mmu_num_active_ltcs_r()                                 (0x00100ec0U)
+#define fb_mmu_num_active_ltcs_count_v(r)                  (((r) >> 0U) & 0x1fU)
+#define fb_mmu_cbc_max_r()                                         (0x00100eccU)
+#define fb_mmu_cbc_max_comptagline_f(v)             ((U32(v) & 0xffffffU) << 0U)
+#define fb_mmu_cbc_max_comptagline_m()                    (U32(0xffffffU) << 0U)
+#define fb_mmu_cbc_base_r()                                        (0x00100ec4U)
+#define fb_mmu_cbc_base_address_f(v)               ((U32(v) & 0x3ffffffU) << 0U)
+#define fb_mmu_vpr_mode_r()                                        (0x001fa800U)
+#define fb_mmu_vpr_mode_fetch_v(r)                          (((r) >> 2U) & 0x1U)
+#define fb_mmu_vpr_mode_fetch_false_v()                            (0x00000000U)
+#define fb_mmu_vpr_mode_fetch_true_f()                                    (0x4U)
+#define fb_mmu_vpr_addr_lo_r()                                     (0x001fa804U)
+#define fb_mmu_vpr_addr_lo_val_v(r)                   (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_vpr_addr_lo_val_alignment_v()                       (0x0000000cU)
+#define fb_mmu_vpr_addr_hi_r()                                     (0x001fa808U)
+#define fb_mmu_vpr_addr_hi_val_v(r)                   (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_vpr_addr_hi_val_alignment_v()                       (0x0000000cU)
+#define fb_mmu_vpr_cya_lo_r()                                      (0x001fa80cU)
+#define fb_mmu_vpr_cya_hi_r()                                      (0x001fa810U)
+#define fb_mmu_wpr1_addr_lo_r()                                    (0x001fa81cU)
+#define fb_mmu_wpr1_addr_lo_val_v(r)                  (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_wpr1_addr_lo_val_alignment_v()                      (0x0000000cU)
+#define fb_mmu_wpr1_addr_hi_r()                                    (0x001fa820U)
+#define fb_mmu_wpr1_addr_hi_val_v(r)                  (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_wpr1_addr_hi_val_alignment_v()                      (0x0000000cU)
+#define fb_mmu_wpr2_addr_lo_r()                                    (0x001fa824U)
+#define fb_mmu_wpr2_addr_lo_val_v(r)                  (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_wpr2_addr_lo_val_alignment_v()                      (0x0000000cU)
+#define fb_mmu_wpr2_addr_hi_r()                                    (0x001fa828U)
+#define fb_mmu_wpr2_addr_hi_val_v(r)                  (((r) >> 4U) & 0xfffffffU)
+#define fb_mmu_wpr2_addr_hi_val_alignment_v()                      (0x0000000cU)
+#define fb_mmu_wpr_allow_read_r()                                  (0x001fa814U)
+#define fb_mmu_wpr_allow_write_r()                                 (0x001fa818U)
+#define fb_mmu_smc_eng_cfg_0_r(i)\
+		(nvgpu_safe_add_u32(0x001f94c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define fb_mmu_smc_eng_cfg_0_remote_swizid_f(v)          ((U32(v) & 0xfU) << 0U)
+#define fb_mmu_smc_eng_cfg_0_remote_swizid_m()                 (U32(0xfU) << 0U)
+#define fb_mmu_smc_eng_cfg_0_mmu_eng_veid_offset_f(v)  ((U32(v) & 0x3fU) << 16U)
+#define fb_mmu_smc_eng_cfg_0_mmu_eng_veid_offset_m()         (U32(0x3fU) << 16U)
+#define fb_mmu_smc_eng_cfg_0_veid_max_f(v)             ((U32(v) & 0x3fU) << 24U)
+#define fb_mmu_smc_eng_cfg_0_veid_max_m()                    (U32(0x3fU) << 24U)
+#define fb_mmu_smc_eng_cfg_1_r(i)\
+		(nvgpu_safe_add_u32(0x001f94e0U, nvgpu_safe_mult_u32((i), 4U)))
+#define fb_mmu_smc_eng_cfg_1_gpc_mask_f(v)            ((U32(v) & 0xffffU) << 0U)
+#define fb_mmu_smc_eng_cfg_1_gpc_mask_m()                   (U32(0xffffU) << 0U)
+#define fb_mmu_mmu_eng_id_cfg_r(i)\
+		(nvgpu_safe_add_u32(0x001f9600U, nvgpu_safe_mult_u32((i), 4U)))
+#define fb_mmu_mmu_eng_id_cfg_remote_swizid_f(v)         ((U32(v) & 0xfU) << 0U)
+#define fb_mmu_mmu_eng_id_cfg_remote_swizid_m()                (U32(0xfU) << 0U)
+#define fb_mmu_hypervisor_ctl_r()                                  (0x00100ed0U)
+#define fb_mmu_hypervisor_ctl_use_smc_veid_tables_f(v)   ((U32(v) & 0x1U) << 3U)
+#define fb_mmu_hypervisor_ctl_use_smc_veid_tables_m()          (U32(0x1U) << 3U)
+#define fb_mmu_hypervisor_ctl_use_smc_veid_tables_enable_v()       (0x00000001U)
+#define fb_mmu_hypervisor_ctl_use_smc_veid_tables_disable_v()      (0x00000000U)
+#define fb_mmu_vidmem_access_bit_r()                               (0x001fa840U)
+#define fb_mmu_vidmem_access_bit_num_range_checker_v()             (0x00000008U)
+#define fb_mmu_vidmem_access_bit_size_v(r)                  (((r) >> 0U) & 0xfU)
+#define fb_mmu_vidmem_access_bit_disable_mode_f(v)      ((U32(v) & 0x1U) << 29U)
+#define fb_mmu_vidmem_access_bit_disable_mode_m()             (U32(0x1U) << 29U)
+#define fb_mmu_vidmem_access_bit_disable_mode_clear_v()            (0x00000000U)
+#define fb_mmu_vidmem_access_bit_mode_f(v)              ((U32(v) & 0x1U) << 30U)
+#define fb_mmu_vidmem_access_bit_mode_m()                     (U32(0x1U) << 30U)
+#define fb_mmu_vidmem_access_bit_mode_access_v()                   (0x00000000U)
+#define fb_mmu_vidmem_access_bit_mode_dirty_v()                    (0x00000001U)
+#define fb_mmu_vidmem_access_bit_enable_f(v)            ((U32(v) & 0x1U) << 31U)
+#define fb_mmu_vidmem_access_bit_enable_m()                   (U32(0x1U) << 31U)
+#define fb_mmu_vidmem_access_bit_enable_false_v()                  (0x00000000U)
+#define fb_mmu_vidmem_access_bit_enable_true_v()                   (0x00000001U)
+#define fb_mmu_vidmem_access_bit_start_addr_lo_r(i)\
+		(nvgpu_safe_add_u32(0x001fa85cU, nvgpu_safe_mult_u32((i), 8U)))
+#define fb_mmu_vidmem_access_bit_start_addr_lo_granularity_f(v)\
+				((U32(v) & 0xfU) << 0U)
+#define fb_mmu_vidmem_access_bit_start_addr_lo_val_m()       (U32(0xffU) << 24U)
+#define fb_mmu_vidmem_access_bit_start_addr_hi_r(i)\
+		(nvgpu_safe_add_u32(0x001fa860U, nvgpu_safe_mult_u32((i), 8U)))
+#define fb_mmu_vidmem_access_bit_dump_r()                          (0x001fa844U)
+#define fb_mmu_vidmem_access_bit_dump_trigger_f(v)      ((U32(v) & 0x1U) << 31U)
+#define fb_mmu_vidmem_access_bit_dump_trigger_v(r)         (((r) >> 31U) & 0x1U)
+#define fb_mmu_vidmem_access_bit_dump_trigger_false_v()            (0x00000000U)
+#define fb_mmu_vidmem_access_bit_dump_trigger_true_v()             (0x00000001U)
+#define fb_mmu_vidmem_access_bit_buffer_lo_r()                     (0x001fa848U)
+#define fb_mmu_vidmem_access_bit_buffer_lo_addr_m()       (U32(0xfffffU) << 12U)
+#define fb_mmu_vidmem_access_bit_buffer_hi_r()                     (0x001fa84cU)
+#define fb_mmu_vidmem_access_bit_buffer_hi_addr_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define fb_mmu_vidmem_access_bit_buffer_size_r()                   (0x001fa850U)
+#define fb_mmu_vidmem_access_bit_buffer_size_val_f(v)\
+				((U32(v) & 0xfffffU) << 0U)
+#define fb_mmu_vidmem_access_bit_buffer_size_enable_f(v)\
+				((U32(v) & 0x1U) << 31U)
+#define fb_mmu_vidmem_access_bit_buffer_size_enable_m()       (U32(0x1U) << 31U)
+#define fb_mmu_vidmem_access_bit_buffer_size_enable_false_v()      (0x00000000U)
+#define fb_mmu_vidmem_access_bit_buffer_size_enable_true_v()       (0x00000001U)
+#define fb_mmu_vidmem_access_bit_buffer_put_r()                    (0x001fa854U)
+#define fb_mmu_vidmem_access_bit_buffer_put_ptr_v(r)    (((r) >> 0U) & 0xfffffU)
+#define fb_hshub_prg_config_r(i)\
+		(nvgpu_safe_add_u32(0x00004c7cU, nvgpu_safe_mult_u32((i), 8192U)))
+#define fb_hshub_prg_config_num_hshubs_v(r)                 (((r) >> 1U) & 0x3U)
+#define fb_hshub_num_active_ltcs_r(i)\
+		(nvgpu_safe_add_u32(0x00004c20U, nvgpu_safe_mult_u32((i), 8192U)))
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_flush_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_flush_ga10b.h
new file mode 100644
index 000000000..0aa3add42
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_flush_ga10b.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_FLUSH_GA10B_H
+#define NVGPU_HW_FLUSH_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define flush_l2_system_invalidate_r()                             (0x00070004U)
+#define flush_l2_system_invalidate_pending_v(r)             (((r) >> 0U) & 0x1U)
+#define flush_l2_system_invalidate_pending_busy_v()                (0x00000001U)
+#define flush_l2_system_invalidate_pending_busy_f()                       (0x1U)
+#define flush_l2_system_invalidate_outstanding_v(r)         (((r) >> 1U) & 0x1U)
+#define flush_l2_system_invalidate_outstanding_true_v()            (0x00000001U)
+#define flush_l2_flush_dirty_r()                                   (0x00070010U)
+#define flush_l2_flush_dirty_pending_v(r)                   (((r) >> 0U) & 0x1U)
+#define flush_l2_flush_dirty_pending_busy_v()                      (0x00000001U)
+#define flush_l2_flush_dirty_pending_busy_f()                             (0x1U)
+#define flush_l2_flush_dirty_outstanding_v(r)               (((r) >> 1U) & 0x1U)
+#define flush_l2_flush_dirty_outstanding_true_v()                  (0x00000001U)
+#define flush_l2_clean_comptags_r()                                (0x0007000cU)
+#define flush_l2_clean_comptags_pending_v(r)                (((r) >> 0U) & 0x1U)
+#define flush_l2_clean_comptags_pending_busy_v()                   (0x00000001U)
+#define flush_l2_clean_comptags_pending_busy_f()                          (0x1U)
+#define flush_l2_clean_comptags_outstanding_v(r)            (((r) >> 1U) & 0x1U)
+#define flush_l2_clean_comptags_outstanding_true_v()               (0x00000001U)
+#define flush_fb_flush_r()                                         (0x00070000U)
+#define flush_fb_flush_pending_v(r)                         (((r) >> 0U) & 0x1U)
+#define flush_fb_flush_pending_busy_v()                            (0x00000001U)
+#define flush_fb_flush_pending_busy_f()                                   (0x1U)
+#define flush_fb_flush_outstanding_v(r)                     (((r) >> 1U) & 0x1U)
+#define flush_fb_flush_outstanding_true_v()                        (0x00000001U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_func_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_func_ga10b.h
new file mode 100644
index 000000000..cdf554f51
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_func_ga10b.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_FUNC_GA10B_H
+#define NVGPU_HW_FUNC_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define func_full_phys_offset_v()                                  (0x00b80000U)
+#define func_doorbell_r()                                          (0x00030090U)
+#define func_cfg0_r()                                              (0x00030000U)
+#define func_priv_cpu_intr_top_en_set_r(i)\
+		(nvgpu_safe_add_u32(0x00001608U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_top_en_clear_r(i)\
+		(nvgpu_safe_add_u32(0x00001610U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_top_en_clear__size_1_v()                (0x00000001U)
+#define func_priv_cpu_intr_top_en_set_r(i)\
+		(nvgpu_safe_add_u32(0x00001608U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_leaf_en_set_r(i)\
+		(nvgpu_safe_add_u32(0x00001200U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_leaf_en_clear_r(i)\
+		(nvgpu_safe_add_u32(0x00001400U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_top_r(i)\
+		(nvgpu_safe_add_u32(0x00001600U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_top__size_1_v()                         (0x00000001U)
+#define func_priv_cpu_intr_leaf_r(i)\
+		(nvgpu_safe_add_u32(0x00001000U, nvgpu_safe_mult_u32((i), 4U)))
+#define func_priv_cpu_intr_leaf__size_1_v()                        (0x00000008U)
+#define func_priv_cpu_intr_pfb_vector_v()                          (0x0000008dU)
+#define func_priv_cpu_intr_pmu_vector_v()                          (0x00000098U)
+#define func_priv_cpu_intr_ltc_all_vector_v()                      (0x00000099U)
+#define func_priv_cpu_intr_pbus_vector_v()                         (0x0000009cU)
+#define func_priv_cpu_intr_priv_ring_vector_v()                    (0x0000009eU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h
new file mode 100644
index 000000000..e6798c13c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_FUSE_GA10B_H
+#define NVGPU_HW_FUSE_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define fuse_status_opt_gpc_r()                                    (0x00820c1cU)
+#define fuse_status_opt_tpc_gpc_r(i)\
+		(nvgpu_safe_add_u32(0x00820c38U, nvgpu_safe_mult_u32((i), 4U)))
+#define fuse_status_opt_rop_gpc_r(i)\
+		(nvgpu_safe_add_u32(0x00822880U, nvgpu_safe_mult_u32((i), 4U)))
+#define fuse_ctrl_opt_tpc_gpc_r(i)\
+		(nvgpu_safe_add_u32(0x00820838U, nvgpu_safe_mult_u32((i), 4U)))
+#define fuse_status_opt_fbio_r()                                   (0x00820c14U)
+#define fuse_status_opt_fbp_r()                                    (0x00820d38U)
+#define fuse_opt_ecc_en_r()                                        (0x00820228U)
+#define fuse_opt_feature_fuses_override_disable_r()                (0x008203f0U)
+#define fuse_opt_vpr_enabled_r()                                   (0x0082067cU)
+#define fuse_opt_vpr_enabled_data_v(r)                      (((r) >> 0U) & 0x1U)
+#define fuse_opt_vpr_auto_fetch_disable_r()                        (0x00820684U)
+#define fuse_opt_vpr_auto_fetch_disable_data_v(r)           (((r) >> 0U) & 0x1U)
+#define fuse_opt_wpr_enabled_r()                                   (0x008205ecU)
+#define fuse_opt_wpr_enabled_data_v(r)                      (((r) >> 0U) & 0x1U)
+#define fuse_opt_sec_debug_en_r()                                  (0x00821040U)
+#define fuse_opt_priv_sec_en_r()                                   (0x00820434U)
+#define fuse_opt_sm_ttu_en_r()                                     (0x00820168U)
+#define fuse_opt_secure_source_isolation_en_r()                    (0x00820410U)
+#define fuse_feature_override_ecc_r()                              (0x0082380cU)
+#define fuse_feature_override_ecc_sm_lrf_v(r)               (((r) >> 0U) & 0x1U)
+#define fuse_feature_override_ecc_sm_lrf_enabled_v()               (0x00000001U)
+#define fuse_feature_override_ecc_sm_lrf_override_v(r)      (((r) >> 3U) & 0x1U)
+#define fuse_feature_override_ecc_sm_lrf_override_true_v()         (0x00000001U)
+#define fuse_feature_override_ecc_sm_l1_data_v(r)           (((r) >> 4U) & 0x1U)
+#define fuse_feature_override_ecc_sm_l1_data_enabled_v()           (0x00000001U)
+#define fuse_feature_override_ecc_sm_l1_data_override_v(r)  (((r) >> 7U) & 0x1U)
+#define fuse_feature_override_ecc_sm_l1_data_override_true_v()     (0x00000001U)
+#define fuse_feature_override_ecc_sm_l1_tag_v(r)            (((r) >> 8U) & 0x1U)
+#define fuse_feature_override_ecc_sm_l1_tag_enabled_v()            (0x00000001U)
+#define fuse_feature_override_ecc_sm_l1_tag_override_v(r)  (((r) >> 11U) & 0x1U)
+#define fuse_feature_override_ecc_sm_l1_tag_override_true_v()      (0x00000001U)
+#define fuse_feature_override_ecc_ltc_v(r)                 (((r) >> 12U) & 0x1U)
+#define fuse_feature_override_ecc_ltc_enabled_v()                  (0x00000001U)
+#define fuse_feature_override_ecc_ltc_override_v(r)        (((r) >> 15U) & 0x1U)
+#define fuse_feature_override_ecc_ltc_override_true_v()            (0x00000001U)
+#define fuse_feature_override_ecc_dram_v(r)                (((r) >> 16U) & 0x1U)
+#define fuse_feature_override_ecc_dram_enabled_v()                 (0x00000001U)
+#define fuse_feature_override_ecc_dram_override_v(r)       (((r) >> 19U) & 0x1U)
+#define fuse_feature_override_ecc_dram_override_true_v()           (0x00000001U)
+#define fuse_feature_override_ecc_sm_cbu_v(r)              (((r) >> 20U) & 0x1U)
+#define fuse_feature_override_ecc_sm_cbu_enabled_v()               (0x00000001U)
+#define fuse_feature_override_ecc_sm_cbu_override_v(r)     (((r) >> 23U) & 0x1U)
+#define fuse_feature_override_ecc_sm_cbu_override_true_v()         (0x00000001U)
+#define fuse_feature_override_ecc_1_r()                            (0x00823810U)
+#define fuse_feature_override_ecc_1_sm_l0_icache_v(r)       (((r) >> 0U) & 0x1U)
+#define fuse_feature_override_ecc_1_sm_l0_icache_enabled_v()       (0x00000001U)
+#define fuse_feature_override_ecc_1_sm_l0_icache_override_v(r)\
+				(((r) >> 1U) & 0x1U)
+#define fuse_feature_override_ecc_1_sm_l0_icache_override_true_v() (0x00000001U)
+#define fuse_feature_override_ecc_1_sm_l1_icache_v(r)       (((r) >> 2U) & 0x1U)
+#define fuse_feature_override_ecc_1_sm_l1_icache_enabled_v()       (0x00000001U)
+#define fuse_feature_override_ecc_1_sm_l1_icache_override_v(r)\
+				(((r) >> 3U) & 0x1U)
+#define fuse_feature_override_ecc_1_sm_l1_icache_override_true_v() (0x00000001U)
+#define fuse_p2prx_pdi_r()                                         (0x00823000U)
+#define fuse_p2prx_pdi_loaded_v(r)                          (((r) >> 1U) & 0x1U)
+#define fuse_p2prx_pdi_loaded_true_v()                             (0x00000001U)
+#define fuse_opt_pdi_0_r()                                         (0x00820344U)
+#define fuse_opt_pdi_1_r()                                         (0x00820348U)
+#define fuse_pmu_fcd_r()                                           (0x00820b18U)
+#define fuse_gsp_fcd_r()                                           (0x00820b1cU)
+#define fuse_pmu_dcs_r()                                           (0x00820af8U)
+#define fuse_gsp_dcs_r()                                           (0x00820afcU)
+#define fuse_pmu_enen_r()                                          (0x00820a24U)
+#define fuse_gsp_enen_r()                                          (0x00820a28U)
+#define fuse_pmu_nvriscv_bre_en_r()                                (0x00820b00U)
+#define fuse_gsp_nvriscv_bre_en_r()                                (0x00820b14U)
+#define fuse_pmu_nvriscv_devd_r()                                  (0x00820b70U)
+#define fuse_gsp_nvriscv_devd_r()                                  (0x00820b10U)
+#define fuse_pmu_nvriscv_pld_r()                                   (0x00820b08U)
+#define fuse_gsp_nvriscv_pld_r()                                   (0x00820b0cU)
+#define fuse_pmu_nvriscv_sen_r()                                   (0x00820b04U)
+#define fuse_gsp_nvriscv_sen_r()                                   (0x00820a0cU)
+#define fuse_pmu_nvriscv_sa_r()                                    (0x00820a04U)
+#define fuse_gsp_nvriscv_sa_r()                                    (0x00820a14U)
+#define fuse_pmu_nvriscv_sh_r()                                    (0x00820a00U)
+#define fuse_gsp_nvriscv_sh_r()                                    (0x00820a10U)
+#define fuse_pmu_nvriscv_si_r()                                    (0x00820a08U)
+#define fuse_gsp_nvriscv_si_r()                                    (0x00820a18U)
+#define fuse_secure_pmu_dbgd_r()                                   (0x00820640U)
+#define fuse_secure_gsp_dbgd_r()                                   (0x0082074cU)
+#define fuse_pkc_pmu_algo_dis_r()                                  (0x0082073cU)
+#define fuse_pkc_gsp_algo_dis_r()                                  (0x00820754U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gmmu_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gmmu_ga10b.h
new file mode 100644
index 000000000..75cd01b59
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gmmu_ga10b.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_GMMU_GA10B_H
+#define NVGPU_HW_GMMU_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define gmmu_new_pde_aperture_video_memory_f()                            (0x2U)
+#define gmmu_new_pde_aperture_sys_mem_coh_f()                             (0x4U)
+#define gmmu_new_pde_aperture_sys_mem_ncoh_f()                            (0x6U)
+#define gmmu_new_pde_address_sys_f(v)               ((U32(v) & 0xffffffU) << 8U)
+#define gmmu_new_pde_vol_true_f()                                         (0x8U)
+#define gmmu_new_pde_address_shift_v()                             (0x0000000cU)
+#define gmmu_new_dual_pde_aperture_big_video_memory_f()                   (0x2U)
+#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f()                    (0x4U)
+#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f()                   (0x6U)
+#define gmmu_new_dual_pde_address_big_sys_f(v)     ((U32(v) & 0xfffffffU) << 4U)
+#define gmmu_new_dual_pde_aperture_small_video_memory_f()                 (0x2U)
+#define gmmu_new_dual_pde_aperture_small_sys_mem_coh_f()                  (0x4U)
+#define gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f()                 (0x6U)
+#define gmmu_new_dual_pde_vol_small_true_f()                              (0x8U)
+#define gmmu_new_dual_pde_vol_big_true_f()                                (0x8U)
+#define gmmu_new_dual_pde_address_small_sys_f(v)    ((U32(v) & 0xffffffU) << 8U)
+#define gmmu_new_dual_pde_address_shift_v()                        (0x0000000cU)
+#define gmmu_new_dual_pde_address_big_shift_v()                    (0x00000008U)
+#define gmmu_new_pte_valid_true_f()                                       (0x1U)
+#define gmmu_new_pte_valid_false_f()                                      (0x0U)
+#define gmmu_new_pte_privilege_true_f()                                  (0x20U)
+#define gmmu_new_pte_address_sys_f(v)               ((U32(v) & 0xffffffU) << 8U)
+#define gmmu_new_pte_address_vid_f(v)               ((U32(v) & 0xffffffU) << 8U)
+#define gmmu_new_pte_vol_true_f()                                         (0x8U)
+#define gmmu_new_pte_aperture_video_memory_f()                            (0x0U)
+#define gmmu_new_pte_aperture_sys_mem_coh_f()                             (0x4U)
+#define gmmu_new_pte_aperture_sys_mem_ncoh_f()                            (0x6U)
+#define gmmu_new_pte_read_only_true_f()                                  (0x40U)
+#define gmmu_new_pte_comptagline_f(v)                ((U32(v) & 0xfffffU) << 4U)
+#define gmmu_new_pte_kind_f(v)                         ((U32(v) & 0xffU) << 24U)
+#define gmmu_new_pte_address_shift_v()                             (0x0000000cU)
+#define gmmu_fault_fault_type_atomic_violation_v()                 (0x0000000fU)
+#define gmmu_fault_client_gpc_rop_3_v()                            (0x00000073U)
+#define gmmu_fault_client_hub_esc_v()                              (0x00000063U)
+#define gmmu_fault_client_type_hub_v()                             (0x00000001U)
+#define gmmu_fault_client_type_gpc_v()                             (0x00000000U)
+#define gmmu_fault_client_type_hub_v()                             (0x00000001U)
+#define gmmu_fault_type_unbound_inst_block_v()                     (0x00000004U)
+#define gmmu_fault_type_pte_v()                                    (0x00000002U)
+#define gmmu_fault_mmu_eng_id_bar2_v()                             (0x000000c0U)
+#define gmmu_fault_mmu_eng_id_physical_v()                         (0x0000001fU)
+#define gmmu_fault_mmu_eng_id_ce0_v()                              (0x0000000fU)
+#define gmmu_fault_buf_size_v()                                    (0x00000020U)
+#define gmmu_fault_buf_entry_inst_aperture_v(r)             (((r) >> 8U) & 0x3U)
+#define gmmu_fault_buf_entry_inst_lo_v(r)              (((r) >> 12U) & 0xfffffU)
+#define gmmu_fault_buf_entry_inst_lo_b()                                   (12U)
+#define gmmu_fault_buf_entry_inst_lo_w()                                    (0U)
+#define gmmu_fault_buf_entry_inst_hi_v(r)            (((r) >> 0U) & 0xffffffffU)
+#define gmmu_fault_buf_entry_inst_hi_w()                                    (1U)
+#define gmmu_fault_buf_entry_addr_phys_aperture_v(r)        (((r) >> 0U) & 0x3U)
+#define gmmu_fault_buf_entry_addr_lo_v(r)              (((r) >> 12U) & 0xfffffU)
+#define gmmu_fault_buf_entry_addr_lo_b()                                   (12U)
+#define gmmu_fault_buf_entry_addr_lo_w()                                    (2U)
+#define gmmu_fault_buf_entry_addr_hi_v(r)            (((r) >> 0U) & 0xffffffffU)
+#define gmmu_fault_buf_entry_addr_hi_w()                                    (3U)
+#define gmmu_fault_buf_entry_timestamp_lo_v(r)       (((r) >> 0U) & 0xffffffffU)
+#define gmmu_fault_buf_entry_timestamp_lo_w()                               (4U)
+#define gmmu_fault_buf_entry_timestamp_hi_v(r)       (((r) >> 0U) & 0xffffffffU)
+#define gmmu_fault_buf_entry_timestamp_hi_w()                               (5U)
+#define gmmu_fault_buf_entry_engine_id_v(r)               (((r) >> 0U) & 0x1ffU)
+#define gmmu_fault_buf_entry_engine_id_w()                                  (6U)
+#define gmmu_fault_buf_entry_fault_type_v(r)               (((r) >> 0U) & 0x1fU)
+#define gmmu_fault_buf_entry_fault_type_w()                                 (7U)
+#define gmmu_fault_buf_entry_replayable_fault_v(r)          (((r) >> 7U) & 0x1U)
+#define gmmu_fault_buf_entry_replayable_fault_true_v()             (0x00000001U)
+#define gmmu_fault_buf_entry_client_v(r)                   (((r) >> 8U) & 0x7fU)
+#define gmmu_fault_buf_entry_access_type_v(r)              (((r) >> 16U) & 0xfU)
+#define gmmu_fault_buf_entry_mmu_client_type_v(r)          (((r) >> 20U) & 0x1U)
+#define gmmu_fault_buf_entry_gpc_id_v(r)                  (((r) >> 24U) & 0x1fU)
+#define gmmu_fault_buf_entry_protected_mode_v(r)           (((r) >> 29U) & 0x1U)
+#define gmmu_fault_buf_entry_replayable_fault_en_v(r)      (((r) >> 30U) & 0x1U)
+#define gmmu_fault_buf_entry_valid_m()                        (U32(0x1U) << 31U)
+#define gmmu_fault_buf_entry_valid_v(r)                    (((r) >> 31U) & 0x1U)
+#define gmmu_fault_buf_entry_valid_w()                                      (7U)
+#define gmmu_fault_buf_entry_valid_true_v()                        (0x00000001U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
new file mode 100644
index 000000000..eff9bc3be
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
@@ -0,0 +1,1206 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_GR_GA10B_H
+#define NVGPU_HW_GR_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define gr_intr_notify_ctrl_r()                                    (0x00400160U)
+#define gr_intr_notify_ctrl_vector_f(v)                ((U32(v) & 0xfffU) << 0U)
+#define gr_intr_notify_ctrl_cpu_enable_f()                         (0x80000000U)
+#define gr_intr_notify_ctrl_gsp_enable_f()                         (0x40000000U)
+#define gr_intr_r()                                                (0x00400100U)
+#define gr_intr_notify_pending_f()                                        (0x1U)
+#define gr_intr_semaphore_pending_f()                                     (0x2U)
+#define gr_intr_illegal_method_pending_f()                               (0x10U)
+#define gr_intr_illegal_notify_pending_f()                               (0x40U)
+#define gr_intr_debug_method_pending_f()                                 (0x80U)
+#define gr_intr_firmware_method_pending_f()                             (0x100U)
+#define gr_intr_buffer_notify_pending_f()                             (0x10000U)
+#define gr_intr_fecs_error_pending_f()                                (0x80000U)
+#define gr_intr_class_error_pending_f()                              (0x100000U)
+#define gr_intr_exception_pending_f()                                (0x200000U)
+#define gr_fecs_intr_r()                                           (0x00400144U)
+#define gr_class_error_r()                                         (0x00400110U)
+#define gr_class_error_code_v(r)                         (((r) >> 0U) & 0xffffU)
+#define gr_intr_en_r()                                             (0x0040013cU)
+#define gr_intr_en_notify__prod_f()                                       (0x1U)
+#define gr_intr_en_semaphore__prod_f()                                    (0x2U)
+#define gr_intr_en_illegal_method__prod_f()                              (0x10U)
+#define gr_intr_en_illegal_notify__prod_f()                              (0x40U)
+#define gr_intr_en_debug_method__prod_f()                                (0x80U)
+#define gr_intr_en_firmware_method__prod_f()                            (0x100U)
+#define gr_intr_en_buffer_notify__prod_f()                            (0x10000U)
+#define gr_intr_en_fecs_error__prod_f()                               (0x80000U)
+#define gr_intr_en_class_error__prod_f()                             (0x100000U)
+#define gr_intr_en_exception__prod_f()                               (0x200000U)
+#define gr_intr_en_fe_debug_intr__prod_f()                           (0x400000U)
+#define gr_intr_retrigger_r()                                      (0x00400158U)
+#define gr_intr_retrigger_trigger_true_f()                                (0x1U)
+#define gr_exception_r()                                           (0x00400108U)
+#define gr_exception_gpc_m()                                  (U32(0x1U) << 24U)
+#define gr_exception_mme_fe1_m()                               (U32(0x1U) << 9U)
+#define gr_exception1_r()                                          (0x00400118U)
+#define gr_exception_en_r()                                        (0x00400138U)
+#define gr_exception_en_fe_enabled_f()                                    (0x1U)
+#define gr_exception_en_gpc_enabled_f()                             (0x1000000U)
+#define gr_exception_en_memfmt_enabled_f()                                (0x2U)
+#define gr_exception_en_ds_enabled_f()                                   (0x10U)
+#define gr_exception_en_pd_enabled_f()                                    (0x4U)
+#define gr_exception_en_scc_enabled_f()                                   (0x8U)
+#define gr_exception_en_ssync_enabled_f()                                (0x20U)
+#define gr_exception_en_mme_enabled_f()                                  (0x80U)
+#define gr_exception_en_sked_enabled_f()                                (0x100U)
+#define gr_exception_en_mme_fe1_enabled_f()                             (0x200U)
+#define gr_exception1_en_r()                                       (0x00400130U)
+#define gr_gpfifo_ctl_r()                                          (0x00400500U)
+#define gr_gpfifo_ctl_access_f(v)                        ((U32(v) & 0x1U) << 0U)
+#define gr_gpfifo_ctl_access_enabled_f()                                  (0x1U)
+#define gr_gpfifo_ctl_semaphore_access_f(v)             ((U32(v) & 0x1U) << 16U)
+#define gr_gpfifo_ctl_semaphore_access_enabled_f()                    (0x10000U)
+#define gr_gpfifo_status_r()                                       (0x00400504U)
+#define gr_trapped_addr_r()                                        (0x00400704U)
+#define gr_trapped_addr_mthd_v(r)                         (((r) >> 2U) & 0xfffU)
+#define gr_trapped_addr_subch_v(r)                         (((r) >> 16U) & 0x7U)
+#define gr_trapped_addr_mme_generated_v(r)                 (((r) >> 20U) & 0x1U)
+#define gr_trapped_addr_datahigh_v(r)                      (((r) >> 24U) & 0x1U)
+#define gr_trapped_addr_priv_v(r)                          (((r) >> 28U) & 0x1U)
+#define gr_trapped_data_lo_r()                                     (0x00400708U)
+#define gr_trapped_data_hi_r()                                     (0x0040070cU)
+#define gr_trapped_data_mme_r()                                    (0x00400710U)
+#define gr_trapped_data_mme_pc_v(r)                       (((r) >> 0U) & 0xfffU)
+#define gr_status_r()                                              (0x00400700U)
+#define gr_status_state_v(r)                                (((r) >> 0U) & 0x1U)
+#define gr_status_state_busy_v()                                   (0x00000001U)
+#define gr_status_fe_method_upper_v(r)                      (((r) >> 1U) & 0x1U)
+#define gr_status_fe_method_upper_busy_v()                         (0x00000001U)
+#define gr_status_fe_method_lower_v(r)                      (((r) >> 2U) & 0x1U)
+#define gr_status_fe_method_lower_busy_v()                         (0x00000001U)
+#define gr_status_1_r()                                            (0x00400604U)
+#define gr_engine_config_r()                                       (0x00400614U)
+#define gr_engine_config_supported_3d_true_f()                            (0x1U)
+#define gr_engine_config_supported_compute_true_f()                       (0x2U)
+#define gr_engine_config_supported_i2m_true_f()                           (0x4U)
+#define gr_engine_config_supported_2d_true_f()                            (0x8U)
+#define gr_engine_status_r()                                       (0x0040060cU)
+#define gr_pri_gpc0_gpccs_gpc_exception_r()                        (0x00502c90U)
+#define gr_pri_gpc0_gpccs_gpc_exception_en_r()                     (0x00502c94U)
+#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_r()                   (0x00504508U)
+#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r()                (0x0050450cU)
+#define gr_activity_0_r()                                          (0x00400380U)
+#define gr_activity_1_r()                                          (0x00400384U)
+#define gr_activity_1_memfmt_b()                                            (6U)
+#define gr_activity_4_r()                                          (0x00400390U)
+#define gr_activity_4_gpc0_s()                                              (3U)
+#define gr_activity_4_gpc0_v(r)                             (((r) >> 0U) & 0x7U)
+#define gr_activity_4_gpc0_empty_v()                               (0x00000000U)
+#define gr_activity_4_gpc0_preempted_v()                           (0x00000004U)
+#define gr_pri_sked_activity_r()                                   (0x00407054U)
+#define gr_pri_gpc0_gpccs_gpc_activity0_r()                        (0x00502c80U)
+#define gr_pri_gpc0_gpccs_gpc_activity1_r()                        (0x00502c84U)
+#define gr_pri_gpc0_gpccs_gpc_activity2_r()                        (0x00502c88U)
+#define gr_pri_gpc0_gpccs_gpc_activity3_r()                        (0x00502c8cU)
+#define gr_pri_gpc0_gpccs_gpc_activity4_r()                        (0x00502c9cU)
+#define gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r()                  (0x00504500U)
+#define gr_pri_gpcs_gpccs_gpc_activity_0_r()                       (0x0041ac80U)
+#define gr_pri_gpcs_gpccs_gpc_activity_1_r()                       (0x0041ac84U)
+#define gr_pri_gpcs_gpccs_gpc_activity_2_r()                       (0x0041ac88U)
+#define gr_pri_gpcs_gpccs_gpc_activity_3_r()                       (0x0041ac8cU)
+#define gr_pri_gpcs_gpccs_gpc_activity_4_r()                       (0x0041ac9cU)
+#define gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r()                  (0x00419d00U)
+#define gr_pri_ds_mpipe_status_r()                                 (0x00405858U)
+#define gr_pri_fe_go_idle_info_r()                                 (0x00404194U)
+#define gr_pri_fe_chip_def_info_r()                                (0x00404030U)
+#define gr_pri_fe_chip_def_info_max_veid_count_init_v()            (0x00000040U)
+#define gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r()             (0x00504238U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r()                     (0x00504358U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m()\
+				(U32(0x1U) << 0U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m()\
+				(U32(0x1U) << 1U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m()\
+				(U32(0x1U) << 3U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m()\
+				(U32(0x1U) << 8U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m()\
+				(U32(0x1U) << 9U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m()\
+				(U32(0x1U) << 10U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m()\
+				(U32(0x1U) << 11U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 24U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 26U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f()          (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r()        (0x0050435cU)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r()      (0x00504360U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s()        (16U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r()                 (0x0050436cU)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 8U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 10U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m()\
+				(U32(0x1U) << 0U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f()      (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r()    (0x00504370U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r()  (0x00504374U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s()    (16U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r()                     (0x00504638U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m()\
+				(U32(0x1U) << 0U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m()\
+				(U32(0x1U) << 4U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m()\
+				(U32(0x1U) << 6U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 16U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 18U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f()          (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r()        (0x0050463cU)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r()      (0x00504640U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s()        (16U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r()                  (0x00504624U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m()\
+				(U32(0x1U) << 0U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m()\
+				(U32(0x1U) << 4U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m()\
+				(U32(0x1U) << 5U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m()\
+				(U32(0x1U) << 6U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m()\
+				(U32(0x1U) << 7U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 8U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 10U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f()       (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r()     (0x00504628U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s()       (16U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r()   (0x0050462cU)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s()     (16U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_r()                  (0x0050464cU)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 16U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 18U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m()\
+				(U32(0x1U) << 6U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f()       (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r()     (0x00504650U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s()       (16U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r()   (0x00504654U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s()     (16U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_r()                    (0x00504388U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 24U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 26U) & 0x1U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_l0ic_data_m()\
+				(U32(0x1U) << 0U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_l0ic_data_m()\
+				(U32(0x1U) << 8U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_l0ic_predecode_m()\
+				(U32(0x1U) << 1U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_l0ic_predecode_m()\
+				(U32(0x1U) << 9U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_corrected_err_urf_data_m()\
+				(U32(0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_uncorrected_err_urf_data_m()\
+				(U32(0x1U) << 10U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_status_reset_task_f()         (0x40000000U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_corrected_err_count_r()       (0x0050438cU)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_corrected_err_count_total_s()         (16U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_uncorrected_err_count_r()     (0x00504390U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_uncorrected_err_count_total_s()       (16U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_r()                    (0x00419b54U)
+#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_task_f()         (0x1U)
+#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_task_f()         (0x2U)
+#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_task_f()         (0x4U)
+#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_task_f()         (0x8U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_r()                    (0x00504354U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 9U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_init_f()         (0x0U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_init_f()         (0x0U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_init_f()         (0x0U)
+#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_init_f()         (0x0U)
+#define gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_r()                (0x00419b68U)
+#define gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_task_f()      (0x1U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_r()                (0x00504368U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 3U)
+#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_init_f()      (0x0U)
+#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_r()                 (0x00419e20U)
+#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_task_f()       (0x1U)
+#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_pixprf_task_f()     (0x10U)
+#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_miss_fifo_task_f()  (0x20U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r()                 (0x00504620U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_inject_corrected_err_f(v)\
+				((U32(v) & 0x1U) << 2U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 3U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_pixprf_init_f()      (0x0U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_miss_fifo_init_f()   (0x0U)
+#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_init_f()       (0x0U)
+#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_r()                    (0x00419e34U)
+#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_task_f()       (0x1U)
+#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_task_f()    (0x4U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_r()                    (0x00504634U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 5U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_init_f()       (0x0U)
+#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_init_f()    (0x0U)
+#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_r()                 (0x00419e48U)
+#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_task_f()     (0x4U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_r()                 (0x00504648U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 5U)
+#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_init_f()     (0x0U)
+#define gr_pri_gpcs_tpcs_sm_rams_ecc_control_r()                   (0x00419b84U)
+#define gr_pri_gpcs_tpcs_sm_rams_ecc_control_scrub_l0ic_data_task_f()     (0x1U)
+#define gr_pri_gpcs_tpcs_sm_rams_ecc_control_scrub_l0ic_predecode_task_f()\
+				(0x2U)
+#define gr_pri_gpcs_tpcs_sm_rams_ecc_control_scrub_urf_data_task_f()      (0x4U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_control_r()                   (0x00504384U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_control_scrub_l0ic_data_init_f()     (0x0U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_control_scrub_l0ic_predecode_init_f()\
+				(0x0U)
+#define gr_pri_gpc0_tpc0_sm_rams_ecc_control_scrub_urf_data_init_f()      (0x0U)
+#define gr_pri_gpc0_tpc0_tex_m_routing_r()                         (0x005042c4U)
+#define gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()                    (0x0U)
+#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()                      (0x1U)
+#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()                      (0x2U)
+#define gr_pipe_bundle_address_r()                                 (0x00400200U)
+#define gr_pipe_bundle_address_value_v(r)                (((r) >> 0U) & 0xffffU)
+#define gr_pipe_bundle_address_veid_f(v)               ((U32(v) & 0x3fU) << 20U)
+#define gr_pipe_bundle_data_r()                                    (0x00400204U)
+#define gr_pipe_bundle_data_hi_r()                                 (0x0040020cU)
+#define gr_pipe_bundle_config_r()                                  (0x00400208U)
+#define gr_pipe_bundle_config_override_pipe_mode_disabled_f()             (0x0U)
+#define gr_pipe_bundle_config_override_pipe_mode_enabled_f()       (0x80000000U)
+#define gr_gpc0_tpc0_mpc_hww_esr_r()                               (0x00504430U)
+#define gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f()                 (0x40000000U)
+#define gr_gpc0_tpc0_mpc_hww_esr_info_r()                          (0x00504434U)
+#define gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(r)            (((r) >> 0U) & 0x3fU)
+#define gr_gpc0_tpc0_pe_hww_esr_r()                                (0x00504084U)
+#define gr_gpc0_tpc0_pe_hww_esr_reset_task_f()                     (0x40000000U)
+#define gr_gpc0_prop_hww_esr_r()                                   (0x00500420U)
+#define gr_gpc0_prop_hww_esr_reset_active_f()                      (0x40000000U)
+#define gr_gpc0_prop_hww_esr_coord_r()                             (0x00500434U)
+#define gr_gpc0_prop_hww_esr_format_r()                            (0x00500438U)
+#define gr_gpc0_prop_hww_esr_state_r()                             (0x0050043cU)
+#define gr_gpc0_prop_hww_esr_state2_r()                            (0x00500440U)
+#define gr_gpc0_prop_hww_esr_offset_r()                            (0x00500444U)
+#define gr_gpc0_zcull_hww_esr_r()                                  (0x00500900U)
+#define gr_gpc0_zcull_hww_esr_reset_active_f()                     (0x40000000U)
+#define gr_gpc0_setup_hww_esr_r()                                  (0x00500824U)
+#define gr_gpc0_setup_hww_esr_reset_active_f()                     (0x40000000U)
+#define gr_gpc0_ppc0_pes_hww_esr_r()                               (0x00503038U)
+#define gr_gpc0_ppc0_pes_hww_esr_reset_task_f()                    (0x40000000U)
+#define gr_gpc0_gpccs_hww_esr_r()                                  (0x00502c98U)
+#define gr_gpc0_gpccs_hww_esr_ecc_corrected_m()                (U32(0x1U) << 0U)
+#define gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m()              (U32(0x1U) << 1U)
+#define gr_gpccs_falcon_ecc_control_r()                            (0x0050268cU)
+#define gr_gpccs_falcon_ecc_control_inject_corrected_err_f(v)\
+				((U32(v) & 0x1U) << 0U)
+#define gr_gpccs_falcon_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 1U)
+#define gr_fe_hww_esr_r()                                          (0x00404000U)
+#define gr_fe_hww_esr_reset_active_f()                             (0x40000000U)
+#define gr_fe_hww_esr_en_enable_f()                                (0x80000000U)
+#define gr_mme_fe1_hww_esr_r()                                     (0x0040a790U)
+#define gr_mme_fe1_hww_esr_reset_active_f()                        (0x40000000U)
+#define gr_mme_fe1_hww_esr_en_enable_f()                           (0x80000000U)
+#define gr_mme_fe1_hww_esr_info_r()                                (0x0040a794U)
+#define gr_mme_fe1_hww_esr_info_mthd_r()                           (0x0040a7a0U)
+#define gr_mme_fe1_hww_esr_info_mthd2_r()                          (0x0040a7bcU)
+#define gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r()            (0x00419eacU)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r()            (0x0050472cU)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()\
+				(0x4U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f()   (0x10U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f() (0x20U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f()\
+				(0x40U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f()\
+				(0x100U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_poison_data_report_f()\
+				(0x1000U)
+#define gr_gpcs_tpcs_sms_hww_global_esr_r()                        (0x00419eb4U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_r()                        (0x00504734U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()              (0x10U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f()            (0x20U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f() (0x40U)
+#define gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f()  (0x4U)
+#define gr_fe_go_idle_timeout_r()                                  (0x00404154U)
+#define gr_fe_go_idle_timeout_count_disabled_f()                          (0x0U)
+#define gr_fe_go_idle_timeout_count_prod_f()                           (0x1800U)
+#define gr_fe_compute_go_idle_timeout_r()                          (0x00404160U)
+#define gr_fe_compute_go_idle_timeout_count_disabled_f()                  (0x0U)
+#define gr_fe_compute_go_idle_timeout_count_init_f()                     (0x40U)
+#define gr_fe_object_table_r(i)\
+		(nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_fe_object_table_nvclass_v(r)                  (((r) >> 0U) & 0xffffU)
+#define gr_fe_tpc_fs_r(i)\
+		(nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_pri_mme_shadow_ram_index_r()                            (0x00404488U)
+#define gr_pri_mme_shadow_ram_index_write_trigger_f()              (0x80000000U)
+#define gr_pri_mme_shadow_ram_data_r()                             (0x0040448cU)
+#define gr_mme_hww_esr_r()                                         (0x00404490U)
+#define gr_mme_hww_esr_reset_active_f()                            (0x40000000U)
+#define gr_mme_hww_esr_en_enable_f()                               (0x80000000U)
+#define gr_memfmt_hww_esr_r()                                      (0x00404600U)
+#define gr_memfmt_hww_esr_reset_active_f()                         (0x40000000U)
+#define gr_memfmt_hww_esr_en_enable_f()                            (0x80000000U)
+#define gr_fecs_cpuctl_r()                                         (0x00409100U)
+#define gr_fecs_cpuctl_startcpu_f(v)                     ((U32(v) & 0x1U) << 1U)
+#define gr_fecs_cpuctl_alias_r()                                   (0x00409130U)
+#define gr_fecs_dmactl_r()                                         (0x0040910cU)
+#define gr_fecs_dmactl_require_ctx_f(v)                  ((U32(v) & 0x1U) << 0U)
+#define gr_fecs_dmactl_dmem_scrubbing_m()                      (U32(0x1U) << 1U)
+#define gr_fecs_dmactl_imem_scrubbing_m()                      (U32(0x1U) << 2U)
+#define gr_fecs_mailbox0_r()                                       (0x00409040U)
+#define gr_fecs_mailbox1_r()                                       (0x00409044U)
+#define gr_fecs_imemc_r(i)\
+		(nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_fecs_imemc_offs_f(v)                         ((U32(v) & 0x3fU) << 2U)
+#define gr_fecs_imemc_blk_f(v)                        ((U32(v) & 0xffffU) << 8U)
+#define gr_fecs_imemc_aincw_f(v)                        ((U32(v) & 0x1U) << 24U)
+#define gr_fecs_imemd_r(i)\
+		(nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_fecs_imemt_r(i)\
+		(nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_fecs_imemt_tag_f(v)                        ((U32(v) & 0xffffU) << 0U)
+#define gr_fecs_dmemc_r(i)\
+		(nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U)))
+#define gr_fecs_dmemc_offs_f(v)                         ((U32(v) & 0x3fU) << 2U)
+#define gr_fecs_dmemc_blk_f(v)                        ((U32(v) & 0xffffU) << 8U)
+#define gr_fecs_dmemc_aincw_f(v)                        ((U32(v) & 0x1U) << 24U)
+#define gr_fecs_dmemd_r(i)\
+		(nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U)))
+#define gr_fecs_dmatrfbase_r()                                     (0x00409110U)
+#define gr_fecs_dmatrfmoffs_r()                                    (0x00409114U)
+#define gr_fecs_dmatrffboffs_r()                                   (0x0040911cU)
+#define gr_fecs_dmatrfcmd_r()                                      (0x00409118U)
+#define gr_fecs_dmatrfcmd_imem_f(v)                      ((U32(v) & 0x1U) << 4U)
+#define gr_fecs_dmatrfcmd_write_f(v)                     ((U32(v) & 0x1U) << 5U)
+#define gr_fecs_dmatrfcmd_size_f(v)                      ((U32(v) & 0x7U) << 8U)
+#define gr_fecs_dmatrfcmd_ctxdma_f(v)                   ((U32(v) & 0x7U) << 12U)
+#define gr_fecs_bootvec_r()                                        (0x00409104U)
+#define gr_fecs_bootvec_vec_f(v)                  ((U32(v) & 0xffffffffU) << 0U)
+#define gr_fecs_irqsset_r()                                        (0x00409000U)
+#define gr_fecs_falcon_hwcfg_r()                                   (0x00409108U)
+#define gr_gpcs_gpccs_irqsset_r()                                  (0x0041a000U)
+#define gr_gpcs_gpccs_falcon_hwcfg_r()                             (0x0041a108U)
+#define gr_fecs_current_ctx_r()                                    (0x00409b00U)
+#define gr_fecs_current_ctx_ptr_f(v)               ((U32(v) & 0xfffffffU) << 0U)
+#define gr_fecs_current_ctx_ptr_v(r)                  (((r) >> 0U) & 0xfffffffU)
+#define gr_fecs_current_ctx_target_vid_mem_f()                            (0x0U)
+#define gr_fecs_current_ctx_target_sys_mem_coh_f()                 (0x20000000U)
+#define gr_fecs_current_ctx_target_sys_mem_ncoh_f()                (0x30000000U)
+#define gr_fecs_current_ctx_valid_f(v)                  ((U32(v) & 0x1U) << 31U)
+#define gr_fecs_current_ctx_valid_false_f()                               (0x0U)
+#define gr_fecs_method_data_r()                                    (0x00409500U)
+#define gr_fecs_method_push_r()                                    (0x00409504U)
+#define gr_fecs_method_push_adr_f(v)                   ((U32(v) & 0xfffU) << 0U)
+#define gr_fecs_method_push_adr_bind_pointer_v()                   (0x00000003U)
+#define gr_fecs_method_push_adr_discover_image_size_v()            (0x00000010U)
+#define gr_fecs_method_push_adr_wfi_golden_save_v()                (0x00000009U)
+#define gr_fecs_method_push_adr_discover_zcull_image_size_v()      (0x00000016U)
+#define gr_fecs_method_push_adr_discover_pm_image_size_v()         (0x00000025U)
+#define gr_fecs_method_push_adr_discover_reglist_image_size_v()    (0x00000030U)
+#define gr_fecs_method_push_adr_set_reglist_bind_instance_v()      (0x00000031U)
+#define gr_fecs_method_push_adr_set_reglist_virtual_address_v()    (0x00000032U)
+#define gr_fecs_method_push_adr_stop_ctxsw_v()                     (0x00000038U)
+#define gr_fecs_method_push_adr_start_ctxsw_v()                    (0x00000039U)
+#define gr_fecs_method_push_adr_set_watchdog_timeout_f()                 (0x21U)
+#define gr_fecs_method_push_adr_discover_preemption_image_size_v() (0x0000001aU)
+#define gr_fecs_method_push_adr_halt_pipeline_v()                  (0x00000004U)
+#define gr_fecs_method_push_adr_configure_interrupt_completion_option_v()\
+				(0x0000003aU)
+#define gr_fecs_method_push_adr_smpc_global_mode_start_v()         (0x00000069U)
+#define gr_fecs_method_push_adr_smpc_global_mode_stop_v()          (0x0000006aU)
+#define gr_fecs_host_int_status_r()                                (0x00409c18U)
+#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) ((U32(v) & 0x1U) << 16U)
+#define gr_fecs_host_int_status_umimp_firmware_method_f(v)\
+				((U32(v) & 0x1U) << 17U)
+#define gr_fecs_host_int_status_watchdog_active_f()                   (0x80000U)
+#define gr_fecs_host_int_status_ctxsw_intr_f(v)       ((U32(v) & 0xffffU) << 0U)
+#define gr_fecs_host_int_status_ecc_corrected_m()             (U32(0x1U) << 21U)
+#define gr_fecs_host_int_status_ecc_uncorrected_m()           (U32(0x1U) << 22U)
+#define gr_fecs_host_int_clear_r()                                 (0x00409c20U)
+#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f()                      (0x2U)
+#define gr_fecs_host_int_enable_r()                                (0x00409c24U)
+#define gr_fecs_host_int_enable_ctxsw_intr0_enable_f()                    (0x1U)
+#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f()                    (0x2U)
+#define gr_fecs_host_int_enable_fault_during_ctxsw_enable_f()         (0x10000U)
+#define gr_fecs_host_int_enable_umimp_firmware_method_enable_f()      (0x20000U)
+#define gr_fecs_host_int_enable_umimp_illegal_method_enable_f()       (0x40000U)
+#define gr_fecs_host_int_enable_watchdog_enable_f()                   (0x80000U)
+#define gr_fecs_host_int_enable_flush_when_busy_enable_f()           (0x100000U)
+#define gr_fecs_host_int_enable_ecc_corrected_enable_f()             (0x200000U)
+#define gr_fecs_host_int_enable_ecc_uncorrected_enable_f()           (0x400000U)
+#define gr_fecs_ctxsw_reset_ctl_r()                                (0x00409614U)
+#define gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f()                     (0x0U)
+#define gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f()            (0x10U)
+#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f()             (0x0U)
+#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f()          (0x100U)
+#define gr_gpccs_ctxsw_reset_ctl_r()                               (0x0041a614U)
+#define gr_gpccs_ctxsw_reset_ctl_gpc_halt_disabled_f()                    (0x0U)
+#define gr_gpccs_ctxsw_reset_ctl_gpc_reset_disabled_f()                  (0x20U)
+#define gr_gpccs_ctxsw_reset_ctl_gpc_context_reset_disabled_f()         (0x200U)
+#define gr_gpccs_ctxsw_reset_ctl_gpc_context_reset_enabled_f()            (0x0U)
+#define gr_gpccs_ctxsw_reset_ctl_zcull_reset_disabled_f()               (0x800U)
+#define gr_gpccs_ctxsw_reset_ctl_zcull_reset_enabled_f()                  (0x0U)
+#define gr_fecs_ctx_state_store_major_rev_id_r()                   (0x0040960cU)
+#define gr_fecs_ctxsw_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_fecs_ctxsw_mailbox__size_1_v()                          (0x00000012U)
+#define gr_fecs_ctxsw_mailbox_value_f(v)          ((U32(v) & 0xffffffffU) << 0U)
+#define gr_fecs_ctxsw_mailbox_value_pass_v()                       (0x00000001U)
+#define gr_fecs_ctxsw_mailbox_value_fail_v()                       (0x00000002U)
+#define gr_fecs_ctxsw_mailbox_value_ctxsw_checksum_mismatch_v()    (0x00000021U)
+#define gr_fecs_ctxsw_func_tracing_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_fecs_ctxsw_func_tracing_mailbox__size_1_v()             (0x00000006U)
+#define gr_fecs_cfg_r()                                            (0x00409620U)
+#define gr_fecs_cfg_imem_sz_v(r)                           (((r) >> 0U) & 0xffU)
+#define gr_fecs_ctxsw_status_1_r()                                 (0x00409400U)
+#define gr_fecs_new_ctx_r()                                        (0x00409b04U)
+#define gr_fecs_ctxsw_status_fe_0_r()                              (0x00409c00U)
+#define gr_gpc0_gpccs_ctxsw_status_gpc_0_r()                       (0x00502c04U)
+#define gr_gpc0_gpccs_ctxsw_status_1_r()                           (0x00502400U)
+#define gr_fecs_ctxsw_idlestate_r()                                (0x00409420U)
+#define gr_gpc0_gpccs_ctxsw_idlestate_r()                          (0x00502420U)
+#define gr_rstr2d_gpc_map_r(i)\
+		(nvgpu_safe_add_u32(0x0040780cU, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_rstr2d_map_table_cfg_r()                                (0x004078bcU)
+#define gr_rstr2d_map_table_cfg_row_offset_f(v)         ((U32(v) & 0xffU) << 0U)
+#define gr_rstr2d_map_table_cfg_num_entries_f(v)        ((U32(v) & 0xffU) << 8U)
+#define gr_pd_hww_esr_r()                                          (0x00406018U)
+#define gr_pd_hww_esr_reset_active_f()                             (0x40000000U)
+#define gr_pd_hww_esr_en_enable_f()                                (0x80000000U)
+#define gr_pd_num_tpc_per_gpc_r(i)\
+		(nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_pd_num_tpc_per_gpc__size_1_v()                          (0x00000004U)
+#define gr_pd_num_tpc_per_gpc_count0_f(v)                ((U32(v) & 0xfU) << 0U)
+#define gr_pd_num_tpc_per_gpc_count1_f(v)                ((U32(v) & 0xfU) << 4U)
+#define gr_pd_num_tpc_per_gpc_count2_f(v)                ((U32(v) & 0xfU) << 8U)
+#define gr_pd_num_tpc_per_gpc_count3_f(v)               ((U32(v) & 0xfU) << 12U)
+#define gr_pd_num_tpc_per_gpc_count4_f(v)               ((U32(v) & 0xfU) << 16U)
+#define gr_pd_num_tpc_per_gpc_count5_f(v)               ((U32(v) & 0xfU) << 20U)
+#define gr_pd_num_tpc_per_gpc_count6_f(v)               ((U32(v) & 0xfU) << 24U)
+#define gr_pd_num_tpc_per_gpc_count7_f(v)               ((U32(v) & 0xfU) << 28U)
+#define gr_pd_ab_dist_cfg0_r()                                     (0x004064c0U)
+#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f()                 (0x80000000U)
+#define gr_pd_ab_dist_cfg1_r()                                     (0x004064c4U)
+#define gr_pd_ab_dist_cfg1_max_batches_init_f()                        (0xffffU)
+#define gr_pd_ab_dist_cfg1_max_output_f(v)           ((U32(v) & 0xffffU) << 16U)
+#define gr_pd_ab_dist_cfg1_max_output_granularity_v()              (0x00000080U)
+#define gr_pd_ab_dist_cfg2_r()                                     (0x004064c8U)
+#define gr_pd_ab_dist_cfg2_token_limit_f(v)           ((U32(v) & 0x3fffU) << 0U)
+#define gr_pd_ab_dist_cfg2_token_limit_init_v()                    (0x00000480U)
+#define gr_pd_ab_dist_cfg2_state_limit_f(v)          ((U32(v) & 0x3fffU) << 16U)
+#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v()  (0x00000020U)
+#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v()     (0x00000480U)
+#define gr_pd_dist_skip_table_r(i)\
+		(nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_pd_dist_skip_table__size_1_v()                          (0x00000008U)
+#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v)         ((U32(v) & 0xffU) << 0U)
+#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v)         ((U32(v) & 0xffU) << 8U)
+#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v)        ((U32(v) & 0xffU) << 16U)
+#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v)        ((U32(v) & 0xffU) << 24U)
+#define gr_ds_tga_constraintlogic_beta_r()                         (0x00405830U)
+#define gr_ds_tga_constraintlogic_beta_cbsize_f(v)  ((U32(v) & 0x3fffffU) << 0U)
+#define gr_ds_tga_constraintlogic_alpha_r()                        (0x0040585cU)
+#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v)   ((U32(v) & 0xffffU) << 0U)
+#define gr_ds_hww_esr_r()                                          (0x00405840U)
+#define gr_ds_hww_esr_reset_task_f()                               (0x40000000U)
+#define gr_ds_hww_esr_en_enabled_f()                               (0x80000000U)
+#define gr_ds_num_tpc_per_gpc_r(i)\
+		(nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_scc_bundle_cb_base_r()                                  (0x00408004U)
+#define gr_scc_bundle_cb_base_addr_39_8_f(v)      ((U32(v) & 0xffffffffU) << 0U)
+#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v()             (0x00000008U)
+#define gr_scc_bundle_cb_size_r()                                  (0x00408008U)
+#define gr_scc_bundle_cb_size_div_256b_f(v)            ((U32(v) & 0x7ffU) << 0U)
+#define gr_scc_bundle_cb_size_div_256b__prod_v()                   (0x00000030U)
+#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v()        (0x00000100U)
+#define gr_scc_bundle_cb_size_valid_true_f()                       (0x80000000U)
+#define gr_scc_pagepool_base_r()                                   (0x0040800cU)
+#define gr_scc_pagepool_base_addr_39_8_f(v)       ((U32(v) & 0xffffffffU) << 0U)
+#define gr_scc_pagepool_base_addr_39_8_align_bits_v()              (0x00000008U)
+#define gr_scc_pagepool_r()                                        (0x00408010U)
+#define gr_scc_pagepool_total_pages_f(v)               ((U32(v) & 0x3ffU) << 0U)
+#define gr_scc_pagepool_total_pages_hwmax_v()                      (0x00000000U)
+#define gr_scc_pagepool_total_pages_hwmax_value_v()                (0x00000200U)
+#define gr_scc_pagepool_total_pages_byte_granularity_v()           (0x00000100U)
+#define gr_scc_pagepool_valid_true_f()                             (0x80000000U)
+#define gr_scc_rm_rtv_cb_base_r()                                  (0x00408070U)
+#define gr_scc_rm_rtv_cb_base_addr_39_8_f(v)      ((U32(v) & 0xffffffffU) << 0U)
+#define gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f()                    (0x8U)
+#define gr_scc_rm_rtv_cb_size_r()                                  (0x00408074U)
+#define gr_scc_rm_rtv_cb_size_div_256b_f(v)           ((U32(v) & 0x7fffU) << 0U)
+#define gr_scc_rm_rtv_cb_size_div_256b_byte_granularity_v()        (0x00000100U)
+#define gr_scc_rm_rtv_cb_size_div_256b_default_f()                      (0x800U)
+#define gr_scc_rm_rtv_cb_size_div_256b_db_adder_f()                       (0x0U)
+#define gr_scc_rm_rtv_cb_size_div_256b_gfxp_adder_f()                    (0x20U)
+#define gr_gpcs_gcc_rm_rtv_cb_base_r()                             (0x00419034U)
+#define gr_gpcs_gcc_rm_rtv_cb_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
+#define gr_scc_rm_gfxp_reserve_r()                                 (0x00408078U)
+#define gr_scc_rm_gfxp_reserve_rtv_cb_size_div_256b_f(v)\
+				((U32(v) & 0x1ffU) << 0U)
+#define gr_scc_hww_esr_r()                                         (0x00408030U)
+#define gr_scc_hww_esr_reset_active_f()                            (0x40000000U)
+#define gr_scc_hww_esr_en_enable_f()                               (0x80000000U)
+#define gr_ssync_hww_esr_r()                                       (0x00405a14U)
+#define gr_ssync_hww_esr_reset_active_f()                          (0x40000000U)
+#define gr_ssync_hww_esr_en_enable_f()                             (0x80000000U)
+#define gr_sked_hww_esr_en_r()                                     (0x00407024U)
+#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m()\
+				(U32(0x1U) << 25U)
+#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f()   (0x0U)
+#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f()\
+				(0x2000000U)
+#define gr_cwd_fs_r()                                              (0x00405b00U)
+#define gr_cwd_fs_num_gpcs_f(v)                         ((U32(v) & 0xffU) << 0U)
+#define gr_cwd_fs_num_tpcs_f(v)                         ((U32(v) & 0xffU) << 8U)
+#define gr_cwd_gpc_tpc_id_r(i)\
+		(nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_cwd_gpc_tpc_id_tpc0_s()                                          (4U)
+#define gr_cwd_gpc_tpc_id_tpc0_f(v)                      ((U32(v) & 0xfU) << 0U)
+#define gr_cwd_gpc_tpc_id_gpc0_s()                                          (4U)
+#define gr_cwd_gpc_tpc_id_gpc0_f(v)                      ((U32(v) & 0xfU) << 4U)
+#define gr_cwd_sm_id_r(i)\
+		(nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_cwd_sm_id__size_1_v()                                   (0x00000010U)
+#define gr_gpc0_fs_gpc_r()                                         (0x00502608U)
+#define gr_gpc0_fs_gpc_num_available_tpcs_v(r)             (((r) >> 0U) & 0x1fU)
+#define gr_gpc0_fs_gpc_num_available_zculls_v(r)          (((r) >> 16U) & 0x1fU)
+#define gr_gpc0_cfg_r()                                            (0x00502620U)
+#define gr_gpc0_cfg_imem_sz_v(r)                           (((r) >> 0U) & 0xffU)
+#define gr_gpc0_zcull_fs_r()                                       (0x00500910U)
+#define gr_gpc0_zcull_fs_num_sms_f(v)                  ((U32(v) & 0x1ffU) << 0U)
+#define gr_gpc0_zcull_fs_num_active_banks_f(v)          ((U32(v) & 0xfU) << 16U)
+#define gr_gpc0_zcull_ram_addr_r()                                 (0x00500914U)
+#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\
+				((U32(v) & 0xfU) << 0U)
+#define gr_gpc0_zcull_ram_addr_row_offset_f(v)           ((U32(v) & 0xfU) << 8U)
+#define gr_gpc0_zcull_sm_num_rcp_r()                               (0x00500918U)
+#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v)  ((U32(v) & 0xffffffU) << 0U)
+#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v()             (0x00800000U)
+#define gr_gpc0_zcull_total_ram_size_r()                           (0x00500920U)
+#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v)\
+				((U32(v) & 0xffffU) << 0U)
+#define gr_gpc0_zcull_zcsize_r(i)\
+		(nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U)))
+#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v()        (0x00000040U)
+#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v()         (0x00000010U)
+#define gr_gpc0_gpm_pd_sm_id_r(i)\
+		(nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpc0_gpm_pd_sm_id_id_f(v)                    ((U32(v) & 0xffU) << 0U)
+#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\
+		(nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r)           (((r) >> 0U) & 0xffU)
+#define gr_gpc0_tpc0_sm_cfg_r()                                    (0x00504608U)
+#define gr_gpc0_tpc0_sm_cfg_tpc_id_f(v)               ((U32(v) & 0xffffU) << 0U)
+#define gr_gpc0_tpc0_sm_arch_r()                                   (0x00504330U)
+#define gr_gpc0_tpc0_sm_arch_warp_count_v(r)               (((r) >> 0U) & 0xffU)
+#define gr_gpc0_tpc0_sm_arch_spa_version_v(r)             (((r) >> 8U) & 0xfffU)
+#define gr_gpc0_tpc0_sm_arch_sm_version_v(r)             (((r) >> 20U) & 0xfffU)
+#define gr_gpc0_ppc0_pes_vsc_strem_r()                             (0x00503018U)
+#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m()               (U32(0x1U) << 0U)
+#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f()                     (0x1U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_r()                          (0x005030c0U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v)        ((U32(v) & 0x3fffffU) << 0U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m()               (U32(0x3fffffU) << 0U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()                (0x00000800U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v()                   (0x00001100U)
+#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v()            (0x00000020U)
+#define gr_gpc0_ppc0_cbm_beta_cb_offset_r()                        (0x005030f4U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_size_r()                         (0x005030e4U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v)         ((U32(v) & 0xffffU) << 0U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m()                (U32(0xffffU) << 0U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v()               (0x00000800U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v()           (0x00000020U)
+#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r()                       (0x005030f8U)
+#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r()             (0x005030f0U)
+#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\
+				((U32(v) & 0x3fffffU) << 0U)
+#define gr_gpcs_tpcs_tex_rm_cb_0_r()                               (0x00419e00U)
+#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpcs_tpcs_tex_rm_cb_1_r()                               (0x00419e04U)
+#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) ((U32(v) & 0x1fffffU) << 0U)
+#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f()           (0x80U)
+#define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f()                    (0x80000000U)
+#define gr_gpccs_cpuctl_r()                                        (0x0041a100U)
+#define gr_gpccs_cpuctl_startcpu_f(v)                    ((U32(v) & 0x1U) << 1U)
+#define gr_gpccs_dmactl_r()                                        (0x0041a10cU)
+#define gr_gpccs_dmactl_require_ctx_f(v)                 ((U32(v) & 0x1U) << 0U)
+#define gr_gpccs_dmactl_imem_scrubbing_m()                     (U32(0x1U) << 2U)
+#define gr_gpccs_imemc_r(i)\
+		(nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_gpccs_imemc_offs_f(v)                        ((U32(v) & 0x3fU) << 2U)
+#define gr_gpccs_imemc_blk_f(v)                       ((U32(v) & 0xffffU) << 8U)
+#define gr_gpccs_imemc_aincw_f(v)                       ((U32(v) & 0x1U) << 24U)
+#define gr_gpccs_imemd_r(i)\
+		(nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_gpccs_imemt_r(i)\
+		(nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U)))
+#define gr_gpccs_imemt_tag_f(v)                       ((U32(v) & 0xffffU) << 0U)
+#define gr_gpccs_dmemc_r(i)\
+		(nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U)))
+#define gr_gpccs_dmemc_offs_f(v)                        ((U32(v) & 0x3fU) << 2U)
+#define gr_gpccs_dmemc_blk_f(v)                       ((U32(v) & 0xffffU) << 8U)
+#define gr_gpccs_dmemc_aincw_f(v)                       ((U32(v) & 0x1U) << 24U)
+#define gr_gpccs_dmemd_r(i)\
+		(nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U)))
+#define gr_gpccs_ctxsw_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpccs_ctxsw_mailbox__size_1_v()                         (0x00000012U)
+#define gr_gpccs_ctxsw_mailbox_value_f(v)         ((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpc0_gpccs_ctxsw_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x00502800U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpc0_gpccs_ctxsw_func_tracing_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x005028c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpc0_gpccs_ctxsw_func_tracing_mailbox__size_1_v()       (0x00000006U)
+#define gr_gpcs_swdx_bundle_cb_base_r()                            (0x00418e24U)
+#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpcs_swdx_bundle_cb_size_r()                            (0x00418e28U)
+#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v)      ((U32(v) & 0x7ffU) << 0U)
+#define gr_gpcs_swdx_bundle_cb_size_valid_true_f()                 (0x80000000U)
+#define gr_gpc0_swdx_rm_spill_buffer_size_r()                      (0x005001dcU)
+#define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v)   ((U32(v) & 0xffffU) << 0U)
+#define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v()         (0x000002e0U)
+#define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\
+				(0x00000100U)
+#define gr_gpc0_swdx_rm_spill_buffer_addr_r()                      (0x005001d8U)
+#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()      (0x00000008U)
+#define gr_gpcs_swdx_beta_cb_ctrl_r()                              (0x004181e4U)
+#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v)    ((U32(v) & 0xfffU) << 0U)
+#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v()            (0x00000100U)
+#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r()                          (0x0041befcU)
+#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v)\
+				((U32(v) & 0xfffU) << 0U)
+#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\
+		(nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v)         ((U32(v) & 0x3fffffU) << 0U)
+#define gr_gpcs_swdx_tc_beta_cb_size_v_m()                (U32(0x3fffffU) << 0U)
+#define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r()                 (0x00418100U)
+#define gr_gpcs_swdx_dss_zbc_z_r(i)\
+		(nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_swdx_dss_zbc_z__size_1_v()                         (0x0000000fU)
+#define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r()                 (0x0041814cU)
+#define gr_gpcs_swdx_dss_zbc_s_r(i)\
+		(nvgpu_safe_add_u32(0x0041815cU, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_swdx_dss_zbc_s__size_1_v()                         (0x0000000fU)
+#define gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r()                 (0x00418198U)
+#define gr_gpcs_setup_attrib_cb_base_r()                           (0x00418810U)
+#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v)\
+				((U32(v) & 0xfffffffU) << 0U)
+#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()     (0x0000000cU)
+#define gr_gpcs_setup_attrib_cb_base_valid_true_f()                (0x80000000U)
+#define gr_crstr_gpc_map_r(i)\
+		(nvgpu_safe_add_u32(0x00418b08U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_crstr_gpc_map_tile0_f(v)                     ((U32(v) & 0x1fU) << 0U)
+#define gr_crstr_gpc_map_tile1_f(v)                     ((U32(v) & 0x1fU) << 5U)
+#define gr_crstr_gpc_map_tile2_f(v)                    ((U32(v) & 0x1fU) << 10U)
+#define gr_crstr_gpc_map_tile3_f(v)                    ((U32(v) & 0x1fU) << 15U)
+#define gr_crstr_gpc_map_tile4_f(v)                    ((U32(v) & 0x1fU) << 20U)
+#define gr_crstr_gpc_map_tile5_f(v)                    ((U32(v) & 0x1fU) << 25U)
+#define gr_crstr_map_table_cfg_r()                                 (0x00418bb8U)
+#define gr_crstr_map_table_cfg_row_offset_f(v)          ((U32(v) & 0xffU) << 0U)
+#define gr_crstr_map_table_cfg_num_entries_f(v)         ((U32(v) & 0xffU) << 8U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_r(i)\
+		(nvgpu_safe_add_u32(0x00418980U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(v)   ((U32(v) & 0x7U) << 0U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(v)   ((U32(v) & 0x7U) << 4U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(v)   ((U32(v) & 0x7U) << 8U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(v)  ((U32(v) & 0x7U) << 12U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(v)  ((U32(v) & 0x7U) << 16U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(v)  ((U32(v) & 0x7U) << 20U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(v)  ((U32(v) & 0x7U) << 24U)
+#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(v)  ((U32(v) & 0x7U) << 28U)
+#define gr_gpcs_gcc_pagepool_base_r()                              (0x00419004U)
+#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v)  ((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpcs_gcc_pagepool_r()                                   (0x00419008U)
+#define gr_gpcs_gcc_pagepool_total_pages_f(v)          ((U32(v) & 0x3ffU) << 0U)
+#define gr_gpcs_tpcs_pe_vaf_r()                                    (0x0041980cU)
+#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f()                    (0x10U)
+#define gr_gpcs_tpcs_mpc_pix_debug_r()                             (0x00419c04U)
+#define gr_gpcs_tpcs_mpc_pix_debug_cta_subpartition_skew_m()  (U32(0x1U) << 13U)
+#define gr_gpcs_tpcs_mpc_pix_debug_cta_subpartition_skew_disable_f()      (0x0U)
+#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r()                (0x00419848U)
+#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v)\
+				((U32(v) & 0xfffffffU) << 0U)
+#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f()     (0x10000000U)
+#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r()               (0x00419c2cU)
+#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v)\
+				((U32(v) & 0xfffffffU) << 0U)
+#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f()    (0x10000000U)
+#define gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r()              (0x00419ea8U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r()              (0x00504728U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r()              (0x00504728U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f()\
+				(0x4U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f()\
+				(0x20U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f() (0x40U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f()\
+				(0x100U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f()\
+				(0x200U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f()\
+				(0x800U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f()   (0x2000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f()  (0x4000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f()\
+				(0x8000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f()\
+				(0x10000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f()\
+				(0x40000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f()\
+				(0x800000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_tex_format_report_f()\
+				(0x1000000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_tex_layout_report_f()\
+				(0x2000000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f()\
+				(0x4000000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_arrive_report_f() (0x8000000U)
+#define gr_gpcs_tpcs_tpccs_tpc_exception_en_r()                    (0x00419d0cU)
+#define gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()                (0x2U)
+#define gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f()              (0x10U)
+#define gr_gpcs_tpcs_tpccs_tpc_exception_en_pe_enabled_f()                (0x4U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_en_r()                    (0x0050450cU)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r)         (((r) >> 1U) & 0x1U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f()                (0x2U)
+#define gr_gpcs_gpccs_gpc_exception_en_r()                         (0x0041ac94U)
+#define gr_gpcs_gpccs_gpc_exception_en_gcc_enabled_f()                    (0x4U)
+#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v)        ((U32(v) & 0xffU) << 16U)
+#define gr_gpcs_gpccs_gpc_exception_en_gpccs_enabled_f()               (0x4000U)
+#define gr_gpcs_gpccs_gpc_exception_en_gpcmmu0_enabled_f()             (0x2000U)
+#define gr_gpcs_gpccs_gpc_exception_en_crop0_enabled_f()            (0x4000000U)
+#define gr_gpcs_gpccs_gpc_exception_en_zrop0_enabled_f()            (0x8000000U)
+#define gr_gpcs_gpccs_gpc_exception_en_rrh0_enabled_f()            (0x10000000U)
+#define gr_gpcs_gpccs_gpc_exception_en_crop1_enabled_f()           (0x20000000U)
+#define gr_gpcs_gpccs_gpc_exception_en_zrop1_enabled_f()           (0x40000000U)
+#define gr_gpcs_gpccs_gpc_exception_en_rrh1_enabled_f()            (0x80000000U)
+#define gr_gpc0_gpccs_gpc_exception_r()                            (0x00502c90U)
+#define gr_gpc0_gpccs_gpc_exception_prop_m()                   (U32(0x1U) << 0U)
+#define gr_gpc0_gpccs_gpc_exception_zcull_m()                  (U32(0x1U) << 1U)
+#define gr_gpc0_gpccs_gpc_exception_setup_m()                  (U32(0x1U) << 3U)
+#define gr_gpc0_gpccs_gpc_exception_pes0_m()                   (U32(0x1U) << 4U)
+#define gr_gpc0_gpccs_gpc_exception_pes1_m()                   (U32(0x1U) << 5U)
+#define gr_gpc0_gpccs_gpc_exception_gcc_v(r)                (((r) >> 2U) & 0x1U)
+#define gr_gpc0_gpccs_gpc_exception_tpc_v(r)              (((r) >> 16U) & 0xffU)
+#define gr_gpc0_gpccs_gpc_exception_gpccs_m()                 (U32(0x1U) << 14U)
+#define gr_gpc0_gpccs_gpc_exception_gpcmmu0_m()               (U32(0x1U) << 13U)
+#define gr_gpc0_gpccs_gpc_exception_crop0_pending_f()               (0x4000000U)
+#define gr_gpc0_gpccs_gpc_exception_zrop0_pending_f()               (0x8000000U)
+#define gr_gpc0_gpccs_gpc_exception_rrh0_pending_f()               (0x10000000U)
+#define gr_gpc0_gpccs_gpc_exception_crop1_pending_f()              (0x20000000U)
+#define gr_gpc0_gpccs_gpc_exception_zrop1_pending_f()              (0x40000000U)
+#define gr_gpc0_gpccs_gpc_exception_rrh1_pending_f()               (0x80000000U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_r()                       (0x00504508U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(r)            (((r) >> 1U) & 0x1U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v()            (0x00000001U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m()               (U32(0x1U) << 4U)
+#define gr_gpc0_tpc0_tpccs_tpc_exception_pe_m()                (U32(0x1U) << 2U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_r()                         (0x00504704U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m()       (U32(0x1U) << 0U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f()               (0x1U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f()              (0x0U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m()       (U32(0x1U) << 31U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f()     (0x80000000U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f()           (0x0U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m()    (U32(0x1U) << 3U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f()        (0x8U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f()       (0x0U)
+#define gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f()        (0x40000000U)
+#define gr_gpc0_tpc0_sm0_warp_valid_mask_0_r()                     (0x00504708U)
+#define gr_gpc0_tpc0_sm0_warp_valid_mask_1_r()                     (0x0050470cU)
+#define gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r()                 (0x00504710U)
+#define gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r()                 (0x00504714U)
+#define gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r()                  (0x00504718U)
+#define gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r()                  (0x0050471cU)
+#define gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r()                 (0x00419e90U)
+#define gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r()                 (0x00419e94U)
+#define gr_gpcs_tpcs_sms_dbgr_status0_r()                          (0x00419e80U)
+#define gr_gpc0_tpc0_sm0_dbgr_status0_r()                          (0x00504700U)
+#define gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(r)      (((r) >> 4U) & 0x1U)
+#define gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v()         (0x00000001U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_r()                          (0x00504730U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(r)         (((r) >> 0U) & 0xffffU)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v()               (0x00000000U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f()           (0x2U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f()             (0x5U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f()               (0x6U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f()            (0x8U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f()    (0x9U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f()       (0xbU)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f()                   (0xdU)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f()                  (0xeU)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f()           (0xfU)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f()       (0x10U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f()   (0x12U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f()                (0x17U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f()               (0x18U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f()               (0x19U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f()                 (0x20U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_arrive_f()                   (0x21U)
+#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r()                         (0x0050460cU)
+#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(r)       (((r) >> 0U) & 0x1U)
+#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(r)       (((r) >> 1U) & 0x1U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r()                       (0x00504738U)
+#define gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r()                    (0x0050473cU)
+#define gr_gpcs_tpcs_pes_vsc_vpc_r()                               (0x0041be08U)
+#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f()                (0x4U)
+#define gr_ppcs_wwdx_map_gpc_map_r(i)\
+		(nvgpu_safe_add_u32(0x0041bf00U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_ppcs_wwdx_map_table_cfg_r()                             (0x0041bfd0U)
+#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v)      ((U32(v) & 0xffU) << 0U)
+#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v)     ((U32(v) & 0xffU) << 8U)
+#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r()                           (0x0041bfd4U)
+#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v)\
+				((U32(v) & 0xffffffU) << 0U)
+#define gr_ppcs_wwdx_map_table_cfg_coeff_r(i)\
+		(nvgpu_safe_add_u32(0x0041bfb0U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v()               (0x00000005U)
+#define gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(v)\
+				((U32(v) & 0xffU) << 0U)
+#define gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(v)\
+				((U32(v) & 0xffU) << 8U)
+#define gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(v)\
+				((U32(v) & 0xffU) << 16U)
+#define gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(v)\
+				((U32(v) & 0xffU) << 24U)
+#define gr_gpcs_rops_zrop_hww_esr_r()                              (0x0041bc38U)
+#define gr_gpcs_rops_zrop_hww_esr_reset_active_f()                 (0x40000000U)
+#define gr_gpcs_rops_zrop_hww_esr_en_enable_f()                    (0x80000000U)
+#define gr_gpc0_rop0_zrop_hww_esr_r()                              (0x00503838U)
+#define gr_gpc0_rop0_zrop_hww_esr_reset_active_f()                 (0x40000000U)
+#define gr_gpc0_rop0_zrop_hww_esr_en_enable_f()                    (0x80000000U)
+#define gr_gpcs_rops_crop_hww_esr_r()                              (0x0041bcbcU)
+#define gr_gpcs_rops_crop_hww_esr_reset_active_f()                 (0x40000000U)
+#define gr_gpcs_rops_crop_hww_esr_en_enable_f()                    (0x80000000U)
+#define gr_gpc0_rop0_crop_hww_esr_r()                              (0x005038bcU)
+#define gr_gpc0_rop0_crop_hww_esr_reset_active_f()                 (0x40000000U)
+#define gr_gpc0_rop0_crop_hww_esr_en_enable_f()                    (0x80000000U)
+#define gr_gpc0_rop0_rrh_status_r()                                (0x00503868U)
+#define gr_zcull_bytes_per_aliquot_per_gpu_v()                     (0x00000020U)
+#define gr_zcull_save_restore_header_bytes_per_gpc_v()             (0x00000020U)
+#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v()   (0x000000c0U)
+#define gr_zcull_subregion_qty_v()                                 (0x00000010U)
+#define gr_gpcs_tpcs_tex_in_dbg_r()                                (0x00419a00U)
+#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(v)\
+				((U32(v) & 0x1U) << 19U)
+#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m()      (U32(0x1U) << 19U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_r()                             (0x00419bf0U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(v) ((U32(v) & 0x1U) << 5U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m()        (U32(0x1U) << 5U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(v)\
+				((U32(v) & 0x1U) << 10U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m()       (U32(0x1U) << 10U)
+#define gr_fe_pwr_mode_r()                                         (0x00404170U)
+#define gr_fe_pwr_mode_mode_auto_f()                                      (0x0U)
+#define gr_fe_pwr_mode_mode_force_on_f()                                  (0x2U)
+#define gr_fe_pwr_mode_req_v(r)                             (((r) >> 4U) & 0x1U)
+#define gr_fe_pwr_mode_req_send_f()                                      (0x10U)
+#define gr_fe_pwr_mode_req_done_v()                                (0x00000000U)
+#define gr_gpcs_pri_mmu_ctrl_r()                                   (0x00418880U)
+#define gr_gpcs_pri_mmu_ctrl_vm_pg_size_m()                    (U32(0x1U) << 0U)
+#define gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m()        (U32(0x1U) << 11U)
+#define gr_gpcs_pri_mmu_ctrl_comp_fault_m()                    (U32(0x1U) << 2U)
+#define gr_gpcs_pri_mmu_ctrl_miss_gran_m()                     (U32(0x3U) << 3U)
+#define gr_gpcs_pri_mmu_ctrl_cache_mode_m()                    (U32(0x3U) << 5U)
+#define gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m()       (U32(0x3U) << 24U)
+#define gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m()\
+				(U32(0x1U) << 27U)
+#define gr_gpcs_pri_mmu_pm_unit_mask_r()                           (0x00418890U)
+#define gr_gpcs_pri_mmu_pm_req_mask_r()                            (0x00418894U)
+#define gr_gpcs_pri_mmu_debug_ctrl_r()                             (0x004188b0U)
+#define gr_gpcs_pri_mmu_debug_ctrl_debug_m()                  (U32(0x1U) << 16U)
+#define gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f()                  (0x10000U)
+#define gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f()                     (0x0U)
+#define gr_gpcs_pri_mmu_debug_wr_r()                               (0x004188b4U)
+#define gr_gpcs_pri_mmu_debug_rd_r()                               (0x004188b8U)
+#define gr_gpcs_mmu_num_active_ltcs_r()                            (0x004188acU)
+#define gr_gpcs_mmu_vidmem_access_bit_r()                          (0x0041833cU)
+#define gr_gpcs_tpcs_sms_dbgr_control0_r()                         (0x00419e84U)
+#define gr_fe_gfxp_wfi_timeout_r()                                 (0x004041c0U)
+#define gr_gpcs_tpcs_sm_texio_control_r()                          (0x00419bd8U)
+#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m()  (U32(0x7U) << 8U)
+#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\
+				(0x100U)
+#define gr_gpcs_tpcs_sm_disp_ctrl_r()                              (0x00419ba4U)
+#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m()             (U32(0x3U) << 11U)
+#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()              (0x1000U)
+#define gr_debug_0_r()                                             (0x00400080U)
+#define gr_debug_0_scg_force_slow_drain_tpc_m()               (U32(0x1U) << 11U)
+#define gr_debug_0_scg_force_slow_drain_tpc_enabled_f()                 (0x800U)
+#define gr_debug_2_r()                                             (0x00400088U)
+#define gr_debug_2_gfxp_wfi_timeout_unit_m()                  (U32(0x1U) << 27U)
+#define gr_debug_2_gfxp_wfi_timeout_unit_usec_f()                         (0x0U)
+#define gr_debug_2_graphics_auto_go_idle_m()                  (U32(0x1U) << 17U)
+#define gr_debug_2_graphics_auto_go_idle_disabled_f()                     (0x0U)
+#define gr_debug_2_graphics_auto_go_idle_enabled_f()                  (0x20000U)
+#define gr_debug_2_compute_auto_go_idle_m()                   (U32(0x1U) << 18U)
+#define gr_debug_2_compute_auto_go_idle_disabled_f()                      (0x0U)
+#define gr_debug_2_compute_auto_go_idle_enabled_f()                   (0x40000U)
+#define gr_pri_gpcs_rops_crop_zbc_index_r()                        (0x0041bcb4U)
+#define gr_pri_gpcs_rops_crop_zbc_index_address_f(v)    ((U32(v) & 0x1fU) << 0U)
+#define gr_pri_gpcs_rops_crop_zbc_index_address_min_v()            (0x00000001U)
+#define gr_pri_gpcs_rops_crop_zbc_index_address_max_v()            (0x0000001eU)
+#define gr_pri_gpcs_rops_crop_zbc_color_clear_value_0_r()          (0x0041bcecU)
+#define gr_pri_gpcs_rops_crop_zbc_color_clear_value_0_bits_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define gr_pri_gpcs_rops_crop_zbc_color_clear_value_1_r()          (0x0041bcf0U)
+#define gr_pri_gpcs_rops_crop_zbc_color_clear_value_1_bits_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define gr_pri_gpcs_rops_crop_zbc_color_clear_value_2_r()          (0x0041bcf4U)
+#define gr_pri_gpcs_rops_crop_zbc_color_clear_value_2_bits_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define gr_pri_gpcs_rops_crop_zbc_color_clear_value_3_r()          (0x0041bcf8U)
+#define gr_pri_gpcs_rops_crop_zbc_color_clear_value_3_bits_f(v)\
+				((U32(v) & 0xffffffffU) << 0U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r()        (0x00584200U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r()        (0x00584204U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r()            (0x00584208U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r()            (0x00584210U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r()            (0x00584214U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r()            (0x00584218U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r()            (0x0058421cU)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r()            (0x0058420cU)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r()            (0x00584220U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r()            (0x00584224U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r()            (0x00584228U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r()            (0x0058422cU)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r()            (0x00584230U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r()            (0x00584234U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r()            (0x00584238U)
+#define gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r()            (0x0058423cU)
+#define gr_egpc0_etpc0_sm0_dsm_perf_counter4_r()                   (0x00584614U)
+#define gr_egpc0_etpc0_sm0_dsm_perf_counter5_r()                   (0x00584618U)
+#define gr_egpc0_etpc0_sm0_dsm_perf_counter6_r()                   (0x0058461cU)
+#define gr_egpc0_etpc0_sm0_dsm_perf_counter7_r()                   (0x00584620U)
+#define gr_pri_gpcs_rops_crop_debug4_r()                           (0x0041bc8cU)
+#define gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_s()                     (1U)
+#define gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_m()       (U32(0x1U) << 18U)
+#define gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_to_inf_v()     (0x00000000U)
+#define gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_to_inf_f()            (0x0U)
+#define gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_to_maxval_v()  (0x00000001U)
+#define gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_to_maxval_f()     (0x40000U)
+#define gr_pri_gpcs_rop0_crop_status1_r()                          (0x0041b8a0U)
+#define gr_pri_gpcs_rops_crop_status1_r()                          (0x0041bca0U)
+#define gr_pri_gpcs_rop0_zrop_status_r()                           (0x0041b820U)
+#define gr_pri_gpcs_rop0_zrop_status2_r()                          (0x0041b824U)
+#define gr_pri_gpcs_rops_zrop_status_r()                           (0x0041bc20U)
+#define gr_pri_gpcs_rops_zrop_status2_r()                          (0x0041bc24U)
+#define gr_gpc0_gpccs_falcon_ecc_status_r()                        (0x00502678U)
+#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m() (U32(0x1U) << 0U)
+#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m() (U32(0x1U) << 1U)
+#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m()\
+				(U32(0x1U) << 4U)
+#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m()\
+				(U32(0x1U) << 5U)
+#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 10U)
+#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 8U)
+#define gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()             (0x80000000U)
+#define gr_gpc0_gpccs_falcon_ecc_address_r()                       (0x00502684U)
+#define gr_gpc0_gpccs_falcon_ecc_address_row_address_v(r)\
+				(((r) >> 0U) & 0xfffffU)
+#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r()           (0x0050267cU)
+#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r()         (0x00502680U)
+#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_fecs_falcon_ecc_status_r()                              (0x00409678U)
+#define gr_fecs_falcon_ecc_status_corrected_err_imem_m()       (U32(0x1U) << 0U)
+#define gr_fecs_falcon_ecc_status_corrected_err_dmem_m()       (U32(0x1U) << 1U)
+#define gr_fecs_falcon_ecc_status_uncorrected_err_imem_m()     (U32(0x1U) << 4U)
+#define gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m()     (U32(0x1U) << 5U)
+#define gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 10U)
+#define gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 8U)
+#define gr_fecs_falcon_ecc_status_reset_task_f()                   (0x80000000U)
+#define gr_fecs_falcon_ecc_address_r()                             (0x00409684U)
+#define gr_fecs_falcon_ecc_address_row_address_v(r)     (((r) >> 0U) & 0xfffffU)
+#define gr_fecs_falcon_ecc_corrected_err_count_r()                 (0x0040967cU)
+#define gr_fecs_falcon_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_fecs_falcon_ecc_uncorrected_err_count_r()               (0x00409680U)
+#define gr_fecs_falcon_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_fecs_falcon_ecc_control_r()                             (0x0040968cU)
+#define gr_fecs_falcon_ecc_control_inject_corrected_err_f(v)\
+				((U32(v) & 0x1U) << 0U)
+#define gr_fecs_falcon_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 1U)
+#define gr_pri_gpc0_gcc_l15_ecc_control_r()                        (0x00501044U)
+#define gr_pri_gpc0_gcc_l15_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 1U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_r()                         (0x00501048U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m() (U32(0x1U) << 0U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m() (U32(0x1U) << 1U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m()\
+				(U32(0x1U) << 4U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m()\
+				(U32(0x1U) << 5U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(r)\
+				(((r) >> 8U) & 0x1U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(r)\
+				(((r) >> 10U) & 0x1U)
+#define gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f()              (0x40000000U)
+#define gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r()            (0x0050104cU)
+#define gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r()          (0x00501054U)
+#define gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s()            (16U)
+#define gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_gpc0_mmu0_l1tlb_ecc_control_r()                         (0x00501410U)
+#define gr_gpc0_mmu0_l1tlb_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 5U)
+#define gr_gpc0_mmu0_gpcmmu_global_esr_r()                         (0x00501424U)
+#define gr_gpc0_mmu0_gpcmmu_global_esr_ecc_corrected_m()       (U32(0x1U) << 0U)
+#define gr_gpc0_mmu0_gpcmmu_global_esr_ecc_uncorrected_m()     (U32(0x1U) << 1U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_r()                          (0x00501414U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m()\
+				(U32(0x1U) << 0U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m()\
+				(U32(0x1U) << 2U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m()\
+				(U32(0x1U) << 1U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m()\
+				(U32(0x1U) << 3U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 18U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 16U)
+#define gr_gpc0_mmu0_l1tlb_ecc_status_reset_task_f()               (0x40000000U)
+#define gr_gpc0_mmu0_l1tlb_ecc_address_r()                         (0x00501420U)
+#define gr_gpc0_mmu0_l1tlb_ecc_corrected_err_count_r()             (0x00501418U)
+#define gr_gpc0_mmu0_l1tlb_ecc_corrected_err_count_total_s()               (16U)
+#define gr_gpc0_mmu0_l1tlb_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_gpc0_mmu0_l1tlb_ecc_uncorrected_err_count_r()           (0x0050141cU)
+#define gr_gpc0_mmu0_l1tlb_ecc_uncorrected_err_count_total_s()             (16U)
+#define gr_gpc0_mmu0_l1tlb_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define gr_gpcs_gpccs_engine_reset_ctl_r()                         (0x0041a610U)
+#define gr_gpcs_gpccs_engine_reset_ctl_gpc_engine_reset_enabled_f()       (0x0U)
+#define gr_gpcs_gpccs_engine_reset_ctl_gpc_engine_reset_disabled_f()      (0x1U)
+#define gr_gpc0_gpccs_engine_reset_ctl_r()                         (0x00502610U)
+#define gr_gpc0_gpccs_engine_reset_ctl_gpc_engine_reset_v(r)\
+				(((r) >> 0U) & 0x1U)
+#define gr_gpc0_gpccs_engine_reset_ctl_gpc_engine_reset_disabled_v()\
+				(0x00000001U)
+#define gr_gpcs_tpcs_cau_control_r(i)\
+		(nvgpu_safe_add_u32(0x00419980U, nvgpu_safe_mult_u32((i), 64U)))
+#define gr_gpcs_tpcs_cau_control__size_1_v()                       (0x00000002U)
+#define gr_egpcs_etpcs_sm_dsm_perf_counter_control_r()             (0x00481a48U)
+#define gr_egpcs_etpcs_sm_dsm_perf_counter_control0_r()            (0x00481a08U)
+#define gr_egpcs_etpcs_sm_dsm_perf_counter_control5_r()            (0x00481a0cU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ltc_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ltc_ga10b.h
new file mode 100644
index 000000000..3a20da83d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ltc_ga10b.h
@@ -0,0 +1,373 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_LTC_GA10B_H
+#define NVGPU_HW_LTC_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define ltc_pltcg_base_v()                                         (0x00140000U)
+#define ltc_ltc0_lts0_v()                                          (0x00140400U)
+#define ltc_ltcs_ltss_v()                                          (0x0017e200U)
+#define ltc_ltcs_ltss_tstg_set_mgmt0_r()                           (0x0017e2acU)
+#define ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_f(v)\
+				((U32(v) & 0x1fU) << 16U)
+#define ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_m()      (U32(0x1fU) << 16U)
+#define ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_v(r)  (((r) >> 16U) & 0x1fU)
+#define ltc_ltcs_ltss_tstg_cfg2_r()                                (0x0017e298U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_l1_promote_f(v)  ((U32(v) & 0x3U) << 16U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_l1_promote_m()         (U32(0x3U) << 16U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_l1_promote_v(r)     (((r) >> 16U) & 0x3U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_l1_promote_none_v()         (0x00000000U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_l1_promote_64b_v()          (0x00000001U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_l1_promote_128b_v()         (0x00000002U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_t1_promote_f(v)  ((U32(v) & 0x3U) << 18U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_t1_promote_m()         (U32(0x3U) << 18U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_t1_promote_v(r)     (((r) >> 18U) & 0x3U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_t1_promote_none_v()         (0x00000000U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_t1_promote_64b_v()          (0x00000001U)
+#define ltc_ltcs_ltss_tstg_cfg2_vidmem_t1_promote_128b_v()         (0x00000002U)
+#define ltc_ltcs_ltss_tstg_cfg3_r()                                (0x0017e29cU)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_l1_promote_f(v)  ((U32(v) & 0x3U) << 16U)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_l1_promote_m()         (U32(0x3U) << 16U)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_l1_promote_v(r)     (((r) >> 16U) & 0x3U)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_l1_promote_none_v()         (0x00000000U)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_l1_promote_64b_v()          (0x00000001U)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_l1_promote_128b_v()         (0x00000002U)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_t1_promote_f(v)  ((U32(v) & 0x3U) << 18U)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_t1_promote_m()         (U32(0x3U) << 18U)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_t1_promote_v(r)     (((r) >> 18U) & 0x3U)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_t1_promote_none_v()         (0x00000000U)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_t1_promote_64b_v()          (0x00000001U)
+#define ltc_ltcs_ltss_tstg_cfg3_sysmem_t1_promote_128b_v()         (0x00000002U)
+#define ltc_ltcs_ltss_cbc_ctrl1_r()                                (0x0017e26cU)
+#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f()                          (0x1U)
+#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f()                     (0x2U)
+#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f()                          (0x4U)
+#define ltc_ltc0_lts0_cbc_ctrl1_r()                                (0x0014046cU)
+#define ltc_ltcs_ltss_cbc_ctrl2_r()                                (0x0017e270U)
+#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v)\
+				((U32(v) & 0xfffffU) << 0U)
+#define ltc_ltcs_ltss_cbc_ctrl3_r()                                (0x0017e274U)
+#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v)\
+				((U32(v) & 0xfffffU) << 0U)
+#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v()         (0x000fffffU)
+#define ltc_ltcs_ltss_cbc_base_r()                                 (0x0017e278U)
+#define ltc_ltcs_ltss_cbc_base_alignment_shift_v()                 (0x0000000bU)
+#define ltc_ltcs_ltss_cbc_param_r()                                (0x0017e280U)
+#define ltc_ltcs_ltss_cbc_param_bytes_per_comptagline_per_slice_v(r)\
+				(((r) >> 0U) & 0x3ffU)
+#define ltc_ltcs_ltss_cbc_param2_r()                               (0x0017e3f4U)
+#define ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define ltc_ltcs_ltss_cbc_param2_cache_line_size_v(r)      (((r) >> 24U) & 0xfU)
+#define ltc_ltcs_ltss_cbc_param2_slices_per_ltc_v(r)       (((r) >> 28U) & 0xfU)
+#define ltc_ltcs_ltss_tstg_set_mgmt_3_r()                          (0x0017e2b4U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_ce_imm_m()\
+				(U32(0x1U) << 23U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_ce_imm_enabled_f()\
+				(0x800000U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_fclr_imm_m()\
+				(U32(0x1U) << 21U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_fclr_imm_enabled_f()\
+				(0x200000U)
+#define ltc_ltcs_ltss_dstg_zbc_index_r()                           (0x0017e338U)
+#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v)       ((U32(v) & 0x1fU) << 0U)
+#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
+		(nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U)))
+#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v()       (0x00000004U)
+#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r()               (0x0017e34cU)
+#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r()             (0x0017e204U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_2_r()                          (0x0017e2b0U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f()   (0x10000000U)
+#define ltc_ltcs_ltss_intr_r()                                     (0x0017e20cU)
+#define ltc_ltcs_ltss_intr_idle_error_cbc_m()                  (U32(0x1U) << 1U)
+#define ltc_ltcs_ltss_intr_idle_error_cbc_reset_f()                       (0x2U)
+#define ltc_ltcs_ltss_intr_en_idle_error_cbc_m()              (U32(0x1U) << 17U)
+#define ltc_ltcs_ltss_intr_en_idle_error_cbc_enabled_f()              (0x20000U)
+#define ltc_ltcs_ltss_intr_idle_error_tstg_m()                 (U32(0x1U) << 2U)
+#define ltc_ltcs_ltss_intr_idle_error_tstg_reset_f()                      (0x4U)
+#define ltc_ltcs_ltss_intr_en_idle_error_tstg_m()             (U32(0x1U) << 18U)
+#define ltc_ltcs_ltss_intr_en_idle_error_tstg_enabled_f()             (0x40000U)
+#define ltc_ltcs_ltss_intr_idle_error_dstg_m()                 (U32(0x1U) << 3U)
+#define ltc_ltcs_ltss_intr_idle_error_dstg_reset_f()                      (0x8U)
+#define ltc_ltcs_ltss_intr_en_idle_error_dstg_m()             (U32(0x1U) << 19U)
+#define ltc_ltcs_ltss_intr_en_idle_error_dstg_enabled_f()             (0x80000U)
+#define ltc_ltcs_ltss_intr_evicted_cb_m()                      (U32(0x1U) << 4U)
+#define ltc_ltcs_ltss_intr_evicted_cb_reset_f()                          (0x10U)
+#define ltc_ltcs_ltss_intr_en_evicted_cb_m()                  (U32(0x1U) << 20U)
+#define ltc_ltcs_ltss_intr_en_evicted_cb_enabled_f()                 (0x100000U)
+#define ltc_ltcs_ltss_intr_illegal_compstat_m()                (U32(0x1U) << 5U)
+#define ltc_ltcs_ltss_intr_illegal_compstat_reset_f()                    (0x20U)
+#define ltc_ltcs_ltss_intr_en_illegal_compstat_m()            (U32(0x1U) << 21U)
+#define ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f()           (0x200000U)
+#define ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f()               (0x0U)
+#define ltc_ltcs_ltss_intr_illegal_atomic_m()                 (U32(0x1U) << 12U)
+#define ltc_ltcs_ltss_intr_illegal_atomic_reset_f()                    (0x1000U)
+#define ltc_ltcs_ltss_intr_en_illegal_atomic_m()              (U32(0x1U) << 28U)
+#define ltc_ltcs_ltss_intr_en_illegal_atomic_enabled_f()           (0x10000000U)
+#define ltc_ltcs_ltss_intr_blkactivity_err_m()                (U32(0x1U) << 13U)
+#define ltc_ltcs_ltss_intr_blkactivity_err_reset_f()                   (0x2000U)
+#define ltc_ltcs_ltss_intr_en_blkactivity_err_m()             (U32(0x1U) << 29U)
+#define ltc_ltcs_ltss_intr_en_blkactivity_err_enabled_f()          (0x20000000U)
+#define ltc_ltcs_ltss_intr_illegal_compstat_access_m()        (U32(0x1U) << 14U)
+#define ltc_ltcs_ltss_intr_illegal_compstat_access_reset_f()           (0x4000U)
+#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_m()     (U32(0x1U) << 30U)
+#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_enabled_f()  (0x40000000U)
+#define ltc_ltcs_ltss_intr2_r()                                    (0x0017e208U)
+#define ltc_ltcs_ltss_intr2_trdone_invalid_tdtag_m()           (U32(0x1U) << 0U)
+#define ltc_ltcs_ltss_intr2_trdone_invalid_tdtag_reset_f()                (0x1U)
+#define ltc_ltcs_ltss_intr2_en_trdone_invalid_tdtag_m()       (U32(0x1U) << 16U)
+#define ltc_ltcs_ltss_intr2_en_trdone_invalid_tdtag_enabled_f()       (0x10000U)
+#define ltc_ltcs_ltss_intr2_unexpected_trdone_m()              (U32(0x1U) << 1U)
+#define ltc_ltcs_ltss_intr2_unexpected_trdone_reset_f()                   (0x2U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_trdone_m()          (U32(0x1U) << 17U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_trdone_enabled_f()          (0x20000U)
+#define ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_data_m() (U32(0x1U) << 2U)
+#define ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_data_reset_f()      (0x4U)
+#define ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_data_m()\
+				(U32(0x1U) << 18U)
+#define ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_data_enabled_f()\
+				(0x40000U)
+#define ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_cancel_m()\
+				(U32(0x1U) << 3U)
+#define ltc_ltcs_ltss_intr2_rwc_upg_unexpected_trdone_cancel_reset_f()    (0x8U)
+#define ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_cancel_m()\
+				(U32(0x1U) << 19U)
+#define ltc_ltcs_ltss_intr2_en_rwc_upg_unexpected_trdone_cancel_enabled_f()\
+				(0x80000U)
+#define ltc_ltcs_ltss_intr2_prbrs_invalid_subid_m()            (U32(0x1U) << 4U)
+#define ltc_ltcs_ltss_intr2_prbrs_invalid_subid_reset_f()                (0x10U)
+#define ltc_ltcs_ltss_intr2_en_prbrs_invalid_subid_m()        (U32(0x1U) << 20U)
+#define ltc_ltcs_ltss_intr2_en_prbrs_invalid_subid_enabled_f()       (0x100000U)
+#define ltc_ltcs_ltss_intr2_unexpected_prbrs_m()               (U32(0x1U) << 5U)
+#define ltc_ltcs_ltss_intr2_unexpected_prbrs_reset_f()                   (0x20U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_prbrs_m()           (U32(0x1U) << 21U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_prbrs_enabled_f()          (0x200000U)
+#define ltc_ltcs_ltss_intr2_prbin_unexpected_prbrs_m()         (U32(0x1U) << 6U)
+#define ltc_ltcs_ltss_intr2_prbin_unexpected_prbrs_reset_f()             (0x40U)
+#define ltc_ltcs_ltss_intr2_en_prbin_unexpected_prbrs_m()     (U32(0x1U) << 22U)
+#define ltc_ltcs_ltss_intr2_en_prbin_unexpected_prbrs_enabled_f()    (0x400000U)
+#define ltc_ltcs_ltss_intr2_prbimo_unexpected_prbrs_m()        (U32(0x1U) << 7U)
+#define ltc_ltcs_ltss_intr2_prbimo_unexpected_prbrs_reset_f()            (0x80U)
+#define ltc_ltcs_ltss_intr2_en_prbimo_unexpected_prbrs_m()    (U32(0x1U) << 23U)
+#define ltc_ltcs_ltss_intr2_en_prbimo_unexpected_prbrs_enabled_f()   (0x800000U)
+#define ltc_ltcs_ltss_intr2_prbx_missing_data_m()              (U32(0x1U) << 8U)
+#define ltc_ltcs_ltss_intr2_prbx_missing_data_reset_f()                 (0x100U)
+#define ltc_ltcs_ltss_intr2_en_prbx_missing_data_m()          (U32(0x1U) << 24U)
+#define ltc_ltcs_ltss_intr2_en_prbx_missing_data_enabled_f()        (0x1000000U)
+#define ltc_ltcs_ltss_intr2_prbx_unexpected_data_m()           (U32(0x1U) << 9U)
+#define ltc_ltcs_ltss_intr2_prbx_unexpected_data_reset_f()              (0x200U)
+#define ltc_ltcs_ltss_intr2_en_prbx_unexpected_data_m()       (U32(0x1U) << 25U)
+#define ltc_ltcs_ltss_intr2_en_prbx_unexpected_data_enabled_f()     (0x2000000U)
+#define ltc_ltcs_ltss_intr2_prbrs_unexpected_pa7_m()          (U32(0x1U) << 10U)
+#define ltc_ltcs_ltss_intr2_prbrs_unexpected_pa7_reset_f()              (0x400U)
+#define ltc_ltcs_ltss_intr2_en_prbrs_unexpected_pa7_m()       (U32(0x1U) << 26U)
+#define ltc_ltcs_ltss_intr2_en_prbrs_unexpected_pa7_enabled_f()     (0x4000000U)
+#define ltc_ltcs_ltss_intr2_trdone_unexpected_pa7_m()         (U32(0x1U) << 11U)
+#define ltc_ltcs_ltss_intr2_trdone_unexpected_pa7_reset_f()             (0x800U)
+#define ltc_ltcs_ltss_intr2_en_trdone_unexpected_pa7_m()      (U32(0x1U) << 27U)
+#define ltc_ltcs_ltss_intr2_en_trdone_unexpected_pa7_enabled_f()    (0x8000000U)
+#define ltc_ltcs_ltss_intr2_sysfill_bypass_invalid_subid_m()  (U32(0x1U) << 12U)
+#define ltc_ltcs_ltss_intr2_sysfill_bypass_invalid_subid_reset_f()     (0x1000U)
+#define ltc_ltcs_ltss_intr2_en_sysfill_bypass_invalid_subid_m()\
+				(U32(0x1U) << 28U)
+#define ltc_ltcs_ltss_intr2_en_sysfill_bypass_invalid_subid_enabled_f()\
+				(0x10000000U)
+#define ltc_ltcs_ltss_intr2_unexpected_sysfill_bypass_m()     (U32(0x1U) << 13U)
+#define ltc_ltcs_ltss_intr2_unexpected_sysfill_bypass_reset_f()        (0x2000U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_sysfill_bypass_m()  (U32(0x1U) << 29U)
+#define ltc_ltcs_ltss_intr2_en_unexpected_sysfill_bypass_enabled_f()\
+				(0x20000000U)
+#define ltc_ltcs_ltss_intr2_checkedin_unexpected_prbrs_m()    (U32(0x1U) << 14U)
+#define ltc_ltcs_ltss_intr2_checkedin_unexpected_prbrs_reset_f()       (0x4000U)
+#define ltc_ltcs_ltss_intr2_en_checkedin_unexpected_prbrs_m() (U32(0x1U) << 30U)
+#define ltc_ltcs_ltss_intr2_en_checkedin_unexpected_prbrs_enabled_f()\
+				(0x40000000U)
+#define ltc_ltcs_ltss_intr2_checkedin_unexpected_trdone_m()   (U32(0x1U) << 15U)
+#define ltc_ltcs_ltss_intr2_checkedin_unexpected_trdone_reset_f()      (0x8000U)
+#define ltc_ltcs_ltss_intr2_en_checkedin_unexpected_trdone_m()\
+				(U32(0x1U) << 31U)
+#define ltc_ltcs_ltss_intr2_en_checkedin_unexpected_trdone_enabled_f()\
+				(0x80000000U)
+#define ltc_ltcs_ltss_intr3_r()                                    (0x0017e388U)
+#define ltc_ltcs_ltss_intr3_checkedout_rwc_upg_unexpected_nvport_m()\
+				(U32(0x1U) << 0U)
+#define ltc_ltcs_ltss_intr3_checkedout_rwc_upg_unexpected_nvport_reset_f()\
+				(0x1U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_rwc_upg_unexpected_nvport_m()\
+				(U32(0x1U) << 16U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_rwc_upg_unexpected_nvport_enabled_f()\
+				(0x10000U)
+#define ltc_ltcs_ltss_intr3_checkedout_trdone_unexpected_nvport_m()\
+				(U32(0x1U) << 1U)
+#define ltc_ltcs_ltss_intr3_checkedout_trdone_unexpected_nvport_reset_f() (0x2U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_trdone_unexpected_nvport_m()\
+				(U32(0x1U) << 17U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_trdone_unexpected_nvport_enabled_f()\
+				(0x20000U)
+#define ltc_ltcs_ltss_intr3_checkedout_prbrs_unexpected_nvport_m()\
+				(U32(0x1U) << 2U)
+#define ltc_ltcs_ltss_intr3_checkedout_prbrs_unexpected_nvport_reset_f()  (0x4U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_prbrs_unexpected_nvport_m()\
+				(U32(0x1U) << 18U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_prbrs_unexpected_nvport_enabled_f()\
+				(0x40000U)
+#define ltc_ltcs_ltss_intr3_checkedout_ninb_ncnp_req_m()       (U32(0x1U) << 3U)
+#define ltc_ltcs_ltss_intr3_checkedout_ninb_ncnp_req_reset_f()            (0x8U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_ninb_ncnp_req_m()   (U32(0x1U) << 19U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_ninb_ncnp_req_enabled_f()   (0x80000U)
+#define ltc_ltcs_ltss_intr3_checkedout_creq_ncnp_req_m()       (U32(0x1U) << 4U)
+#define ltc_ltcs_ltss_intr3_checkedout_creq_ncnp_req_reset_f()           (0x10U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_creq_ncnp_req_m()   (U32(0x1U) << 20U)
+#define ltc_ltcs_ltss_intr3_en_checkedout_creq_ncnp_req_enabled_f()  (0x100000U)
+#define ltc_ltcs_ltss_intr3_rmwrs_invalid_subid_m()            (U32(0x1U) << 5U)
+#define ltc_ltcs_ltss_intr3_rmwrs_invalid_subid_reset_f()                (0x20U)
+#define ltc_ltcs_ltss_intr3_en_rmwrs_invalid_subid_m()        (U32(0x1U) << 21U)
+#define ltc_ltcs_ltss_intr3_en_rmwrs_invalid_subid_enabled_f()       (0x200000U)
+#define ltc_ltcs_ltss_intr3_unexpected_rmwrs_m()               (U32(0x1U) << 6U)
+#define ltc_ltcs_ltss_intr3_unexpected_rmwrs_reset_f()                   (0x40U)
+#define ltc_ltcs_ltss_intr3_en_unexpected_rmwrs_m()           (U32(0x1U) << 22U)
+#define ltc_ltcs_ltss_intr3_en_unexpected_rmwrs_enabled_f()          (0x400000U)
+#define ltc_ltcs_ltss_intr3_ecc_corrected_m()                  (U32(0x1U) << 7U)
+#define ltc_ltcs_ltss_intr3_ecc_uncorrected_m()                (U32(0x1U) << 8U)
+#define ltc_ltcs_ltss_intr3_illegal_access_kind_type1_m()     (U32(0x1U) << 10U)
+#define ltc_ltcs_ltss_intr3_illegal_access_kind_type1_reset_f()         (0x400U)
+#define ltc_ltcs_ltss_intr3_en_illegal_access_kind_type1_m()  (U32(0x1U) << 26U)
+#define ltc_ltcs_ltss_intr3_en_illegal_access_kind_type1_enabled_f()\
+				(0x4000000U)
+#define ltc_ltcs_ltss_intr3_illegal_access_kind_type2_m()     (U32(0x1U) << 11U)
+#define ltc_ltcs_ltss_intr3_illegal_access_kind_type2_reset_f()         (0x800U)
+#define ltc_ltcs_ltss_intr3_en_illegal_access_kind_type2_m()  (U32(0x1U) << 27U)
+#define ltc_ltcs_ltss_intr3_en_illegal_access_kind_type2_enabled_f()\
+				(0x8000000U)
+#define ltc_ltcs_ltss_intr3_dtm_kind_invalid_m()              (U32(0x1U) << 12U)
+#define ltc_ltcs_ltss_intr3_dtm_kind_invalid_reset_f()                 (0x1000U)
+#define ltc_ltcs_ltss_intr3_en_dtm_kind_invalid_m()           (U32(0x1U) << 28U)
+#define ltc_ltcs_ltss_intr3_en_dtm_kind_invalid_enabled_f()        (0x10000000U)
+#define ltc_ltcs_ltss_intr3_dtm_comptag_invalid_m()           (U32(0x1U) << 13U)
+#define ltc_ltcs_ltss_intr3_dtm_comptag_invalid_reset_f()              (0x2000U)
+#define ltc_ltcs_ltss_intr3_en_dtm_comptag_invalid_m()        (U32(0x1U) << 29U)
+#define ltc_ltcs_ltss_intr3_en_dtm_comptag_invalid_enabled_f()     (0x20000000U)
+#define ltc_ltcs_ltss_intr3_cdcmp_ip_error_m()                (U32(0x1U) << 14U)
+#define ltc_ltcs_ltss_intr3_cdcmp_ip_error_reset_f()                   (0x4000U)
+#define ltc_ltcs_ltss_intr3_en_cdcmp_ip_error_m()             (U32(0x1U) << 30U)
+#define ltc_ltcs_ltss_intr3_en_cdcmp_ip_error_enabled_f()          (0x40000000U)
+#define ltc_ltc0_lts0_intr_r()                                     (0x0014040cU)
+#define ltc_ltc0_lts0_intr2_r()                                    (0x00140408U)
+#define ltc_ltc0_lts0_intr3_r()                                    (0x00140588U)
+#define ltc_ltcs_ltss_tstg_cmgmt0_r()                              (0x0017e2a0U)
+#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f()                  (0x1U)
+#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f()  (0x300U)
+#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\
+				(0x10000000U)
+#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\
+				(0x20000000U)
+#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\
+				(0x40000000U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_r()                              (0x0017e2a4U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f()                       (0x1U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f()       (0x300U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f()  (0x10000U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f()  (0x10000000U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\
+				(0x20000000U)
+#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U)
+#define ltc_ltc0_ltss_tstg_cmgmt0_r()                              (0x001402a0U)
+#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f()                  (0x1U)
+#define ltc_ltc0_ltss_tstg_cmgmt1_r()                              (0x001402a4U)
+#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f()                       (0x1U)
+#define ltc_ltc0_lts0_tstg_info_1_r()                              (0x0014058cU)
+#define ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(r)  (((r) >> 0U) & 0xffffU)
+#define ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(r)      (((r) >> 16U) & 0x1fU)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_r()                          (0x0017e39cU)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_m()   (U32(0x1U) << 7U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_disabled_f()     (0x0U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_enabled_f()     (0x80U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_m()  (U32(0x1U) << 29U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_disabled_f()     (0x0U)
+#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_enabled_f()\
+				(0x20000000U)
+#define ltc_ltc0_lts0_dstg_ecc_address_r()                         (0x00140520U)
+#define ltc_ltc0_lts0_dstg_ecc_address_info_ram_m()           (U32(0x1U) << 22U)
+#define ltc_ltc0_lts0_l2_cache_ecc_address_r()                     (0x001404fcU)
+#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r()         (0x001404f4U)
+#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s()           (16U)
+#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r()       (0x001404f8U)
+#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s()         (16U)
+#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_r()                      (0x001404f0U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()\
+				(U32(0x1U) << 0U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m()\
+				(U32(0x1U) << 1U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m()\
+				(U32(0x1U) << 2U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m()\
+				(U32(0x1U) << 3U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m()\
+				(U32(0x1U) << 4U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m()\
+				(U32(0x1U) << 5U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 16U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 18U)
+#define ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f()           (0x40000000U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_mc_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_mc_ga10b.h
new file mode 100644
index 000000000..b741f0217
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_mc_ga10b.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_MC_GA10B_H
+#define NVGPU_HW_MC_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define mc_boot_0_r()                                              (0x00000000U)
+#define mc_boot_0_architecture_v(r)                       (((r) >> 24U) & 0x1fU)
+#define mc_boot_0_implementation_v(r)                      (((r) >> 20U) & 0xfU)
+#define mc_boot_0_major_revision_v(r)                       (((r) >> 4U) & 0xfU)
+#define mc_boot_0_minor_revision_v(r)                       (((r) >> 0U) & 0xfU)
+#define mc_enable_r()                                              (0x00000200U)
+#define mc_enable_perfmon_m()                                 (U32(0x1U) << 28U)
+#define mc_elpg_enable_r()                                         (0x0000020cU)
+#define mc_elpg_enable_xbar_enabled_f()                                   (0x4U)
+#define mc_elpg_enable_l2_enabled_f()                                     (0x8U)
+#define mc_elpg_enable_hub_enabled_f()                             (0x20000000U)
+#define mc_device_enable_r(i)\
+		(nvgpu_safe_add_u32(0x00000600U, nvgpu_safe_mult_u32((i), 4U)))
+#define mc_device_enable__size_1_v()                               (0x00000001U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pbdma_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pbdma_ga10b.h
new file mode 100644
index 000000000..27a83fae3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pbdma_ga10b.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PBDMA_GA10B_H
+#define NVGPU_HW_PBDMA_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pbdma_gp_entry1_r()                                        (0x10000004U)
+#define pbdma_gp_entry1_length_f(v)                ((U32(v) & 0x1fffffU) << 10U)
+#define pbdma_gp_base_r(i)\
+		(nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_base_offset_f(v)                 ((U32(v) & 0x1fffffffU) << 3U)
+#define pbdma_gp_base_rsvd_s()                                              (3U)
+#define pbdma_gp_base_hi_r(i)\
+		(nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_base_hi_offset_f(v)                    ((U32(v) & 0xffU) << 0U)
+#define pbdma_gp_base_hi_limit2_f(v)                   ((U32(v) & 0x1fU) << 16U)
+#define pbdma_gp_fetch_r(i)\
+		(nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_get_r(i)\
+		(nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_put_r(i)\
+		(nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_get_r(i)\
+		(nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_get_hi_r(i)\
+		(nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_put_r(i)\
+		(nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_put_hi_r(i)\
+		(nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_pb_header_r(i)\
+		(nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_pb_header_method_zero_f()                                   (0x0U)
+#define pbdma_pb_header_subchannel_zero_f()                               (0x0U)
+#define pbdma_pb_header_level_main_f()                                    (0x0U)
+#define pbdma_pb_header_first_true_f()                               (0x400000U)
+#define pbdma_pb_header_type_inc_f()                               (0x20000000U)
+#define pbdma_pb_header_type_non_inc_f()                           (0x60000000U)
+#define pbdma_hdr_shadow_r(i)\
+		(nvgpu_safe_add_u32(0x0004006cU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_shadow_0_r(i)\
+		(nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_gp_shadow_1_r(i)\
+		(nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_subdevice_r(i)\
+		(nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_subdevice_id_f(v)                        ((U32(v) & 0xfffU) << 0U)
+#define pbdma_subdevice_status_active_f()                          (0x10000000U)
+#define pbdma_subdevice_channel_dma_enable_f()                     (0x20000000U)
+#define pbdma_method0_r(i)\
+		(nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_method0_fifo_size_v()                                (0x00000004U)
+#define pbdma_method0_addr_f(v)                        ((U32(v) & 0xfffU) << 2U)
+#define pbdma_method0_addr_v(r)                           (((r) >> 2U) & 0xfffU)
+#define pbdma_method0_subch_v(r)                           (((r) >> 16U) & 0x7U)
+#define pbdma_method0_first_true_f()                                 (0x400000U)
+#define pbdma_method0_valid_true_f()                               (0x80000000U)
+#define pbdma_method1_r(i)\
+		(nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_method2_r(i)\
+		(nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_method3_r(i)\
+		(nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_acquire_r(i)\
+		(nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_acquire_retry_man_2_f()                                     (0x2U)
+#define pbdma_acquire_retry_exp_2_f()                                   (0x100U)
+#define pbdma_acquire_timeout_exp_f(v)                  ((U32(v) & 0xfU) << 11U)
+#define pbdma_acquire_timeout_exp_max_v()                          (0x0000000fU)
+#define pbdma_acquire_timeout_man_f(v)               ((U32(v) & 0xffffU) << 15U)
+#define pbdma_acquire_timeout_man_max_v()                          (0x0000ffffU)
+#define pbdma_acquire_timeout_en_enable_f()                        (0x80000000U)
+#define pbdma_signature_r(i)\
+		(nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_signature_sw_zero_f()                                       (0x0U)
+#define pbdma_config_r(i)\
+		(nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_config_auth_level_privileged_f()                          (0x100U)
+#define pbdma_config_userd_writeback_m()                      (U32(0x1U) << 12U)
+#define pbdma_config_userd_writeback_enable_f()                        (0x1000U)
+#define pbdma_hce_ctrl_r(i)\
+		(nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_hce_ctrl_hce_priv_mode_yes_f()                             (0x20U)
+#define pbdma_intr_0_r(i)\
+		(nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_intr_0__size_1_v()                                   (0x00000006U)
+#define pbdma_intr_0_gpfifo_pending_f()                                (0x2000U)
+#define pbdma_intr_0_gpptr_pending_f()                                 (0x4000U)
+#define pbdma_intr_0_gpentry_pending_f()                               (0x8000U)
+#define pbdma_intr_0_gpcrc_pending_f()                                (0x10000U)
+#define pbdma_intr_0_pbptr_pending_f()                                (0x20000U)
+#define pbdma_intr_0_pbentry_pending_f()                              (0x40000U)
+#define pbdma_intr_0_pbcrc_pending_f()                                (0x80000U)
+#define pbdma_intr_0_method_pending_f()                              (0x200000U)
+#define pbdma_intr_0_device_pending_f()                              (0x800000U)
+#define pbdma_intr_0_eng_reset_pending_f()                          (0x1000000U)
+#define pbdma_intr_0_semaphore_pending_f()                          (0x2000000U)
+#define pbdma_intr_0_acquire_pending_f()                            (0x4000000U)
+#define pbdma_intr_0_pri_pending_f()                                (0x8000000U)
+#define pbdma_intr_0_pbseg_pending_f()                             (0x40000000U)
+#define pbdma_intr_0_signature_pending_f()                         (0x80000000U)
+#define pbdma_intr_1_r(i)\
+		(nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_intr_1_ctxnotvalid_pending_f()                       (0x80000000U)
+#define pbdma_intr_0_en_set_tree_r(i,j)\
+		(nvgpu_safe_add_u32(nvgpu_safe_add_u32(0x00040170U, \
+		nvgpu_safe_mult_u32((i), 2048U)), nvgpu_safe_mult_u32((j), 4U)))
+#define pbdma_intr_0_en_set_tree__size_1_v()                       (0x00000006U)
+#define pbdma_intr_0_en_set_tree_gpfifo_enabled_f()                    (0x2000U)
+#define pbdma_intr_0_en_set_tree_gpptr_enabled_f()                     (0x4000U)
+#define pbdma_intr_0_en_set_tree_gpentry_enabled_f()                   (0x8000U)
+#define pbdma_intr_0_en_set_tree_gpcrc_enabled_f()                    (0x10000U)
+#define pbdma_intr_0_en_set_tree_pbptr_enabled_f()                    (0x20000U)
+#define pbdma_intr_0_en_set_tree_pbentry_enabled_f()                  (0x40000U)
+#define pbdma_intr_0_en_set_tree_pbcrc_enabled_f()                    (0x80000U)
+#define pbdma_intr_0_en_set_tree_method_enabled_f()                  (0x200000U)
+#define pbdma_intr_0_en_set_tree_device_enabled_f()                  (0x800000U)
+#define pbdma_intr_0_en_set_tree_eng_reset_enabled_f()              (0x1000000U)
+#define pbdma_intr_0_en_set_tree_semaphore_enabled_f()              (0x2000000U)
+#define pbdma_intr_0_en_set_tree_acquire_enabled_f()                (0x4000000U)
+#define pbdma_intr_0_en_set_tree_pri_enabled_f()                    (0x8000000U)
+#define pbdma_intr_0_en_set_tree_pbseg_enabled_f()                 (0x40000000U)
+#define pbdma_intr_0_en_set_tree_signature_enabled_f()             (0x80000000U)
+#define pbdma_intr_0_en_clear_tree_r(i,j)\
+		(nvgpu_safe_add_u32(nvgpu_safe_add_u32(0x00040190U, \
+		nvgpu_safe_mult_u32((i), 2048U)), nvgpu_safe_mult_u32((j), 4U)))
+#define pbdma_intr_0_en_clear_tree__size_1_v()                     (0x00000006U)
+#define pbdma_intr_0_en_clear_tree__size_2_v()                     (0x00000002U)
+#define pbdma_intr_0_en_clear_tree_gpfifo_enabled_f()                  (0x2000U)
+#define pbdma_intr_0_en_clear_tree_gpptr_enabled_f()                   (0x4000U)
+#define pbdma_intr_0_en_clear_tree_gpentry_enabled_f()                 (0x8000U)
+#define pbdma_intr_0_en_clear_tree_gpcrc_enabled_f()                  (0x10000U)
+#define pbdma_intr_0_en_clear_tree_pbptr_enabled_f()                  (0x20000U)
+#define pbdma_intr_0_en_clear_tree_pbentry_enabled_f()                (0x40000U)
+#define pbdma_intr_0_en_clear_tree_pbcrc_enabled_f()                  (0x80000U)
+#define pbdma_intr_0_en_clear_tree_method_enabled_f()                (0x200000U)
+#define pbdma_intr_0_en_clear_tree_device_enabled_f()                (0x800000U)
+#define pbdma_intr_0_en_clear_tree_eng_reset_enabled_f()            (0x1000000U)
+#define pbdma_intr_0_en_clear_tree_semaphore_enabled_f()            (0x2000000U)
+#define pbdma_intr_0_en_clear_tree_acquire_enabled_f()              (0x4000000U)
+#define pbdma_intr_0_en_clear_tree_pri_enabled_f()                  (0x8000000U)
+#define pbdma_intr_0_en_clear_tree_pbseg_enabled_f()               (0x40000000U)
+#define pbdma_intr_0_en_clear_tree_signature_enabled_f()           (0x80000000U)
+#define pbdma_intr_1_en_set_tree_r(i,j)\
+		(nvgpu_safe_add_u32(nvgpu_safe_add_u32(0x00040180U, \
+		nvgpu_safe_mult_u32((i), 2048U)), nvgpu_safe_mult_u32((j), 4U)))
+#define pbdma_intr_1_en_set_tree_hce_re_illegal_op_enabled_f()            (0x1U)
+#define pbdma_intr_1_en_set_tree_hce_re_alignb_enabled_f()                (0x2U)
+#define pbdma_intr_1_en_set_tree_hce_priv_enabled_f()                     (0x4U)
+#define pbdma_intr_1_en_set_tree_hce_illegal_mthd_enabled_f()             (0x8U)
+#define pbdma_intr_1_en_set_tree_hce_illegal_class_enabled_f()           (0x10U)
+#define pbdma_intr_1_en_set_tree_ctxnotvalid_enabled_f()           (0x80000000U)
+#define pbdma_intr_1_en_clear_tree_r(i,j)\
+		(nvgpu_safe_add_u32(nvgpu_safe_add_u32(0x000401a0U, \
+		nvgpu_safe_mult_u32((i), 2048U)), nvgpu_safe_mult_u32((j), 4U)))
+#define pbdma_intr_1_en_clear_tree_hce_re_illegal_op_enabled_f()          (0x1U)
+#define pbdma_intr_1_en_clear_tree_hce_re_alignb_enabled_f()              (0x2U)
+#define pbdma_intr_1_en_clear_tree_hce_priv_enabled_f()                   (0x4U)
+#define pbdma_intr_1_en_clear_tree_hce_illegal_mthd_enabled_f()           (0x8U)
+#define pbdma_intr_1_en_clear_tree_hce_illegal_class_enabled_f()         (0x10U)
+#define pbdma_intr_1_en_clear_tree_ctxnotvalid_enabled_f()         (0x80000000U)
+#define pbdma_udma_nop_r()                                         (0x00000008U)
+#define pbdma_target_r(i)\
+		(nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_target_engine_f(v)                         ((U32(v) & 0x3U) << 0U)
+#define pbdma_target_eng_ctx_valid_true_f()                           (0x10000U)
+#define pbdma_target_ce_ctx_valid_true_f()                            (0x20000U)
+#define pbdma_set_channel_info_r(i)\
+		(nvgpu_safe_add_u32(0x000400fcU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_set_channel_info_veid_f(v)                ((U32(v) & 0x3fU) << 8U)
+#define pbdma_set_channel_info_chid_f(v)              ((U32(v) & 0xfffU) << 16U)
+#define pbdma_status_sched_r(i)\
+		(nvgpu_safe_add_u32(0x0004015cU, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_status_sched_tsgid_v(r)                     (((r) >> 0U) & 0xfffU)
+#define pbdma_status_sched_chan_status_v(r)                (((r) >> 13U) & 0x7U)
+#define pbdma_status_sched_chan_status_valid_v()                   (0x00000001U)
+#define pbdma_status_sched_chan_status_chsw_save_v()               (0x00000005U)
+#define pbdma_status_sched_chan_status_chsw_load_v()               (0x00000006U)
+#define pbdma_status_sched_chan_status_chsw_switch_v()             (0x00000007U)
+#define pbdma_status_sched_next_tsgid_v(r)               (((r) >> 16U) & 0xfffU)
+#define pbdma_intr_notify_r(i)\
+		(nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_intr_notify_vector_f(v)                  ((U32(v) & 0xfffU) << 0U)
+#define pbdma_intr_notify_ctrl_gsp_disable_f()                            (0x0U)
+#define pbdma_intr_notify_ctrl_cpu_enable_f()                      (0x80000000U)
+#define pbdma_cfg0_r(i)\
+		(nvgpu_safe_add_u32(0x00040104U, nvgpu_safe_mult_u32((i), 2048U)))
+#define pbdma_cfg0__size_1_v()                                     (0x00000006U)
+#define pbdma_cfg0_pbdma_fault_id_v(r)                    (((r) >> 0U) & 0x3ffU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h
new file mode 100644
index 000000000..0a27088e7
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PERF_GA10B_H
+#define NVGPU_HW_PERF_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define perf_pmmgpc_perdomain_offset_v()                           (0x00000200U)
+#define perf_pmmsys_perdomain_offset_v()                           (0x00000200U)
+#define perf_pmmgpc_base_v()                                       (0x00180000U)
+#define perf_pmmgpc_extent_v()                                     (0x00183fffU)
+#define perf_pmmsys_base_v()                                       (0x00260000U)
+#define perf_pmmsys_extent_v()                                     (0x00263fffU)
+#define perf_pmmfbp_base_v()                                       (0x00200000U)
+#define perf_pmmfbp_extent_v()                                     (0x00203fffU)
+#define perf_pmasys_control_r()                                    (0x0024a000U)
+#define perf_pmasys_channel_control_r(i)\
+		(nvgpu_safe_add_u32(0x0024a730U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_control__size_1_v()                    (0x00000001U)
+#define perf_pmasys_channel_control_membuf_status_overflowed_f()         (0x10U)
+#define perf_pmasys_channel_control_membuf_clear_status_doit_f()         (0x20U)
+#define perf_pmasys_channel_control_user_r(i)\
+		(nvgpu_safe_add_u32(0x0024a620U, nvgpu_safe_mult_u32((i), 384U)))
+#define perf_pmasys_channel_control_user__size_1_v()               (0x00000001U)
+#define perf_pmasys_channel_control_user_stream_m()            (U32(0x1U) << 0U)
+#define perf_pmasys_channel_control_user_stream_enable_f()                (0x1U)
+#define perf_pmasys_channel_control_user_stream_disable_f()               (0x0U)
+#define perf_pmasys_channel_control_user_update_bytes_m()     (U32(0x1U) << 31U)
+#define perf_pmasys_channel_control_user_update_bytes_doit_f()     (0x80000000U)
+#define perf_pmasys_channel_mem_block_r(i)\
+		(nvgpu_safe_add_u32(0x0024a638U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_mem_block__size_1_v()                  (0x00000001U)
+#define perf_pmasys_channel_mem_block_base_f(v)    ((U32(v) & 0xfffffffU) << 0U)
+#define perf_pmasys_channel_mem_block_target_f(v)       ((U32(v) & 0x3U) << 28U)
+#define perf_pmasys_channel_mem_block_target_lfb_f()                      (0x0U)
+#define perf_pmasys_channel_mem_block_target_sys_coh_f()           (0x20000000U)
+#define perf_pmasys_channel_mem_block_target_sys_ncoh_f()          (0x30000000U)
+#define perf_pmasys_channel_mem_block_valid_true_f()               (0x80000000U)
+#define perf_pmasys_channel_mem_block_valid_false_f()                     (0x0U)
+#define perf_pmasys_channel_outbase_r(i)\
+		(nvgpu_safe_add_u32(0x0024a644U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_outbase__size_1_v()                    (0x00000001U)
+#define perf_pmasys_channel_outbaseupper_r(i)\
+		(nvgpu_safe_add_u32(0x0024a648U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_outbaseupper__size_1_v()               (0x00000001U)
+#define perf_pmasys_channel_outbaseupper_ptr_f(v)       ((U32(v) & 0xffU) << 0U)
+#define perf_pmasys_channel_outsize_r(i)\
+		(nvgpu_safe_add_u32(0x0024a64cU, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_outsize__size_1_v()                    (0x00000001U)
+#define perf_pmasys_channel_mem_head_r(i)\
+		(nvgpu_safe_add_u32(0x0024a650U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_mem_head__size_1_v()                   (0x00000001U)
+#define perf_pmasys_channel_mem_bytes_r(i)\
+		(nvgpu_safe_add_u32(0x0024a654U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_mem_bytes__size_1_v()                  (0x00000001U)
+#define perf_pmasys_channel_mem_bump_r(i)\
+		(nvgpu_safe_add_u32(0x0024a624U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_mem_bump__size_1_v()                   (0x00000001U)
+#define perf_pmasys_channel_mem_bytes_addr_r(i)\
+		(nvgpu_safe_add_u32(0x0024a658U, nvgpu_safe_mult_u32((i), 4U)))
+#define perf_pmasys_channel_mem_bytes_addr__size_1_v()             (0x00000001U)
+#define perf_pmasys_channel_mem_bytes_addr_ptr_f(v)\
+				((U32(v) & 0x3fffffffU) << 2U)
+#define perf_pmasys_channel_mem_bytes_addr_ptr_b()                          (2U)
+#define perf_pmasys_enginestatus_r()                               (0x0024a75cU)
+#define perf_pmasys_enginestatus_rbufempty_v(r)             (((r) >> 4U) & 0x1U)
+#define perf_pmasys_enginestatus_rbufempty_empty_v()               (0x00000001U)
+#define perf_pmasys_enginestatus_rbufempty_empty_f()                     (0x10U)
+#define perf_pmasys_enginestatus_status_v(r)                (((r) >> 0U) & 0x7U)
+#define perf_pmasys_enginestatus_status_empty_v()                  (0x00000000U)
+#define perf_pmasys_controlreg_r()                                 (0x0024a03cU)
+#define perf_pmasys_controlreg_legacy_mode_m()                 (U32(0x1U) << 0U)
+#define perf_pmasys_controlreg_legacy_mode_enable_f()                     (0x0U)
+#define perf_pmasys_controlreg_legacy_mode_disable_f()                    (0x1U)
+#define perf_pmmsys_engine_sel_r(i)\
+		(nvgpu_safe_add_u32(0x0026006cU, nvgpu_safe_mult_u32((i), 512U)))
+#define perf_pmmsys_engine_sel__size_1_v()                         (0x0000000cU)
+#define perf_pmmfbp_engine_sel_r(i)\
+		(nvgpu_safe_add_u32(0x0020006cU, nvgpu_safe_mult_u32((i), 512U)))
+#define perf_pmmfbp_engine_sel__size_1_v()                         (0x00000005U)
+#define perf_pmmgpc_engine_sel_r(i)\
+		(nvgpu_safe_add_u32(0x0018006cU, nvgpu_safe_mult_u32((i), 512U)))
+#define perf_pmmgpc_engine_sel__size_1_v()                         (0x00000010U)
+#define perf_pmmsys_control_r(i)\
+		(nvgpu_safe_add_u32(0x0026009cU, nvgpu_safe_mult_u32((i), 512U)))
+#define perf_pmmfbp_fbps_control_r(i)\
+		(nvgpu_safe_add_u32(0x0027c09cU, nvgpu_safe_mult_u32((i), 512U)))
+#define perf_pmmgpc_gpcs_control_r(i)\
+		(nvgpu_safe_add_u32(0x0027809cU, nvgpu_safe_mult_u32((i), 512U)))
+#define perf_pmmsysrouter_global_cntrl_r()                         (0x00248000U)
+#define perf_pmmsysrouter_global_cntrl_hs_stream_enable_m()    (U32(0x1U) << 8U)
+#define perf_pmmsysrouter_global_cntrl_hs_stream_enable_true_f()        (0x100U)
+#define perf_pmmsysrouter_global_cntrl_hs_stream_enable_false_f()         (0x0U)
+#define perf_pmmgpcrouter_global_cntrl_r()                         (0x00244000U)
+#define perf_pmmfbprouter_global_cntrl_r()                         (0x00246000U)
+#define perf_pmmsysrouter_hs_config_r()                            (0x00248150U)
+#define perf_pmmgpcrouter_hs_config_r()                            (0x00244150U)
+#define perf_pmmfbprouter_hs_config_r()                            (0x00246150U)
+#define perf_pmmsysrouter_perfmonstatus_r()                        (0x00248014U)
+#define perf_pmmsysrouter_enginestatus_r()                         (0x00248010U)
+#define perf_pmmsysrouter_enginestatus_status_v(r)          (((r) >> 0U) & 0x7U)
+#define perf_pmmsysrouter_enginestatus_status_empty_v()            (0x00000000U)
+#define perf_pmmsysrouter_enginestatus_status_quiescent_v()        (0x00000003U)
+#define perf_pmmgpcrouter_perfmonstatus_r()                        (0x00244014U)
+#define perf_pmmgpcrouter_enginestatus_r()                         (0x00244010U)
+#define perf_pmmfbprouter_perfmonstatus_r()                        (0x00246014U)
+#define perf_pmmfbprouter_enginestatus_r()                         (0x00246010U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h
new file mode 100644
index 000000000..82486985b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PGSP_GA10B_H
+#define NVGPU_HW_PGSP_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pgsp_falcon2_gsp_base_r()                                  (0x00111000U)
+#define pgsp_falcon_irqsset_r()                                    (0x00110000U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pram_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pram_ga10b.h
new file mode 100644
index 000000000..87c9afc1a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pram_ga10b.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRAM_GA10B_H
+#define NVGPU_HW_PRAM_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_fbp_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_fbp_ga10b.h
new file mode 100644
index 000000000..b97ac9fe2
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_fbp_ga10b.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRI_FBP_GA10B_H
+#define NVGPU_HW_PRI_FBP_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pri_fbp_fbp0_priv_error_adr_r()                            (0x00128120U)
+#define pri_fbp_fbp0_priv_error_wrdat_r()                          (0x00128124U)
+#define pri_fbp_fbp0_priv_error_info_r()                           (0x00128128U)
+#define pri_fbp_fbp0_priv_error_info_subid_v(r)           (((r) >> 24U) & 0xffU)
+#define pri_fbp_fbp0_priv_error_info_local_ordering_v(r)   (((r) >> 22U) & 0x1U)
+#define pri_fbp_fbp0_priv_error_info_priv_level_v(r)       (((r) >> 20U) & 0x3U)
+#define pri_fbp_fbp0_priv_error_info_priv_master_v(r)      (((r) >> 0U) & 0xffU)
+#define pri_fbp_fbp0_priv_error_code_r()                           (0x0012812cU)
+#define pri_fbp_pri_fence_r()                                      (0x001281fcU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_gpc_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_gpc_ga10b.h
new file mode 100644
index 000000000..28322e25c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_gpc_ga10b.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRI_GPC_GA10B_H
+#define NVGPU_HW_PRI_GPC_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pri_gpc_gpc0_priv_error_adr_r()                            (0x00124120U)
+#define pri_gpc_gpc0_priv_error_wrdat_r()                          (0x00124124U)
+#define pri_gpc_gpc0_priv_error_info_r()                           (0x00124128U)
+#define pri_gpc_gpc0_priv_error_info_subid_v(r)           (((r) >> 24U) & 0xffU)
+#define pri_gpc_gpc0_priv_error_info_local_ordering_v(r)   (((r) >> 22U) & 0x1U)
+#define pri_gpc_gpc0_priv_error_info_priv_level_v(r)       (((r) >> 20U) & 0x3U)
+#define pri_gpc_gpc0_priv_error_info_priv_master_v(r)      (((r) >> 0U) & 0xffU)
+#define pri_gpc_gpc0_priv_error_code_r()                           (0x0012412cU)
+#define pri_gpc_pri_fence_r()                                      (0x001241fcU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_ringmaster_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_ringmaster_ga10b.h
new file mode 100644
index 000000000..3e26e5dd6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_ringmaster_ga10b.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRI_RINGMASTER_GA10B_H
+#define NVGPU_HW_PRI_RINGMASTER_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pri_ringmaster_command_r()                                 (0x0012004cU)
+#define pri_ringmaster_command_cmd_m()                        (U32(0x3fU) << 0U)
+#define pri_ringmaster_command_cmd_v(r)                    (((r) >> 0U) & 0x3fU)
+#define pri_ringmaster_command_cmd_no_cmd_v()                      (0x00000000U)
+#define pri_ringmaster_command_cmd_ack_interrupt_f()                      (0x2U)
+#define pri_ringmaster_command_cmd_enumerate_and_start_ring_f()           (0x4U)
+#define pri_ringmaster_master_ring_start_results_r()               (0x00120050U)
+#define pri_ringmaster_master_ring_start_results_connectivity_pass_f()    (0x1U)
+#define pri_ringmaster_intr_status0_r()                            (0x00120058U)
+#define pri_ringmaster_intr_status0_ring_start_conn_fault_v(r)\
+				(((r) >> 0U) & 0x1U)
+#define pri_ringmaster_intr_status0_disconnect_fault_v(r)   (((r) >> 1U) & 0x1U)
+#define pri_ringmaster_intr_status0_overflow_fault_v(r)     (((r) >> 2U) & 0x1U)
+#define pri_ringmaster_intr_status0_ring_enum_fault_v(r)    (((r) >> 3U) & 0x1U)
+#define pri_ringmaster_intr_status0_gpc_rs_map_config_fault_v(r)\
+				(((r) >> 4U) & 0x1U)
+#define pri_ringmaster_intr_status0_gbl_write_error_fbp_v(r)\
+				(((r) >> 16U) & 0xffffU)
+#define pri_ringmaster_intr_status0_gbl_write_error_sys_v(r)\
+				(((r) >> 8U) & 0x1U)
+#define pri_ringmaster_intr_status1_r()                            (0x0012005cU)
+#define pri_ringmaster_enum_fbp_r()                                (0x00120074U)
+#define pri_ringmaster_enum_fbp_count_v(r)                 (((r) >> 0U) & 0x1fU)
+#define pri_ringmaster_enum_gpc_r()                                (0x00120078U)
+#define pri_ringmaster_enum_gpc_count_v(r)                 (((r) >> 0U) & 0x1fU)
+#define pri_ringmaster_enum_ltc_r()                                (0x0012006cU)
+#define pri_ringmaster_gpc_rs_map_r(i)\
+		(nvgpu_safe_add_u32(0x001200c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define pri_ringmaster_gpc_rs_map_smc_enable_f(v)       ((U32(v) & 0x1U) << 31U)
+#define pri_ringmaster_gpc_rs_map_smc_enable_m()              (U32(0x1U) << 31U)
+#define pri_ringmaster_gpc_rs_map_smc_enable_true_v()              (0x00000001U)
+#define pri_ringmaster_gpc_rs_map_smc_enable_false_v()             (0x00000000U)
+#define pri_ringmaster_gpc_rs_map_smc_engine_id_f(v)     ((U32(v) & 0x1U) << 8U)
+#define pri_ringmaster_gpc_rs_map_smc_engine_id_m()            (U32(0x1U) << 8U)
+#define pri_ringmaster_gpc_rs_map_smc_engine_local_cluster_id_f(v)\
+				((U32(v) & 0x1U) << 0U)
+#define pri_ringmaster_gpc_rs_map_smc_engine_local_cluster_id_m()\
+				(U32(0x1U) << 0U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_ringstation_sys_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_ringstation_sys_ga10b.h
new file mode 100644
index 000000000..1eac1493d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_ringstation_sys_ga10b.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRI_RINGSTATION_SYS_GA10B_H
+#define NVGPU_HW_PRI_RINGSTATION_SYS_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pri_ringstation_sys_master_ring_start_results_r()          (0x00120050U)
+#define pri_ringstation_sys_master_ring_start_results_connectivity_pass_f()\
+				(0x1U)
+#define pri_ringstation_sys_bar0_to_pri_window_r()                 (0x00122144U)
+#define pri_ringstation_sys_bar0_to_pri_window_index_f(v)\
+				((U32(v) & 0x3fU) << 0U)
+#define pri_ringstation_sys_bar0_to_pri_window_index_m()      (U32(0x3fU) << 0U)
+#define pri_ringstation_sys_bar0_to_pri_window_enable_f(v)\
+				((U32(v) & 0x1U) << 31U)
+#define pri_ringstation_sys_bar0_to_pri_window_enable_m()     (U32(0x1U) << 31U)
+#define pri_ringstation_sys_bar0_to_pri_window_enable_enable_v()   (0x00000001U)
+#define pri_ringstation_sys_bar0_to_pri_window_enable_disable_v()  (0x00000000U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_sys_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_sys_ga10b.h
new file mode 100644
index 000000000..2c71724f6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pri_sys_ga10b.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRI_SYS_GA10B_H
+#define NVGPU_HW_PRI_SYS_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pri_sys_priv_error_adr_r()                                 (0x00122120U)
+#define pri_sys_priv_error_wrdat_r()                               (0x00122124U)
+#define pri_sys_priv_error_info_r()                                (0x00122128U)
+#define pri_sys_priv_error_info_subid_v(r)                (((r) >> 24U) & 0xffU)
+#define pri_sys_priv_error_info_local_ordering_v(r)        (((r) >> 22U) & 0x1U)
+#define pri_sys_priv_error_info_priv_level_v(r)            (((r) >> 20U) & 0x3U)
+#define pri_sys_priv_error_info_priv_master_v(r)           (((r) >> 0U) & 0xffU)
+#define pri_sys_priv_error_code_r()                                (0x0012212cU)
+#define pri_sys_pri_fence_r()                                      (0x001221fcU)
+#define pri_sys_pri_error_r()                                      (0x00000000U)
+#define pri_sys_pri_error_code_v(r)                    (((r) >> 8U) & 0xffffffU)
+#define pri_sys_pri_error_code_host_fecs_err_v()                   (0x00bad00fU)
+#define pri_sys_pri_error_code_host_pri_timeout_v()                (0x00bad001U)
+#define pri_sys_pri_error_code_host_fb_ack_timeout_v()             (0x00bad0b0U)
+#define pri_sys_pri_error_code_fecs_pri_timeout_v()                (0x00badf10U)
+#define pri_sys_pri_error_code_fecs_pri_orphan_v()                 (0x00badf20U)
+#define pri_sys_pri_error_code_fecs_dead_ring_v()                  (0x00badf30U)
+#define pri_sys_pri_error_code_fecs_trap_v()                       (0x00badf40U)
+#define pri_sys_pri_error_code_fecs_pri_client_err_v()             (0x00badf50U)
+#define pri_sys_pri_error_code_fecs_pri_lock_from_security_sensor_v()\
+				(0x00badf60U)
+#define pri_sys_pri_error_extra_v(r)                       (((r) >> 0U) & 0xffU)
+#define pri_sys_pri_error_extra_async_idle_v()                     (0x00000001U)
+#define pri_sys_pri_error_extra_extra_sync_req_v()                 (0x00000020U)
+#define pri_sys_pri_error_extra_no_such_address_v()                (0x00000040U)
+#define pri_sys_pri_error_fecs_pri_route_err_extra_write_only_v()  (0x00000045U)
+#define pri_sys_pri_error_local_priv_ring_extra_no_such_target_v() (0x00000080U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_priscv_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_priscv_ga10b.h
new file mode 100644
index 000000000..19bfc59e8
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_priscv_ga10b.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PRISCV_GA10B_H
+#define NVGPU_HW_PRISCV_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define priscv_priscv_cpuctl_r()                                   (0x00000388U)
+#define priscv_priscv_cpuctl_startcpu_true_f()                            (0x1U)
+#define priscv_priscv_cpuctl_halted_v(r)                    (((r) >> 4U) & 0x1U)
+#define priscv_priscv_br_retcode_r()                               (0x0000065cU)
+#define priscv_priscv_br_retcode_result_v(r)                (((r) >> 0U) & 0x3U)
+#define priscv_priscv_br_retcode_result_fail_f()                          (0x2U)
+#define priscv_priscv_br_retcode_result_pass_f()                          (0x3U)
+#define priscv_priscv_bcr_ctrl_r()                                 (0x00000668U)
+#define priscv_priscv_bcr_dmaaddr_fmccode_lo_r()                   (0x00000678U)
+#define priscv_priscv_bcr_dmaaddr_fmccode_hi_r()                   (0x0000067cU)
+#define priscv_priscv_bcr_dmaaddr_fmcdata_lo_r()                   (0x00000680U)
+#define priscv_priscv_bcr_dmaaddr_fmcdata_hi_r()                   (0x00000684U)
+#define priscv_priscv_bcr_dmaaddr_pkcparam_lo_r()                  (0x00000670U)
+#define priscv_priscv_bcr_dmaaddr_pkcparam_hi_r()                  (0x00000674U)
+#define priscv_priscv_bcr_dmacfg_r()                               (0x0000066cU)
+#define priscv_priscv_bcr_dmacfg_target_noncoherent_system_f()            (0x2U)
+#define priscv_priscv_bcr_dmacfg_lock_locked_f()                   (0x80000000U)
+#define priscv_riscv_irqmask_r()                                   (0x00000528U)
+#define priscv_riscv_irqdest_r()                                   (0x0000052cU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_proj_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_proj_ga10b.h
new file mode 100644
index 000000000..bdd6b4c96
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_proj_ga10b.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PROJ_GA10B_H
+#define NVGPU_HW_PROJ_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define proj_gpc_base_v()                                          (0x00500000U)
+#define proj_gpc_shared_base_v()                                   (0x00418000U)
+#define proj_gpc_stride_v()                                        (0x00008000U)
+#define proj_gpc_priv_stride_v()                                   (0x00000800U)
+#define proj_gpc_addr_width_v()                                    (0x0000000fU)
+#define proj_fbp_priv_stride_v()                                   (0x00000800U)
+#define proj_ltc_stride_v()                                        (0x00002000U)
+#define proj_lts_stride_v()                                        (0x00000200U)
+#define proj_ppc_in_gpc_base_v()                                   (0x00003000U)
+#define proj_ppc_in_gpc_shared_base_v()                            (0x00003e00U)
+#define proj_ppc_in_gpc_stride_v()                                 (0x00000200U)
+#define proj_rop_base_v()                                          (0x00410000U)
+#define proj_rop_shared_base_v()                                   (0x00408800U)
+#define proj_rop_stride_v()                                        (0x00000400U)
+#define proj_rop_in_gpc_base_v()                                   (0x00003800U)
+#define proj_rop_in_gpc_shared_base_v()                            (0x00003c00U)
+#define proj_rop_in_gpc_pri_shared_index_v()                       (0x00000002U)
+#define proj_rop_in_gpc_stride_v()                                 (0x00000200U)
+#define proj_tpc_in_gpc_base_v()                                   (0x00004000U)
+#define proj_tpc_in_gpc_stride_v()                                 (0x00000800U)
+#define proj_tpc_in_gpc_shared_base_v()                            (0x00001800U)
+#define proj_tpc_addr_width_v()                                    (0x0000000bU)
+#define proj_smpc_base_v()                                         (0x00000200U)
+#define proj_smpc_shared_base_v()                                  (0x00000300U)
+#define proj_smpc_unique_base_v()                                  (0x00000600U)
+#define proj_smpc_stride_v()                                       (0x00000100U)
+#define proj_host_num_engines_v()                                  (0x00000006U)
+#define proj_host_num_pbdma_v()                                    (0x00000006U)
+#define proj_scal_litter_num_tpc_per_gpc_v()                       (0x00000004U)
+#define proj_scal_litter_num_fbps_v()                              (0x00000002U)
+#define proj_scal_litter_num_fbpas_v()                             (0x00000000U)
+#define proj_scal_litter_num_gpcs_v()                              (0x00000002U)
+#define proj_scal_litter_num_pes_per_gpc_v()                       (0x00000002U)
+#define proj_scal_litter_num_zcull_banks_v()                       (0x00000004U)
+#define proj_scal_litter_num_sm_per_tpc_v()                        (0x00000002U)
+#define proj_scal_litter_num_ltc_lts_sets_v()                      (0x00000100U)
+#define proj_scal_litter_num_ltc_lts_ways_v()                      (0x00000010U)
+#define proj_sm_unique_base_v()                                    (0x00000700U)
+#define proj_sm_shared_base_v()                                    (0x00000680U)
+#define proj_sm_stride_v()                                         (0x00000080U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pwr_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pwr_ga10b.h
new file mode 100644
index 000000000..8e7b7e260
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pwr_ga10b.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PWR_GA10B_H
+#define NVGPU_HW_PWR_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define pwr_falcon2_pwr_base_r()                                   (0x0010b000U)
+#define pwr_falcon_irqsset_r()                                     (0x0010a000U)
+#define pwr_falcon_irqsset_swgen0_set_f()                                (0x40U)
+#define pwr_falcon_irqsclr_r()                                     (0x0010a004U)
+#define pwr_falcon_irqstat_r()                                     (0x0010a008U)
+#define pwr_falcon_irqstat_halt_true_f()                                 (0x10U)
+#define pwr_falcon_irqstat_exterr_true_f()                               (0x20U)
+#define pwr_falcon_irqstat_swgen0_true_f()                               (0x40U)
+#define pwr_falcon_irqstat_ext_ecc_parity_true_f()                      (0x400U)
+#define pwr_pmu_ecc_intr_status_r()                                (0x0010abfcU)
+#define pwr_pmu_ecc_intr_status_corrected_m()                  (U32(0x1U) << 0U)
+#define pwr_pmu_ecc_intr_status_uncorrected_m()                (U32(0x1U) << 1U)
+#define pwr_falcon_irqmset_r()                                     (0x0010a010U)
+#define pwr_falcon_irqmset_gptmr_f(v)                    ((U32(v) & 0x1U) << 0U)
+#define pwr_falcon_irqmset_wdtmr_f(v)                    ((U32(v) & 0x1U) << 1U)
+#define pwr_falcon_irqmset_mthd_f(v)                     ((U32(v) & 0x1U) << 2U)
+#define pwr_falcon_irqmset_ctxsw_f(v)                    ((U32(v) & 0x1U) << 3U)
+#define pwr_falcon_irqmset_halt_f(v)                     ((U32(v) & 0x1U) << 4U)
+#define pwr_falcon_irqmset_exterr_f(v)                   ((U32(v) & 0x1U) << 5U)
+#define pwr_falcon_irqmset_swgen0_f(v)                   ((U32(v) & 0x1U) << 6U)
+#define pwr_falcon_irqmset_swgen1_f(v)                   ((U32(v) & 0x1U) << 7U)
+#define pwr_falcon_irqmset_ext_ecc_parity_f(v)          ((U32(v) & 0x1U) << 10U)
+#define pwr_falcon_irqmask_r()                                     (0x0010a018U)
+#define pwr_falcon_irqdest_r()                                     (0x0010a01cU)
+#define pwr_falcon_irqdest_host_gptmr_f(v)               ((U32(v) & 0x1U) << 0U)
+#define pwr_falcon_irqdest_host_wdtmr_f(v)               ((U32(v) & 0x1U) << 1U)
+#define pwr_falcon_irqdest_host_mthd_f(v)                ((U32(v) & 0x1U) << 2U)
+#define pwr_falcon_irqdest_host_ctxsw_f(v)               ((U32(v) & 0x1U) << 3U)
+#define pwr_falcon_irqdest_host_halt_f(v)                ((U32(v) & 0x1U) << 4U)
+#define pwr_falcon_irqdest_host_exterr_f(v)              ((U32(v) & 0x1U) << 5U)
+#define pwr_falcon_irqdest_host_swgen0_f(v)              ((U32(v) & 0x1U) << 6U)
+#define pwr_falcon_irqdest_host_swgen1_f(v)              ((U32(v) & 0x1U) << 7U)
+#define pwr_falcon_irqdest_host_ext_ecc_parity_f(v)     ((U32(v) & 0x1U) << 10U)
+#define pwr_falcon_irqdest_target_gptmr_f(v)            ((U32(v) & 0x1U) << 16U)
+#define pwr_falcon_irqdest_target_wdtmr_f(v)            ((U32(v) & 0x1U) << 17U)
+#define pwr_falcon_irqdest_target_mthd_f(v)             ((U32(v) & 0x1U) << 18U)
+#define pwr_falcon_irqdest_target_ctxsw_f(v)            ((U32(v) & 0x1U) << 19U)
+#define pwr_falcon_irqdest_target_halt_f(v)             ((U32(v) & 0x1U) << 20U)
+#define pwr_falcon_irqdest_target_exterr_f(v)           ((U32(v) & 0x1U) << 21U)
+#define pwr_falcon_irqdest_target_swgen0_f(v)           ((U32(v) & 0x1U) << 22U)
+#define pwr_falcon_irqdest_target_swgen1_f(v)           ((U32(v) & 0x1U) << 23U)
+#define pwr_falcon_irqdest_target_ext_ecc_parity_f(v)   ((U32(v) & 0x1U) << 26U)
+#define pwr_falcon_mailbox1_r()                                    (0x0010a044U)
+#define pwr_falcon_itfen_r()                                       (0x0010a048U)
+#define pwr_falcon_itfen_ctxen_enable_f()                                 (0x1U)
+#define pwr_falcon_os_r()                                          (0x0010a080U)
+#define pwr_falcon_cpuctl_r()                                      (0x0010a100U)
+#define pwr_falcon_cpuctl_startcpu_f(v)                  ((U32(v) & 0x1U) << 1U)
+#define pwr_falcon_cpuctl_alias_r()                                (0x0010a130U)
+#define pwr_falcon_hwcfg2_r()                                      (0x0010a0f4U)
+#define pwr_falcon_hwcfg2_dbgmode_v(r)                      (((r) >> 3U) & 0x1U)
+#define pwr_falcon_hwcfg2_dbgmode_enable_v()                       (0x00000001U)
+#define pwr_falcon_dmatrfbase_r()                                  (0x0010a110U)
+#define pwr_falcon_dmatrfbase1_r()                                 (0x0010a128U)
+#define pwr_falcon_dmatrfmoffs_r()                                 (0x0010a114U)
+#define pwr_falcon_dmatrfcmd_r()                                   (0x0010a118U)
+#define pwr_falcon_dmatrfcmd_imem_f(v)                   ((U32(v) & 0x1U) << 4U)
+#define pwr_falcon_dmatrfcmd_write_f(v)                  ((U32(v) & 0x1U) << 5U)
+#define pwr_falcon_dmatrfcmd_size_f(v)                   ((U32(v) & 0x7U) << 8U)
+#define pwr_falcon_dmatrfcmd_ctxdma_f(v)                ((U32(v) & 0x7U) << 12U)
+#define pwr_falcon_dmatrffboffs_r()                                (0x0010a11cU)
+#define pwr_falcon_exterraddr_r()                                  (0x0010a168U)
+#define pwr_falcon_exterrstat_r()                                  (0x0010a16cU)
+#define pwr_falcon_exterrstat_valid_m()                       (U32(0x1U) << 31U)
+#define pwr_falcon_exterrstat_valid_v(r)                   (((r) >> 31U) & 0x1U)
+#define pwr_falcon_exterrstat_valid_true_v()                       (0x00000001U)
+#define pwr_falcon_dmemc_r(i)\
+		(nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U)))
+#define pwr_falcon_dmemc_offs_f(v)                      ((U32(v) & 0x3fU) << 2U)
+#define pwr_falcon_dmemc_blk_f(v)                     ((U32(v) & 0xffffU) << 8U)
+#define pwr_falcon_dmemc_aincw_f(v)                     ((U32(v) & 0x1U) << 24U)
+#define pwr_falcon_dmemd_r(i)\
+		(nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U)))
+#define pwr_pmu_new_instblk_r()                                    (0x0010a480U)
+#define pwr_pmu_new_instblk_ptr_f(v)               ((U32(v) & 0xfffffffU) << 0U)
+#define pwr_pmu_new_instblk_target_sys_coh_f()                     (0x20000000U)
+#define pwr_pmu_new_instblk_target_sys_ncoh_f()                    (0x30000000U)
+#define pwr_pmu_new_instblk_valid_f(v)                  ((U32(v) & 0x1U) << 30U)
+#define pwr_pmu_mutex_id_r()                                       (0x0010a488U)
+#define pwr_pmu_mutex_id_value_v(r)                        (((r) >> 0U) & 0xffU)
+#define pwr_pmu_mutex_id_value_init_v()                            (0x00000000U)
+#define pwr_pmu_mutex_id_value_not_avail_v()                       (0x000000ffU)
+#define pwr_pmu_mutex_id_release_r()                               (0x0010a48cU)
+#define pwr_pmu_mutex_id_release_value_f(v)             ((U32(v) & 0xffU) << 0U)
+#define pwr_pmu_mutex_id_release_value_m()                    (U32(0xffU) << 0U)
+#define pwr_pmu_mutex_r(i)\
+		(nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_mutex__size_1_v()                                  (0x00000010U)
+#define pwr_pmu_mutex_value_f(v)                        ((U32(v) & 0xffU) << 0U)
+#define pwr_pmu_mutex_value_v(r)                           (((r) >> 0U) & 0xffU)
+#define pwr_pmu_mutex_value_initial_lock_f()                              (0x0U)
+#define pwr_pmu_queue_head_r(i)\
+		(nvgpu_safe_add_u32(0x0010a800U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_queue_head__size_1_v()                             (0x00000008U)
+#define pwr_pmu_queue_head_address_f(v)           ((U32(v) & 0xffffffffU) << 0U)
+#define pwr_pmu_queue_head_address_v(r)              (((r) >> 0U) & 0xffffffffU)
+#define pwr_pmu_queue_tail_r(i)\
+		(nvgpu_safe_add_u32(0x0010a820U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_queue_tail__size_1_v()                             (0x00000008U)
+#define pwr_pmu_queue_tail_address_f(v)           ((U32(v) & 0xffffffffU) << 0U)
+#define pwr_pmu_queue_tail_address_v(r)              (((r) >> 0U) & 0xffffffffU)
+#define pwr_pmu_msgq_head_r()                                      (0x0010a4c8U)
+#define pwr_pmu_msgq_head_val_f(v)                ((U32(v) & 0xffffffffU) << 0U)
+#define pwr_pmu_msgq_head_val_v(r)                   (((r) >> 0U) & 0xffffffffU)
+#define pwr_pmu_msgq_tail_r()                                      (0x0010a4ccU)
+#define pwr_pmu_msgq_tail_val_f(v)                ((U32(v) & 0xffffffffU) << 0U)
+#define pwr_pmu_msgq_tail_val_v(r)                   (((r) >> 0U) & 0xffffffffU)
+#define pwr_pmu_idle_mask_r(i)\
+		(nvgpu_safe_add_u32(0x0010be40U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_idle_mask_gr_enabled_f()                                  (0x1U)
+#define pwr_pmu_idle_mask_ce_2_enabled_f()                           (0x200000U)
+#define pwr_pmu_idle_count_r(i)\
+		(nvgpu_safe_add_u32(0x0010bf80U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_idle_count_value_v(r)                (((r) >> 0U) & 0x7fffffffU)
+#define pwr_pmu_idle_count_reset_f(v)                   ((U32(v) & 0x1U) << 31U)
+#define pwr_pmu_idle_ctrl_r(i)\
+		(nvgpu_safe_add_u32(0x0010bfc0U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_idle_ctrl_value_m()                            (U32(0x3U) << 0U)
+#define pwr_pmu_idle_ctrl_value_busy_f()                                  (0x2U)
+#define pwr_pmu_idle_ctrl_value_always_f()                                (0x3U)
+#define pwr_pmu_idle_ctrl_filter_m()                           (U32(0x1U) << 2U)
+#define pwr_pmu_idle_ctrl_filter_disabled_f()                             (0x0U)
+#define pwr_pmu_idle_mask_supp_r(i)\
+		(nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32((i), 8U)))
+#define pwr_pmu_idle_threshold_r(i)\
+		(nvgpu_safe_add_u32(0x0010be00U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_idle_threshold_value_f(v)         ((U32(v) & 0x7fffffffU) << 0U)
+#define pwr_pmu_idle_intr_r()                                      (0x0010a9e8U)
+#define pwr_pmu_idle_intr_en_f(v)                        ((U32(v) & 0x1U) << 0U)
+#define pwr_pmu_idle_intr_status_r()                               (0x0010a9ecU)
+#define pwr_pmu_idle_intr_status_intr_f(v)               ((U32(v) & 0x1U) << 0U)
+#define pwr_pmu_idle_intr_status_intr_v(r)                  (((r) >> 0U) & 0x1U)
+#define pwr_pmu_idle_mask_1_supp_r(i)\
+		(nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32((i), 8U)))
+#define pwr_pmu_idle_ctrl_supp_r(i)\
+		(nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32((i), 8U)))
+#define pwr_pmu_debug_r(i)\
+		(nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_debug__size_1_v()                                  (0x00000004U)
+#define pwr_pmu_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_mailbox__size_1_v()                                (0x0000000cU)
+#define pwr_pmu_bar0_addr_r()                                      (0x0010a7a0U)
+#define pwr_pmu_bar0_data_r()                                      (0x0010a7a4U)
+#define pwr_pmu_bar0_ctl_r()                                       (0x0010a7acU)
+#define pwr_pmu_bar0_timeout_r()                                   (0x0010a7a8U)
+#define pwr_pmu_bar0_fecs_error_r()                                (0x0010a988U)
+#define pwr_pmu_bar0_host_error_r()                                (0x0010a990U)
+#define pwr_pmu_bar0_error_status_r()                              (0x0010a7b0U)
+#define pwr_pmu_bar0_error_status_timeout_host_m()             (U32(0x1U) << 0U)
+#define pwr_pmu_bar0_error_status_timeout_fecs_m()             (U32(0x1U) << 1U)
+#define pwr_pmu_bar0_error_status_cmd_hwerr_m()                (U32(0x1U) << 2U)
+#define pwr_pmu_bar0_error_status_err_cmd_m()                  (U32(0x1U) << 3U)
+#define pwr_pmu_bar0_error_status_hosterr_m()                 (U32(0x1U) << 30U)
+#define pwr_pmu_bar0_error_status_fecserr_m()                 (U32(0x1U) << 31U)
+#define pwr_pmu_pg_idlefilth_r(i)\
+		(nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_pg_ppuidlefilth_r(i)\
+		(nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_pg_idle_cnt_r(i)\
+		(nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_pg_intren_r(i)\
+		(nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_pmu_falcon_ecc_control_r()                             (0x0010a484U)
+#define pwr_pmu_falcon_ecc_control_inject_corrected_err_f(v)\
+				((U32(v) & 0x1U) << 0U)
+#define pwr_pmu_falcon_ecc_control_inject_uncorrected_err_f(v)\
+				((U32(v) & 0x1U) << 1U)
+#define pwr_pmu_falcon_ecc_status_r()                              (0x0010a6b0U)
+#define pwr_pmu_falcon_ecc_status_corrected_err_imem_m()       (U32(0x1U) << 0U)
+#define pwr_pmu_falcon_ecc_status_corrected_err_dmem_m()       (U32(0x1U) << 1U)
+#define pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m()     (U32(0x1U) << 8U)
+#define pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_m()     (U32(0x1U) << 9U)
+#define pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 16U)
+#define pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_m()\
+				(U32(0x1U) << 18U)
+#define pwr_pmu_falcon_ecc_status_reset_task_f()                   (0x80000000U)
+#define pwr_pmu_falcon_ecc_address_r()                             (0x0010a6b4U)
+#define pwr_pmu_falcon_ecc_address_row_address_v(r)      (((r) >> 0U) & 0xffffU)
+#define pwr_pmu_falcon_ecc_corrected_err_count_r()                 (0x0010a6b8U)
+#define pwr_pmu_falcon_ecc_corrected_err_count_total_s()                   (16U)
+#define pwr_pmu_falcon_ecc_corrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define pwr_pmu_falcon_ecc_uncorrected_err_count_r()               (0x0010a6bcU)
+#define pwr_pmu_falcon_ecc_uncorrected_err_count_total_s()                 (16U)
+#define pwr_pmu_falcon_ecc_uncorrected_err_count_total_v(r)\
+				(((r) >> 0U) & 0xffffU)
+#define pwr_fbif_transcfg_r(i)\
+		(nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32((i), 4U)))
+#define pwr_fbif_transcfg_target_local_fb_f()                             (0x0U)
+#define pwr_fbif_transcfg_target_coherent_sysmem_f()                      (0x1U)
+#define pwr_fbif_transcfg_target_noncoherent_sysmem_f()                   (0x2U)
+#define pwr_fbif_transcfg_mem_type_virtual_f()                            (0x0U)
+#define pwr_fbif_transcfg_mem_type_physical_f()                           (0x4U)
+#define pwr_falcon_engine_r()                                      (0x0010a3c0U)
+#define pwr_falcon_engine_reset_true_f()                                  (0x1U)
+#define pwr_falcon_engine_reset_false_f()                                 (0x0U)
+#define pwr_riscv_irqmask_r()                                      (0x0010b528U)
+#define pwr_riscv_irqdest_r()                                      (0x0010b52cU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ram_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ram_ga10b.h
new file mode 100644
index 000000000..b558c0a95
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ram_ga10b.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_RAM_GA10B_H
+#define NVGPU_HW_RAM_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define ram_in_page_dir_base_target_vid_mem_f()                           (0x0U)
+#define ram_in_page_dir_base_target_sys_mem_coh_f()                       (0x2U)
+#define ram_in_page_dir_base_target_sys_mem_ncoh_f()                      (0x3U)
+#define ram_in_page_dir_base_vol_true_f()                                 (0x4U)
+#define ram_in_use_ver2_pt_format_true_f()                              (0x400U)
+#define ram_in_big_page_size_m()                              (U32(0x1U) << 11U)
+#define ram_in_big_page_size_w()                                          (128U)
+#define ram_in_big_page_size_128kb_f()                                    (0x0U)
+#define ram_in_big_page_size_64kb_f()                                   (0x800U)
+#define ram_in_page_dir_base_lo_f(v)                ((U32(v) & 0xfffffU) << 12U)
+#define ram_in_page_dir_base_lo_w()                                       (128U)
+#define ram_in_page_dir_base_hi_f(v)              ((U32(v) & 0xffffffffU) << 0U)
+#define ram_in_page_dir_base_hi_w()                                       (129U)
+#define ram_in_engine_cs_s()                                                (1U)
+#define ram_in_engine_cs_f(v)                            ((U32(v) & 0x1U) << 3U)
+#define ram_in_engine_cs_m()                                   (U32(0x1U) << 3U)
+#define ram_in_engine_cs_v(r)                               (((r) >> 3U) & 0x1U)
+#define ram_in_engine_cs_wfi_v()                                   (0x00000000U)
+#define ram_in_engine_wfi_mode_f(v)                      ((U32(v) & 0x1U) << 2U)
+#define ram_in_engine_wfi_mode_virtual_v()                         (0x00000001U)
+#define ram_in_engine_wfi_target_w()                                      (132U)
+#define ram_in_engine_wfi_ptr_lo_f(v)               ((U32(v) & 0xfffffU) << 12U)
+#define ram_in_engine_wfi_ptr_hi_f(v)                   ((U32(v) & 0xffU) << 0U)
+#define ram_in_engine_wfi_ptr_hi_w()                                      (133U)
+#define ram_in_engine_wfi_veid_f(v)                     ((U32(v) & 0x3fU) << 0U)
+#define ram_in_engine_wfi_veid_w()                                        (134U)
+#define ram_in_eng_method_buffer_addr_lo_w()                              (136U)
+#define ram_in_eng_method_buffer_addr_hi_w()                              (137U)
+#define ram_in_sc_pdb_valid_long_w(i)\
+		(166ULL + (((i)*1ULL)/32ULL))
+#define ram_in_sc_page_dir_base_target_f(v, i)\
+		((U32(v) & 0x3U) << (0U + (i)*0U))
+#define ram_in_sc_page_dir_base_target_vid_mem_v()                 (0x00000000U)
+#define ram_in_sc_page_dir_base_target_sys_mem_coh_v()             (0x00000002U)
+#define ram_in_sc_page_dir_base_target_sys_mem_ncoh_v()            (0x00000003U)
+#define ram_in_sc_page_dir_base_vol_f(v, i)\
+		((U32(v) & 0x1U) << (2U + (i)*0U))
+#define ram_in_sc_page_dir_base_vol_w(i)\
+		(168U + (((i)*128U)/32U))
+#define ram_in_sc_page_dir_base_vol_true_v()                       (0x00000001U)
+#define ram_in_sc_page_dir_base_fault_replay_tex_f(v, i)\
+		((U32(v) & 0x1U) << (4U + (i)*0U))
+#define ram_in_sc_page_dir_base_fault_replay_gcc_f(v, i)\
+		((U32(v) & 0x1U) << (5U + (i)*0U))
+#define ram_in_sc_use_ver2_pt_format_f(v, i)\
+		((U32(v) & 0x1U) << (10U + (i)*0U))
+#define ram_in_sc_big_page_size_f(v, i)\
+		((U32(v) & 0x1U) << (11U + (i)*0U))
+#define ram_in_sc_page_dir_base_hi_w(i)\
+		(169U + (((i)*128U)/32U))
+#define ram_in_sc_page_dir_base_lo_0_f(v)           ((U32(v) & 0xfffffU) << 12U)
+#define ram_in_base_shift_v()                                      (0x0000000cU)
+#define ram_in_alloc_size_v()                                      (0x00001000U)
+#define ram_fc_size_val_v()                                        (0x00000200U)
+#define ram_fc_signature_w()                                                (4U)
+#define ram_fc_pb_get_w()                                                   (6U)
+#define ram_fc_pb_get_hi_w()                                                (7U)
+#define ram_fc_pb_top_level_get_w()                                         (8U)
+#define ram_fc_pb_top_level_get_hi_w()                                      (9U)
+#define ram_fc_acquire_w()                                                 (12U)
+#define ram_fc_sem_addr_hi_w()                                             (14U)
+#define ram_fc_sem_addr_lo_w()                                             (15U)
+#define ram_fc_sem_payload_lo_w()                                          (16U)
+#define ram_fc_sem_payload_hi_w()                                          (39U)
+#define ram_fc_sem_execute_w()                                             (17U)
+#define ram_fc_gp_base_w()                                                 (18U)
+#define ram_fc_gp_base_hi_w()                                              (19U)
+#define ram_fc_pb_put_w()                                                  (23U)
+#define ram_fc_pb_put_hi_w()                                               (24U)
+#define ram_fc_pb_header_w()                                               (33U)
+#define ram_fc_pb_count_w()                                                (34U)
+#define ram_fc_subdevice_w()                                               (37U)
+#define ram_fc_target_w()                                                  (43U)
+#define ram_fc_hce_ctrl_w()                                                (57U)
+#define ram_fc_config_w()                                                  (61U)
+#define ram_fc_set_channel_info_w()                                        (63U)
+#define ram_fc_intr_notify_w()                                             (62U)
+#define ram_userd_base_shift_v()                                   (0x00000009U)
+#define ram_userd_put_w()                                                  (16U)
+#define ram_userd_get_w()                                                  (17U)
+#define ram_userd_ref_w()                                                  (18U)
+#define ram_userd_put_hi_w()                                               (19U)
+#define ram_userd_top_level_get_w()                                        (22U)
+#define ram_userd_top_level_get_hi_w()                                     (23U)
+#define ram_userd_get_hi_w()                                               (24U)
+#define ram_userd_gp_get_w()                                               (34U)
+#define ram_userd_gp_put_w()                                               (35U)
+#define ram_rl_entry_size_v()                                      (0x00000010U)
+#define ram_rl_entry_type_channel_v()                              (0x00000000U)
+#define ram_rl_entry_type_tsg_v()                                  (0x00000001U)
+#define ram_rl_entry_chan_runqueue_selector_f(v)         ((U32(v) & 0x1U) << 1U)
+#define ram_rl_entry_chan_inst_target_f(v)               ((U32(v) & 0x3U) << 4U)
+#define ram_rl_entry_chan_inst_target_sys_mem_ncoh_v()             (0x00000003U)
+#define ram_rl_entry_chan_inst_target_sys_mem_coh_v()              (0x00000002U)
+#define ram_rl_entry_chan_inst_target_vid_mem_v()                  (0x00000000U)
+#define ram_rl_entry_chan_userd_target_f(v)              ((U32(v) & 0x3U) << 6U)
+#define ram_rl_entry_chan_userd_target_vid_mem_v()                 (0x00000000U)
+#define ram_rl_entry_chan_userd_target_sys_mem_coh_v()             (0x00000002U)
+#define ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()            (0x00000003U)
+#define ram_rl_entry_chan_userd_ptr_lo_f(v)         ((U32(v) & 0xffffffU) << 8U)
+#define ram_rl_entry_chan_userd_ptr_hi_f(v)       ((U32(v) & 0xffffffffU) << 0U)
+#define ram_rl_entry_chid_f(v)                         ((U32(v) & 0xfffU) << 0U)
+#define ram_rl_entry_chan_inst_ptr_lo_f(v)          ((U32(v) & 0xfffffU) << 12U)
+#define ram_rl_entry_chan_inst_ptr_hi_f(v)        ((U32(v) & 0xffffffffU) << 0U)
+#define ram_rl_entry_tsg_timeslice_scale_f(v)           ((U32(v) & 0xfU) << 16U)
+#define ram_rl_entry_tsg_timeslice_timeout_f(v)        ((U32(v) & 0xffU) << 24U)
+#define ram_rl_entry_tsg_length_f(v)                    ((U32(v) & 0xffU) << 0U)
+#define ram_rl_entry_tsg_tsgid_f(v)                    ((U32(v) & 0xfffU) << 0U)
+#define ram_rl_entry_chan_userd_ptr_align_shift_v()                (0x00000008U)
+#define ram_rl_entry_chan_inst_ptr_align_shift_v()                 (0x0000000cU)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_runlist_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_runlist_ga10b.h
new file mode 100644
index 000000000..143ea6aec
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_runlist_ga10b.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_RUNLIST_GA10B_H
+#define NVGPU_HW_RUNLIST_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define runlist_channel_config_r()                                 (0x00000004U)
+#define runlist_channel_config_num_channels_log2_2k_v()            (0x0000000bU)
+#define runlist_channel_config_chram_bar0_offset_v(r) (((r) >> 4U) & 0xfffffffU)
+#define runlist_channel_config_chram_bar0_offset_b()                        (4U)
+#define runlist_doorbell_config_r()                                (0x00000008U)
+#define runlist_doorbell_config_id_v(r)                 (((r) >> 16U) & 0xffffU)
+#define runlist_fb_config_r()                                      (0x0000000cU)
+#define runlist_fb_config_fb_thread_id_v(r)                (((r) >> 0U) & 0xffU)
+#define runlist_pbdma_config_r(i)\
+		(nvgpu_safe_add_u32(0x00000010U, nvgpu_safe_mult_u32((i), 4U)))
+#define runlist_pbdma_config__size_1_v()                           (0x00000002U)
+#define runlist_pbdma_config_id_v(r)                       (((r) >> 0U) & 0xffU)
+#define runlist_pbdma_config_pbdma_bar0_offset_v(r)     (((r) >> 10U) & 0xffffU)
+#define runlist_pbdma_config_valid_v(r)                    (((r) >> 31U) & 0x1U)
+#define runlist_pbdma_config_valid_true_v()                        (0x00000001U)
+#define runlist_userd_writeback_r()                                (0x00000028U)
+#define runlist_userd_writeback_timer_100us_f()                          (0x64U)
+#define runlist_userd_writeback_timescale_0_f()                           (0x0U)
+#define runlist_engine_status0_r(i)\
+		(nvgpu_safe_add_u32(0x00000200U, nvgpu_safe_mult_u32((i), 64U)))
+#define runlist_engine_status0_tsgid_v(r)                 (((r) >> 0U) & 0xfffU)
+#define runlist_engine_status0_ctx_status_v(r)             (((r) >> 13U) & 0x7U)
+#define runlist_engine_status0_ctx_status_valid_v()                (0x00000001U)
+#define runlist_engine_status0_ctx_status_save_v()                 (0x00000005U)
+#define runlist_engine_status0_ctx_status_load_v()                 (0x00000006U)
+#define runlist_engine_status0_ctx_status_switch_v()               (0x00000007U)
+#define runlist_engine_status0_ctxsw_in_progress_f()                   (0x8000U)
+#define runlist_engine_status0_next_tsgid_v(r)           (((r) >> 16U) & 0xfffU)
+#define runlist_engine_status0_faulted_v(r)                (((r) >> 30U) & 0x1U)
+#define runlist_engine_status0_faulted_true_v()                    (0x00000001U)
+#define runlist_engine_status0_engine_v(r)                 (((r) >> 31U) & 0x1U)
+#define runlist_engine_status0_engine_busy_v()                     (0x00000001U)
+#define runlist_engine_status1_r(i)\
+		(nvgpu_safe_add_u32(0x00000204U, nvgpu_safe_mult_u32((i), 64U)))
+#define runlist_engine_status1_intr_id_v(r)               (((r) >> 16U) & 0x1fU)
+#define runlist_engine_status_debug_r(i)\
+		(nvgpu_safe_add_u32(0x00000228U, nvgpu_safe_mult_u32((i), 64U)))
+#define runlist_engine_status_debug_engine_id_v(r)        (((r) >> 24U) & 0x3fU)
+#define runlist_chram_channel_r(i)\
+		(nvgpu_safe_add_u32(0x00000000U, nvgpu_safe_mult_u32((i), 4U)))
+#define runlist_chram_channel_enable_v(r)                   (((r) >> 1U) & 0x1U)
+#define runlist_chram_channel_enable_in_use_v()                    (0x00000001U)
+#define runlist_chram_channel_next_v(r)                     (((r) >> 2U) & 0x1U)
+#define runlist_chram_channel_next_true_v()                        (0x00000001U)
+#define runlist_chram_channel_busy_v(r)                     (((r) >> 3U) & 0x1U)
+#define runlist_chram_channel_busy_true_v()                        (0x00000001U)
+#define runlist_chram_channel_eng_faulted_v(r)              (((r) >> 5U) & 0x1U)
+#define runlist_chram_channel_eng_faulted_true_v()                 (0x00000001U)
+#define runlist_chram_channel_ctx_reload_v(r)               (((r) >> 9U) & 0x1U)
+#define runlist_chram_channel_ctx_reload_true_v()                  (0x00000001U)
+#define runlist_chram_channel_status_v(r)                  (((r) >> 8U) & 0x1fU)
+#define runlist_chram_channel_status_idle_v()                      (0x00000000U)
+#define runlist_chram_channel_status_pending_v()                   (0x00000001U)
+#define runlist_chram_channel_status_pending_ctx_reload_v()        (0x00000003U)
+#define runlist_chram_channel_status_pending_acquire_fail_v()      (0x00000011U)
+#define runlist_chram_channel_status_pending_acquire_fail_ctx_reload_v()\
+				(0x00000013U)
+#define runlist_chram_channel_status_pbdma_busy_v()                (0x00000004U)
+#define runlist_chram_channel_status_pbdma_busy_and_eng_busy_v()   (0x0000000cU)
+#define runlist_chram_channel_status_eng_busy_v()                  (0x00000008U)
+#define runlist_chram_channel_status_eng_busy_pending_acquire_fail_v()\
+				(0x00000019U)
+#define runlist_chram_channel_status_eng_busy_pending_v()          (0x00000009U)
+#define runlist_chram_channel_status_pbdma_busy_ctx_reload_v()     (0x00000006U)
+#define runlist_chram_channel_status_pbdma_busy_eng_busy_ctx_reload_v()\
+				(0x0000000eU)
+#define runlist_chram_channel_status_busy_ctx_reload_v()           (0x0000000aU)
+#define runlist_chram_channel_status_eng_busy_pending_ctx_reload_v()\
+				(0x0000000bU)
+#define runlist_chram_channel_status_eng_busy_pending_acquire_fail_ctx_reload_v()\
+				(0x0000001bU)
+#define runlist_chram_channel_update_f(v)         ((U32(v) & 0xffffffffU) << 0U)
+#define runlist_chram_channel_update_enable_channel_v()            (0x00000002U)
+#define runlist_chram_channel_update_disable_channel_v()           (0x00000003U)
+#define runlist_chram_channel_update_force_ctx_reload_v()          (0x00000200U)
+#define runlist_chram_channel_update_reset_pbdma_faulted_v()       (0x00000011U)
+#define runlist_chram_channel_update_reset_eng_faulted_v()         (0x00000021U)
+#define runlist_chram_channel_update_clear_channel_v()             (0xffffffffU)
+#define runlist_submit_base_lo_r()                                 (0x00000080U)
+#define runlist_submit_base_lo_ptr_align_shift_v()                 (0x0000000aU)
+#define runlist_submit_base_lo_ptr_lo_f(v)         ((U32(v) & 0x3fffffU) << 10U)
+#define runlist_submit_base_lo_target_vid_mem_f()                         (0x0U)
+#define runlist_submit_base_lo_target_sys_mem_coherent_f()                (0x2U)
+#define runlist_submit_base_lo_target_sys_mem_noncoherent_f()             (0x3U)
+#define runlist_submit_base_hi_r()                                 (0x00000084U)
+#define runlist_submit_base_hi_ptr_hi_f(v)              ((U32(v) & 0xffU) << 0U)
+#define runlist_submit_r()                                         (0x00000088U)
+#define runlist_submit_length_f(v)                    ((U32(v) & 0xffffU) << 0U)
+#define runlist_submit_length_max_v()                              (0x0000ffffU)
+#define runlist_submit_offset_f(v)                   ((U32(v) & 0xffffU) << 16U)
+#define runlist_submit_info_r()                                    (0x0000008cU)
+#define runlist_submit_info_pending_true_f()                           (0x8000U)
+#define runlist_sched_disable_r()                                  (0x00000094U)
+#define runlist_sched_disable_runlist_enabled_v()                  (0x00000000U)
+#define runlist_sched_disable_runlist_disabled_v()                 (0x00000001U)
+#define runlist_preempt_r()                                        (0x00000098U)
+#define runlist_preempt_id_f(v)                        ((U32(v) & 0xfffU) << 0U)
+#define runlist_preempt_tsg_preempt_pending_true_f()                 (0x100000U)
+#define runlist_preempt_runlist_preempt_pending_true_f()             (0x200000U)
+#define runlist_preempt_type_runlist_f()                                  (0x0U)
+#define runlist_preempt_type_tsg_f()                                (0x1000000U)
+#define runlist_virtual_channel_cfg_r(i)\
+		(nvgpu_safe_add_u32(0x00000300U, nvgpu_safe_mult_u32((i), 4U)))
+#define runlist_virtual_channel_cfg_mask_hw_mask_hw_init_f()            (0x7ffU)
+#define runlist_virtual_channel_cfg_pending_enable_true_f()        (0x80000000U)
+#define runlist_intr_vectorid_r(i)\
+		(nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32((i), 4U)))
+#define runlist_intr_vectorid__size_1_v()                          (0x00000002U)
+#define runlist_intr_vectorid_vector_v(r)                 (((r) >> 0U) & 0xfffU)
+#define runlist_intr_vectorid_gsp_enable_f()                       (0x40000000U)
+#define runlist_intr_vectorid_cpu_enable_f()                       (0x80000000U)
+#define runlist_intr_retrigger_r(i)\
+		(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U)))
+#define runlist_intr_retrigger_trigger_true_f()                           (0x1U)
+#define runlist_intr_0_r()                                         (0x00000100U)
+#define runlist_intr_0_ctxsw_timeout_eng_pending_f(i)\
+		((U32(0x1U) << (0U + ((i)*1U))))
+#define runlist_intr_0_ctxsw_timeout_eng_reset_f(i)\
+		((U32(0x1U) << (0U + ((i)*1U))))
+#define runlist_intr_0_bad_tsg_pending_f()                             (0x1000U)
+#define runlist_intr_0_pbdmai_intr_tree_j_pending_f(i, j)\
+		((U32(0x1U) << (16U + ((i)*1U) + ((j)*2U))))
+#define runlist_intr_0_pbdmai_intr_tree_j__size_1_v()              (0x00000002U)
+#define runlist_intr_bad_tsg_r()                                   (0x00000174U)
+#define runlist_intr_bad_tsg_code_v(r)                      (((r) >> 0U) & 0xfU)
+#define runlist_intr_0_en_set_tree_r(i)\
+		(nvgpu_safe_add_u32(0x00000120U, nvgpu_safe_mult_u32((i), 8U)))
+#define runlist_intr_0_en_set_tree_ctxsw_timeout_eng0_enabled_f()         (0x1U)
+#define runlist_intr_0_en_set_tree_ctxsw_timeout_eng1_enabled_f()         (0x2U)
+#define runlist_intr_0_en_set_tree_ctxsw_timeout_eng2_enabled_f()         (0x4U)
+#define runlist_intr_0_en_set_tree_bad_tsg_enabled_f()                 (0x1000U)
+#define runlist_intr_0_en_set_tree_pbdma0_intr_tree_0_enabled_f()     (0x10000U)
+#define runlist_intr_0_en_set_tree_pbdma1_intr_tree_0_enabled_f()     (0x20000U)
+#define runlist_intr_0_en_clear_tree_r(i)\
+		(nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32((i), 8U)))
+#define runlist_intr_0_en_clear_tree_ctxsw_timeout_eng0_enabled_f()       (0x1U)
+#define runlist_intr_0_en_clear_tree_ctxsw_timeout_eng1_enabled_f()       (0x2U)
+#define runlist_intr_0_en_clear_tree_ctxsw_timeout_eng2_enabled_f()       (0x4U)
+#define runlist_engine_ctxsw_timeout_info_r(i)\
+		(nvgpu_safe_add_u32(0x00000224U, nvgpu_safe_mult_u32((i), 64U)))
+#define runlist_engine_ctxsw_timeout_info__size_1_v()              (0x00000003U)
+#define runlist_engine_ctxsw_timeout_info_prev_tsgid_v(r)\
+				(((r) >> 0U) & 0x3fffU)
+#define runlist_engine_ctxsw_timeout_info_ctxsw_state_v(r) (((r) >> 14U) & 0x3U)
+#define runlist_engine_ctxsw_timeout_info_ctxsw_state_load_v()     (0x00000001U)
+#define runlist_engine_ctxsw_timeout_info_ctxsw_state_save_v()     (0x00000002U)
+#define runlist_engine_ctxsw_timeout_info_ctxsw_state_switch_v()   (0x00000003U)
+#define runlist_engine_ctxsw_timeout_info_next_tsgid_v(r)\
+				(((r) >> 16U) & 0x3fffU)
+#define runlist_engine_ctxsw_timeout_info_status_v(r)      (((r) >> 30U) & 0x3U)
+#define runlist_engine_ctxsw_timeout_info_status_ack_received_v()  (0x00000002U)
+#define runlist_engine_ctxsw_timeout_info_status_dropped_timeout_v()\
+				(0x00000003U)
+#define runlist_engine_ctxsw_timeout_config_r(i)\
+		(nvgpu_safe_add_u32(0x00000220U, nvgpu_safe_mult_u32((i), 64U)))
+#define runlist_engine_ctxsw_timeout_config__size_1_v()            (0x00000003U)
+#define runlist_engine_ctxsw_timeout_config_period_f(v)\
+				((U32(v) & 0x7fffffffU) << 0U)
+#define runlist_engine_ctxsw_timeout_config_period_v(r)\
+				(((r) >> 0U) & 0x7fffffffU)
+#define runlist_engine_ctxsw_timeout_config_period_max_f()         (0x7fffffffU)
+#define runlist_engine_ctxsw_timeout_config_detection_disabled_f()        (0x0U)
+#define runlist_engine_ctxsw_timeout_config_detection_enabled_f()  (0x80000000U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h
new file mode 100644
index 000000000..7bab11227
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_SMCARB_GA10B_H
+#define NVGPU_HW_SMCARB_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define smcarb_smc_partition_gpc_map_r(i)\
+		(nvgpu_safe_add_u32(0x0000cc00U, nvgpu_safe_mult_u32((i), 4U)))
+#define smcarb_smc_partition_gpc_map_sys_pipe_local_gpc_id_f(v)\
+				((U32(v) & 0x1fU) << 0U)
+#define smcarb_smc_partition_gpc_map_sys_pipe_local_gpc_id_m()\
+				(U32(0x1fU) << 0U)
+#define smcarb_smc_partition_gpc_map_sys_pipe_id_f(v)   ((U32(v) & 0x1fU) << 8U)
+#define smcarb_smc_partition_gpc_map_sys_pipe_id_m()          (U32(0x1fU) << 8U)
+#define smcarb_smc_partition_gpc_map_physical_gpc_id_v(r) (((r) >> 16U) & 0x1fU)
+#define smcarb_smc_partition_gpc_map_ugpu_id_v(r)          (((r) >> 24U) & 0x1U)
+#define smcarb_smc_partition_gpc_map_valid_f(v)         ((U32(v) & 0x1U) << 31U)
+#define smcarb_smc_partition_gpc_map_valid_m()                (U32(0x1U) << 31U)
+#define smcarb_smc_partition_gpc_map_valid_true_v()                (0x00000001U)
+#define smcarb_smc_partition_gpc_map_valid_false_v()               (0x00000000U)
+#define smcarb_sys_pipe_info_r()                                   (0x0000cc80U)
+#define smcarb_sys_pipe_info_mode_f(v)                   ((U32(v) & 0x1U) << 0U)
+#define smcarb_sys_pipe_info_mode_m()                          (U32(0x1U) << 0U)
+#define smcarb_sys_pipe_info_mode_v(r)                      (((r) >> 0U) & 0x1U)
+#define smcarb_sys_pipe_info_mode_legacy_v()                       (0x00000000U)
+#define smcarb_sys_pipe_info_mode_smc_v()                          (0x00000001U)
+#define smcarb_ugpu_gpc_count_r()                                  (0x0000cc84U)
+#define smcarb_ugpu_gpc_count_ugpu0_v(r)                   (((r) >> 0U) & 0x1fU)
+#define smcarb_ugpu_gpc_count_ugpu1_v(r)                   (((r) >> 8U) & 0x1fU)
+#define smcarb_timestamp_ctrl_r()                                  (0x0000cc8cU)
+#define smcarb_timestamp_ctrl_disable_tick_m()                 (U32(0x1U) << 0U)
+#define smcarb_timestamp_ctrl_disable_tick__prod_f()                      (0x0U)
+#define smcarb_max_partitionable_sys_pipes_v()                     (0x00000002U)
+#define smcarb_allowed_swizzid__size1_v()                          (0x00000001U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_therm_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_therm_ga10b.h
new file mode 100644
index 000000000..cf5f78555
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_therm_ga10b.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_THERM_GA10B_H
+#define NVGPU_HW_THERM_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define therm_use_a_r()                                            (0x00020798U)
+#define therm_use_a_ext_therm_0_enable_f()                                (0x1U)
+#define therm_use_a_ext_therm_1_enable_f()                                (0x2U)
+#define therm_use_a_ext_therm_2_enable_f()                                (0x4U)
+#define therm_evt_ext_therm_0_r()                                  (0x00020700U)
+#define therm_evt_ext_therm_0_slow_factor_f(v)         ((U32(v) & 0x3fU) << 24U)
+#define therm_evt_ext_therm_1_r()                                  (0x00020704U)
+#define therm_evt_ext_therm_1_slow_factor_f(v)         ((U32(v) & 0x3fU) << 24U)
+#define therm_evt_ext_therm_2_r()                                  (0x00020708U)
+#define therm_evt_ext_therm_2_slow_factor_f(v)         ((U32(v) & 0x3fU) << 24U)
+#define therm_config2_r()                                          (0x00020130U)
+#define therm_config2_grad_step_duration_f(v)            ((U32(v) & 0xfU) << 8U)
+#define therm_config2_grad_step_duration_m()                   (U32(0xfU) << 8U)
+#define therm_config2_slowdown_factor_extended_f(v)     ((U32(v) & 0x1U) << 24U)
+#define therm_config2_grad_enable_f(v)                  ((U32(v) & 0x1U) << 31U)
+#define therm_gate_ctrl_r(i)\
+		(nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U)))
+#define therm_gate_ctrl_eng_clk_m()                            (U32(0x3U) << 0U)
+#define therm_gate_ctrl_eng_clk_run_f()                                   (0x0U)
+#define therm_gate_ctrl_eng_clk_auto_f()                                  (0x1U)
+#define therm_gate_ctrl_eng_clk_stop_f()                                  (0x2U)
+#define therm_gate_ctrl_blk_clk_m()                            (U32(0x3U) << 2U)
+#define therm_gate_ctrl_blk_clk_run_f()                                   (0x0U)
+#define therm_gate_ctrl_blk_clk_auto_f()                                  (0x4U)
+#define therm_gate_ctrl_idle_holdoff_m()                       (U32(0x1U) << 4U)
+#define therm_gate_ctrl_idle_holdoff_on_f()                              (0x10U)
+#define therm_gate_ctrl_eng_idle_filt_exp_m()                 (U32(0x1fU) << 8U)
+#define therm_gate_ctrl_eng_idle_filt_exp__prod_f()                     (0x600U)
+#define therm_gate_ctrl_eng_idle_filt_mant_m()                (U32(0x7U) << 13U)
+#define therm_gate_ctrl_eng_idle_filt_mant__prod_f()                   (0x2000U)
+#define therm_gate_ctrl_eng_delay_before_m()                  (U32(0xfU) << 16U)
+#define therm_gate_ctrl_eng_delay_before__prod_f()                    (0x40000U)
+#define therm_gate_ctrl_eng_delay_after_m()                   (U32(0xfU) << 20U)
+#define therm_gate_ctrl_eng_delay_after__prod_f()                         (0x0U)
+#define therm_fecs_idle_filter_r()                                 (0x00020288U)
+#define therm_fecs_idle_filter_value_m()                (U32(0xffffffffU) << 0U)
+#define therm_fecs_idle_filter_value__prod_f()                            (0x0U)
+#define therm_hubmmu_idle_filter_r()                               (0x0002028cU)
+#define therm_hubmmu_idle_filter_value_m()              (U32(0xffffffffU) << 0U)
+#define therm_hubmmu_idle_filter_value__prod_f()                          (0x0U)
+#define therm_clk_slowdown_2_r(i)\
+		(nvgpu_safe_add_u32(0x000201a0U, nvgpu_safe_mult_u32((i), 4U)))
+#define therm_clk_slowdown_2_idle_condition_a_select_f(v)\
+				((U32(v) & 0xfU) << 0U)
+#define therm_clk_slowdown_2_idle_condition_a_type_never_f()             (0x40U)
+#define therm_clk_slowdown_2_idle_condition_b_type_never_f()           (0x4000U)
+#define therm_grad_stepping_table_r(i)\
+		(nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U)))
+#define therm_grad_stepping_table_slowdown_factor0_f(v) ((U32(v) & 0x3fU) << 0U)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1_f()          (0x0U)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()        (0x1U)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()          (0x2U)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()          (0x6U)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()          (0xeU)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by16_f()        (0x1eU)
+#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by31_f()        (0x3cU)
+#define therm_grad_stepping_table_slowdown_factor1_f(v) ((U32(v) & 0x3fU) << 6U)
+#define therm_grad_stepping_table_slowdown_factor2_f(v)\
+				((U32(v) & 0x3fU) << 12U)
+#define therm_grad_stepping_table_slowdown_factor3_f(v)\
+				((U32(v) & 0x3fU) << 18U)
+#define therm_grad_stepping_table_slowdown_factor4_f(v)\
+				((U32(v) & 0x3fU) << 24U)
+#define therm_grad_stepping0_r()                                   (0x000202c0U)
+#define therm_grad_stepping0_feature_enable_f()                           (0x1U)
+#define therm_grad_stepping1_r()                                   (0x000202c4U)
+#define therm_grad_stepping1_pdiv_duration_f(v)      ((U32(v) & 0x1ffffU) << 0U)
+#define therm_clk_timing_r(i)\
+		(nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U)))
+#define therm_clk_timing_grad_slowdown_enabled_f()                    (0x10000U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_timer_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_timer_ga10b.h
new file mode 100644
index 000000000..9c36ccee4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_timer_ga10b.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_TIMER_GA10B_H
+#define NVGPU_HW_TIMER_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define timer_pri_timeout_save_0_r()                               (0x00009084U)
+#define timer_pri_timeout_save_0_fecs_tgt_v(r)             (((r) >> 31U) & 0x1U)
+#define timer_pri_timeout_save_0_addr_v(r)             (((r) >> 2U) & 0x7fffffU)
+#define timer_pri_timeout_save_0_write_v(r)                 (((r) >> 1U) & 0x1U)
+#define timer_pri_timeout_save_1_r()                               (0x00009088U)
+#define timer_pri_timeout_fecs_errcode_r()                         (0x0000908cU)
+#define timer_time_0_r()                                           (0x00009400U)
+#define timer_time_1_r()                                           (0x00009410U)
+#define timer_gr_tick_freq_r()                                     (0x00009480U)
+#define timer_gr_tick_freq_select_f(v)                   ((U32(v) & 0x7U) << 0U)
+#define timer_gr_tick_freq_select_max_f()                                 (0x0U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_top_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_top_ga10b.h
new file mode 100644
index 000000000..546ba9a05
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_top_ga10b.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function/Macro naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_TOP_GA10B_H
+#define NVGPU_HW_TOP_GA10B_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define top_num_gpcs_r()                                           (0x00022430U)
+#define top_num_gpcs_value_v(r)                            (((r) >> 0U) & 0x1fU)
+#define top_tpc_per_gpc_r()                                        (0x00022434U)
+#define top_tpc_per_gpc_value_v(r)                         (((r) >> 0U) & 0x1fU)
+#define top_num_fbps_r()                                           (0x00022438U)
+#define top_num_fbps_value_v(r)                            (((r) >> 0U) & 0x1fU)
+#define top_ltc_per_fbp_r()                                        (0x00022450U)
+#define top_ltc_per_fbp_value_v(r)                         (((r) >> 0U) & 0x1fU)
+#define top_slices_per_ltc_r()                                     (0x0002245cU)
+#define top_slices_per_ltc_value_v(r)                      (((r) >> 0U) & 0x1fU)
+#define top_num_ltcs_r()                                           (0x00022454U)
+#define top_num_ltcs_value_v(r)                            (((r) >> 0U) & 0x1fU)
+#define top_num_ces_r()                                            (0x00022444U)
+#define top_num_ces_value_v(r)                             (((r) >> 0U) & 0x1fU)
+#define top_device_info_cfg_r()                                    (0x000224fcU)
+#define top_device_info_cfg_version_v(r)                    (((r) >> 0U) & 0xfU)
+#define top_device_info_cfg_version_init_v()                       (0x00000002U)
+#define top_device_info_cfg_num_rows_v(r)                (((r) >> 20U) & 0xfffU)
+#define top_device_info2_r(i)\
+		(nvgpu_safe_add_u32(0x00022800U, nvgpu_safe_mult_u32((i), 4U)))
+#define top_device_info2_row_chain_v(r)                    (((r) >> 31U) & 0x1U)
+#define top_device_info2_row_chain_more_v()                        (0x00000001U)
+#define top_device_info2_row_chain_last_v()                        (0x00000000U)
+#define top_device_info2_dev_fault_id_v(r)                (((r) >> 0U) & 0x7ffU)
+#define top_device_info2_dev_instance_id_v(r)             (((r) >> 16U) & 0xffU)
+#define top_device_info2_dev_type_enum_v(r)               (((r) >> 24U) & 0x7fU)
+#define top_device_info2_dev_reset_id_v(r)                 (((r) >> 0U) & 0xffU)
+#define top_device_info2_dev_device_pri_base_v(r)       (((r) >> 8U) & 0x3ffffU)
+#define top_device_info2_dev_device_pri_base_b()                            (8U)
+#define top_device_info2_dev_is_engine_v(r)                (((r) >> 30U) & 0x1U)
+#define top_device_info2_dev_is_engine_true_v()                    (0x00000001U)
+#define top_device_info2_dev_rleng_id_v(r)                  (((r) >> 0U) & 0x3U)
+#define top_device_info2_dev_runlist_pri_base_v(r)      (((r) >> 10U) & 0xffffU)
+#define top_device_info2_dev_runlist_pri_base_b()                          (10U)
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_cic.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_cic.h
new file mode 100644
index 000000000..d406b2e8f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_cic.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_CIC_H
+#define NVGPU_NEXT_CIC_H
+
+/**
+ * @file
+ *
+ * Declare intr specific struct and defines.
+ */
+#include <nvgpu/types.h>
+#include <nvgpu/static_analysis.h>
+
+#define U32_BITS		32U
+#define DIV_BY_U32_BITS(x)	((x) / U32_BITS)
+#define MOD_BY_U32_BITS(x)	((x) % U32_BITS)
+
+#define RESET_ID_TO_REG_IDX(x)		DIV_BY_U32_BITS((x))
+#define RESET_ID_TO_REG_BIT(x)		MOD_BY_U32_BITS((x))
+#define RESET_ID_TO_REG_MASK(x)		BIT32(RESET_ID_TO_REG_BIT((x)))
+
+#define GPU_VECTOR_TO_LEAF_REG(i)	DIV_BY_U32_BITS((i))
+#define GPU_VECTOR_TO_LEAF_BIT(i)	MOD_BY_U32_BITS((i))
+#define GPU_VECTOR_TO_LEAF_MASK(i) (BIT32(GPU_VECTOR_TO_LEAF_BIT(i)))
+#define GPU_VECTOR_TO_SUBTREE(i)	((GPU_VECTOR_TO_LEAF_REG(i)) / 2U)
+#define GPU_VECTOR_TO_LEAF_SHIFT(i) \
+	(nvgpu_safe_mult_u32(((GPU_VECTOR_TO_LEAF_REG(i)) % 2U), 32U))
+
+#define HOST2SOC_0_SUBTREE		0U
+#define HOST2SOC_1_SUBTREE		1U
+#define HOST2SOC_2_SUBTREE		2U
+#define HOST2SOC_3_SUBTREE		3U
+#define HOST2SOC_NUM_SUBTREE		4U
+
+#define HOST2SOC_SUBTREE_TO_TOP_IDX(i)	((i) / 32U)
+#define HOST2SOC_SUBTREE_TO_TOP_BIT(i)	((i) % 32U)
+#define HOST2SOC_SUBTREE_TO_LEAF0(i) \
+		(nvgpu_safe_mult_u32((i), 2U))
+#define HOST2SOC_SUBTREE_TO_LEAF1(i) \
+		(nvgpu_safe_add_u32((nvgpu_safe_mult_u32((i), 2U)), 1U))
+
+#define STALL_SUBTREE_TOP_IDX		0U
+#define STALL_SUBTREE_TOP_BITS \
+		((BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_1_SUBTREE))) | \
+		 (BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_2_SUBTREE))) | \
+		 (BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_3_SUBTREE))))
+
+/**
+ * These should not contradict NVGPU_CIC_INTR_UNIT_* defines.
+ */
+#define NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR			10U
+#define NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR	11U
+#define NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR		12U
+#define NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT		13U
+#define NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT		14U
+#define NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT			15U
+#define NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0			16U
+#define NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_1			17U
+#define NVGPU_CIC_INTR_UNIT_GR_STALL				18U
+#define NVGPU_CIC_INTR_UNIT_CE_STALL				19U
+#define NVGPU_CIC_INTR_UNIT_MAX					20U
+
+#define NVGPU_CIC_INTR_VECTORID_SIZE_MAX				32U
+#define NVGPU_CIC_INTR_VECTORID_SIZE_ONE				1U
+
+#define RUNLIST_INTR_TREE_0					0U
+#define RUNLIST_INTR_TREE_1					1U
+
+void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
+		u32 num_entries);
+bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit);
+bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
+		u64 *subtree_mask);
+
+#endif /* NVGPU_NEXT_CIC_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_class.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_class.h
new file mode 100644
index 000000000..daefcd83a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_class.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_CLASS_H
+#define NVGPU_NEXT_CLASS_H
+
+#define AMPERE_SMC_PARTITION_REF	0xC637U
+#define	AMPERE_B			0xC797U
+#define	AMPERE_A			0xC697U
+#define AMPERE_DMA_COPY_A		0xC6B5U
+#define AMPERE_DMA_COPY_B		0xC7B5U
+#define AMPERE_COMPUTE_A		0xC6C0U
+#define	AMPERE_COMPUTE_B		0xC7C0U
+#define AMPERE_CHANNEL_GPFIFO_A		0xC56FU
+#define AMPERE_CHANNEL_GPFIFO_B		0xC76FU
+
+#endif /* NVGPU_NEXT_CLASS_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_device.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_device.h
new file mode 100644
index 000000000..98a450029
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_device.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_TOP_H
+#define NVGPU_NEXT_TOP_H
+
+#include <nvgpu/pbdma.h>
+
+struct nvgpu_device_next {
+	/**
+	 * True if the device is an method engine behind host.
+	 */
+	bool engine;
+
+	/**
+	 * Runlist Engine ID; only valid if #engine is true.
+	 */
+	u32 rleng_id;
+
+	/**
+	 * Runlist PRI base - byte aligned based address. CHRAM offset can
+	 * be computed from this.
+	 */
+	u32 rl_pri_base;
+
+	/**
+	 * PBDMA info for this device. It may contain multiple PBDMAs as
+	 * there can now be multiple PBDMAs per runlist.
+	 *
+	 * This is in some ways awkward; devices seem to be more directly
+	 * linked to runlists; runlists in turn have PBDMAs. Granted that
+	 * means there's a computable relation between devices and PBDMAs
+	 * it may make sense to not have this link.
+	 */
+	struct nvgpu_next_pbdma_info pbdma_info;
+
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_ecc.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_ecc.h
new file mode 100644
index 000000000..3ddb016a7
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_ecc.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_ECC_H
+#define NVGPU_NEXT_ECC_H
+
+		/* Leave extra tab to fit into nvgpu_ecc.fb structure */
+		struct nvgpu_ecc_stat *mmu_l2tlb_ecc_corrected_unique_err_count;
+		/** hubmmu l2tlb uncorrected unique error count. */
+		struct nvgpu_ecc_stat *mmu_l2tlb_ecc_uncorrected_unique_err_count;
+		/** hubmmu hubtlb corrected unique error count. */
+		struct nvgpu_ecc_stat *mmu_hubtlb_ecc_corrected_unique_err_count;
+		/** hubmmu hubtlb uncorrected unique error count. */
+		struct nvgpu_ecc_stat *mmu_hubtlb_ecc_uncorrected_unique_err_count;
+		/** hubmmu fillunit corrected unique error count. */
+		struct nvgpu_ecc_stat *mmu_fillunit_ecc_corrected_unique_err_count;
+		/** hubmmu fillunit uncorrected unique error count. */
+		struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_unique_err_count;
+
+#endif /* NVGPU_NEXT_ECC_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engine_status.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engine_status.h
new file mode 100644
index 000000000..deb981dcf
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engine_status.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_ENGINE_STATUS_H
+#define NVGPU_NEXT_ENGINE_STATUS_H
+
+/**
+ * @file
+ *
+ * Declare device info specific struct and defines.
+ */
+#include <nvgpu/types.h>
+
+struct nvgpu_next_engine_status_info {
+	/** Engine status_1 h/w register's read value. */
+	u32 reg1_data;
+};
+#endif /* NVGPU_NEXT_ENGINE_STATUS_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engines.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engines.h
new file mode 100644
index 000000000..77754d5af
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engines.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_ENGINES_H
+#define NVGPU_NEXT_ENGINES_H
+
+/**
+ * @file
+ *
+ * Declare engine info specific struct and defines.
+ */
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_device;
+
+#define ENGINE_PBDMA_INSTANCE0 0U
+
+int nvgpu_next_engine_init_one_dev(struct gk20a *g,
+				   const struct nvgpu_device *dev);
+
+#endif /* NVGPU_NEXT_ENGINES_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_err.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_err.h
new file mode 100644
index 000000000..0744909e2
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_err.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_ERR_H
+#define NVGPU_NEXT_ERR_H
+
+/*
+ * Error IDs for SM unit.
+ */
+#define GPU_SM_RAMS_ECC_CORRECTED	(21U)
+#define GPU_SM_RAMS_ECC_UNCORRECTED	(22U)
+
+#endif /* NVGPU_NEXT_ERR_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_errata.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_errata.h
new file mode 100644
index 000000000..9628c37d3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_errata.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_ERRATA_H
+#define NVGPU_NEXT_ERRATA_H
+
+#define ERRATA_FLAGS_NEXT						\
+	/* GA100 */							\
+	DEFINE_ERRATA(NVGPU_ERRATA_200601972, "GA100", "LTC TSTG"),	\
+	/* GA10B */							\
+	DEFINE_ERRATA(NVGPU_ERRATA_2969956, "GA10B", "FMODEL FB LTCS"),	\
+	DEFINE_ERRATA(NVGPU_ERRATA_200677649, "GA10B", "UCODE"),	\
+	DEFINE_ERRATA(NVGPU_ERRATA_3154076, "GA10B", "PROD VAL"),	\
+	DEFINE_ERRATA(NVGPU_ERRATA_3288192, "GA10B", "L4 SCF NOT SUPPORTED"),
+
+#endif /* NVGPU_NEXT_ERRATA_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fb.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fb.h
new file mode 100644
index 000000000..6263e98fc
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fb.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_FB_H
+#define NVGPU_NEXT_FB_H
+
+/* VAB track all accesses (read and write) */
+#define NVGPU_VAB_MODE_ACCESS	BIT32(0U)
+/* VAB track only writes (writes and read-modify-writes) */
+#define NVGPU_VAB_MODE_DIRTY	BIT32(1U)
+
+/* No change to VAB logging with VPR setting requested */
+#define NVGPU_VAB_LOGGING_VPR_NONE  0U
+/* VAB logging disabled if vpr IN_USE=1, regardless of PROTECTED_MODE */
+#define NVGPU_VAB_LOGGING_VPR_IN_USE_DISABLED  BIT32(0U)
+/* VAB logging disabled if vpr PROTECTED_MODE=1, regardless of IN_USE */
+#define NVGPU_VAB_LOGGING_VPR_PROTECTED_DISABLED  BIT32(1U)
+/* VAB logging enabled regardless of IN_USE and PROTECTED_MODE */
+#define NVGPU_VAB_LOGGING_VPR_ENABLED  BIT32(2U)
+/* VAB logging disabled regardless of IN_USE and PROTECTED_MODE */
+#define NVGPU_VAB_LOGGING_VPR_DISABLED  BIT32(3U)
+
+struct nvgpu_vab_range_checker {
+
+	/*
+	 * in: starting physical address. Must be aligned by
+         *     1 << (granularity_shift + bitmask_size_shift) where
+	 *     bitmask_size_shift is a HW specific constant.
+	 */
+	u64 start_phys_addr;
+
+	/* in: log2 of coverage granularity per bit */
+	u8  granularity_shift;
+
+	u8  reserved[7];
+};
+
+struct nvgpu_vab {
+	u32 user_num_range_checkers;
+	struct nvgpu_mem buffer;
+};
+
+int nvgpu_fb_vab_init_hal(struct gk20a *g);
+int nvgpu_fb_vab_teardown_hal(struct gk20a *g);
+
+#endif /* NVGPU_NEXT_FB_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fuse.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fuse.h
new file mode 100644
index 000000000..5e687ae53
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fuse.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_FUSE_H
+#define NVGPU_NEXT_FUSE_H
+
+/**
+ * @file
+ *
+ * Declare device info specific struct and defines.
+ */
+#include <nvgpu/types.h>
+
+struct nvgpu_fuse_feature_override_ecc {
+	/** overide_ecc register feature */
+	/** sm_lrf enable */
+	bool sm_lrf_enable;
+	/** sm_lrf override */
+	bool sm_lrf_override;
+	/** sm_l1_data enable */
+	bool sm_l1_data_enable;
+	/** sm_l1_data overide */
+	bool sm_l1_data_override;
+	/** sm_l1_tag enable */
+	bool sm_l1_tag_enable;
+	/** sm_l1_tag overide */
+	bool sm_l1_tag_override;
+	/** ltc enable */
+	bool ltc_enable;
+	/** ltc overide */
+	bool ltc_override;
+	/** dram enable */
+	bool dram_enable;
+	/** dram overide */
+	bool dram_override;
+	/** sm_cbu enable */
+	bool sm_cbu_enable;
+	/** sm_cbu overide */
+	bool sm_cbu_override;
+
+	/** override_ecc_1 register feature */
+	/** sm_l0_icache enable */
+	bool sm_l0_icache_enable;
+	/** sm_l0_icache overide */
+	bool sm_l0_icache_override;
+	/** sm_l1_icache enable */
+	bool sm_l1_icache_enable;
+	/** sm_l1_icache overide */
+	bool sm_l1_icache_override;
+};
+
+#endif /* NVGPU_NEXT_FUSE_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ce.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ce.h
new file mode 100644
index 000000000..f6997b952
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ce.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_CE_H
+#define NVGPU_NEXT_GOPS_CE_H
+
+	/* Leave extra tab to fit into gops_ce structure */
+
+	void (*intr_retrigger)(struct gk20a *g, u32 inst_id);
+
+#endif /* NVGPU_NEXT_GOPS_CE_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_cg.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_cg.h
new file mode 100644
index 000000000..0dd821d58
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_cg.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_CG_H
+#define NVGPU_NEXT_GOPS_CG_H
+
+	/* Leave extra tab to fit into gops_cg structure */
+
+	void (*slcg_runlist_load_gating_prod)(struct gk20a *g, bool prod);
+	void (*blcg_runlist_load_gating_prod)(struct gk20a *g, bool prod);
+
+	/* Ring station slcg prod gops */
+	void (*slcg_rs_ctrl_fbp_load_gating_prod)(struct gk20a *g, bool prod);
+	void (*slcg_rs_ctrl_gpc_load_gating_prod)(struct gk20a *g, bool prod);
+	void (*slcg_rs_ctrl_sys_load_gating_prod)(struct gk20a *g, bool prod);
+	void (*slcg_rs_fbp_load_gating_prod)(struct gk20a *g, bool prod);
+	void (*slcg_rs_gpc_load_gating_prod)(struct gk20a *g, bool prod);
+	void (*slcg_rs_sys_load_gating_prod)(struct gk20a *g, bool prod);
+
+	void (*slcg_timer_load_gating_prod)(struct gk20a *g, bool prod);
+
+	void (*elcg_ce_load_gating_prod)(struct gk20a *g, bool prod);
+
+#endif /* NVGPU_NEXT_GOPS_CG_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb.h
new file mode 100644
index 000000000..57658ec0a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_FB_H
+#define NVGPU_NEXT_GOPS_FB_H
+
+	/* Leave extra tab to fit into gops_fb structure */
+
+	u32 (*get_num_active_ltcs)(struct gk20a *g);
+
+#ifdef CONFIG_NVGPU_MIG
+	int (*config_veid_smc_map)(struct gk20a *g, bool enable);
+	int (*set_smc_eng_config)(struct gk20a *g, bool enable);
+	int (*set_remote_swizid)(struct gk20a *g, bool enable);
+#endif
+	struct gops_fb_vab vab;
+
+#endif /* NVGPU_NEXT_GOPS_FB_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb_vab.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb_vab.h
new file mode 100644
index 000000000..a215868cc
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb_vab.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_FB_VAB_H
+#define NVGPU_NEXT_GOPS_FB_VAB_H
+
+struct nvgpu_vab_range_checker;
+
+struct gops_fb_vab {
+	/**
+	 * @brief Initialize VAB
+	 *
+	 */
+	int (*init)(struct gk20a *g);
+
+	/**
+	 * @brief Initialize VAB range checkers and enable VAB tracking
+	 *
+	 */
+	int (*reserve)(struct gk20a *g, u32 vab_mode, u32 num_range_checkers,
+		struct nvgpu_vab_range_checker *vab_range_checker);
+
+	/**
+	 * @brief Trigger VAB dump, copy buffer to user and clear
+	 *
+	 */
+	int (*dump_and_clear)(struct gk20a *g, u64 *user_buf,
+		u64 user_buf_size);
+
+	/**
+	 * @brief Disable VAB
+	 *
+	 */
+	int (*release)(struct gk20a *g);
+
+	/**
+	 * @brief Free VAB resources
+	 *
+	 */
+	int (*teardown)(struct gk20a *g);
+};
+
+#endif /* NVGPU_NEXT_GOPS_FB_VAB_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fifo.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fifo.h
new file mode 100644
index 000000000..affe95b7f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fifo.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_FIFO_H
+#define NVGPU_NEXT_GOPS_FIFO_H
+
+	/* Leave extra tab to fit into gops_fifo structure */
+
+	void (*runlist_intr_retrigger)(struct gk20a *g, u32 intr_tree);
+
+#endif /* NVGPU_NEXT_GOPS_FIFO_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fuse.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fuse.h
new file mode 100644
index 000000000..1d6957511
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fuse.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_FUSE_H
+#define NVGPU_NEXT_GOPS_FUSE_H
+
+	/* Leave extra tab to fit into gops_fuse structure */
+
+	void (*write_feature_override_ecc)(struct gk20a *g, u32 val);
+	void (*write_feature_override_ecc_1)(struct gk20a *g, u32 val);
+	void (*read_feature_override_ecc)(struct gk20a *g,
+			struct nvgpu_fuse_feature_override_ecc *ecc_feature);
+	u32 (*fuse_opt_sm_ttu_en)(struct gk20a *g);
+	u32 (*opt_sec_source_isolation_en)(struct gk20a *g);
+
+#endif /* NVGPU_NEXT_GOPS_FUSE_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr.h
new file mode 100644
index 000000000..d470f4bc3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_GR_H
+#define NVGPU_NEXT_GOPS_GR_H
+
+	/* Leave extra tab to fit into gops_gr_intr structure */
+	void (*vab_init)(struct gk20a *g, u32 vab_reg);
+	void (*vab_release)(struct gk20a *g, u32 vab_reg);
+
+#endif /* NVGPU_NEXT_GOPS_GR_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h
new file mode 100644
index 000000000..13fcab4c7
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_GR_CTXSW_PROG_H
+#define NVGPU_NEXT_GOPS_GR_CTXSW_PROG_H
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+	u32 (*hw_get_main_header_size)(void);
+	u32 (*hw_get_gpccs_header_stride)(void);
+	u32 (*get_compute_sysreglist_offset)(u32 *fecs_hdr);
+	u32 (*get_gfx_sysreglist_offset)(u32 *fecs_hdr);
+	u32 (*get_ltsreglist_offset)(u32 *fecs_hdr);
+	u32 (*get_compute_gpcreglist_offset)(u32 *gpccs_hdr);
+	u32 (*get_gfx_gpcreglist_offset)(u32 *gpccs_hdr);
+	u32 (*get_compute_tpcreglist_offset)(u32 *gpccs_hdr, u32 tpc_num);
+	u32 (*get_gfx_tpcreglist_offset)(u32 *gpccs_hdr, u32 tpc_num);
+	u32 (*get_compute_ppcreglist_offset)(u32 *gpccs_hdr);
+	u32 (*get_gfx_ppcreglist_offset)(u32 *gpccs_hdr);
+	u32 (*get_compute_etpcreglist_offset)(u32 *gpccs_hdr);
+	u32 (*get_gfx_etpcreglist_offset)(u32 *gpccs_hdr);
+#endif
+
+#endif /* NVGPU_NEXT_GOPS_GR_CTXSW_PROG_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_init.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_init.h
new file mode 100644
index 000000000..91c67adc8
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_init.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_GR_INIT_H
+#define NVGPU_NEXT_GOPS_GR_INIT_H
+
+	/* Leave extra tab to fit into gops_gr structure */
+
+	void (*auto_go_idle)(struct gk20a *g, bool enable);
+	void (*eng_config)(struct gk20a *g);
+	int (*reset_gpcs)(struct gk20a *g);
+	int (*sm_id_config_early)(struct gk20a *g,
+			struct nvgpu_gr_config *config);
+
+#endif /* NVGPU_NEXT_GOPS_GR_INIT_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_intr.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_intr.h
new file mode 100644
index 000000000..a3517ab71
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_intr.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_GR_INTR_H
+#define NVGPU_NEXT_GOPS_GR_INTR_H
+
+	/* Leave extra tab to fit into gops_gr_intr structure */
+	void (*retrigger)(struct gk20a *g);
+	u32 (*enable_mask)(struct gk20a *g);
+
+#endif /* NVGPU_NEXT_GOPS_GR_INTR_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_grmgr.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_grmgr.h
new file mode 100644
index 000000000..189476636
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_grmgr.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_GRMGR_H
+#define NVGPU_NEXT_GOPS_GRMGR_H
+
+	/* Leave extra tab to fit into gops_grmgr structure */
+
+	u32 (*get_max_sys_pipes)(struct gk20a *g);
+	const struct nvgpu_mig_gpu_instance_config* (*get_mig_config_ptr)(
+			struct gk20a *g);
+	u32 (*get_allowed_swizzid_size)(struct gk20a *g);
+	int (*get_gpc_instance_gpcgrp_id)(struct gk20a *g,
+			u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id);
+	int (*get_mig_gpu_instance_config)(struct gk20a *g,
+		const char **config_name, u32 *num_config_supported);
+	void (*load_timestamp_prod)(struct gk20a *g);
+
+#endif /* NVGPU_NEXT_GOPS_GRMGR_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc.h
new file mode 100644
index 000000000..63ac81217
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_LTC_H
+#define NVGPU_NEXT_GOPS_LTC_H
+
+	/* Leave extra tab to fit into gops_ltc structure */
+	u32 (*pri_shared_addr)(struct gk20a *g, u32 addr);
+	void (*ltc_lts_set_mgmt_setup)(struct gk20a *g);
+#endif /* NVGPU_NEXT_GOPS_LTC_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc_intr.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc_intr.h
new file mode 100644
index 000000000..6c78c8f4b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc_intr.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_LTC_INTR_H
+#define NVGPU_NEXT_GOPS_LTC_INTR_H
+
+	/* Leave extra tab to fit into gops_ltc structure */
+	void (*isr_extra)(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value);
+	void (*ltc_intr3_configure_extra)(struct gk20a *g, u32 *reg);
+
+#endif /* NVGPU_NEXT_GOPS_LTC_INTR_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_mc.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_mc.h
new file mode 100644
index 000000000..4cf160516
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_mc.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_MC_H
+#define NVGPU_NEXT_GOPS_MC_H
+
+	/* Leave extra tab to fit into gops_mc structure */
+
+	/**
+	 * @brief Reset HW engines.
+	 *
+	 * @param g [in]		The GPU driver struct.
+	 * @param devtype [in]		Type of device.
+	 *
+	 * This function is invoked to reset the engines while initializing
+	 * GR, CE and other engines during #nvgpu_finalize_poweron.
+	 *
+	 * Steps:
+	 * - Compute reset mask for all engines of given devtype.
+	 * - Disable given HW engines.
+	 *   - Acquire g->mc.enable_lock spinlock.
+	 *   - Read mc_device_enable_r register and clear the bits in read value
+	 *     corresponding to HW engines to be disabled.
+	 *   - Write mc_device_enable_r with the updated value.
+	 *   - Poll mc_device_enable_r to confirm register write success.
+	 *   - Release g->mc.enable_lock spinlock.
+	 * - If GR engines are being reset, reset GPCs.
+	 * - Enable the HW engines.
+	 *   - Acquire g->mc.enable_lock spinlock.
+	 *   - Read mc_device_enable_r register and set the bits in read value
+	 *     corresponding to HW engines to be enabled.
+	 *   - Write mc_device_enable_r with the updated value.
+	 *   - Poll mc_device_enable_r to confirm register write success.
+	 *   - Release g->mc.enable_lock spinlock.
+	 */
+	int (*reset_engines_all)(struct gk20a *g, u32 devtype);
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+	void (*elpg_enable)(struct gk20a *g);
+#endif
+	bool (*intr_get_unit_info)(struct gk20a *g, u32 unit);
+
+#endif /* NVGPU_NEXT_GOPS_MC_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_pbdma.h
new file mode 100644
index 000000000..348763f02
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_pbdma.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_PBDMA_H
+#define NVGPU_NEXT_GOPS_PBDMA_H
+
+	/* Leave extra tab to fit into gops_pbdma structure */
+
+	u32 (*set_channel_info_chid)(u32 chid);
+	u32 (*set_intr_notify)(u32 eng_intr_vector);
+	u32 (*get_mmu_fault_id)(struct gk20a *g, u32 pbdma_id);
+	void (*pbdma_force_ce_split)(struct gk20a *g);
+	u32 (*get_num_of_pbdmas)(void);
+
+#endif /* NVGPU_NEXT_GOPS_PBDMA_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_perf.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_perf.h
new file mode 100644
index 000000000..890e275d6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_perf.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_PERF_H
+#define NVGPU_NEXT_GOPS_PERF_H
+
+	/* Leave extra tab to fit into gops_fifo structure */
+	void (*enable_hs_streaming)(struct gk20a *g, bool enable);
+	void (*reset_hs_streaming_credits)(struct gk20a *g);
+	void (*enable_pmasys_legacy_mode)(struct gk20a *g, bool enable);
+
+#endif /* NVGPU_NEXT_GOPS_PERF_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_priv_ring.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_priv_ring.h
new file mode 100644
index 000000000..2d85305dc
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_priv_ring.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_PRIV_RING_H
+#define NVGPU_NEXT_GOPS_PRIV_RING_H
+
+	/* Leave extra tab to fit into gops_ce structure */
+#ifdef CONFIG_NVGPU_MIG
+	int (*config_gr_remap_window)(struct gk20a *g, u32 gr_syspipe_indx,
+		bool enable);
+	int (*config_gpc_rs_map)(struct gk20a *g, bool enable);
+#endif
+
+#endif /* NVGPU_NEXT_GOPS_PRIV_RING_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_runlist.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_runlist.h
new file mode 100644
index 000000000..d25e2d826
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_runlist.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_NEXT_GOPS_RUNLIST_H
+#define NVGPU_NEXT_GOPS_RUNLIST_H
+
+	/* Leave extra tab to fit into gops_runlist structure */
+
+	u32 (*get_runlist_id)(struct gk20a *g, u32 runlist_pri_base);
+	u32 (*get_engine_id_from_rleng_id)(struct gk20a *g,
+				u32 rleng_id, u32 runlist_pri_base);
+	u32 (*get_chram_bar0_offset)(struct gk20a *g, u32 runlist_pri_base);
+	void (*get_pbdma_info)(struct gk20a *g, u32 runlist_pri_base,
+				struct nvgpu_next_pbdma_info *pbdma_info);
+	u32 (*get_engine_intr_id)(struct gk20a *g, u32 runlist_pri_base,
+			u32 rleng_id);
+	u32 (*get_esched_fb_thread_id)(struct gk20a *g, u32 runlist_pri_base);
+
+#endif /* NVGPU_NEXT_GOPS_RUNLIST_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_litter.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_litter.h
new file mode 100644
index 000000000..38b31a861
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_litter.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_LITTER_H
+#define NVGPU_NEXT_LITTER_H
+
+/*
+ * Litter constants.
+ * These should be in sync with GPU_LIT_* constants defined in nvgpu/gk20a.h.
+ */
+#define GPU_LIT_ROP_IN_GPC_BASE			52
+#define GPU_LIT_ROP_IN_GPC_SHARED_BASE		53
+#define GPU_LIT_ROP_IN_GPC_PRI_SHARED_IDX	54
+#define GPU_LIT_ROP_IN_GPC_STRIDE		55
+
+
+#endif /* NVGPU_NEXT_LITTER_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mc.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mc.h
new file mode 100644
index 000000000..63b7875d8
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mc.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_MC_H
+#define NVGPU_NEXT_MC_H
+
+/**
+ * @file
+ *
+ * Declare intr specific struct.
+ */
+#include <nvgpu/types.h>
+#include <nvgpu/cic.h>
+
+struct nvgpu_intr_unit_info {
+	/**
+	 * top bit 0 -> subtree 0 -> leaf0, leaf1 -> leaf 0, 1
+	 * top bit 1 -> subtree 1 -> leaf0, leaf1 -> leaf 2, 3
+	 * top bit 2 -> subtree 2 -> leaf0, leaf1 -> leaf 4, 5
+	 * top bit 3 -> subtree 3 -> leaf0, leaf1 -> leaf 6, 7
+	 */
+	/**
+	 * h/w defined vectorids for the s/w defined intr unit.
+	 * Upto 32 vectorids (32 bits of a leaf register) are supported for
+	 * the intr units that support multiple vector ids.
+	 */
+	u32 vectorid[NVGPU_CIC_INTR_VECTORID_SIZE_MAX];
+	/** number of vectorid supported by the intr unit */
+	u32 vectorid_size;
+	u32 subtree;	/** subtree number corresponding to vectorid */
+	u64 subtree_mask; /** leaf1_leaf0 value for the intr unit */
+	/**
+	 * This flag will be set to true after all the fields
+	 * of nvgpu_intr_unit_info are configured.
+	 */
+	bool valid;
+};
+
+struct nvgpu_next_mc {
+	/**
+	 * intr info array indexed by s/w defined intr unit name
+	 */
+	struct nvgpu_intr_unit_info intr_unit_info[NVGPU_CIC_INTR_UNIT_MAX];
+	/**
+	 * Leaf mask per subtree. Subtree is a pair of leaf registers.
+	 * Each subtree corresponds to a bit in intr_top register.
+	 */
+	u64 subtree_mask_restore[HOST2SOC_NUM_SUBTREE];
+};
+#endif /* NVGPU_NEXT_MC_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mm.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mm.h
new file mode 100644
index 000000000..4a6bd9f66
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mm.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_MM_H
+#define NVGPU_NEXT_MM_H
+
+	/** VAB struct */
+	struct nvgpu_vab vab;
+
+#endif /* NVGPU_NEXT_MM_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_netlist.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_netlist.h
new file mode 100644
index 000000000..c04859c28
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_netlist.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_NETLIST_H
+#define NVGPU_NEXT_NETLIST_H
+
+/**
+ * @file
+ *
+ */
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_netlist_vars;
+struct netlist_av_list;
+
+bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g,
+			u32 region_id, u8 *src, u32 size,
+			struct nvgpu_netlist_vars *netlist_vars, int *err_code);
+void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g);
+
+struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(
+							struct gk20a *g);
+struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(
+							struct gk20a *g);
+#ifdef CONFIG_NVGPU_GRAPHICS
+struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(
+							struct gk20a *g);
+struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(
+							struct gk20a *g);
+#endif /* CONFIG_NVGPU_GRAPHICS */
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g,
+			u32 region_id, u8 *src, u32 size,
+			struct nvgpu_netlist_vars *netlist_vars, int *err_code);
+void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g);
+
+struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs(
+							struct gk20a *g);
+#ifdef CONFIG_NVGPU_GRAPHICS
+struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(
+							struct gk20a *g);
+struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(
+							struct gk20a *g);
+#endif /* CONFIG_NVGPU_GRAPHICS */
+u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g);
+u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g);
+u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g);
+u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g);
+u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g);
+void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g);
+#endif /* CONFIG_NVGPU_DEBUGGER */
+
+#endif /* NVGPU_NEXT_NETLIST_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_pbdma.h
new file mode 100644
index 000000000..9303b8c40
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_pbdma.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_PBDMA_H
+#define NVGPU_NEXT_PBDMA_H
+
+/**
+ * @file
+ *
+ * Declare pbdma specific struct and defines.
+ */
+#include <nvgpu/types.h>
+
+#define PBDMA_PER_RUNLIST_SIZE		2U
+#define NVGPU_INVALID_PBDMA_PRI_BASE	U32_MAX
+#define NVGPU_INVALID_PBDMA_ID		U32_MAX
+
+struct nvgpu_next_pbdma_info {
+	/** The pri offset of the i'th PBDMA for runlist_pri_base */
+	u32 pbdma_pri_base[PBDMA_PER_RUNLIST_SIZE];
+	/** The ID of the i'th PBDMA that runs channels on this runlist */
+	u32 pbdma_id[PBDMA_PER_RUNLIST_SIZE];
+};
+
+#endif /* NVGPU_NEXT_PBDMA_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_runlist.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_runlist.h
new file mode 100644
index 000000000..96abe038d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_runlist.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_NEXT_RUNLIST_H
+#define NVGPU_NEXT_RUNLIST_H
+
+/**
+ * @file
+ *
+ * Declare runlist info specific struct and defines.
+ */
+#include <nvgpu/types.h>
+
+struct nvgpu_next_pbdma_info;
+struct nvgpu_device;
+struct nvgpu_fifo;
+
+#define RLENG_PER_RUNLIST_SIZE			3
+
+struct nvgpu_next_runlist {
+	/** Runlist pri base - offset into device's runlist space */
+	u32 runlist_pri_base;
+	/** Channel ram address in bar0 pri space */
+	u32 chram_bar0_offset;
+	/** Pointer to pbdma info stored in engine_info*/
+	const struct nvgpu_next_pbdma_info *pbdma_info;
+	/** Pointer to engine info for per runlist engine id */
+	const struct nvgpu_device *rl_dev_list[RLENG_PER_RUNLIST_SIZE];
+};
+
+void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f);
+
+#endif /* NVGPU_NEXT_RUNLIST_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_sim.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_sim.h
new file mode 100644
index 000000000..c850bd0e8
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_sim.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_SIM_NEXT_H
+#define NVGPU_SIM_NEXT_H
+
+#include <nvgpu/types.h>
+
+#ifdef CONFIG_NVGPU_SIM
+
+struct gk20a;
+
+void nvgpu_next_init_sim_support(struct gk20a *g);
+
+#endif
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g);
+void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g);
+#endif /* CONFIG_NVGPU_DEBUGGER */
+
+int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g);
+void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g);
+#endif /* NVGPU_SIM_NEXT_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/riscv.h b/drivers/gpu/nvgpu/include/nvgpu/riscv.h
new file mode 100644
index 000000000..97c7a4b33
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/riscv.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_RISCV_H
+#define NVGPU_RISCV_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/falcon.h>
+struct gk20a;
+struct nvgpu_falcon;
+
+/**
+ * @brief Read the riscv register.
+ *
+ * @param flcn [in] The falcon.
+ * @param offset [in] offset of the register.
+ *
+ * This function is called to read a register with common flcn offset.
+ *
+ * Steps:
+ * - Read and return data from register at \a offset from
+ *   the base of riscv core of \a flcn.
+ *
+ * @return register data.
+ */
+u32 nvgpu_riscv_readl(struct nvgpu_falcon *flcn, u32 offset);
+
+/**
+ * @brief Write to the riscv register.
+ *
+ * @param flcn [in] The falcon.
+ * @param offset [in] Index of the register.
+ * @param data [in] Data to be written to the register.
+ *
+ * This function is called to write to a register with common flcn offset.
+ *
+ * Steps:
+ * - Write \a data to register at \a offet from base of
+ *   riscv core of \a flcn.
+ */
+void nvgpu_riscv_writel(struct nvgpu_falcon *flcn,
+                                       u32 offset, u32 val);
+
+/**
+ * @brief Dump RISCV BootROM status.
+ *
+ * @param flcn [in] The falcon.
+ *
+ * This function is called to get the status of RISCV BootROM.
+ *
+ * Steps:
+ * - Print the flcn's RISCV BCR control configuratation.
+ * - Print the flcn's RISCV BR priv lockdown status.
+ * - Print the flcn's BR retcode value.
+ */
+void nvgpu_riscv_dump_brom_stats(struct nvgpu_falcon *flcn);
+
+/**
+ * @brief Get the size of falcon's memory.
+ *
+ * @param flcn [in] The falcon.
+ * @param type [in] Falcon memory type (IMEM, DMEM).
+ *		    - Supported types: MEM_DMEM (0), MEM_IMEM (1)
+ * @param size [out] Size of the falcon memory type.
+ *
+ * This function is called to get the size of falcon's memory for validation
+ * while copying to IMEM/DMEM.
+ *
+ * Steps:
+ * - Validate that the passed in falcon struct is not NULL and is for supported
+ *   falcon. If not valid, return -EINVAL.
+ * - Read the size of the falcon memory of \a type in bytes from the HW config
+ *   register in output parameter \a size.
+ *
+ * @return 0 in case of success, < 0 in case of failure.
+ */
+int nvgpu_riscv_hs_ucode_load_bootstrap(struct nvgpu_falcon *flcn,
+						struct nvgpu_firmware *manifest_fw,
+						struct nvgpu_firmware *code_fw,
+						struct nvgpu_firmware *data_fw,
+						u64 ucode_sysmem_desc_addr);
+#endif /* NVGPU_RISCV_H */
diff --git a/drivers/gpu/nvgpu/nvgpu_next_gpuid.h b/drivers/gpu/nvgpu/nvgpu_next_gpuid.h
new file mode 100644
index 000000000..428056282
--- /dev/null
+++ b/drivers/gpu/nvgpu/nvgpu_next_gpuid.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <common/falcon/falcon_sw_ga10b.h>
+#include <common/acr/acr_sw_ga10b.h>
+#include <common/acr/acr_sw_ga100.h>
+
+#ifndef NVGPU_NEXT_GPUID_H
+#define NVGPU_NEXT_GPUID_H
+
+#define NVGPU_NEXT_GPUID	0x0000017b
+
+#define NVGPU_NEXT_FECS_UCODE_SIG "ga10b/fecs_sig.bin"
+#define NVGPU_NEXT_GPCCS_UCODE_SIG "ga10b/gpccs_sig.bin"
+
+#define NVGPU_NEXT_INIT_HAL		ga10b_init_hal
+#define NVGPU_NEXT_INIT_OS_OPS		nvgpu_ga10b_init_os_ops
+#define NVGPU_NEXT_COMPATIBLE		"nvidia,ga10b"
+#define NVGPU_NEXT_PLATFORM		ga10b_tegra_platform
+
+#define NVGPU_NEXT_COMPATIBLE_VGPU "nvidia,ga10b-vgpu"
+#define NVGPU_NEXT_VGPU_INIT_HAL vgpu_ga10b_init_hal
+#define NVGPU_NEXT_PLATFORM_VGPU ga10b_vgpu_tegra_platform
+
+#define NVGPU_NEXT_PROFILER_QUIESCE	nvgpu_next_profiler_hs_stream_quiesce
+#ifdef CONFIG_NVGPU_DGPU
+#define NVGPU_NEXT_DGPU_GPUID		0x00000170
+#define NVGPU_NEXT_DGPU_INIT_HAL	ga100_init_hal
+#define NEXT_DGPU_FECS_UCODE_SIG	"ga100/fecs_sig.bin"
+#define NEXT_DGPU_GPCCS_UCODE_SIG	"ga100/gpccs_sig.bin"
+
+extern int ga100_init_hal(struct gk20a *g);
+#endif
+
+struct nvgpu_os_linux;
+
+extern int ga10b_init_hal(struct gk20a *g);
+
+extern struct gk20a_platform ga10b_tegra_platform;
+
+extern void nvgpu_next_perfmon_sw_init(struct gk20a *g,
+		struct nvgpu_pmu_perfmon *perfmon);
+
+extern void nvgpu_next_pg_sw_init(struct gk20a *g, struct nvgpu_pmu_pg *pg);
+
+int vgpu_ga10b_init_hal(struct gk20a *g);
+extern struct gk20a_platform ga10b_vgpu_tegra_platform;
+
+extern void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g);
+
+#endif
diff --git a/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.c b/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.c
new file mode 100644
index 000000000..4f52ecdcb
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.c
@@ -0,0 +1,137 @@
+/*
+ * GA10B Tegra Platform Interface
+ *
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/uaccess.h>
+#include <uapi/linux/nvgpu.h>
+
+#include <nvgpu/profiler.h>
+#include <nvgpu/log.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/kmem.h>
+#include <nvgpu/fb.h>
+
+#include "nvgpu_next_ioctl_prof.h"
+
+static u32 nvgpu_prof_vab_reserve_translate_vab_mode(struct gk20a *g, u32 mode)
+{
+	u32 vab_mode = 0U;
+
+	if (mode == NVGPU_PROFILER_VAB_RANGE_CHECKER_MODE_ACCESS) {
+		vab_mode = NVGPU_VAB_MODE_ACCESS;
+	} else if (mode == NVGPU_PROFILER_VAB_RANGE_CHECKER_MODE_DIRTY) {
+		vab_mode = NVGPU_VAB_MODE_DIRTY;
+	} else {
+		nvgpu_err(g, "Unknown vab mode: 0x%x", mode);
+	}
+
+	return vab_mode;
+}
+
+static int nvgpu_prof_ioctl_vab_reserve(struct nvgpu_profiler_object *prof,
+		struct nvgpu_profiler_vab_reserve_args *arg)
+{
+	struct gk20a *g = prof->g;
+	int err;
+	u32 vab_mode = nvgpu_prof_vab_reserve_translate_vab_mode(g,
+		(u32)arg->vab_mode);
+	struct nvgpu_profiler_vab_range_checker *user_ckr =
+		(struct nvgpu_profiler_vab_range_checker *)(uintptr_t)
+		arg->range_checkers_ptr;
+	struct nvgpu_vab_range_checker *ckr;
+
+	if (arg->num_range_checkers == 0) {
+		nvgpu_err(g, "Range checkers cannot be zero");
+		return -EINVAL;
+	}
+
+	ckr = nvgpu_kzalloc(g, sizeof(struct nvgpu_vab_range_checker) *
+		arg->num_range_checkers);
+	if (copy_from_user(ckr, user_ckr,
+		sizeof(struct nvgpu_vab_range_checker) *
+		arg->num_range_checkers)) {
+		return -EFAULT;
+	}
+
+	err = g->ops.fb.vab.reserve(g, vab_mode, arg->num_range_checkers, ckr);
+
+	nvgpu_kfree(g, ckr);
+
+	return err;
+}
+
+static int nvgpu_prof_ioctl_vab_flush(struct nvgpu_profiler_object *prof,
+		struct nvgpu_profiler_vab_flush_state_args *arg)
+{
+	int err;
+	struct gk20a *g = prof->g;
+	u64 *user_data = nvgpu_kzalloc(g, arg->buffer_size);
+
+	err = g->ops.fb.vab.dump_and_clear(g, user_data, arg->buffer_size);
+	if (err < 0) {
+		goto fail;
+	}
+
+	if (copy_to_user((void __user *)(uintptr_t)arg->buffer_ptr,
+			user_data, arg->buffer_size)) {
+		nvgpu_err(g, "copy_to_user failed!");
+		err = -EFAULT;
+	}
+
+fail:
+	nvgpu_kfree(g, user_data);
+	return err;
+}
+
+int nvgpu_next_prof_fops_ioctl(struct nvgpu_profiler_object *prof,
+	unsigned int cmd, void *buf)
+{
+	int err = -ENOTTY;
+	struct gk20a *g = prof->g;
+
+	switch (cmd) {
+	case NVGPU_PROFILER_IOCTL_VAB_RESERVE:
+		if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_VAB_ENABLED)) {
+			break;
+		}
+
+		err = nvgpu_prof_ioctl_vab_reserve(prof,
+			(struct nvgpu_profiler_vab_reserve_args *)buf);
+		break;
+
+	case NVGPU_PROFILER_IOCTL_VAB_FLUSH_STATE:
+		if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_VAB_ENABLED)) {
+			break;
+		}
+
+		err = nvgpu_prof_ioctl_vab_flush(prof,
+			(struct nvgpu_profiler_vab_flush_state_args *)buf);
+		break;
+
+	case NVGPU_PROFILER_IOCTL_VAB_RELEASE:
+		if (nvgpu_is_enabled(g, NVGPU_SUPPORT_VAB_ENABLED)) {
+			err = g->ops.fb.vab.release(g);
+		}
+		break;
+
+	default:
+		nvgpu_err(g, "unrecognized profiler ioctl cmd: 0x%x", cmd);
+		err = -ENOTTY;
+		break;
+	}
+	return err;
+}
diff --git a/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.h b/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.h
new file mode 100644
index 000000000..52e08ce05
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef LINUX_NVGPU_NEXT_IOCTL_PROF_H
+#define LINUX_NVGPU_NEXT_IOCTL_PROF_H
+
+struct nvgpu_profiler_object;
+
+int nvgpu_next_prof_fops_ioctl(struct nvgpu_profiler_object *prof,
+	unsigned int cmd, void *buf);
+
+#endif /* LINUX_NVGPU_NEXT_IOCTL_PROF_H */
diff --git a/drivers/gpu/nvgpu/os/linux/nvlink/hal/ga10b_mssnvlink.c b/drivers/gpu/nvgpu/os/linux/nvlink/hal/ga10b_mssnvlink.c
new file mode 100644
index 000000000..c3018718f
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/nvlink/hal/ga10b_mssnvlink.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/soc.h>
+#include <os/linux/module.h>
+#include <os/linux/os_linux.h>
+
+#define MSS_NVLINK_INTERNAL_NUM                 8U
+#define MSS_NVLINK_GLOBAL_CREDIT_CONTROL_0      0x00000010
+#define MSS_NVLINK_MCF_MEMORY_TYPE_CONTROL_0    0x00000040
+
+#define MSS_NVLINK_SIZE                         0x00001000
+#define MSS_NVLINK_1_BASE                       0x01f20000
+#define MSS_NVLINK_2_BASE                       0x01f40000
+#define MSS_NVLINK_3_BASE                       0x01f60000
+#define MSS_NVLINK_4_BASE                       0x01f80000
+#define MSS_NVLINK_5_BASE                       0x01fa0000
+#define MSS_NVLINK_6_BASE                       0x01fc0000
+#define MSS_NVLINK_7_BASE                       0x01fe0000
+#define MSS_NVLINK_8_BASE                       0x01e00000
+#define MSS_NVLINK_INIT_CREDITS                 0x00000001U
+#define MSS_NVLINK_FORCE_COH_SNP		0x3U
+
+void ga10b_init_nvlink_soc_credits(struct gk20a *g)
+{
+	u32 i = 0U;
+	u32 val = MSS_NVLINK_INIT_CREDITS;
+	struct device *dev = dev_from_gk20a(g);
+
+	u32 nvlink_base[MSS_NVLINK_INTERNAL_NUM] = {
+		MSS_NVLINK_1_BASE, MSS_NVLINK_2_BASE, MSS_NVLINK_3_BASE,
+		MSS_NVLINK_4_BASE, MSS_NVLINK_5_BASE, MSS_NVLINK_6_BASE,
+		MSS_NVLINK_7_BASE, MSS_NVLINK_8_BASE
+	};
+
+	void __iomem *mssnvlink_control[MSS_NVLINK_INTERNAL_NUM];
+
+	if (nvgpu_platform_is_simulation(g)) {
+		nvgpu_log(g, gpu_dbg_info, "simulation platform: "
+			"nvlink soc credits not required");
+		return;
+	}
+
+	if (nvgpu_is_bpmp_running(g) ) {
+		nvgpu_log(g, gpu_dbg_info, "bpmp running: "
+			"nvlink soc credits init done by bpmp");
+		return;
+	}
+	/* init nvlink soc credits and force snoop */
+	for (i = 0U; i < MSS_NVLINK_INTERNAL_NUM; i++) {
+		mssnvlink_control[i] = nvgpu_devm_ioremap(dev,
+			nvlink_base[i], MSS_NVLINK_SIZE);
+	}
+
+	nvgpu_log(g, gpu_dbg_info, "init nvlink soc credits");
+
+	for (i = 0U; i < MSS_NVLINK_INTERNAL_NUM; i++) {
+		writel_relaxed(val, (*(mssnvlink_control + i) +
+				 MSS_NVLINK_GLOBAL_CREDIT_CONTROL_0));
+	}
+
+	/*
+	 * Set force snoop, always snoop all nvlink memory transactions
+	 * (both coherent and non-coherent)
+	 */
+	nvgpu_log(g, gpu_dbg_info, "set force snoop");
+
+	for (i = 0U; i < MSS_NVLINK_INTERNAL_NUM; i++) {
+		val = readl_relaxed((*(mssnvlink_control + i) +
+			MSS_NVLINK_MCF_MEMORY_TYPE_CONTROL_0));
+		val &= ~(MSS_NVLINK_FORCE_COH_SNP);
+		val |= MSS_NVLINK_FORCE_COH_SNP;
+		writel_relaxed(val, *(mssnvlink_control + i) +
+			MSS_NVLINK_MCF_MEMORY_TYPE_CONTROL_0);
+	}
+}
diff --git a/drivers/gpu/nvgpu/os/linux/platform_ga10b_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_ga10b_tegra.c
new file mode 100644
index 000000000..0e09c1f0d
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/platform_ga10b_tegra.c
@@ -0,0 +1,325 @@
+/*
+ * GA10B Tegra Platform Interface
+ *
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/of_platform.h>
+#include <linux/debugfs.h>
+#include <linux/dma-buf.h>
+#include <linux/nvmap.h>
+#include <linux/reset.h>
+#include <linux/iommu.h>
+#include <linux/hashtable.h>
+#include <linux/clk.h>
+#ifdef CONFIG_TEGRA_BWMGR
+#include <linux/platform/tegra/emc_bwmgr.h>
+#endif
+#include <linux/pm_runtime.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/nvhost.h>
+
+#include <uapi/linux/nvgpu.h>
+
+#include "os/linux/platform_gk20a.h"
+#include "os/linux/clk.h"
+#include "os/linux/scale.h"
+
+#include "os/linux/platform_gp10b.h"
+
+#include "os/linux/os_linux.h"
+#include "os/linux/platform_gk20a_tegra.h"
+
+#define EMC3D_GA10B_RATIO 500
+
+#define GPCCLK_INIT_RATE 1000000000UL
+#define SYSCLK_INIT_RATE 204000000UL
+
+struct gk20a_platform_clk tegra_ga10b_clocks[] = {
+	{"sysclk", SYSCLK_INIT_RATE},
+	{"gpc0clk", GPCCLK_INIT_RATE},
+	{"gpc1clk", GPCCLK_INIT_RATE},
+	{"fuse", UINT_MAX}
+};
+
+static int ga10b_tegra_get_clocks(struct device *dev)
+{
+	return gp10b_tegra_acquire_platform_clocks(dev, tegra_ga10b_clocks,
+			ARRAY_SIZE(tegra_ga10b_clocks));
+}
+
+void ga10b_tegra_scale_init(struct device *dev)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+	struct gk20a_scale_profile *profile = platform->g->scale_profile;
+
+	if (!profile)
+		return;
+
+	platform->g->emc3d_ratio = EMC3D_GA10B_RATIO;
+
+	gp10b_tegra_scale_init(dev);
+}
+
+static void ga10b_tegra_scale_exit(struct device *dev)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+	struct gk20a_scale_profile *profile = platform->g->scale_profile;
+
+	if (profile)
+		tegra_bwmgr_unregister(
+			(struct tegra_bwmgr_client *)profile->private_data);
+}
+
+static int ga10b_tegra_probe(struct device *dev)
+{
+	struct gk20a_platform *platform = dev_get_drvdata(dev);
+	int err;
+	bool joint_xpu_rail = false;
+	struct gk20a *g = platform->g;
+#ifdef CONFIG_OF
+	struct device_node *of_chosen;
+#endif
+
+	err = nvgpu_nvhost_syncpt_init(platform->g);
+	if (err) {
+		if (err != -ENOSYS)
+			return err;
+	}
+
+	err = gk20a_tegra_init_secure_alloc(platform);
+	if (err)
+		return err;
+
+	platform->disable_bigpage = !iommu_get_domain_for_dev(dev) &&
+		(NVGPU_CPU_PAGE_SIZE < SZ_64K);
+
+#ifdef CONFIG_OF
+	of_chosen = of_find_node_by_path("/chosen");
+	if (!of_chosen)
+		return -ENODEV;
+
+	joint_xpu_rail = of_property_read_bool(of_chosen,
+				"nvidia,tegra-joint_xpu_rail");
+#endif
+
+	if (joint_xpu_rail) {
+		nvgpu_log_info(g, "XPU rails are joint\n");
+		platform->can_railgate_init = false;
+		nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, false);
+	}
+
+	err = ga10b_tegra_get_clocks(dev);
+	if (err != 0) {
+		return err;
+	}
+	nvgpu_linux_init_clk_support(platform->g);
+
+	nvgpu_mutex_init(&platform->clk_get_freq_lock);
+
+	return 0;
+}
+
+static int ga10b_tegra_late_probe(struct device *dev)
+{
+	return 0;
+}
+
+static int ga10b_tegra_remove(struct device *dev)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+
+	ga10b_tegra_scale_exit(dev);
+
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+	nvgpu_free_nvhost_dev(get_gk20a(dev));
+#endif
+
+	nvgpu_mutex_destroy(&platform->clk_get_freq_lock);
+
+	return 0;
+}
+
+static bool ga10b_tegra_is_railgated(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+	bool ret = false;
+
+	if (pm_runtime_status_suspended(dev)) {
+		ret = true;
+	}
+
+	nvgpu_log(g, gpu_dbg_info, "railgated? %s", ret ? "yes" : "no");
+
+	return ret;
+}
+
+static int ga10b_tegra_railgate(struct device *dev)
+{
+#ifdef CONFIG_TEGRA_BWMGR
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+	struct gk20a_scale_profile *profile = platform->g->scale_profile;
+
+	/* remove emc frequency floor */
+	if (profile)
+		tegra_bwmgr_set_emc(
+			(struct tegra_bwmgr_client *)profile->private_data,
+			0, TEGRA_BWMGR_SET_EMC_FLOOR);
+#endif /* CONFIG_TEGRA_BWMGR */
+
+	gp10b_tegra_clks_control(dev, false);
+
+	return 0;
+}
+
+static int ga10b_tegra_unrailgate(struct device *dev)
+{
+	int ret = 0;
+#ifdef CONFIG_TEGRA_BWMGR
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+	struct gk20a_scale_profile *profile = platform->g->scale_profile;
+#endif
+
+	gp10b_tegra_clks_control(dev, true);
+
+#ifdef CONFIG_TEGRA_BWMGR
+	/* to start with set emc frequency floor to max rate*/
+	if (profile)
+		tegra_bwmgr_set_emc(
+			(struct tegra_bwmgr_client *)profile->private_data,
+			tegra_bwmgr_get_max_emc_rate(),
+			TEGRA_BWMGR_SET_EMC_FLOOR);
+#endif
+	return ret;
+}
+
+static int ga10b_tegra_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static bool is_tpc_mask_valid(struct gk20a_platform *platform, u32 tpc_pg_mask)
+{
+	u32 i;
+	bool valid = false;
+
+	for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) {
+		if (tpc_pg_mask == platform->valid_tpc_mask[i]) {
+			valid = true;
+			break;
+		}
+	}
+	return valid;
+}
+
+static void ga10b_tegra_set_tpc_pg_mask(struct device *dev, u32 tpc_pg_mask)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+	struct gk20a *g = get_gk20a(dev);
+
+	if (is_tpc_mask_valid(platform, tpc_pg_mask)) {
+		g->tpc_pg_mask = tpc_pg_mask;
+	}
+}
+
+struct gk20a_platform ga10b_tegra_platform = {
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+	.has_syncpoints = true,
+#endif
+
+	/* ptimer src frequency in hz*/
+	.ptimer_src_freq = 31250000,
+
+	.ch_wdt_init_limit_ms = 5000,
+
+	.probe = ga10b_tegra_probe,
+	.late_probe = ga10b_tegra_late_probe,
+	.remove = ga10b_tegra_remove,
+	.railgate_delay_init    = 500,
+	.can_railgate_init      = false,
+
+	/* add tpc powergate JIRA NVGPU-4683 */
+	.can_tpc_powergate      = false,
+
+	.set_tpc_pg_mask	= ga10b_tegra_set_tpc_pg_mask,
+
+	.can_slcg               = false,
+	.can_blcg               = false,
+	.can_elcg               = false,
+	.enable_slcg            = false,
+	.enable_blcg            = false,
+	.enable_elcg            = false,
+	.enable_perfmon         = true,
+
+	/* power management configuration  JIRA NVGPU-4683 */
+	.enable_elpg            = true,
+	.enable_elpg_ms         = true,
+	.can_elpg_init          = true,
+	.enable_aelpg           = false,
+
+	/* power management callbacks */
+	.suspend = ga10b_tegra_suspend,
+	.railgate = ga10b_tegra_railgate,
+	.unrailgate = ga10b_tegra_unrailgate,
+	.is_railgated = ga10b_tegra_is_railgated,
+
+	.busy = gk20a_tegra_busy,
+	.idle = gk20a_tegra_idle,
+
+	.clk_round_rate = gp10b_round_clk_rate,
+	.get_clk_freqs = gp10b_clk_get_freqs,
+
+	/* frequency scaling configuration */
+	.initscale = ga10b_tegra_scale_init,
+	.prescale = gp10b_tegra_prescale,
+	.postscale = gp10b_tegra_postscale,
+	/* Enable ga10b frequency scaling - JIRA NVGPU-4683 */
+	.devfreq_governor = NULL,
+
+	.qos_notify = gk20a_scale_qos_notify,
+
+	.dump_platform_dependencies = gk20a_tegra_debug_dump,
+
+	.platform_chip_id = TEGRA_234,
+	.soc_name = "tegra23x",
+
+	.honors_aperture = true,
+	.unified_memory = true,
+
+	/*
+	 * This specifies the maximum contiguous size of a DMA mapping to Linux
+	 * kernel's DMA framework.
+	 * The IOMMU is capable of mapping all of physical memory and hence
+	 * dma_mask is set to memory size (128GB in this case).
+	 * For iGPU, nvgpu executes own dma allocs (e.g. alloc_page()) and
+	 * sg_table construction. No IOMMU mapping is required and so dma_mask
+	 * value is not important.
+	 * However, for dGPU connected over PCIe through an IOMMU, dma_mask is
+	 * significant. In this case, IOMMU bit in GPU physical address is not
+	 * relevant.
+	 */
+	.dma_mask = DMA_BIT_MASK(37),
+
+	.reset_assert = gp10b_tegra_reset_assert,
+	.reset_deassert = gp10b_tegra_reset_deassert,
+
+	/*
+	 * Size includes total size of ctxsw VPR buffers.
+	 * The size can vary for different chips as attribute ctx buffer
+	 * size depends on max number of tpcs supported on the chip.
+	 */
+	.secure_buffer_size = 0x400000, /* 4 MB */
+};
diff --git a/drivers/gpu/nvgpu/os/linux/vgpu/ga10b/platform_ga10b_vgpu_tegra.c b/drivers/gpu/nvgpu/os/linux/vgpu/ga10b/platform_ga10b_vgpu_tegra.c
new file mode 100644
index 000000000..7dcc31134
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/vgpu/ga10b/platform_ga10b_vgpu_tegra.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/platform_device.h>
+
+#include <linux/dma-mapping.h>
+
+#include <nvgpu/nvhost.h>
+#include <nvgpu/gk20a.h>
+
+#include "common/vgpu/clk_vgpu.h"
+#include "os/linux/platform_gk20a.h"
+#include "os/linux/os_linux.h"
+#include "os/linux/vgpu/vgpu_linux.h"
+#include "os/linux/vgpu/platform_vgpu_tegra.h"
+#include "os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.h"
+
+struct gk20a_platform ga10b_vgpu_tegra_platform = {
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+	.has_syncpoints = true,
+#endif
+
+	/* power management configuration */
+	.can_railgate_init      = false,
+	.can_elpg_init          = false,
+	.enable_slcg            = false,
+	.enable_blcg            = false,
+	.enable_elcg            = false,
+	.enable_elpg            = false,
+	.enable_elpg_ms         = false,
+	.enable_aelpg           = false,
+	.can_slcg               = false,
+	.can_blcg               = false,
+	.can_elcg               = false,
+
+	.ch_wdt_init_limit_ms = 5000,
+
+	.probe = gv11b_vgpu_probe,
+
+	.clk_round_rate = vgpu_plat_clk_round_rate,
+	.get_clk_freqs = vgpu_plat_clk_get_freqs,
+
+	.platform_chip_id = TEGRA_194_VGPU,
+
+	/* frequency scaling configuration */
+	.devfreq_governor = "userspace",
+
+	.virtual_dev = true,
+
+	/* power management callbacks */
+	.suspend = vgpu_tegra_suspend,
+	.resume = vgpu_tegra_resume,
+
+	.unified_memory = true,
+	.dma_mask = DMA_BIT_MASK(36),
+};