From 3e5fda3730e95fb67884e1ca9364737cf810e8fd Mon Sep 17 00:00:00 2001 From: Divya Singhatwaria Date: Fri, 17 May 2019 14:47:09 +0530 Subject: [PATCH] gpu: nvgpu: Fix MISRA 17.7 violations for PMU-FW unit - Rule 17.7 states that the value returned by a function having non-void return type shall be used. - Fix this violation by proper error handling. JIRA NVGPU-3419 Change-Id: Ia66906747cc2a95ea7f1ce5da16e4251ff521e53 Signed-off-by: Divya Singhatwaria Reviewed-on: https://git-master.nvidia.com/r/2121936 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Sagar Kamble GVS: Gerrit_Virtual_Submit Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c b/drivers/gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c index a41b087d0..190152a96 100644 --- a/drivers/gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c +++ b/drivers/gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c @@ -56,6 +56,20 @@ exit: return err; } +static void pmu_free_ns_ucode_blob(struct gk20a *g) +{ + struct nvgpu_pmu *pmu = g->pmu; + struct mm_gk20a *mm = &g->mm; + struct vm_gk20a *vm = mm->pmu.vm; + struct pmu_rtos_fw *rtos_fw = pmu->fw; + + nvgpu_log_fn(g, " "); + + if (nvgpu_mem_is_valid(&rtos_fw->ucode)) { + nvgpu_dma_unmap_free(vm, &rtos_fw->ucode); + } +} + int nvgpu_pmu_ns_fw_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu) { int err; @@ -70,7 +84,14 @@ int nvgpu_pmu_ns_fw_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu) /* Do non-secure PMU boot */ nvgpu_mutex_acquire(&pmu->isr_mutex); - nvgpu_falcon_reset(pmu->flcn); + err = nvgpu_falcon_reset(pmu->flcn); + if (err != 0) { + nvgpu_err(g, "falcon reset failed"); + /* free the ns ucode blob */ + pmu_free_ns_ucode_blob(g); + nvgpu_mutex_release(&pmu->isr_mutex); + return err; + } pmu->isr_enabled = true; nvgpu_mutex_release(&pmu->isr_mutex);