From 3e6779d554bcb561d961b717b585776664dc7147 Mon Sep 17 00:00:00 2001 From: Amurthyreddy Date: Mon, 15 Oct 2018 10:30:17 +0530 Subject: [PATCH] gpu: nvgpu: MISRA 14.4 err/ret/status as boolean MISRA rule 14.4 doesn't allow the usage of integer types as booleans in the controlling expression of an if statement or an iteration statement. Fix violations where the integer variables err, ret, status are used as booleans in the controlling expression of if and loop statements. JIRA NVGPU-1019 Change-Id: I36494e84ee6cd4a108e2a539f48f102e47e2f7f4 Signed-off-by: Amurthyreddy Reviewed-on: https://git-master.nvidia.com/r/1926820 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/clk/clk.c | 89 ++++++++++--------- drivers/gpu/nvgpu/clk/clk.h | 10 +-- drivers/gpu/nvgpu/clk/clk_arb.c | 10 +-- drivers/gpu/nvgpu/clk/clk_domain.c | 40 ++++----- drivers/gpu/nvgpu/clk/clk_domain.h | 2 +- drivers/gpu/nvgpu/clk/clk_fll.c | 16 ++-- drivers/gpu/nvgpu/clk/clk_freq_controller.c | 20 ++--- drivers/gpu/nvgpu/clk/clk_prog.c | 42 ++++----- drivers/gpu/nvgpu/clk/clk_prog.h | 4 +- drivers/gpu/nvgpu/clk/clk_vf_point.c | 24 ++--- drivers/gpu/nvgpu/clk/clk_vin.c | 28 +++--- drivers/gpu/nvgpu/clk/clk_vin.h | 4 +- .../nvgpu/common/boardobj/boardobjgrpmask.c | 16 ++-- .../common/sync/channel_sync_semaphore.c | 4 +- .../gpu/nvgpu/include/nvgpu/boardobjgrpmask.h | 16 ++-- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 6 +- drivers/gpu/nvgpu/pmgr/pmgr.c | 16 ++-- drivers/gpu/nvgpu/pmgr/pmgr.h | 2 +- drivers/gpu/nvgpu/pmgr/pmgrpmu.c | 48 +++++----- drivers/gpu/nvgpu/pmgr/pmgrpmu.h | 2 +- drivers/gpu/nvgpu/pmgr/pwrdev.c | 10 +-- drivers/gpu/nvgpu/pmgr/pwrmonitor.c | 14 +-- drivers/gpu/nvgpu/pmgr/pwrpolicy.c | 40 ++++----- drivers/gpu/nvgpu/pmu_perf/perf_gv100.c | 6 +- drivers/gpu/nvgpu/pmu_perf/perf_gv100.h | 2 +- drivers/gpu/nvgpu/pmu_perf/pmu_perf.c | 6 +- drivers/gpu/nvgpu/pmu_perf/pmu_perf.h | 2 +- drivers/gpu/nvgpu/pmu_perf/vfe_equ.c | 24 ++--- drivers/gpu/nvgpu/pmu_perf/vfe_var.c | 54 +++++------ 29 files changed, 279 insertions(+), 278 deletions(-) diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index d44981b62..4292f1f8c 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c @@ -61,7 +61,7 @@ int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload) { struct pmu_cmd cmd; struct pmu_payload payload; - u32 status; + int status; u32 seqdesc; struct nv_pmu_clk_rpc rpccall; struct clkrpc_pmucmdhandler_params handler; @@ -102,7 +102,7 @@ int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload) PMU_COMMAND_QUEUE_LPQ, clkrpc_pmucmdhandler, (void *)&handler, &seqdesc, ~0); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to post clk RPC cmd %x", cmd.cmd.clk.cmd_type); goto done; @@ -120,11 +120,11 @@ done: return status; } -u32 clk_freq_effective_avg(struct gk20a *g, u32 clkDomainMask) { +int clk_freq_effective_avg(struct gk20a *g, u32 *freqkHz, u32 clkDomainMask) { struct pmu_cmd cmd; struct pmu_payload payload; - u32 status; + int status = 0; u32 seqdesc; struct nv_pmu_clk_rpc rpccall; struct clkrpc_pmucmdhandler_params handler; @@ -162,7 +162,7 @@ u32 clk_freq_effective_avg(struct gk20a *g, u32 clkDomainMask) { PMU_COMMAND_QUEUE_LPQ, clkrpc_pmucmdhandler, (void *)&handler, &seqdesc, ~0); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to post clk RPC cmd %x", cmd.cmd.clk.cmd_type); goto done; @@ -177,7 +177,7 @@ u32 clk_freq_effective_avg(struct gk20a *g, u32 clkDomainMask) { goto done; } - return rpccall.params.clk_freq_effective_avg.freqkHz[clkDomainMask]; + *freqkHz = rpccall.params.clk_freq_effective_avg.freqkHz[clkDomainMask]; done: return status; @@ -187,7 +187,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx) { struct pmu_cmd cmd; struct pmu_payload payload; - u32 status; + int status; u32 seqdesc; struct nv_pmu_clk_rpc rpccall; struct clkrpc_pmucmdhandler_params handler; @@ -240,7 +240,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx) } } - if (status) { + if (status != 0) { nvgpu_err(g, "Error in generating mask used to select CFC"); goto done; } @@ -268,7 +268,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx) clkrpc_pmucmdhandler, (void *)&handler, &seqdesc, ~0); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to post clk RPC cmd %x", cmd.cmd.clk.cmd_type); goto done; @@ -287,11 +287,11 @@ done: return status; } -u32 clk_pmu_vin_load(struct gk20a *g) +int clk_pmu_vin_load(struct gk20a *g) { struct pmu_cmd cmd; struct pmu_payload payload; - u32 status; + int status; u32 seqdesc; struct nv_pmu_clk_rpc rpccall; struct clkrpc_pmucmdhandler_params handler; @@ -330,7 +330,7 @@ u32 clk_pmu_vin_load(struct gk20a *g) clkrpc_pmucmdhandler, (void *)&handler, &seqdesc, ~0); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to post clk RPC cmd %x", cmd.cmd.clk.cmd_type); goto done; @@ -424,11 +424,11 @@ u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g, return 0; } -static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) +static int clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) { struct pmu_cmd cmd; struct pmu_payload payload; - u32 status; + int status; u32 seqdesc; struct nv_pmu_clk_rpc rpccall; struct clkrpc_pmucmdhandler_params handler; @@ -478,7 +478,7 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) clkrpc_pmucmdhandler, (void *)&handler, &seqdesc, ~0); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to post clk RPC cmd %x", cmd.cmd.clk.cmd_type); goto done; @@ -555,7 +555,7 @@ int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk) /*set regime ids */ status = get_regime_id(g, CTRL_CLK_DOMAIN_GPC2CLK, &setfllclk->current_regime_id_gpc); - if (status) { + if (status != 0) { goto done; } @@ -564,7 +564,7 @@ int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk) status = get_regime_id(g, CTRL_CLK_DOMAIN_SYS2CLK, &setfllclk->current_regime_id_sys); - if (status) { + if (status != 0) { goto done; } @@ -573,7 +573,7 @@ int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk) status = get_regime_id(g, CTRL_CLK_DOMAIN_XBAR2CLK, &setfllclk->current_regime_id_xbar); - if (status) { + if (status != 0) { goto done; } @@ -582,26 +582,26 @@ int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk) status = clk_pmu_vf_inject(g, setfllclk); - if (status) { + if (status != 0) { nvgpu_err(g, "vf inject to change clk failed"); } /* save regime ids */ status = set_regime_id(g, CTRL_CLK_DOMAIN_XBAR2CLK, setfllclk->target_regime_id_xbar); - if (status) { + if (status != 0) { goto done; } status = set_regime_id(g, CTRL_CLK_DOMAIN_GPC2CLK, setfllclk->target_regime_id_gpc); - if (status) { + if (status != 0) { goto done; } status = set_regime_id(g, CTRL_CLK_DOMAIN_SYS2CLK, setfllclk->target_regime_id_sys); - if (status) { + if (status != 0) { goto done; } done: @@ -650,7 +650,7 @@ int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk) (struct clk_domain *)p3xslave, &clkmhz, setfllclk->gpc2clkmhz); - if (status) { + if (status != 0) { status = -EINVAL; goto done; } @@ -669,9 +669,9 @@ done: return status; } -u32 clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain) +int clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain) { - u32 status = -EINVAL; + int status = -EINVAL; struct clk_domain *pdomain; u8 i; struct clk_pmupstate *pclk = &g->clk_pmu; @@ -744,7 +744,7 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk) (struct clk_domain *)p3xslave, &clkmhz, fllclk->clkmhz); - if (status) { + if (status != 0) { status = -EINVAL; goto done; } @@ -762,7 +762,7 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk) /*set regime ids */ status = get_regime_id(g, CTRL_CLK_DOMAIN_GPCCLK, &setfllclk.current_regime_id_gpc); - if (status) { + if (status != 0) { goto done; } @@ -771,7 +771,7 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk) status = get_regime_id(g, CTRL_CLK_DOMAIN_SYSCLK, &setfllclk.current_regime_id_sys); - if (status) { + if (status != 0) { goto done; } @@ -780,7 +780,7 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk) status = get_regime_id(g, CTRL_CLK_DOMAIN_XBARCLK, &setfllclk.current_regime_id_xbar); - if (status) { + if (status != 0) { goto done; } @@ -789,7 +789,7 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk) status = clk_pmu_vf_inject(g, &setfllclk); - if (status) { + if (status != 0) { nvgpu_err(g, "vf inject to change clk failed"); } @@ -797,26 +797,26 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk) /* save regime ids */ status = set_regime_id(g, CTRL_CLK_DOMAIN_XBARCLK, setfllclk.target_regime_id_xbar); - if (status) { + if (status != 0) { goto done; } status = set_regime_id(g, CTRL_CLK_DOMAIN_GPCCLK, setfllclk.target_regime_id_gpc); - if (status) { + if (status != 0) { goto done; } status = set_regime_id(g, CTRL_CLK_DOMAIN_SYSCLK, setfllclk.target_regime_id_sys); - if (status) { + if (status != 0) { goto done; } done: return status; } -u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g) +int nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g) { int status; struct change_fll_clk bootfllclk; @@ -825,21 +825,21 @@ u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g) u32 voltuv = 0; status = clk_vf_point_cache(g); - if (status) { + if (status != 0) { nvgpu_err(g,"caching failed"); return status; } status = clk_domain_get_f_or_v(g, CTRL_CLK_DOMAIN_GPCCLK, &gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC); - if (status) { + if (status != 0) { return status; } voltuv = gpcclk_voltuv; status = volt_set_voltage(g, voltuv, 0); - if (status) { + if (status != 0) { nvgpu_err(g, "attempt to set boot voltage failed %d", voltuv); @@ -849,7 +849,7 @@ u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g) bootfllclk.clkmhz = gpcclk_clkmhz; bootfllclk.voltuv = voltuv; status = clk_program_fllclks(g, &bootfllclk); - if (status) { + if (status != 0) { nvgpu_err(g, "attempt to set boot gpcclk failed"); } @@ -858,10 +858,11 @@ u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g) /* * Read clocks after some delay with below method * & extract clock data from buffer - * clk_freq_effective_avg(g, CTRL_CLK_DOMAIN_GPCCLK | - * CTRL_CLK_DOMAIN_XBARCLK | - * CTRL_CLK_DOMAIN_SYSCLK | - * CTRL_CLK_DOMAIN_NVDCLK) + * u32 freqkHz; + * status = clk_freq_effective_avg(g, &freqkHz, CTRL_CLK_DOMAIN_GPCCLK | + * CTRL_CLK_DOMAIN_XBARCLK | + * CTRL_CLK_DOMAIN_SYSCLK | + * CTRL_CLK_DOMAIN_NVDCLK) * */ return status; @@ -904,7 +905,7 @@ int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g) return status; } -u32 clk_domain_get_f_or_v( +int clk_domain_get_f_or_v( struct gk20a *g, u32 clkapidomain, u16 *pclkmhz, @@ -912,7 +913,7 @@ u32 clk_domain_get_f_or_v( u8 railidx ) { - u32 status = -EINVAL; + int status = -EINVAL; struct clk_domain *pdomain; u8 i; struct clk_pmupstate *pclk = &g->clk_pmu; diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h index 0cffc2bd2..12f374f1e 100644 --- a/drivers/gpu/nvgpu/clk/clk.h +++ b/drivers/gpu/nvgpu/clk/clk.h @@ -119,9 +119,9 @@ struct vbios_clocks_table_1x_hal_clock_entry { #define BOOT_GPC2CLK_MHZ 2581U -u32 clk_pmu_vin_load(struct gk20a *g); -u32 clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain); -u32 clk_domain_get_f_or_v( +int clk_pmu_vin_load(struct gk20a *g); +int clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain); +int clk_domain_get_f_or_v( struct gk20a *g, u32 clkapidomain, u16 *pclkmhz, @@ -137,8 +137,8 @@ u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g, u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g, struct nv_pmu_clk_rpc *rpccall, struct set_fll_clk *setfllclk); -u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g); +int nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g); int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g); int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload); -u32 clk_freq_effective_avg(struct gk20a *g, u32 clkDomainMask); +int clk_freq_effective_avg(struct gk20a *g, u32 *freqkHz, u32 clkDomainMask); #endif /* NVGPU_CLK_H */ diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c index 26db4f95f..c444428f8 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.c +++ b/drivers/gpu/nvgpu/clk/clk_arb.c @@ -413,11 +413,11 @@ exit_vf_table: static void nvgpu_clk_arb_run_vf_table_cb(struct nvgpu_clk_arb *arb) { struct gk20a *g = arb->g; - u32 err; + int err; /* get latest vf curve from pmu */ err = clk_vf_point_cache(g); - if (err) { + if (err != 0) { nvgpu_err(g, "failed to cache VF table"); nvgpu_clk_arb_set_global_alarm(g, EVENT(ALARM_VF_TABLE_UPDATE_FAILED)); @@ -742,12 +742,12 @@ int nvgpu_clk_arb_worker_init(struct gk20a *g) nvgpu_init_list_node(&g->clk_arb_worker.items); nvgpu_spinlock_init(&g->clk_arb_worker.items_lock); err = nvgpu_mutex_init(&g->clk_arb_worker.start_lock); - if (err) + if (err != 0) goto error_check; err = __nvgpu_clk_arb_worker_start(g); error_check: - if (err) { + if (err != 0) { nvgpu_err(g, "failed to start clk arb poller thread"); return err; } @@ -962,7 +962,7 @@ int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, case NVGPU_CLK_DOMAIN_GPCCLK: ret = g->ops.clk_arb.get_arbiter_clk_range(g, CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz); - if (!ret) { + if (ret == 0) { *min_mhz /= 2; *max_mhz /= 2; } diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c index b29044235..6aa666577 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/clk/clk_domain.c @@ -132,7 +132,7 @@ static int _clk_domains_pmudatainit_3x(struct gk20a *g, int status = 0; status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); - if (status) { + if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for clk domain 0x%x", status); @@ -199,7 +199,7 @@ int clk_domain_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); status = boardobjgrpconstruct_e32(g, &g->clk_pmu.clk_domainobjs.super); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk domain, status - 0x%x", status); @@ -213,7 +213,7 @@ int clk_domain_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_domain, CLK_DOMAIN); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); @@ -239,7 +239,7 @@ int clk_domain_sw_setup(struct gk20a *g) sizeof(struct ctrl_clk_clk_delta)); status = devinit_get_clocks_table(g, pclkdomainobjs); - if (status) { + if (status != 0) { goto done; } @@ -250,7 +250,7 @@ int clk_domain_sw_setup(struct gk20a *g) CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG)) { status = boardobjgrpmask_bitset( &pclkdomainobjs->prog_domains_mask.super, i); - if (status) { + if (status != 0) { goto done; } } @@ -259,7 +259,7 @@ int clk_domain_sw_setup(struct gk20a *g) CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER)) { status = boardobjgrpmask_bitset( &pclkdomainobjs->master_domains_mask.super, i); - if (status) { + if (status != 0) { goto done; } } @@ -747,7 +747,7 @@ static int clkdomainvfsearch_stub( return -EINVAL; } -static u32 clkdomaingetfpoints_stub( +static int clkdomaingetfpoints_stub( struct gk20a *g, struct clk_pmupstate *pclk, struct clk_domain *pdomain, @@ -771,7 +771,7 @@ static int clk_domain_construct_super(struct gk20a *g, status = boardobj_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -834,7 +834,7 @@ static int clk_domain_construct_3x(struct gk20a *g, ptmpobj->type_mask = BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X); status = clk_domain_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -994,7 +994,7 @@ done: return status; } -static u32 clkdomaingetfpoints +static int clkdomaingetfpoints ( struct gk20a *g, struct clk_pmupstate *pclk, @@ -1004,7 +1004,7 @@ static u32 clkdomaingetfpoints u8 rail ) { - u32 status = 0; + int status = 0; struct clk_domain_3x_master *p3xmaster = (struct clk_domain_3x_master *)pdomain; struct clk_prog *pprog = NULL; @@ -1042,7 +1042,7 @@ static u32 clkdomaingetfpoints pprog1xmaster = (struct clk_prog_1x_master *)pprog; status = pprog1xmaster->getfpoints(g, pclk, pprog1xmaster, &fpointscount, &freqpointsdata, rail); - if (status) { + if (status != 0) { *pfpointscount = 0; goto done; } @@ -1202,7 +1202,7 @@ static int clk_domain_construct_3x_prog(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG); status = clk_domain_construct_3x(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -1366,7 +1366,7 @@ static int clkdomainclkproglink_3x_master(struct gk20a *g, nvgpu_log_info(g, " "); status = clkdomainclkproglink_3x_prog(g, pclk, pdomain); - if (status) { + if (status != 0) { goto done; } @@ -1386,7 +1386,7 @@ static int clkdomainclkproglink_3x_master(struct gk20a *g, pprog1xmaster = (struct clk_prog_1x_master *)pprog; status = pprog1xmaster->vfflatten(g, pclk, pprog1xmaster, BOARDOBJ_GET_IDX(p3xmaster), &freq_max_last_mhz); - if (status) { + if (status != 0) { goto done; } } @@ -1490,7 +1490,7 @@ static int clk_domain_construct_3x_master(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER); status = clk_domain_construct_3x_prog(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -1555,7 +1555,7 @@ static int clk_domain_construct_3x_fixed(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED); status = clk_domain_construct_3x(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -1575,7 +1575,7 @@ static int clk_domain_construct_3x_fixed(struct gk20a *g, static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs) { struct boardobj *board_obj_ptr = NULL; - u32 status; + int status; nvgpu_log_info(g, " %d", BOARDOBJ_GET_TYPE(pargs)); switch (BOARDOBJ_GET_TYPE(pargs)) { @@ -1609,7 +1609,7 @@ static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs) return NULL; } - if (status) { + if (status != 0) { return NULL; } @@ -1654,7 +1654,7 @@ int clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk) BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super), struct clk_domain *, pdomain, i) { status = pdomain->clkdomainclkproglink(g, pclk, pdomain); - if (status) { + if (status != 0) { nvgpu_err(g, "error flattening VF for CLK DOMAIN - 0x%x", pdomain->domain); diff --git a/drivers/gpu/nvgpu/clk/clk_domain.h b/drivers/gpu/nvgpu/clk/clk_domain.h index e4e79298a..4146133cb 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.h +++ b/drivers/gpu/nvgpu/clk/clk_domain.h @@ -52,7 +52,7 @@ typedef int clkgetslaveclk(struct gk20a *g, struct clk_pmupstate *pclk, struct clk_domain *pdomain, u16 *clkmhz, u16 masterclkmhz); -typedef u32 clkgetfpoints(struct gk20a *g, struct clk_pmupstate *pclk, +typedef int clkgetfpoints(struct gk20a *g, struct clk_pmupstate *pclk, struct clk_domain *pdomain, u32 *pfpointscount, u16 *pfreqpointsinmhz, u8 rail); diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index 58bfa88f4..384e854d9 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c @@ -54,7 +54,7 @@ static int _clk_fll_devgrp_pmudatainit_super(struct gk20a *g, nvgpu_log_info(g, " "); status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); - if (status) { + if (status != 0) { nvgpu_err(g, "failed to init fll pmuobjgrp"); return status; } @@ -129,7 +129,7 @@ int clk_fll_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); status = boardobjgrpconstruct_e32(g, &g->clk_pmu.avfs_fllobjs.super); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for fll, status - 0x%x", status); goto done; @@ -141,7 +141,7 @@ int clk_fll_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_fll_device, CLK_FLL_DEVICE); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); @@ -160,14 +160,14 @@ int clk_fll_sw_setup(struct gk20a *g) boardobjgrpmask_e32_init(&pfllobjs->lut_prog_master_mask, NULL); status = devinit_get_fll_device_table(g, pfllobjs); - if (status) { + if (status != 0) { goto done; } status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, &g->clk_pmu.avfs_fllobjs.super.super, clk, CLK, clk_fll_device, CLK_FLL_DEVICE); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); @@ -191,7 +191,7 @@ int clk_fll_sw_setup(struct gk20a *g) status = boardobjgrpmask_bitset( &pfllobjs->lut_prog_master_mask.super, BOARDOBJ_GET_IDX(pfll)); - if (status) { + if (status != 0) { nvgpu_err(g, "err setting lutprogmask"); goto done; } @@ -200,7 +200,7 @@ int clk_fll_sw_setup(struct gk20a *g) status = pfll_master->lut_broadcast_slave_register( g, pfllobjs, pfll_master, pfll); - if (status) { + if (status != 0) { nvgpu_err(g, "err setting lutslavemask"); goto done; } @@ -418,7 +418,7 @@ static struct fll_device *construct_fll_device(struct gk20a *g, nvgpu_log_info(g, " "); status = boardobj_construct_super(g, &board_obj_ptr, sizeof(struct fll_device), pargs); - if (status) { + if (status != 0) { return NULL; } diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c index 4dbcb8cbb..d841e8728 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c @@ -42,7 +42,7 @@ static int clk_freq_controller_pmudatainit_super(struct gk20a *g, int status = 0; status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); - if (status) { + if (status != 0) { return status; } @@ -75,7 +75,7 @@ static int clk_freq_controller_pmudatainit_pi(struct gk20a *g, status = clk_freq_controller_pmudatainit_super(g, board_obj_ptr, ppmudata); - if (status) { + if (status != 0) { return -1; } @@ -104,7 +104,7 @@ static int clk_freq_controller_construct_super(struct gk20a *g, int status = 0; status = boardobj_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -136,7 +136,7 @@ static int clk_freq_controller_construct_pi(struct gk20a *g, status = clk_freq_controller_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -170,7 +170,7 @@ static struct clk_freq_controller *clk_clk_freq_controller_construct( status = clk_freq_controller_construct_pi(g, &board_obj_ptr, sizeof(struct clk_freq_controller_pi), pargs); - if (status) { + if (status != 0) { return NULL; } @@ -312,7 +312,7 @@ static int clk_get_freq_controller_table(struct gk20a *g, status = boardobjgrp_objinsert( &pclk_freq_controllers->super.super, (struct boardobj *)pclk_freq_cntr, entry_idx); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to insert clock freq cntlr boardobj for"); status = -EINVAL; @@ -379,7 +379,7 @@ static int _clk_freq_controllers_pmudatainit(struct gk20a *g, int status = 0; status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); - if (status) { + if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for clk freq ctrs 0x%x", status); @@ -407,7 +407,7 @@ int clk_freq_controller_sw_setup(struct gk20a *g) pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers; status = boardobjgrpconstruct_e32(g, &pclk_freq_controllers->super); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk FCT, status - 0x%x", status); @@ -429,7 +429,7 @@ int clk_freq_controller_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_freq_controller, CLK_FREQ_CONTROLLER); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); @@ -437,7 +437,7 @@ int clk_freq_controller_sw_setup(struct gk20a *g) } status = clk_get_freq_controller_table(g, pclk_freq_controllers); - if (status) { + if (status != 0) { nvgpu_err(g, "error reading freq controller table - 0x%x", status); goto done; diff --git a/drivers/gpu/nvgpu/clk/clk_prog.c b/drivers/gpu/nvgpu/clk/clk_prog.c index c8bc10888..a70ae026b 100644 --- a/drivers/gpu/nvgpu/clk/clk_prog.c +++ b/drivers/gpu/nvgpu/clk/clk_prog.c @@ -50,10 +50,10 @@ static int _clk_progs_pmudatainit(struct gk20a *g, (struct nv_pmu_clk_clk_prog_boardobjgrp_set_header *) pboardobjgrppmu; struct clk_progs *pprogs = (struct clk_progs *)pboardobjgrp; - u32 status = 0; + int status = 0; status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); - if (status) { + if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for clk prog 0x%x", status); goto done; @@ -97,7 +97,7 @@ int clk_prog_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); status = boardobjgrpconstruct_e255(g, &g->clk_pmu.clk_progobjs.super); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk prog, status - 0x%x", status); @@ -111,7 +111,7 @@ int clk_prog_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_prog, CLK_PROG); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); @@ -122,13 +122,13 @@ int clk_prog_sw_setup(struct gk20a *g) pboardobjgrp->pmudatainstget = _clk_progs_pmudata_instget; status = devinit_get_clk_prog_table(g, pclkprogobjs); - if (status) { + if (status != 0) { nvgpu_err(g, "Error parsing the clk prog Vbios tables"); goto done; } status = clk_domain_clk_prog_link(g, &g->clk_pmu); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing VF point board objects"); goto done; } @@ -885,7 +885,7 @@ static int clk_prog_pmudatainit_35_master_table(struct gk20a *g, return status; } -static u32 _clk_prog_1x_master_rail_construct_vf_point(struct gk20a *g, +static int _clk_prog_1x_master_rail_construct_vf_point(struct gk20a *g, struct clk_pmupstate *pclk, struct clk_prog_1x_master *p1xmaster, struct ctrl_clk_clk_prog_1x_master_vf_entry *p_vf_rail, @@ -893,7 +893,7 @@ static u32 _clk_prog_1x_master_rail_construct_vf_point(struct gk20a *g, u8 *p_vf_point_idx) { struct clk_vf_point *p_vf_point; - u32 status; + int status; nvgpu_log_info(g, " "); @@ -906,7 +906,7 @@ static u32 _clk_prog_1x_master_rail_construct_vf_point(struct gk20a *g, &pclk->clk_vf_pointobjs.super.super, &p_vf_point->super, *p_vf_point_idx); - if (status) { + if (status != 0) { goto done; } @@ -926,7 +926,7 @@ static int clk_prog_construct_super(struct gk20a *g, status = boardobj_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -951,7 +951,7 @@ static int clk_prog_construct_1x(struct gk20a *g, nvgpu_log_info(g, " "); ptmpobj->type_mask |= (u32)BIT(CTRL_CLK_CLK_PROG_TYPE_1X); status = clk_prog_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -1013,7 +1013,7 @@ static int clk_prog_construct_1x_master(struct gk20a *g, ptmpobj->type_mask |= (u32)BIT(CTRL_CLK_CLK_PROG_TYPE_1X_MASTER); status = clk_prog_construct_1x(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -1113,7 +1113,7 @@ static int clk_prog_construct_1x_master_ratio(struct gk20a *g, ptmpobj->type_mask |= (u32)BIT(CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO); status = clk_prog_construct_1x_master(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -1203,7 +1203,7 @@ static int clk_prog_construct_1x_master_table(struct gk20a *g, ptmpobj->type_mask |= (u32)BIT(CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE); status = clk_prog_construct_1x_master(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -1228,7 +1228,7 @@ static int clk_prog_construct_1x_master_table(struct gk20a *g, (u8 *)ptmpprog->p_slave_entries, slavesize); exit: - if (status) { + if (status != 0) { (*ppboardobj)->destruct(*ppboardobj); } @@ -1329,7 +1329,7 @@ static struct clk_prog *construct_clk_prog(struct gk20a *g, void *pargs) return NULL; } - if (status) { + if (status != 0) { if (board_obj_ptr != NULL) { board_obj_ptr->destruct(board_obj_ptr); } @@ -1341,7 +1341,7 @@ static struct clk_prog *construct_clk_prog(struct gk20a *g, void *pargs) return (struct clk_prog *)board_obj_ptr; } -static u32 vfflatten_prog_1x_master(struct gk20a *g, +static int vfflatten_prog_1x_master(struct gk20a *g, struct clk_pmupstate *pclk, struct clk_prog_1x_master *p1xmaster, u8 clk_domain_idx, u16 *pfreqmaxlastmhz) @@ -1353,7 +1353,7 @@ static u32 vfflatten_prog_1x_master(struct gk20a *g, struct clk_vf_point_freq freq; struct clk_vf_point_volt volt; } vf_point_data; - u32 status = 0; + int status = 0; u8 step_count; u8 freq_step_size_mhz = 0; u8 vf_point_idx; @@ -1405,7 +1405,7 @@ static u32 vfflatten_prog_1x_master(struct gk20a *g, status = _clk_prog_1x_master_rail_construct_vf_point(g, pclk, p1xmaster, p_vf_rail, &vf_point_data.vf_point, &vf_point_idx); - if (status) { + if (status != 0) { goto done; } } while (step_count-- > 0U); @@ -1426,7 +1426,7 @@ static u32 vfflatten_prog_1x_master(struct gk20a *g, status = _clk_prog_1x_master_rail_construct_vf_point(g, pclk, p1xmaster, p_vf_rail, &vf_point_data.vf_point, &vf_point_idx); - if (status) { + if (status != 0) { goto done; } } @@ -1602,7 +1602,7 @@ static u32 vflookup_prog_1x_master return 0; } -static u32 getfpoints_prog_1x_master +static int getfpoints_prog_1x_master ( struct gk20a *g, struct clk_pmupstate *pclk, diff --git a/drivers/gpu/nvgpu/clk/clk_prog.h b/drivers/gpu/nvgpu/clk/clk_prog.h index 603d25486..3248e69d3 100644 --- a/drivers/gpu/nvgpu/clk/clk_prog.h +++ b/drivers/gpu/nvgpu/clk/clk_prog.h @@ -34,7 +34,7 @@ int clk_prog_sw_setup(struct gk20a *g); int clk_prog_pmu_setup(struct gk20a *g); struct clk_prog_1x_master; -typedef u32 vf_flatten(struct gk20a *g, struct clk_pmupstate *pclk, +typedef int vf_flatten(struct gk20a *g, struct clk_pmupstate *pclk, struct clk_prog_1x_master *p1xmaster, u8 clk_domain_idx, u16 *pfreqmaxlastmhz); @@ -48,7 +48,7 @@ typedef int get_slaveclk(struct gk20a *g, struct clk_pmupstate *pclk, u8 slave_clk_domain_idx, u16 *pclkmhz, u16 masterclkmhz); -typedef u32 get_fpoints(struct gk20a *g, struct clk_pmupstate *pclk, +typedef int get_fpoints(struct gk20a *g, struct clk_pmupstate *pclk, struct clk_prog_1x_master *p1xmaster, u32 *pfpointscount, u16 **ppfreqpointsinmhz, u8 rail); diff --git a/drivers/gpu/nvgpu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/clk/clk_vf_point.c index bb99095e6..f6bfb61d7 100644 --- a/drivers/gpu/nvgpu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/clk/clk_vf_point.c @@ -37,10 +37,10 @@ static int _clk_vf_points_pmudatainit(struct gk20a *g, struct boardobjgrp *pboardobjgrp, struct nv_pmu_boardobjgrp_super *pboardobjgrppmu) { - u32 status = 0; + int status = 0; status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); - if (status) { + if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for clk vfpoint 0x%x", status); @@ -100,7 +100,7 @@ int clk_vf_point_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); status = boardobjgrpconstruct_e255(g, &g->clk_pmu.clk_vf_pointobjs.super); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk vfpoint, status - 0x%x", status); @@ -113,7 +113,7 @@ int clk_vf_point_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_vf_point, CLK_VF_POINT); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); @@ -123,7 +123,7 @@ int clk_vf_point_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, &g->clk_pmu.clk_vf_pointobjs.super.super, clk, CLK, clk_vf_point, CLK_VF_POINT); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); @@ -169,7 +169,7 @@ static int clk_vf_point_construct_super(struct gk20a *g, status = boardobj_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -257,7 +257,7 @@ static int clk_vf_point_construct_volt(struct gk20a *g, ptmpobj->type_mask = BIT(CTRL_CLK_CLK_VF_POINT_TYPE_VOLT); status = clk_vf_point_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -288,7 +288,7 @@ static int clk_vf_point_construct_freq(struct gk20a *g, ptmpobj->type_mask = BIT(CTRL_CLK_CLK_VF_POINT_TYPE_FREQ); status = clk_vf_point_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -324,7 +324,7 @@ struct clk_vf_point *construct_clk_vf_point(struct gk20a *g, void *pargs) return NULL; } - if (status) { + if (status != 0) { return NULL; } @@ -407,7 +407,7 @@ int clk_vf_point_cache(struct gk20a *g) pboardobjgrpmask = &pclk_vf_points->super.mask.super; status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask); - if (status) { + if (status != 0) { nvgpu_err(g, "err getting boardobjs from pmu"); return status; } @@ -417,14 +417,14 @@ int clk_vf_point_cache(struct gk20a *g) status = pboardobjgrp->pmustatusinstget(g, (struct nv_pmu_boardobjgrp *)pboardobjgrppmu, &pboardobjpmustatus, index); - if (status) { + if (status != 0) { nvgpu_err(g, "could not get status object instance"); return status; } status = clk_vf_point_update(g, pboardobj, (struct nv_pmu_boardobj *)pboardobjpmustatus); - if (status) { + if (status != 0) { nvgpu_err(g, "invalid data from pmu at %d", index); return status; } diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c index 93b1de454..4648dddaa 100644 --- a/drivers/gpu/nvgpu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/clk/clk_vin.c @@ -58,11 +58,11 @@ static int vin_device_init_pmudata_super(struct gk20a *g, struct boardobj *board_obj_ptr, struct nv_pmu_boardobj *ppmudata); -u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g, +int clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g, struct avfsvinobjs *pvinobjs, struct vin_device_v20 *pvindev) { - u32 status = 0; + int status = 0; u32 slope, intercept; u8 i; @@ -74,7 +74,7 @@ u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g, pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i); status = g->ops.fuse.read_vin_cal_slope_intercept_fuse(g, pvindev->super.id, &slope, &intercept); - if (status) { + if (status != 0) { nvgpu_err(g, "err reading vin cal for id %x", pvindev->super.id); return status; @@ -87,11 +87,11 @@ u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g, } -u32 clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g, +int clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g, struct avfsvinobjs *pvinobjs, struct vin_device_v20 *pvindev) { - u32 status = 0; + int status = 0; s8 gain, offset; u8 i; @@ -103,7 +103,7 @@ u32 clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g, pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i); status = g->ops.fuse.read_vin_cal_gain_offset_fuse(g, pvindev->super.id, &gain, &offset); - if (status) { + if (status != 0) { nvgpu_err(g, "err reading vin cal for id %x", pvindev->super.id); return status; @@ -189,7 +189,7 @@ int clk_vin_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); status = boardobjgrpconstruct_e32(g, &g->clk_pmu.avfs_vinobjs.super); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk vin, statu - 0x%x", status); @@ -203,7 +203,7 @@ int clk_vin_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_vin_device, CLK_VIN_DEVICE); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); @@ -215,7 +215,7 @@ int clk_vin_sw_setup(struct gk20a *g) pboardobjgrp->pmustatusinstget = _clk_vin_devgrp_pmustatus_instget; status = devinit_get_vin_device_table(g, &g->clk_pmu.avfs_vinobjs); - if (status) { + if (status != 0) { goto done; } @@ -225,7 +225,7 @@ int clk_vin_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, &g->clk_pmu.avfs_vinobjs.super.super, clk, CLK, clk_vin_device, CLK_VIN_DEVICE); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); @@ -386,7 +386,7 @@ static int vin_device_construct_v10(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_CLK_VIN_TYPE_V10); status = vin_device_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -416,7 +416,7 @@ static int vin_device_construct_v20(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_CLK_VIN_TYPE_V20); status = vin_device_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -440,7 +440,7 @@ static int vin_device_construct_super(struct gk20a *g, int status = 0; status = boardobj_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -477,7 +477,7 @@ static struct vin_device *construct_vin_device(struct gk20a *g, void *pargs) return NULL; }; - if (status) { + if (status != 0) { return NULL; } diff --git a/drivers/gpu/nvgpu/clk/clk_vin.h b/drivers/gpu/nvgpu/clk/clk_vin.h index 833adf8fc..293d0086a 100644 --- a/drivers/gpu/nvgpu/clk/clk_vin.h +++ b/drivers/gpu/nvgpu/clk/clk_vin.h @@ -69,10 +69,10 @@ boardobj_pmudatainit vindeviceinit_pmudata_super; int clk_vin_sw_setup(struct gk20a *g); int clk_vin_pmu_setup(struct gk20a *g); -u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g, +int clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g, struct avfsvinobjs *pvinobjs, struct vin_device_v20 *pvindev); -u32 clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g, +int clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g, struct avfsvinobjs *pvinobjs, struct vin_device_v20 *pvindev); diff --git a/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c b/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c index 451d8b5dd..958bc9b28 100644 --- a/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c +++ b/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c @@ -77,7 +77,7 @@ int boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize, return 0; } -u32 boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize, +int boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize, struct ctrl_boardobjgrp_mask *extmask) { u8 index; @@ -113,7 +113,7 @@ int boardobjgrpmask_clr(struct boardobjgrpmask *mask) return 0; } -u32 boardobjgrpmask_set(struct boardobjgrpmask *mask) +int boardobjgrpmask_set(struct boardobjgrpmask *mask) { u8 index; @@ -127,7 +127,7 @@ u32 boardobjgrpmask_set(struct boardobjgrpmask *mask) return 0; } -u32 boardobjgrpmask_inv(struct boardobjgrpmask *mask) +int boardobjgrpmask_inv(struct boardobjgrpmask *mask) { u8 index; @@ -261,7 +261,7 @@ int boardobjgrpmask_bitset(struct boardobjgrpmask *mask, u8 bitidx) return 0; } -u32 boardobjgrpmask_bitinv(struct boardobjgrpmask *mask, u8 bitidx) +int boardobjgrpmask_bitinv(struct boardobjgrpmask *mask, u8 bitidx) { u8 index; u8 offset; @@ -299,7 +299,7 @@ bool boardobjgrpmask_bitget(struct boardobjgrpmask *mask, u8 bitidx) return (mask->data[index] & BIT(offset)) != 0U; } -u32 boardobjgrpmask_and(struct boardobjgrpmask *dst, +int boardobjgrpmask_and(struct boardobjgrpmask *dst, struct boardobjgrpmask *op1, struct boardobjgrpmask *op2) { @@ -319,7 +319,7 @@ u32 boardobjgrpmask_and(struct boardobjgrpmask *dst, return 0; } -u32 boardobjgrpmask_or(struct boardobjgrpmask *dst, +int boardobjgrpmask_or(struct boardobjgrpmask *dst, struct boardobjgrpmask *op1, struct boardobjgrpmask *op2) { @@ -339,7 +339,7 @@ u32 boardobjgrpmask_or(struct boardobjgrpmask *dst, return 0; } -u32 boardobjgrpmask_xor(struct boardobjgrpmask *dst, +int boardobjgrpmask_xor(struct boardobjgrpmask *dst, struct boardobjgrpmask *op1, struct boardobjgrpmask *op2) { @@ -359,7 +359,7 @@ u32 boardobjgrpmask_xor(struct boardobjgrpmask *dst, return 0; } -u32 boardobjgrpmask_copy(struct boardobjgrpmask *dst, +int boardobjgrpmask_copy(struct boardobjgrpmask *dst, struct boardobjgrpmask *src) { u8 index; diff --git a/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c b/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c index 24ac89050..d1a757916 100644 --- a/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c +++ b/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c @@ -187,7 +187,7 @@ static int channel_sync_semaphore_incr_common( incr_cmd_size = c->g->ops.fifo.get_sema_incr_cmd_size(); err = gk20a_channel_alloc_priv_cmdbuf(c, incr_cmd_size, incr_cmd); - if (err) { + if (err != 0) { nvgpu_err(c->g, "not enough priv cmd buffer space"); goto clean_up_sema; @@ -200,7 +200,7 @@ static int channel_sync_semaphore_incr_common( err = nvgpu_os_fence_sema_create(&os_fence, c, semaphore); - if (err) { + if (err != 0) { goto clean_up_sema; } } diff --git a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h index 52819e544..879dd42b6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h +++ b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h @@ -72,13 +72,13 @@ int boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize, struct ctrl_boardobjgrp_mask *extmask); int boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize, struct ctrl_boardobjgrp_mask *extmask); -u32 boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize, +int boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize, struct ctrl_boardobjgrp_mask *extmask); /* Operations on all bits of a single mask.*/ int boardobjgrpmask_clr(struct boardobjgrpmask *mask); -u32 boardobjgrpmask_set(struct boardobjgrpmask *mask); -u32 boardobjgrpmask_inv(struct boardobjgrpmask *mask); +int boardobjgrpmask_set(struct boardobjgrpmask *mask); +int boardobjgrpmask_inv(struct boardobjgrpmask *mask); bool boardobjgrpmask_iszero(struct boardobjgrpmask *mask); u8 boardobjgrpmask_bitsetcount(struct boardobjgrpmask *mask); u8 boardobjgrpmask_bitidxlowest(struct boardobjgrpmask *mask); @@ -87,21 +87,21 @@ u8 boardobjgrpmask_bitidxhighest(struct boardobjgrpmask *mask); /* Operations on a single bit of a single mask */ int boardobjgrpmask_bitclr(struct boardobjgrpmask *mask, u8 bitidx); int boardobjgrpmask_bitset(struct boardobjgrpmask *mask, u8 bitidx); -u32 boardobjgrpmask_bitinv(struct boardobjgrpmask *mask, u8 bitidx); +int boardobjgrpmask_bitinv(struct boardobjgrpmask *mask, u8 bitidx); bool boardobjgrpmask_bitget(struct boardobjgrpmask *mask, u8 bitidx); /* Operations on a multiple masks */ -u32 boardobjgrpmask_and(struct boardobjgrpmask *dst, +int boardobjgrpmask_and(struct boardobjgrpmask *dst, struct boardobjgrpmask *op1, struct boardobjgrpmask *op2); -u32 boardobjgrpmask_or(struct boardobjgrpmask *dst, struct boardobjgrpmask *op1, +int boardobjgrpmask_or(struct boardobjgrpmask *dst, struct boardobjgrpmask *op1, struct boardobjgrpmask *op2); -u32 boardobjgrpmask_xor(struct boardobjgrpmask *dst, +int boardobjgrpmask_xor(struct boardobjgrpmask *dst, struct boardobjgrpmask *op1, struct boardobjgrpmask *op2); /* Special interfaces */ -u32 boardobjgrpmask_copy(struct boardobjgrpmask *dst, +int boardobjgrpmask_copy(struct boardobjgrpmask *dst, struct boardobjgrpmask *src); bool boardobjgrpmask_sizeeq(struct boardobjgrpmask *op1, struct boardobjgrpmask *op2); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index fbc069f8f..58aae7595 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -898,13 +898,13 @@ struct gpu_ops { } volt; struct { u32 (*get_vbios_clk_domain)(u32 vbios_domain); - u32 (*clk_avfs_get_vin_cal_data)(struct gk20a *g, + int (*clk_avfs_get_vin_cal_data)(struct gk20a *g, struct avfsvinobjs *pvinobjs, struct vin_device_v20 *pvindev); u32 (*clk_vf_change_inject_data_fill)(struct gk20a *g, struct nv_pmu_clk_rpc *rpccall, struct set_fll_clk *setfllclk); - u32 (*clk_set_boot_clk)(struct gk20a *g); + int (*clk_set_boot_clk)(struct gk20a *g); }clk; } pmu_ver; struct { @@ -1130,7 +1130,7 @@ struct gpu_ops { bool support_clk_freq_controller; bool support_pmgr_domain; bool support_lpwr_pg; - u32 (*perf_pmu_vfe_load)(struct gk20a *g); + int (*perf_pmu_vfe_load)(struct gk20a *g); u32 lut_num_entries; } clk; struct { diff --git a/drivers/gpu/nvgpu/pmgr/pmgr.c b/drivers/gpu/nvgpu/pmgr/pmgr.c index f5be01bf3..8d7e4485c 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgr.c +++ b/drivers/gpu/nvgpu/pmgr/pmgr.c @@ -31,7 +31,7 @@ int pmgr_pwr_devices_get_power(struct gk20a *g, u32 *val) int status; status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_pwr_devices_get_current_power failed %x", status); } @@ -47,7 +47,7 @@ int pmgr_pwr_devices_get_current(struct gk20a *g, u32 *val) int status; status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_pwr_devices_get_current failed %x", status); } @@ -63,7 +63,7 @@ int pmgr_pwr_devices_get_voltage(struct gk20a *g, u32 *val) int status; status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_pwr_devices_get_current_voltage failed %x", status); } @@ -73,12 +73,12 @@ int pmgr_pwr_devices_get_voltage(struct gk20a *g, u32 *val) return status; } -u32 pmgr_domain_sw_setup(struct gk20a *g) +int pmgr_domain_sw_setup(struct gk20a *g) { - u32 status; + int status; status = pmgr_device_sw_setup(g); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for pmgr devices, status - 0x%x", status); @@ -86,7 +86,7 @@ u32 pmgr_domain_sw_setup(struct gk20a *g) } status = pmgr_monitor_sw_setup(g); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for pmgr monitor, status - 0x%x", status); @@ -94,7 +94,7 @@ u32 pmgr_domain_sw_setup(struct gk20a *g) } status = pmgr_policy_sw_setup(g); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for pmgr policy, status - 0x%x", status); diff --git a/drivers/gpu/nvgpu/pmgr/pmgr.h b/drivers/gpu/nvgpu/pmgr/pmgr.h index 9b142de00..fddfb574a 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgr.h +++ b/drivers/gpu/nvgpu/pmgr/pmgr.h @@ -34,7 +34,7 @@ struct pmgr_pmupstate { struct pmgr_pwr_policy pmgr_policyobjs; }; -u32 pmgr_domain_sw_setup(struct gk20a *g); +int pmgr_domain_sw_setup(struct gk20a *g); int pmgr_domain_pmu_setup(struct gk20a *g); int pmgr_pwr_devices_get_current(struct gk20a *g, u32 *val); int pmgr_pwr_devices_get_voltage(struct gk20a *g, u32 *val); diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c index f5e6cdf17..5ee5683e9 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c +++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c @@ -83,7 +83,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, phandlerparams->success = 1; } -static u32 pmgr_pmu_set_object(struct gk20a *g, +static int pmgr_pmu_set_object(struct gk20a *g, u8 type, u16 dmem_size, u16 fb_size, @@ -92,7 +92,7 @@ static u32 pmgr_pmu_set_object(struct gk20a *g, struct pmu_cmd cmd; struct pmu_payload payload; struct nv_pmu_pmgr_cmd_set_object *pcmd; - u32 status; + int status; u32 seqdesc; struct pmgr_pmucmdhandler_params handlerparams; @@ -122,7 +122,7 @@ static u32 pmgr_pmu_set_object(struct gk20a *g, pmgr_pmucmdhandler, (void *)&handlerparams, &seqdesc, ~0); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to post pmgr cmd for unit %x cmd id %x obj type %x", cmd.hdr.unit_id, pcmd->cmd_type, pcmd->object_type); @@ -143,11 +143,11 @@ exit: return status; } -static u32 pmgr_send_i2c_device_topology_to_pmu(struct gk20a *g) +static int pmgr_send_i2c_device_topology_to_pmu(struct gk20a *g) { struct nv_pmu_pmgr_i2c_device_desc_table i2c_desc_table; u32 idx = g->ina3221_dcb_index; - u32 status = 0; + int status = 0; /* INA3221 I2C device info */ i2c_desc_table.dev_mask = (1UL << idx); @@ -168,7 +168,7 @@ static u32 pmgr_send_i2c_device_topology_to_pmu(struct gk20a *g) PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED, &i2c_desc_table); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_pmu_set_object failed %x", status); } @@ -199,7 +199,7 @@ static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g) &g->pmgr_pmu.pmgr_deviceobjs.super.super, (struct nv_pmu_boardobjgrp_super *)pwr_desc_table); - if (status) { + if (status != 0) { nvgpu_err(g, "boardobjgrp_pmudatainit_legacy failed %x", status); goto exit; @@ -214,7 +214,7 @@ static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g) (u16)sizeof(struct nv_pmu_pmgr_pwr_device_desc_table), pwr_desc_table); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_pmu_set_object failed %x", status); } @@ -249,7 +249,7 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g) &g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super, (struct nv_pmu_boardobjgrp_super *)&(pwr_monitor_pack->channels)); - if (status) { + if (status != 0) { nvgpu_err(g, "boardobjgrp_pmudatainit_legacy failed %x", status); goto exit; @@ -268,7 +268,7 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g) &g->pmgr_pmu.pmgr_monitorobjs.pwr_ch_rels.super, (struct nv_pmu_boardobjgrp_super *)&(pwr_monitor_pack->ch_rels)); - if (status) { + if (status != 0) { nvgpu_err(g, "boardobjgrp_pmudatainit_legacy failed %x", status); goto exit; @@ -285,7 +285,7 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g) (u16)sizeof(struct nv_pmu_pmgr_pwr_monitor_pack), pwr_monitor_pack); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_pmu_set_object failed %x", status); } @@ -343,7 +343,7 @@ static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g) status = ((struct boardobj *)ppolicy)->pmudatainit(g, (struct boardobj *)ppolicy, (struct nv_pmu_boardobj *)&(ppwrpack->policies.policies[indx].data)); - if (status) { + if (status != 0) { nvgpu_err(g, "pmudatainit failed %x indx %x", status, indx); status = -ENOMEM; @@ -370,7 +370,7 @@ static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g) (u16)sizeof(struct nv_pmu_pmgr_pwr_policy_pack), ppwrpack); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_pmu_set_object failed %x", status); } @@ -383,7 +383,7 @@ exit: return status; } -u32 pmgr_pmu_pwr_devices_query_blocking( +int pmgr_pmu_pwr_devices_query_blocking( struct gk20a *g, u32 pwr_dev_mask, struct nv_pmu_pmgr_pwr_devices_query_payload *ppayload) @@ -391,7 +391,7 @@ u32 pmgr_pmu_pwr_devices_query_blocking( struct pmu_cmd cmd; struct pmu_payload payload; struct nv_pmu_pmgr_cmd_pwr_devices_query *pcmd; - u32 status; + int status; u32 seqdesc; struct pmgr_pmucmdhandler_params handlerparams; @@ -421,7 +421,7 @@ u32 pmgr_pmu_pwr_devices_query_blocking( pmgr_pmucmdhandler, (void *)&handlerparams, &seqdesc, ~0); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to post pmgr query cmd for unit %x cmd id %x dev mask %x", cmd.hdr.unit_id, pcmd->cmd_type, pcmd->dev_mask); @@ -442,11 +442,11 @@ exit: return status; } -static u32 pmgr_pmu_load_blocking(struct gk20a *g) +static int pmgr_pmu_load_blocking(struct gk20a *g) { struct pmu_cmd cmd = { {0} }; struct nv_pmu_pmgr_cmd_load *pcmd; - u32 status; + int status; u32 seqdesc; struct pmgr_pmucmdhandler_params handlerparams = {0}; @@ -465,7 +465,7 @@ static u32 pmgr_pmu_load_blocking(struct gk20a *g) pmgr_pmucmdhandler, (void *)&handlerparams, &seqdesc, ~0); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to post pmgr load cmd for unit %x cmd id %x", cmd.hdr.unit_id, pcmd->cmd_type); @@ -492,7 +492,7 @@ int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g) status = pmgr_send_i2c_device_topology_to_pmu(g); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_send_i2c_device_topology_to_pmu failed %x", status); @@ -501,7 +501,7 @@ int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g) if (!BOARDOBJGRP_IS_EMPTY(&g->pmgr_pmu.pmgr_deviceobjs.super.super)) { status = pmgr_send_pwr_device_topology_to_pmu(g); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_send_pwr_device_topology_to_pmu failed %x", status); @@ -514,7 +514,7 @@ int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g) !(BOARDOBJGRP_IS_EMPTY( &g->pmgr_pmu.pmgr_monitorobjs.pwr_ch_rels.super))) { status = pmgr_send_pwr_mointer_to_pmu(g); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_send_pwr_mointer_to_pmu failed %x", status); goto exit; @@ -528,7 +528,7 @@ int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g) !(BOARDOBJGRP_IS_EMPTY( &g->pmgr_pmu.pmgr_policyobjs.pwr_violations.super))) { status = pmgr_send_pwr_policy_to_pmu(g); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_send_pwr_policy_to_pmu failed %x", status); goto exit; @@ -536,7 +536,7 @@ int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g) } status = pmgr_pmu_load_blocking(g); - if (status) { + if (status != 0) { nvgpu_err(g, "pmgr_send_pwr_mointer_to_pmu failed %x", status); goto exit; diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.h b/drivers/gpu/nvgpu/pmgr/pmgrpmu.h index f4ffaef38..5c1618bd4 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.h +++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.h @@ -31,7 +31,7 @@ int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g); -u32 pmgr_pmu_pwr_devices_query_blocking( +int pmgr_pmu_pwr_devices_query_blocking( struct gk20a *g, u32 pwr_dev_mask, struct nv_pmu_pmgr_pwr_devices_query_payload *ppayload); diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c index 7e0d179c3..cd0ed7fd0 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrdev.c +++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c @@ -63,7 +63,7 @@ static int _pwr_domains_pmudatainit_ina3221(struct gk20a *g, u32 indx; status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); - if (status) { + if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for pwr domain 0x%x", status); @@ -101,7 +101,7 @@ static struct boardobj *construct_pwr_device(struct gk20a *g, status = boardobj_construct_super(g, &board_obj_ptr, pargs_size, pargs); - if (status) { + if (status != 0) { return NULL; } @@ -273,7 +273,7 @@ static int devinit_get_pwr_device_table(struct gk20a *g, status = boardobjgrp_objinsert(&ppwrdeviceobjs->super.super, boardobj, obj_index); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to insert pwr device boardobj for %d", index); status = -EINVAL; @@ -296,7 +296,7 @@ int pmgr_device_sw_setup(struct gk20a *g) /* Construct the Super Class and override the Interfaces */ status = boardobjgrpconstruct_e32(g, &g->pmgr_pmu.pmgr_deviceobjs.super); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for pmgr devices, status - 0x%x", status); @@ -310,7 +310,7 @@ int pmgr_device_sw_setup(struct gk20a *g) pboardobjgrp->pmudatainstget = _pwr_device_pmudata_instget; status = devinit_get_pwr_device_table(g, ppwrdeviceobjs); - if (status) { + if (status != 0) { goto done; } diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c index 1a744ad1b..4a1354611 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c +++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c @@ -117,7 +117,7 @@ static int _pwr_domains_pmudatainit_sensor(struct gk20a *g, int status = 0; status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); - if (status) { + if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for pwr sensor 0x%x", status); @@ -153,7 +153,7 @@ static struct boardobj *construct_pwr_topology(struct gk20a *g, status = boardobj_construct_super(g, &board_obj_ptr, pargs_size, pargs); - if (status) { + if (status != 0) { return NULL; } @@ -286,7 +286,7 @@ static int devinit_get_pwr_topology_table(struct gk20a *g, status = boardobjgrp_objinsert(&ppwrmonitorobjs->pwr_channels.super, boardobj, obj_index); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to insert pwr topology boardobj for %d", index); status = -EINVAL; @@ -312,7 +312,7 @@ int pmgr_monitor_sw_setup(struct gk20a *g) /* Construct the Super Class and override the Interfaces */ status = boardobjgrpconstruct_e32(g, &g->pmgr_pmu.pmgr_monitorobjs.pwr_channels); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for pmgr channel, status - 0x%x", status); @@ -327,7 +327,7 @@ int pmgr_monitor_sw_setup(struct gk20a *g) /* Construct the Super Class and override the Interfaces */ status = boardobjgrpconstruct_e32(g, &g->pmgr_pmu.pmgr_monitorobjs.pwr_ch_rels); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for pmgr channel relationship, status - 0x%x", status); @@ -350,12 +350,12 @@ int pmgr_monitor_sw_setup(struct gk20a *g) ppwrmonitorobjs = &(g->pmgr_pmu.pmgr_monitorobjs); status = devinit_get_pwr_topology_table(g, ppwrmonitorobjs); - if (status) { + if (status != 0) { goto done; } status = _pwr_channel_state_init(g); - if (status) { + if (status != 0) { goto done; } diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c index 407800d97..aea705b8f 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c +++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c @@ -32,14 +32,14 @@ #define _pwr_policy_limitarboutputget_helper(p_limit_arb) (p_limit_arb)->output #define _pwr_policy_limitdeltaapply(limit, delta) ((u32)max(((s32)limit) + (delta), 0)) -static u32 _pwr_policy_limitarbinputset_helper(struct gk20a *g, +static int _pwr_policy_limitarbinputset_helper(struct gk20a *g, struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb, u8 client_idx, u32 limit_value) { u8 indx; bool b_found = false; - u32 status = 0; + int status = 0; u32 output = limit_value; for (indx = 0; indx< p_limit_arb->num_inputs; indx++) { @@ -68,20 +68,20 @@ static u32 _pwr_policy_limitarbinputset_helper(struct gk20a *g, } } - if (!status) { + if (status == 0) { p_limit_arb->output = output; } return status; } -static u32 _pwr_policy_limitid_translate(struct gk20a *g, +static int _pwr_policy_limitid_translate(struct gk20a *g, struct pwr_policy *ppolicy, enum pwr_policy_limit_id limit_id, struct ctrl_pmgr_pwr_policy_limit_arbitration **p_limit_arb, struct ctrl_pmgr_pwr_policy_limit_arbitration **p_limit_arb_sec) { - u32 status = 0; + int status = 0; switch (limit_id) { case PWR_POLICY_LIMIT_ID_MIN: @@ -118,13 +118,13 @@ static u32 _pwr_policy_limitid_translate(struct gk20a *g, return status; } -static u32 _pwr_policy_limitarbinputset(struct gk20a *g, +static int _pwr_policy_limitarbinputset(struct gk20a *g, struct pwr_policy *ppolicy, enum pwr_policy_limit_id limit_id, u8 client_idx, u32 limit) { - u32 status = 0; + int status = 0; struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb = NULL; struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb_sec = NULL; @@ -133,12 +133,12 @@ static u32 _pwr_policy_limitarbinputset(struct gk20a *g, limit_id, &p_limit_arb, &p_limit_arb_sec); - if (status) { + if (status != 0) { goto exit; } status = _pwr_policy_limitarbinputset_helper(g, p_limit_arb, client_idx, limit); - if (status) { + if (status != 0) { nvgpu_err(g, "Error setting client limit value: status=0x%08x, limitId=0x%x, clientIdx=0x%x, limit=%d", status, limit_id, client_idx, limit); @@ -167,7 +167,7 @@ static u32 _pwr_policy_limitarboutputget(struct gk20a *g, struct pwr_policy *ppolicy, enum pwr_policy_limit_id limit_id) { - u32 status = 0; + int status = 0; struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb = NULL; status = _pwr_policy_limitid_translate(g, @@ -175,7 +175,7 @@ static u32 _pwr_policy_limitarboutputget(struct gk20a *g, limit_id, &p_limit_arb, NULL); - if (status) { + if (status != 0) { return 0; } @@ -193,7 +193,7 @@ static int _pwr_domains_pmudatainit_hw_threshold(struct gk20a *g, int status = 0; status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); - if (status) { + if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for pwr sensor 0x%x", status); @@ -264,7 +264,7 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g, status = boardobj_construct_super(g, &board_obj_ptr, pargs_size, pargs); - if (status) { + if (status != 0) { return NULL; } @@ -403,7 +403,7 @@ static int _pwr_policy_construct_WAR_SW_Threshold_policy(struct gk20a *g, status = boardobjgrp_objinsert(&ppwrpolicyobjs->pwr_policies.super, boardobj, obj_index); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to insert pwr policy boardobj for %d", obj_index); status = -EINVAL; @@ -680,7 +680,7 @@ static int devinit_get_pwr_policy_table(struct gk20a *g, status = boardobjgrp_objinsert(&ppwrpolicyobjs->pwr_policies.super, boardobj, obj_index); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to insert pwr policy boardobj for %d", index); @@ -697,7 +697,7 @@ static int devinit_get_pwr_policy_table(struct gk20a *g, &pwr_policy_data, sizeof(struct pwr_policy_sw_threshold), obj_index); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to construct_WAR_policy"); status = -EINVAL; goto done; @@ -721,7 +721,7 @@ int pmgr_policy_sw_setup(struct gk20a *g) /* Construct the Super Class and override the Interfaces */ status = boardobjgrpconstruct_e32(g, &g->pmgr_pmu.pmgr_policyobjs.pwr_policies); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for pmgr policy, status - 0x%x", status); @@ -730,7 +730,7 @@ int pmgr_policy_sw_setup(struct gk20a *g) status = boardobjgrpconstruct_e32(g, &g->pmgr_pmu.pmgr_policyobjs.pwr_policy_rels); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for pmgr policy rels, status - 0x%x", status); @@ -739,7 +739,7 @@ int pmgr_policy_sw_setup(struct gk20a *g) status = boardobjgrpconstruct_e32(g, &g->pmgr_pmu.pmgr_policyobjs.pwr_violations); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for pmgr violations, status - 0x%x", status); @@ -763,7 +763,7 @@ int pmgr_policy_sw_setup(struct gk20a *g) pboardobjgrp = &(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super); status = devinit_get_pwr_policy_table(g, ppwrpolicyobjs); - if (status) { + if (status != 0) { goto done; } diff --git a/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c b/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c index 111a2bb46..45f7ab6b4 100644 --- a/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c +++ b/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c @@ -99,15 +99,15 @@ u32 perf_pmu_init_vfe_perf_event(struct gk20a *g) } -u32 gv100_perf_pmu_vfe_load(struct gk20a *g) +int gv100_perf_pmu_vfe_load(struct gk20a *g) { struct nvgpu_pmu *pmu = &g->pmu; struct nv_pmu_rpc_struct_perf_load rpc; - u32 status = 0; + int status = 0; (void) memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perf_load)); PMU_RPC_EXECUTE_CPB(status, pmu, PERF, VFE_INVALIDATE, &rpc, 0); - if (status != 0U) { + if (status != 0) { nvgpu_err(g, "Failed to execute RPC status=0x%x", status); } diff --git a/drivers/gpu/nvgpu/pmu_perf/perf_gv100.h b/drivers/gpu/nvgpu/pmu_perf/perf_gv100.h index d76020967..e3d83d9fe 100644 --- a/drivers/gpu/nvgpu/pmu_perf/perf_gv100.h +++ b/drivers/gpu/nvgpu/pmu_perf/perf_gv100.h @@ -30,7 +30,7 @@ struct gk20a; u32 perf_pmu_init_vfe_perf_event(struct gk20a *g); -u32 gv100_perf_pmu_vfe_load(struct gk20a *g); +int gv100_perf_pmu_vfe_load(struct gk20a *g); #endif /* NVGPU_PERF_GV100_H */ diff --git a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.c b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.c index 3c22759b4..642dab5db 100644 --- a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.c +++ b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.c @@ -67,11 +67,11 @@ static int pmu_handle_perf_event(struct gk20a *g, void *pmu_msg) return 0; } -u32 perf_pmu_vfe_load(struct gk20a *g) +int perf_pmu_vfe_load(struct gk20a *g) { struct pmu_cmd cmd; struct pmu_payload payload; - u32 status; + int status; u32 seqdesc; struct nv_pmu_perf_rpc rpccall; struct perfrpc_pmucmdhandler_params handler; @@ -110,7 +110,7 @@ u32 perf_pmu_vfe_load(struct gk20a *g) perfrpc_pmucmdhandler, (void *)&handler, &seqdesc, ~0); - if (status) { + if (status != 0) { nvgpu_err(g, "unable to post perf RPC cmd %x", cmd.cmd.perf.cmd_type); goto done; diff --git a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h index 365593294..c4ee43d7a 100644 --- a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h +++ b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h @@ -79,6 +79,6 @@ struct perf_pmupstate { struct nvgpu_vfe_invalidate vfe_init; }; -u32 perf_pmu_vfe_load(struct gk20a *g); +int perf_pmu_vfe_load(struct gk20a *g); #endif /* NVGPU_PERF_H */ diff --git a/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c b/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c index 219b22103..65776c0f9 100644 --- a/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c +++ b/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c @@ -42,7 +42,7 @@ static int _vfe_equs_pmudatainit(struct gk20a *g, int status = 0; status = boardobjgrp_pmudatainit_e255(g, pboardobjgrp, pboardobjgrppmu); - if (status) { + if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for vfe equ 0x%x", status); goto done; @@ -82,7 +82,7 @@ int vfe_equ_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); status = boardobjgrpconstruct_e255(g, &g->perf_pmu.vfe_equobjs.super); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk domain, status - 0x%x", status); @@ -96,7 +96,7 @@ int vfe_equ_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, perf, PERF, vfe_equ, VFE_EQU); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); @@ -107,7 +107,7 @@ int vfe_equ_sw_setup(struct gk20a *g) pboardobjgrp->pmudatainstget = _vfe_equs_pmudata_instget; status = devinit_get_vfe_equ_table(g, pvfeequobjs); - if (status) { + if (status != 0) { goto done; } @@ -323,7 +323,7 @@ static int devinit_get_vfe_equ_table(struct gk20a *g, status = boardobjgrp_objinsert(&pvfeequobjs->super.super, (struct boardobj *)pequ, index); - if (status) { + if (status != 0) { nvgpu_err(g, "error adding vfe_equ boardobj %d", index); status = -EINVAL; goto done; @@ -338,14 +338,14 @@ static int _vfe_equ_pmudatainit_super(struct gk20a *g, struct boardobj *board_obj_ptr, struct nv_pmu_boardobj *ppmudata) { - u32 status = 0; + int status = 0; struct vfe_equ *pvfe_equ; struct nv_pmu_vfe_equ *pset; nvgpu_log_info(g, " "); status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); - if (status != 0U) { + if (status != 0) { return status; } @@ -373,7 +373,7 @@ static int vfe_equ_construct_super(struct gk20a *g, status = boardobj_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -435,7 +435,7 @@ static int vfe_equ_construct_compare(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_COMPARE); status = vfe_equ_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -496,7 +496,7 @@ static int vfe_equ_construct_minmax(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_MINMAX); status = vfe_equ_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -555,7 +555,7 @@ static int vfe_equ_construct_quadratic(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_QUADRATIC); status = vfe_equ_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -599,7 +599,7 @@ static struct vfe_equ *construct_vfe_equ(struct gk20a *g, void *pargs) } - if (status) { + if (status != 0) { return NULL; } diff --git a/drivers/gpu/nvgpu/pmu_perf/vfe_var.c b/drivers/gpu/nvgpu/pmu_perf/vfe_var.c index b5fcba4a3..19868a5c1 100644 --- a/drivers/gpu/nvgpu/pmu_perf/vfe_var.c +++ b/drivers/gpu/nvgpu/pmu_perf/vfe_var.c @@ -49,7 +49,7 @@ static int _vfe_vars_pmudatainit(struct gk20a *g, int status = 0; status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); - if (status) { + if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for vfe var 0x%x", status); @@ -104,14 +104,14 @@ static int _vfe_vars_pmustatus_instget(struct gk20a *g, void *pboardobjgrppmu, int vfe_var_sw_setup(struct gk20a *g) { - u32 status; + int status; struct boardobjgrp *pboardobjgrp = NULL; struct vfe_vars *pvfevarobjs; nvgpu_log_info(g, " "); status = boardobjgrpconstruct_e32(g, &g->perf_pmu.vfe_varobjs.super); - if (status) { + if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk domain, status - 0x%x", status); @@ -125,7 +125,7 @@ int vfe_var_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, perf, PERF, vfe_var, VFE_VAR); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); @@ -137,14 +137,14 @@ int vfe_var_sw_setup(struct gk20a *g) pboardobjgrp->pmustatusinstget = _vfe_vars_pmustatus_instget; status = devinit_get_vfe_var_table(g, pvfevarobjs); - if (status) { + if (status != 0) { goto done; } status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, &g->perf_pmu.vfe_varobjs.super.super, perf, PERF, vfe_var, VFE_VAR); - if (status) { + if (status != 0) { nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_GET_STATUS interface - 0x%x", status); @@ -339,7 +339,7 @@ static int vfe_var_construct_super(struct gk20a *g, nvgpu_log_info(g, " "); status = boardobj_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -381,7 +381,7 @@ static int vfe_var_construct_derived(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED); status = vfe_var_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -434,7 +434,7 @@ static int vfe_var_construct_derived_product(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT); status = vfe_var_construct_derived(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -490,7 +490,7 @@ static int vfe_var_construct_derived_sum(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM); status = vfe_var_construct_derived(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -543,13 +543,13 @@ static int _vfe_var_pmudatainit_single_frequency(struct gk20a *g, return status; } -static u32 vfe_var_construct_single_frequency(struct gk20a *g, +static int vfe_var_construct_single_frequency(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { struct boardobj *ptmpobj = (struct boardobj *)pargs; struct vfe_var_single_frequency *pvfevar; - u32 status = 0; + int status = 0; nvgpu_log_info(g, " "); @@ -559,7 +559,7 @@ static u32 vfe_var_construct_single_frequency(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY); status = vfe_var_construct_single(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -625,20 +625,20 @@ static int _vfe_var_pmudatainit_single_sensed_fuse(struct gk20a *g, return status; } -static u32 vfe_var_construct_single_sensed(struct gk20a *g, +static int vfe_var_construct_single_sensed(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { struct boardobj *ptmpobj = (struct boardobj *)pargs; struct vfe_var_single_sensed *pvfevar; - u32 status = 0; + int status = 0; nvgpu_log_info(g, " "); ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED); status = vfe_var_construct_single(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -652,7 +652,7 @@ static u32 vfe_var_construct_single_sensed(struct gk20a *g, return status; } -static u32 vfe_var_construct_single_sensed_fuse(struct gk20a *g, +static int vfe_var_construct_single_sensed_fuse(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { @@ -660,7 +660,7 @@ static u32 vfe_var_construct_single_sensed_fuse(struct gk20a *g, struct vfe_var_single_sensed_fuse *pvfevar; struct vfe_var_single_sensed_fuse *ptmpvar = (struct vfe_var_single_sensed_fuse *)pargs; - u32 status = 0; + int status = 0; nvgpu_log_info(g, " "); @@ -670,7 +670,7 @@ static u32 vfe_var_construct_single_sensed_fuse(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE); status = vfe_var_construct_single_sensed(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -713,7 +713,7 @@ static u32 vfe_var_construct_single_sensed_fuse(struct gk20a *g, goto exit; } exit: - if (status) { + if (status != 0) { (*ppboardobj)->destruct(*ppboardobj); } @@ -751,7 +751,7 @@ static int _vfe_var_pmudatainit_single_sensed_temp(struct gk20a *g, return status; } -static u32 vfe_var_construct_single_sensed_temp(struct gk20a *g, +static int vfe_var_construct_single_sensed_temp(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { @@ -759,7 +759,7 @@ static u32 vfe_var_construct_single_sensed_temp(struct gk20a *g, struct vfe_var_single_sensed_temp *pvfevar; struct vfe_var_single_sensed_temp *ptmpvar = (struct vfe_var_single_sensed_temp *)pargs; - u32 status = 0; + int status = 0; if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP) { return -EINVAL; @@ -767,7 +767,7 @@ static u32 vfe_var_construct_single_sensed_temp(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP); status = vfe_var_construct_single_sensed(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -817,7 +817,7 @@ static int vfe_var_construct_single_voltage(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE); status = vfe_var_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; } @@ -876,7 +876,7 @@ static struct vfe_var *construct_vfe_var(struct gk20a *g, void *pargs) return NULL; } - if (status) { + if (status != 0) { return NULL; } @@ -1053,7 +1053,7 @@ static int devinit_get_vfe_var_table(struct gk20a *g, status = boardobjgrp_objinsert(&pvfevarobjs->super.super, (struct boardobj *)pvar, index); - if (status) { + if (status != 0) { nvgpu_err(g, "error adding vfe_var boardobj %d", index); status = -EINVAL; goto done; @@ -1077,7 +1077,7 @@ static int vfe_var_construct_single(struct gk20a *g, ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE); status = vfe_var_construct_super(g, ppboardobj, size, pargs); - if (status) { + if (status != 0) { return -EINVAL; }