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gpu: nvgpu: fix CERT-C violations in mm

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INT33-C requires that modulo operations check divisor has non-zero value

Jira NVGPU-3882

Change-Id: Ic9cd1ca081f0ef98d5f81bb2d1c43a2a69273275
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210255
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2019-10-02 11:10:01 -07:00
committed by Alex Waterman
parent 4c5058ade7
commit 3eaf08f06f
1 changed files with 1 additions and 0 deletions
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drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c
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@@ -529,6 +529,7 @@ static void gv11b_mm_mmu_fault_handle_buf_valid_entry(struct gk20a *g,
sub_err_type);
nvgpu_assert(get_indx < U32_MAX);
nvgpu_assert(entries != 0U);
get_indx = (get_indx + 1U) % entries;
nvgpu_log(g, gpu_dbg_intr, "new get index = %d", get_indx);