diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a.c index abfaf865d..8e20229c6 100644 --- a/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a.c @@ -223,7 +223,6 @@ u32 gk20a_fifo_pbdma_isr(struct gk20a *g) nvgpu_rc_pbdma_fault(g, f, pbdma_id, error_notifier); } - g->ops.pbdma.intr_clear_all(g, pbdma_id); } } return fifo_intr_0_pbdma_intr_pending_f(); diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c index c6a1b53c1..a095304db 100644 --- a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c +++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c @@ -452,6 +452,7 @@ bool gm20b_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id, &intr_error_notifier)) { recover = true; } + nvgpu_writel(g, pbdma_intr_0_r(pbdma_id), pbdma_intr_0); } if (pbdma_intr_1 != 0U) { @@ -463,6 +464,7 @@ bool gm20b_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id, &intr_error_notifier)) { recover = true; } + nvgpu_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); } if (error_notifier != NULL) { diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 043098bd2..05f09dcc3 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -603,7 +603,6 @@ static const struct gpu_ops gm20b_ops = { .cleanup_sw = nvgpu_pbdma_cleanup_sw, .setup_hw = gm20b_pbdma_setup_hw, .intr_enable = gm20b_pbdma_intr_enable, - .intr_clear_all = gm20b_pbdma_clear_all_intr, .acquire_val = gm20b_pbdma_acquire_val, .get_signature = gm20b_pbdma_get_signature, .dump_status = gm20b_pbdma_dump_status, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index ef73312e1..664468bea 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -667,7 +667,6 @@ static const struct gpu_ops gp10b_ops = { .cleanup_sw = nvgpu_pbdma_cleanup_sw, .setup_hw = gm20b_pbdma_setup_hw, .intr_enable = gm20b_pbdma_intr_enable, - .intr_clear_all = gm20b_pbdma_clear_all_intr, .acquire_val = gm20b_pbdma_acquire_val, .get_signature = gp10b_pbdma_get_signature, .dump_status = gm20b_pbdma_dump_status, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv100.c b/drivers/gpu/nvgpu/hal/init/hal_gv100.c index 4c3887167..2cec1c654 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv100.c @@ -817,7 +817,6 @@ static const struct gpu_ops gv100_ops = { .cleanup_sw = nvgpu_pbdma_cleanup_sw, .setup_hw = gm20b_pbdma_setup_hw, .intr_enable = gv11b_pbdma_intr_enable, - .intr_clear_all = gm20b_pbdma_clear_all_intr, .acquire_val = gm20b_pbdma_acquire_val, .get_signature = gp10b_pbdma_get_signature, .dump_status = gm20b_pbdma_dump_status, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 6f5cfb43d..9bf517d05 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -785,7 +785,6 @@ static const struct gpu_ops gv11b_ops = { .cleanup_sw = nvgpu_pbdma_cleanup_sw, .setup_hw = gv11b_pbdma_setup_hw, .intr_enable = gv11b_pbdma_intr_enable, - .intr_clear_all = gm20b_pbdma_clear_all_intr, .acquire_val = gm20b_pbdma_acquire_val, .get_signature = gp10b_pbdma_get_signature, .dump_status = gm20b_pbdma_dump_status, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index aa29a46d5..5294abde4 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -855,7 +855,6 @@ static const struct gpu_ops tu104_ops = { .cleanup_sw = nvgpu_pbdma_cleanup_sw, .setup_hw = gv11b_pbdma_setup_hw, .intr_enable = gv11b_pbdma_intr_enable, - .intr_clear_all = gm20b_pbdma_clear_all_intr, .acquire_val = gm20b_pbdma_acquire_val, .get_signature = gp10b_pbdma_get_signature, .dump_status = gm20b_pbdma_dump_status, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 3e82b800c..180c26e0b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1102,7 +1102,6 @@ struct gpu_ops { void (*cleanup_sw)(struct gk20a *g); void (*setup_hw)(struct gk20a *g); void (*intr_enable)(struct gk20a *g, bool enable); - void (*intr_clear_all)(struct gk20a *g, u32 pbdma_id); bool (*handle_intr_0)(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0, u32 *error_notifier);