From 3f08cf8a48de5cce06cbe761723775a04a1a60ad Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Sun, 9 Jun 2019 15:31:49 +0530 Subject: [PATCH] gpu: nvgpu: rename feature Make and C flags Name the Make and C flag variables consistently wih syntax: CONFIG_NVGPU_ s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS s/NVGPU_USERD/CONFIG_NVGPU_USERD s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU s/NVGPU_VPR/CONFIG_NVGPU_VPR s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG JIRA NVGPU-3624 Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2130290 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Kconfig | 12 ++-- drivers/gpu/nvgpu/Makefile | 44 ++++++------ drivers/gpu/nvgpu/Makefile.shared.configs | 70 +++++++++---------- drivers/gpu/nvgpu/Makefile.sources | 30 ++++---- drivers/gpu/nvgpu/common/acr/acr.c | 8 +-- drivers/gpu/nvgpu/common/acr/acr_blob_alloc.c | 2 +- drivers/gpu/nvgpu/common/acr/acr_blob_alloc.h | 2 +- .../nvgpu/common/acr/acr_blob_construct_v0.c | 4 +- .../nvgpu/common/acr/acr_blob_construct_v1.c | 2 +- drivers/gpu/nvgpu/common/acr/acr_bootstrap.c | 2 +- drivers/gpu/nvgpu/common/acr/acr_priv.h | 2 +- drivers/gpu/nvgpu/common/acr/acr_sw_gm20b.c | 2 +- drivers/gpu/nvgpu/common/acr/acr_sw_gv100.c | 2 +- drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c | 6 +- drivers/gpu/nvgpu/common/acr/acr_wpr.c | 2 +- drivers/gpu/nvgpu/common/acr/acr_wpr.h | 2 +- drivers/gpu/nvgpu/common/ce/ce.c | 4 +- drivers/gpu/nvgpu/common/clk_arb/clk_arb.c | 8 +-- .../common/engine_queues/engine_mem_queue.c | 2 +- drivers/gpu/nvgpu/common/falcon/falcon.c | 4 +- drivers/gpu/nvgpu/common/fifo/channel.c | 38 +++++----- drivers/gpu/nvgpu/common/fifo/engines.c | 20 +++--- drivers/gpu/nvgpu/common/fifo/fifo.c | 4 +- drivers/gpu/nvgpu/common/fifo/runlist.c | 22 +++--- drivers/gpu/nvgpu/common/fifo/submit.c | 4 +- drivers/gpu/nvgpu/common/fifo/tsg.c | 8 +-- drivers/gpu/nvgpu/common/fifo/userd.c | 8 +-- drivers/gpu/nvgpu/common/gr/ctx.c | 18 ++--- drivers/gpu/nvgpu/common/gr/fs_state.c | 2 +- drivers/gpu/nvgpu/common/gr/global_ctx.c | 6 +- drivers/gpu/nvgpu/common/gr/gr.c | 38 +++++----- drivers/gpu/nvgpu/common/gr/gr_config.c | 16 ++--- drivers/gpu/nvgpu/common/gr/gr_config_priv.h | 2 +- drivers/gpu/nvgpu/common/gr/gr_falcon.c | 18 ++--- drivers/gpu/nvgpu/common/gr/gr_intr.c | 18 ++--- drivers/gpu/nvgpu/common/gr/gr_priv.h | 6 +- drivers/gpu/nvgpu/common/gr/gr_setup.c | 8 +-- drivers/gpu/nvgpu/common/gr/gr_utils.c | 6 +- drivers/gpu/nvgpu/common/gr/obj_ctx.c | 8 +-- drivers/gpu/nvgpu/common/gr/subctx.c | 4 +- drivers/gpu/nvgpu/common/gr/zbc.c | 6 +- drivers/gpu/nvgpu/common/init/nvgpu_init.c | 34 ++++----- drivers/gpu/nvgpu/common/mm/mm.c | 6 +- drivers/gpu/nvgpu/common/mm/vidmem.c | 6 +- drivers/gpu/nvgpu/common/netlist/netlist.c | 8 +-- .../gpu/nvgpu/common/netlist/netlist_priv.h | 2 +- .../nvgpu/common/nvlink/init/device_reginit.c | 2 +- .../common/nvlink/init/device_reginit_gv100.c | 4 +- .../nvlink/intr_and_err_handling_gv100.c | 4 +- .../common/nvlink/link_mode_transitions.c | 2 +- drivers/gpu/nvgpu/common/nvlink/minion.c | 2 +- drivers/gpu/nvgpu/common/nvlink/nvlink.c | 4 +- .../gpu/nvgpu/common/nvlink/nvlink_gv100.c | 4 +- .../gpu/nvgpu/common/nvlink/nvlink_tu104.c | 4 +- drivers/gpu/nvgpu/common/nvlink/probe.c | 2 +- drivers/gpu/nvgpu/common/pmu/lsfm/lsfm.c | 4 +- drivers/gpu/nvgpu/common/pmu/pmu.c | 14 ++-- .../gpu/nvgpu/common/power_features/pg/pg.c | 8 +-- .../common/power_features/power_features.c | 4 +- drivers/gpu/nvgpu/common/rc/rc.c | 6 +- drivers/gpu/nvgpu/common/sim/sim_netlist.c | 12 ++-- .../gpu/nvgpu/common/vgpu/fifo/userd_vgpu.c | 4 +- .../nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c | 36 +++++----- drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c | 4 +- .../nvgpu/common/vgpu/gr/fecs_trace_vgpu.c | 4 +- drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c | 24 +++---- drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h | 4 +- .../nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c | 40 +++++------ .../gpu/nvgpu/common/vgpu/init/init_vgpu.c | 4 +- .../gpu/nvgpu/common/vgpu/intr/intr_vgpu.c | 2 +- drivers/gpu/nvgpu/common/vgpu/vgpu.c | 4 +- drivers/gpu/nvgpu/hal/fb/fb_gm20b.c | 2 +- drivers/gpu/nvgpu/hal/fb/fb_gv11b.c | 2 +- drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c | 10 +-- drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c | 14 ++-- drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c | 14 ++-- drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c | 2 +- .../gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c | 4 +- .../gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.h | 2 +- .../gpu/nvgpu/hal/fifo/runlist_fifo_gv11b.c | 2 +- .../gpu/nvgpu/hal/fifo/runlist_fifo_gv11b.h | 2 +- .../gpu/nvgpu/hal/gr/config/gr_config_gm20b.c | 2 +- .../gpu/nvgpu/hal/gr/config/gr_config_gm20b.h | 2 +- .../hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c | 4 +- .../hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h | 4 +- .../gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c | 19 ++--- .../gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b.c | 6 +- drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c | 2 +- drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c | 6 +- drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.h | 2 +- drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c | 4 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c | 2 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h | 2 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c | 2 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h | 2 +- drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c | 2 +- drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c | 8 +-- drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c | 2 +- drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c | 2 +- drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 62 ++++++++-------- drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 70 +++++++++---------- drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 62 ++++++++-------- drivers/gpu/nvgpu/hal/init/hal_init.c | 4 +- drivers/gpu/nvgpu/hal/init/hal_tu104.c | 68 +++++++++--------- drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c | 4 +- drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.h | 4 +- drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c | 4 +- drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.h | 4 +- drivers/gpu/nvgpu/hal/mc/mc_gm20b.c | 2 +- drivers/gpu/nvgpu/hal/mc/mc_gp10b.c | 2 +- .../nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b.c | 8 +-- .../hal/nvlink/link_mode_transitions_gv100.c | 4 +- .../hal/nvlink/link_mode_transitions_tu104.c | 4 +- drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c | 4 +- drivers/gpu/nvgpu/hal/nvlink/minion_tu104.c | 4 +- drivers/gpu/nvgpu/hal/pmu/pmu_gp106.c | 2 +- drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c | 6 +- drivers/gpu/nvgpu/hal/pramin/pramin_init.c | 4 +- drivers/gpu/nvgpu/hal/rc/rc_gv11b.c | 30 ++++---- drivers/gpu/nvgpu/include/nvgpu/channel.h | 8 +-- drivers/gpu/nvgpu/include/nvgpu/fifo.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/fifo/userd.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 48 ++++++------- drivers/gpu/nvgpu/include/nvgpu/gr/config.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h | 6 +- .../gpu/nvgpu/include/nvgpu/gr/global_ctx.h | 2 +- .../gpu/nvgpu/include/nvgpu/gr/gr_falcon.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h | 8 +-- drivers/gpu/nvgpu/include/nvgpu/gr/setup.h | 4 +- drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/mm.h | 4 +- drivers/gpu/nvgpu/include/nvgpu/netlist.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/pmu.h | 10 +-- .../nvgpu/include/nvgpu/power_features/pg.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/runlist.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/tsg.h | 6 +- .../gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 4 +- drivers/gpu/nvgpu/os/linux/cde.c | 2 +- drivers/gpu/nvgpu/os/linux/debug_fecs_trace.h | 4 +- drivers/gpu/nvgpu/os/linux/driver_common.c | 4 +- drivers/gpu/nvgpu/os/linux/ioctl.c | 4 +- drivers/gpu/nvgpu/os/linux/ioctl_channel.c | 8 +-- drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 12 ++-- drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 10 +-- drivers/gpu/nvgpu/os/linux/linux-channel.c | 2 +- drivers/gpu/nvgpu/os/linux/module.c | 10 +-- drivers/gpu/nvgpu/os/linux/nvlink.c | 8 +-- drivers/gpu/nvgpu/os/linux/nvlink_probe.c | 6 +- drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c | 4 +- userspace/units/fifo/nvgpu-fifo.c | 4 +- userspace/units/fuse/nvgpu-fuse.c | 4 +- 151 files changed, 706 insertions(+), 699 deletions(-) diff --git a/drivers/gpu/nvgpu/Kconfig b/drivers/gpu/nvgpu/Kconfig index 9edfb5703..6a43b3ea8 100644 --- a/drivers/gpu/nvgpu/Kconfig +++ b/drivers/gpu/nvgpu/Kconfig @@ -58,19 +58,19 @@ config NVGPU_TRACK_MEM_USAGE to other OSes which do not have Linux' kmem_leak. -config GK20A_CYCLE_STATS - bool "Support GK20A GPU CYCLE STATS" +config NVGPU_CYCLESTATS + bool "Support GPU CYCLE STATS" depends on GK20A default y help Say Y here to enable the cycle stats debugging features. -config GK20A_CTXSW_TRACE - bool "Support GK20A Context Switch tracing" +config NVGPU_FECS_TRACE + bool "Support NVGPU FECS Context Switch tracing" depends on GK20A default y help - Enable support for the GK20A Context Switch Tracing. In this mode, + Enable support for the NVGPU Context Switch Tracing. In this mode, FECS collects timestamps for contexts loaded on GR engine. This allows tracking context switches on GR engine, as well as identifying processes that submitted work. @@ -168,7 +168,7 @@ config NVGPU_DEBUGGER help Support for debugger APIs -config NVGPU_FEATURE_LS_PMU +config NVGPU_LS_PMU bool "LS PMU support" depends on GK20A default y diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 0aab62696..78dcfdaea 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -18,23 +18,27 @@ endif ccflags-y += -D__NVGPU_PREVENT_UNTRUSTED_SPECULATION ifeq ($(CONFIG_NVGPU_DEBUGGER),y) -ccflags-y += -DNVGPU_DEBUGGER +ccflags-y += -DCONFIG_NVGPU_DEBUGGER endif -ccflags-y += -DNVGPU_FEATURE_ACR_LEGACY -ccflags-y += -DNVGPU_FEATURE_ENGINE_QUEUE -ccflags-y += -DNVGPU_ENGINE -ccflags-y += -DNVGPU_USERD -ccflags-y += -DNVGPU_CHANNEL_WDT -ccflags-y += -DNVGPU_FEATURE_LS_PMU -ccflags-y += -DNVGPU_DGPU_SUPPORT -ccflags-y += -DNVGPU_VPR -ccflags-y += -DNVGPU_REPLAYABLE_FAULT -ccflags-y += -DNVGPU_GRAPHICS -ccflags-y += -DNVGPU_FEATURE_CHANNEL_TSG_SCHEDULING -ccflags-y += -DNVGPU_FEATURE_CHANNEL_TSG_CONTROL -ccflags-y += -DNVGPU_FEATURE_POWER_PG -ccflags-y += -DNVGPU_FEATURE_CE +ifeq ($(CONFIG_TEGRA_NVLINK),y) +ccflags-y += -DCONFIG_NVGPU_NVLINK +endif + +ccflags-y += -DCONFIG_NVGPU_ACR_LEGACY +ccflags-y += -DCONFIG_NVGPU_ENGINE_QUEUE +ccflags-y += -DCONFIG_NVGPU_FIFO_ENGINE_ACTIVITY +ccflags-y += -DCONFIG_NVGPU_USERD +ccflags-y += -DCONFIG_NVGPU_CHANNEL_WDT +ccflags-y += -DCONFIG_NVGPU_LS_PMU +ccflags-y += -DCONFIG_NVGPU_DGPU +ccflags-y += -DCONFIG_NVGPU_VPR +ccflags-y += -DCONFIG_NVGPU_REPLAYABLE_FAULT +ccflags-y += -DCONFIG_NVGPU_GRAPHICS +ccflags-y += -DCONFIG_NVGPU_CHANNEL_TSG_SCHEDULING +ccflags-y += -DCONFIG_NVGPU_CHANNEL_TSG_CONTROL +ccflags-y += -DCONFIG_NVGPU_POWER_PG +ccflags-y += -DCONFIG_NVGPU_CE obj-$(CONFIG_GK20A) := nvgpu.o @@ -438,13 +442,13 @@ nvgpu-$(CONFIG_DEBUG_FS) += \ os/linux/debug_kmem.o endif -nvgpu-$(CONFIG_GK20A_CTXSW_TRACE) += \ +nvgpu-$(CONFIG_NVGPU_FECS_TRACE) += \ common/gr/fecs_trace.o \ hal/gr/fecs_trace/fecs_trace_gm20b.o \ hal/gr/fecs_trace/fecs_trace_gv11b.o \ os/linux/fecs_trace_linux.o -ifeq ($(CONFIG_GK20A_CTXSW_TRACE),y) +ifeq ($(CONFIG_NVGPU_FECS_TRACE),y) nvgpu-$(CONFIG_DEBUG_FS) += \ os/linux/debug_fecs_trace.o endif @@ -487,7 +491,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ os/linux/vgpu/vgpu_linux.o \ os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.o -ifeq ($(CONFIG_GK20A_CTXSW_TRACE),y) +ifeq ($(CONFIG_NVGPU_FECS_TRACE),y) nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ os/linux/vgpu/fecs_trace_vgpu_linux.o endif @@ -610,11 +614,11 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ common/vgpu/gv11b/vgpu_hal_gv11b.o \ common/vgpu/gv11b/vgpu_tsg_gv11b.o \ -nvgpu-$(CONFIG_GK20A_CYCLE_STATS) += \ +nvgpu-$(CONFIG_NVGPU_CYCLESTATS) += \ common/perf/cyclestats_snapshot.o \ common/cyclestats/cyclestats.o ifeq ($(CONFIG_TEGRA_GR_VIRTUALIZATION),y) -nvgpu-$(CONFIG_GK20A_CYCLE_STATS) += \ +nvgpu-$(CONFIG_NVGPU_CYCLESTATS) += \ common/vgpu/perf/cyclestats_snapshot_vgpu.o endif diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs index e46b5457c..20c34c1c9 100644 --- a/drivers/gpu/nvgpu/Makefile.shared.configs +++ b/drivers/gpu/nvgpu/Makefile.shared.configs @@ -56,73 +56,73 @@ NVGPU_COMMON_CFLAGS += \ -DCONFIG_PCI_MSI # Enable debugger APIs for safety build until devctl whitelisting is done -NVGPU_DEBUGGER := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_DEBUGGER +CONFIG_NVGPU_DEBUGGER := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_DEBUGGER # Enable cyclestats APIs for safety build until complete debugger support is enabled -NVGPU_CYCLESTATS_SUPPORT := 1 -NVGPU_COMMON_CFLAGS += -DCONFIG_GK20A_CYCLE_STATS +CONFIG_NVGPU_CYCLESTATS := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_CYCLESTATS # Enable USERD for safety build until we switch to user mode submits only -NVGPU_COMMON_CFLAGS += -DNVGPU_USERD +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_USERD # Enable Channel WDT for safety build until we switch to user mode submits only -NVGPU_COMMON_CFLAGS += -DNVGPU_CHANNEL_WDT +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_CHANNEL_WDT # Enable CE support for safety build until we remove Vidmem clear support. -NVGPU_FEATURE_CE := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_FEATURE_CE +CONFIG_NVGPU_CE := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_CE # Enable Grpahics support for safety build until we switch to compute only -NVGPU_GRAPHICS := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_GRAPHICS +CONFIG_NVGPU_GRAPHICS := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_GRAPHICS -NVGPU_COMMON_CFLAGS += -DNVGPU_ENGINE +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_FIFO_ENGINE_ACTIVITY # Enable Channel/TSG Scheduling for safety build until devctl whitelisting is done -NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_CHANNEL_TSG_SCHEDULING # Enable Channel/TSG Control for safety build until devctl whitelisting is done -NVGPU_FEATURE_CHANNEL_TSG_CONTROL := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_FEATURE_CHANNEL_TSG_CONTROL +CONFIG_NVGPU_CHANNEL_TSG_CONTROL := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_CHANNEL_TSG_CONTROL # # Flags enabled for only the regular build profile. # ifneq ($(profile),safety) # ACR feature to enable old tegra ACR profile support -NVGPU_FEATURE_ACR_LEGACY := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_FEATURE_ACR_LEGACY +CONFIG_NVGPU_ACR_LEGACY := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_ACR_LEGACY -NVGPU_FEATURE_ENGINE_QUEUE := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_FEATURE_ENGINE_QUEUE +CONFIG_NVGPU_ENGINE_QUEUE := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_ENGINE_QUEUE -NVGPU_FECS_TRACE_SUPPORT := 1 -NVGPU_COMMON_CFLAGS += -DCONFIG_GK20A_CTXSW_TRACE +CONFIG_NVGPU_FECS_TRACE := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_FECS_TRACE -IGPU_VIRT_SUPPORT := 1 -NVGPU_COMMON_CFLAGS += -DIGPU_VIRT_SUPPORT +CONFIG_NVGPU_IGPU_VIRT := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_IGPU_VIRT # Enable nvlink support for normal build. -NVGPU_NVLINK_SUPPORT := 1 -NVGPU_COMMON_CFLAGS += -DCONFIG_TEGRA_NVLINK +CONFIG_NVGPU_NVLINK := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_NVLINK # Enable dgpu support for normal build. -NVGPU_DGPU_SUPPORT := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_DGPU_SUPPORT +CONFIG_NVGPU_DGPU := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_DGPU -NVGPU_VPR := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_VPR +CONFIG_NVGPU_VPR := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_VPR -NVGPU_REPLAYABLE_FAULT := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_REPLAYABLE_FAULT +CONFIG_NVGPU_REPLAYABLE_FAULT := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_REPLAYABLE_FAULT # Enable LS PMU support for normal build -NVGPU_FEATURE_LS_PMU := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_FEATURE_LS_PMU +CONFIG_NVGPU_LS_PMU := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_LS_PMU # Enable elpg support for normal build -NVGPU_FEATURE_POWER_PG := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_FEATURE_POWER_PG +CONFIG_NVGPU_POWER_PG := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_POWER_PG endif diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 7e44cfd88..b659af8d8 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -45,7 +45,7 @@ srcs += os/posix/nvgpu.c \ os/posix/posix-vidmem.c \ os/posix/fecs_trace_posix.c -ifdef NVGPU_NVLINK_SUPPORT +ifdef CONFIG_NVGPU_NVLINK srcs += os/posix/posix-nvlink.c endif endif @@ -274,21 +274,21 @@ srcs += common/utils/enabled.c \ hal/top/top_gp106.c \ hal/top/top_gv11b.c -ifeq ($(NVGPU_FEATURE_ACR_LEGACY),1) +ifeq ($(CONFIG_NVGPU_ACR_LEGACY),1) srcs += \ common/acr/acr_blob_construct_v0.c \ common/acr/acr_sw_gm20b.c \ common/acr/acr_sw_gp10b.c endif -ifeq ($(NVGPU_FEATURE_ENGINE_QUEUE),1) +ifeq ($(CONFIG_NVGPU_ENGINE_QUEUE),1) srcs += common/engine_queues/engine_mem_queue.c \ common/engine_queues/engine_dmem_queue.c \ common/engine_queues/engine_emem_queue.c \ common/engine_queues/engine_fb_queue.c endif -ifeq ($(NVGPU_GRAPHICS),1) +ifeq ($(CONFIG_NVGPU_GRAPHICS),1) srcs += common/gr/zbc.c \ common/gr/zcull.c \ hal/gr/zbc/zbc_gm20b.c \ @@ -298,7 +298,7 @@ srcs += common/gr/zbc.c \ hal/gr/zcull/zcull_gv11b.c endif -ifeq ($(NVGPU_DEBUGGER),1) +ifeq ($(CONFIG_NVGPU_DEBUGGER),1) srcs += common/debugger.c \ common/regops/regops.c \ common/gr/hwpm_map.c \ @@ -319,23 +319,23 @@ srcs += common/debugger.c \ hal/gr/gr/gr_tu104.c endif -ifeq ($(NVGPU_FEATURE_CE),1) +ifeq ($(CONFIG_NVGPU_CE),1) srcs += common/ce/ce.c endif -ifeq ($(NVGPU_FECS_TRACE_SUPPORT),1) +ifeq ($(CONFIG_NVGPU_FECS_TRACE),1) srcs += common/gr/fecs_trace.c \ hal/gr/fecs_trace/fecs_trace_gm20b.c \ hal/gr/fecs_trace/fecs_trace_gv11b.c -ifeq ($(IGPU_VIRT_SUPPORT), 1) +ifeq ($(CONFIG_NVGPU_IGPU_VIRT),1) srcs += common/vgpu/gr/fecs_trace_vgpu.c endif endif -ifeq ($(NVGPU_CYCLESTATS_SUPPORT),1) +ifeq ($(CONFIG_NVGPU_CYCLESTATS),1) srcs += common/perf/cyclestats_snapshot.c \ common/cyclestats/cyclestats.c -ifeq ($(IGPU_VIRT_SUPPORT), 1) +ifeq ($(CONFIG_NVGPU_IGPU_VIRT),1) srcs += common/vgpu/perf/cyclestats_snapshot_vgpu.c endif endif @@ -348,7 +348,7 @@ endif srcs += hal/gr/config/gr_config_gm20b.c \ hal/gr/config/gr_config_gv100.c -ifeq ($(NVGPU_FEATURE_LS_PMU),1) +ifeq ($(CONFIG_NVGPU_LS_PMU),1) # Add LS PMU files which are required for normal build srcs += \ common/pmu/boardobj/boardobj.c \ @@ -420,11 +420,11 @@ srcs += \ hal/pmu/pmu_tu104.c endif -ifeq ($(NVGPU_FEATURE_POWER_PG), 1) +ifeq ($(CONFIG_NVGPU_POWER_PG),1) srcs += common/power_features/pg/pg.c endif -ifeq ($(IGPU_VIRT_SUPPORT), 1) +ifeq ($(CONFIG_NVGPU_IGPU_VIRT),1) srcs += common/vgpu/init/init_vgpu.c \ common/vgpu/init/init_hal_vgpu.c \ common/vgpu/ivc/comm_vgpu.c \ @@ -454,7 +454,7 @@ srcs += common/vgpu/init/init_vgpu.c \ common/vgpu/gp10b/vgpu_hal_gp10b.c endif -ifeq ($(NVGPU_NVLINK_SUPPORT), 1) +ifeq ($(CONFIG_NVGPU_NVLINK),1) srcs += common/vbios/nvlink_bios.c \ common/nvlink/probe.c \ common/nvlink/init/device_reginit.c \ @@ -471,7 +471,7 @@ srcs += common/vbios/nvlink_bios.c \ hal/nvlink/link_mode_transitions_tu104.c endif -ifeq ($(NVGPU_DGPU_SUPPORT), 1) +ifeq ($(CONFIG_NVGPU_DGPU),1) srcs += common/sec2/sec2.c \ common/sec2/sec2_allocator.c \ common/sec2/sec2_lsfm.c \ diff --git a/drivers/gpu/nvgpu/common/acr/acr.c b/drivers/gpu/nvgpu/common/acr/acr.c index 07c7a1bff..a63d0d932 100644 --- a/drivers/gpu/nvgpu/common/acr/acr.c +++ b/drivers/gpu/nvgpu/common/acr/acr.c @@ -27,12 +27,12 @@ #include #include "acr_priv.h" -#ifdef NVGPU_FEATURE_ACR_LEGACY +#ifdef CONFIG_NVGPU_ACR_LEGACY #include "acr_sw_gm20b.h" #include "acr_sw_gp10b.h" #endif #include "acr_sw_gv11b.h" -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU #include "acr_sw_gv100.h" #include "acr_sw_tu104.h" #endif @@ -133,7 +133,7 @@ int nvgpu_acr_init(struct gk20a *g, struct nvgpu_acr **acr) } switch (ver) { -#ifdef NVGPU_FEATURE_ACR_LEGACY +#ifdef CONFIG_NVGPU_ACR_LEGACY case GK20A_GPUID_GM20B: case GK20A_GPUID_GM20B_B: nvgpu_gm20b_acr_sw_init(g, *acr); @@ -145,7 +145,7 @@ int nvgpu_acr_init(struct gk20a *g, struct nvgpu_acr **acr) case NVGPU_GPUID_GV11B: nvgpu_gv11b_acr_sw_init(g, *acr); break; -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU case NVGPU_GPUID_GV100: nvgpu_gv100_acr_sw_init(g, *acr); break; diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.c b/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.c index 968da5d9e..8799750bb 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.c +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.c @@ -34,7 +34,7 @@ int nvgpu_acr_alloc_blob_space_sys(struct gk20a *g, size_t size, return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_PHYSICALLY_ADDRESSED, size, mem); } -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size, struct nvgpu_mem *mem) { diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.h b/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.h index da06616eb..d91a8c02b 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.h +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.h @@ -28,7 +28,7 @@ struct nvgpu_mem; int nvgpu_acr_alloc_blob_space_sys(struct gk20a *g, size_t size, struct nvgpu_mem *mem); -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size, struct nvgpu_mem *mem); #endif diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c index 8a825a81a..303d039d9 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c @@ -35,7 +35,7 @@ #include "acr_wpr.h" #include "acr_priv.h" -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU int nvgpu_acr_lsf_pmu_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img) { struct lsf_ucode_desc *lsf_desc; @@ -557,7 +557,7 @@ static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, /* Update the argc/argv members*/ ldr_cfg->argc = 1; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU nvgpu_pmu_fw_get_cmd_line_args_offset(g, &ldr_cfg->argv); #endif *p_bl_gen_desc_size = (u32)sizeof(struct loader_config); diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c index b64e0cf6c..452b41029 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c @@ -39,7 +39,7 @@ static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value) dma_addr->hi |= u64_hi32(value); } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU int nvgpu_acr_lsf_pmu_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img) { struct lsf_ucode_desc_v1 *lsf_desc; diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c index 51f0e7efb..64179536c 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c +++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c @@ -370,7 +370,7 @@ err_release_acr_fw: acr_desc->acr_fw = NULL; return status; } -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU int nvgpu_acr_self_hs_load_bootstrap(struct gk20a *g, struct nvgpu_falcon *flcn, struct nvgpu_firmware *hs_fw, u32 timeout) { diff --git a/drivers/gpu/nvgpu/common/acr/acr_priv.h b/drivers/gpu/nvgpu/common/acr/acr_priv.h index 86eb4fe82..edf2ff137 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_priv.h +++ b/drivers/gpu/nvgpu/common/acr/acr_priv.h @@ -24,7 +24,7 @@ #define ACR_H #include "acr_bootstrap.h" -#ifdef NVGPU_FEATURE_ACR_LEGACY +#ifdef CONFIG_NVGPU_ACR_LEGACY #include "acr_blob_construct_v0.h" #endif #include "acr_blob_construct_v1.h" diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_gm20b.c b/drivers/gpu/nvgpu/common/acr/acr_sw_gm20b.c index 673a0d5de..5299218a9 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_sw_gm20b.c +++ b/drivers/gpu/nvgpu/common/acr/acr_sw_gm20b.c @@ -116,7 +116,7 @@ static u32 gm20b_acr_lsf_pmu(struct gk20a *g, lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE; lsf->is_lazy_bootstrap = false; lsf->is_priv_load = false; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details_v0; lsf->get_cmd_line_args_offset = nvgpu_pmu_fw_get_cmd_line_args_offset; #endif diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_gv100.c b/drivers/gpu/nvgpu/common/acr/acr_sw_gv100.c index e5e1c2e29..ed319a1a5 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_sw_gv100.c +++ b/drivers/gpu/nvgpu/common/acr/acr_sw_gv100.c @@ -94,7 +94,7 @@ static u32 gv100_acr_lsf_pmu(struct gk20a *g, lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE; lsf->is_lazy_bootstrap = false; lsf->is_priv_load = false; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details_v1; lsf->get_cmd_line_args_offset = nvgpu_pmu_fw_get_cmd_line_args_offset; #endif diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c b/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c index dfd5c1533..faa33f929 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c +++ b/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c @@ -24,7 +24,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif @@ -118,7 +118,7 @@ void gv11b_acr_fill_bl_dmem_desc(struct gk20a *g, } /* LSF static config functions */ -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU static u32 gv11b_acr_lsf_pmu(struct gk20a *g, struct acr_lsf_config *lsf) { @@ -180,7 +180,7 @@ static u32 gv11b_acr_lsf_conifg(struct gk20a *g, struct nvgpu_acr *acr) { u32 lsf_enable_mask = 0; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU lsf_enable_mask |= gv11b_acr_lsf_pmu(g, &acr->lsf[FALCON_ID_PMU]); #endif lsf_enable_mask |= gv11b_acr_lsf_fecs(g, &acr->lsf[FALCON_ID_FECS]); diff --git a/drivers/gpu/nvgpu/common/acr/acr_wpr.c b/drivers/gpu/nvgpu/common/acr/acr_wpr.c index 790952bff..2205900d5 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_wpr.c +++ b/drivers/gpu/nvgpu/common/acr/acr_wpr.c @@ -33,7 +33,7 @@ void nvgpu_acr_wpr_info_sys(struct gk20a *g, struct wpr_carveout_info *inf) { g->ops.fb.read_wpr_info(g, &inf->wpr_base, &inf->size); } -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU void nvgpu_acr_wpr_info_vid(struct gk20a *g, struct wpr_carveout_info *inf) { inf->wpr_base = g->mm.vidmem.bootstrap_base; diff --git a/drivers/gpu/nvgpu/common/acr/acr_wpr.h b/drivers/gpu/nvgpu/common/acr/acr_wpr.h index 19d6d753b..aa247d5a9 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_wpr.h +++ b/drivers/gpu/nvgpu/common/acr/acr_wpr.h @@ -33,7 +33,7 @@ struct wpr_carveout_info { }; void nvgpu_acr_wpr_info_sys(struct gk20a *g, struct wpr_carveout_info *inf); -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU void nvgpu_acr_wpr_info_vid(struct gk20a *g, struct wpr_carveout_info *inf); #endif diff --git a/drivers/gpu/nvgpu/common/ce/ce.c b/drivers/gpu/nvgpu/common/ce/ce.c index 7b0074df0..fea953032 100644 --- a/drivers/gpu/nvgpu/common/ce/ce.c +++ b/drivers/gpu/nvgpu/common/ce/ce.c @@ -536,7 +536,7 @@ u32 nvgpu_ce_create_context(struct gk20a *g, goto end; } -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT ce_ctx->ch->wdt.enabled = false; #endif @@ -576,7 +576,7 @@ u32 nvgpu_ce_create_context(struct gk20a *g, (void) memset(ce_ctx->cmd_buf_mem.cpu_va, 0x00, ce_ctx->cmd_buf_mem.size); -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING /* -1 means default channel timeslice value */ if (timeslice != -1) { err = g->ops.tsg.set_timeslice(ce_ctx->tsg, timeslice); diff --git a/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c b/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c index 6c5f5b57c..11bf501cb 100644 --- a/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c +++ b/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c @@ -34,7 +34,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #include #include @@ -107,7 +107,7 @@ void nvgpu_clk_arb_set_global_alarm(struct gk20a *g, u32 alarm) nvgpu_clk_arb_queue_notification(g, &arb->notification_queue, alarm); } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) { struct gk20a *g = arb->g; @@ -383,7 +383,7 @@ static void nvgpu_clk_arb_worker_poll_wakeup_process_item( clk_arb_dbg(g, " "); if (clk_arb_work_item->item_type == CLK_ARB_WORK_UPDATE_VF_TABLE) { -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU nvgpu_clk_arb_run_vf_table_cb(clk_arb_work_item->arb); #endif } else if (clk_arb_work_item->item_type == CLK_ARB_WORK_UPDATE_ARB) { @@ -614,7 +614,7 @@ void nvgpu_clk_arb_release_session(struct gk20a *g, nvgpu_clk_arb_worker_enqueue(g, &arb->update_arb_work_item); } } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU void nvgpu_clk_arb_schedule_vf_table_update(struct gk20a *g) { struct nvgpu_clk_arb *arb = g->clk_arb; diff --git a/drivers/gpu/nvgpu/common/engine_queues/engine_mem_queue.c b/drivers/gpu/nvgpu/common/engine_queues/engine_mem_queue.c index 31c103a06..b2d784659 100644 --- a/drivers/gpu/nvgpu/common/engine_queues/engine_mem_queue.c +++ b/drivers/gpu/nvgpu/common/engine_queues/engine_mem_queue.c @@ -411,7 +411,7 @@ int nvgpu_engine_mem_queue_init(struct nvgpu_engine_mem_queue **queue_p, case QUEUE_TYPE_DMEM: engine_dmem_queue_init(queue); break; -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU case QUEUE_TYPE_EMEM: engine_emem_queue_init(queue); break; diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index ca2c195fc..3913e1ca6 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c @@ -24,7 +24,7 @@ #include #include "falcon_sw_gk20a.h" -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU #include "falcon_sw_gv100.h" #include "falcon_sw_tu104.h" #endif @@ -692,7 +692,7 @@ static int falcon_sw_init(struct gk20a *g, struct nvgpu_falcon *flcn) case NVGPU_GPUID_GV11B: gk20a_falcon_sw_init(flcn); break; -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU case NVGPU_GPUID_GV100: gv100_falcon_sw_init(flcn); break; diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index 176ca2593..f32dacc0d 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c @@ -291,7 +291,7 @@ static void gk20a_free_channel(struct nvgpu_channel *ch, bool force) struct dbg_session_data *session_data, *tmp_s; struct dbg_session_channel_data *ch_data, *tmp; int err; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER bool deferred_reset_pending; #endif @@ -379,7 +379,7 @@ static void gk20a_free_channel(struct nvgpu_channel *ch, bool force) __func__, "references"); } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER /* if engine reset was deferred, perform it now */ nvgpu_mutex_acquire(&f->deferred_reset_mutex); deferred_reset_pending = g->fifo.deferred_reset_pending; @@ -403,7 +403,7 @@ static void gk20a_free_channel(struct nvgpu_channel *ch, bool force) nvgpu_log_info(g, "freeing bound channel context, timeout=%ld", timeout); -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE if (g->ops.gr.fecs_trace.unbind_channel && !ch->vpr) g->ops.gr.fecs_trace.unbind_channel(g, &ch->inst_block); #endif @@ -717,7 +717,7 @@ struct nvgpu_channel *gk20a_open_new_channel(struct gk20a *g, ch->ctxsw_timeout_debug_dump = true; ch->unserviceable = false; -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT /* init kernel watchdog timeout */ ch->wdt.enabled = true; ch->wdt.limit_ms = g->ch_wdt_init_limit_ms; @@ -1211,7 +1211,7 @@ static int nvgpu_channel_setup_ramfc(struct nvgpu_channel *c, u64 pbdma_acquire_timeout = 0ULL; struct gk20a *g = c->g; -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT if (c->wdt.enabled && nvgpu_is_timeouts_enabled(c->g)) { pbdma_acquire_timeout = c->wdt.limit_ms; } @@ -1386,7 +1386,7 @@ int nvgpu_channel_setup_bind(struct nvgpu_channel *c, struct gk20a *g = c->g; int err = 0; -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR if ((args->flags & NVGPU_SETUP_BIND_FLAGS_SUPPORT_VPR) != 0U) { c->vpr = true; } @@ -1568,7 +1568,7 @@ u32 nvgpu_channel_update_gpfifo_get_and_get_free_count(struct nvgpu_channel *ch) return nvgpu_channel_get_gpfifo_free_count(ch); } -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT static void nvgpu_channel_wdt_init(struct nvgpu_channel *ch) { @@ -1762,7 +1762,7 @@ static void nvgpu_channel_wdt_handler(struct nvgpu_channel *ch) gk20a_gr_debug_dump(g); } -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL if (g->ops.tsg.force_reset(ch, NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT, ch->wdt.debug_dump) != 0) { @@ -1826,7 +1826,7 @@ nvgpu_channel_worker_from_worker(struct nvgpu_worker *worker) ((uintptr_t)worker - offsetof(struct nvgpu_channel_worker, worker)); }; -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT static void nvgpu_channel_worker_poll_init(struct nvgpu_worker *worker) { @@ -1890,7 +1890,7 @@ static void nvgpu_channel_worker_poll_wakeup_process_item( } static const struct nvgpu_worker_ops channel_worker_ops = { -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT .pre_process = nvgpu_channel_worker_poll_init, .wakeup_post_process = nvgpu_channel_worker_poll_wakeup_post_process_item, @@ -2009,7 +2009,7 @@ int nvgpu_channel_add_job(struct nvgpu_channel *c, job->num_mapped_buffers = num_mapped_buffers; job->mapped_buffers = mapped_buffers; -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT nvgpu_channel_wdt_start(c); #endif @@ -2058,7 +2058,7 @@ void nvgpu_channel_clean_up_jobs(struct nvgpu_channel *c, struct nvgpu_channel_job *job; struct gk20a *g; bool job_finished = false; -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT bool watchdog_on = false; #endif @@ -2075,7 +2075,7 @@ void nvgpu_channel_clean_up_jobs(struct nvgpu_channel *c, vm = c->vm; g = c->g; -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT /* * If !clean_all, we're in a condition where watchdog isn't supported * anyway (this would be a no-op). @@ -2112,7 +2112,7 @@ void nvgpu_channel_clean_up_jobs(struct nvgpu_channel *c, completed = nvgpu_fence_is_expired(job->post_fence); if (!completed) { -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT /* * The watchdog eventually sees an updated gp_get if * something happened in this loop. A new job can have @@ -2320,7 +2320,7 @@ static void nvgpu_channel_destroy(struct gk20a *g, struct nvgpu_channel *c) nvgpu_mutex_destroy(&c->joblist.cleanup_lock); nvgpu_mutex_destroy(&c->joblist.pre_alloc.read_lock); nvgpu_mutex_destroy(&c->sync_lock); -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) nvgpu_mutex_destroy(&c->cyclestate.cyclestate_buffer_mutex); nvgpu_mutex_destroy(&c->cs_client_mutex); #endif @@ -2377,7 +2377,7 @@ int nvgpu_channel_init_support(struct gk20a *g, u32 chid) nvgpu_spinlock_init(&c->ref_actions_lock); #endif nvgpu_spinlock_init(&c->joblist.dynamic.lock); -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT nvgpu_spinlock_init(&c->wdt.lock); #endif @@ -2389,7 +2389,7 @@ int nvgpu_channel_init_support(struct gk20a *g, u32 chid) nvgpu_mutex_init(&c->joblist.cleanup_lock); nvgpu_mutex_init(&c->joblist.pre_alloc.read_lock); nvgpu_mutex_init(&c->sync_lock); -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) nvgpu_mutex_init(&c->cyclestate.cyclestate_buffer_mutex); nvgpu_mutex_init(&c->cs_client_mutex); #endif @@ -2566,7 +2566,7 @@ void gk20a_channel_semaphore_wakeup(struct gk20a *g, bool post_events) nvgpu_warn(g, "failed to broadcast"); } -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL if (post_events) { struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(c); @@ -2726,7 +2726,7 @@ void nvgpu_channel_debug_dump_all(struct gk20a *g, nvgpu_kfree(g, infos); } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER int nvgpu_channel_deferred_reset_engines(struct gk20a *g, struct nvgpu_channel *ch) { diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index aeb914ab4..c9d548717 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -25,7 +25,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #include #endif @@ -247,7 +247,7 @@ u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g) return reset_mask; } -#ifdef NVGPU_ENGINE +#ifdef CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY int nvgpu_engine_enable_activity(struct gk20a *g, struct nvgpu_engine_info *eng_info) @@ -284,7 +284,7 @@ int nvgpu_engine_disable_activity(struct gk20a *g, { u32 pbdma_chid = NVGPU_INVALID_CHANNEL_ID; u32 engine_chid = NVGPU_INVALID_CHANNEL_ID; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU u32 token = PMU_INVALID_MUTEX_OWNER_ID; int mutex_ret = -EINVAL; #endif @@ -301,7 +301,7 @@ int nvgpu_engine_disable_activity(struct gk20a *g, return -EBUSY; } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (g->ops.pmu.is_pmu_supported(g)) { mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); @@ -356,7 +356,7 @@ int nvgpu_engine_disable_activity(struct gk20a *g, } clean_up: -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (mutex_ret == 0) { if (nvgpu_pmu_lock_release(g, g->pmu, PMU_MUTEX_ID_FIFO, &token) != 0){ @@ -536,13 +536,13 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id) } if (engine_enum == NVGPU_ENGINE_GR) { -#ifdef NVGPU_FEATURE_POWER_PG +#ifdef CONFIG_NVGPU_POWER_PG if (nvgpu_pg_elpg_disable(g) != 0 ) { nvgpu_err(g, "failed to set disable elpg"); } #endif -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE /* * Resetting engine will alter read/write index. Need to flush * circular buffer before re-enabling FECS. @@ -563,7 +563,7 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id) nvgpu_err(g, "failed to halt gr pipe"); } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER /* * resetting engine using mc_enable_r() is not * enough, we do full init sequence @@ -581,7 +581,7 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id) "gr cannot be reset without halting gr pipe"); } -#ifdef NVGPU_FEATURE_POWER_PG +#ifdef CONFIG_NVGPU_POWER_PG if (nvgpu_pg_elpg_enable(g) != 0 ) { nvgpu_err(g, "failed to set enable elpg"); } @@ -924,7 +924,7 @@ u32 nvgpu_engine_get_runlist_busy_engines(struct gk20a *g, u32 runlist_id) return eng_bitmask; } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER bool nvgpu_engine_should_defer_reset(struct gk20a *g, u32 engine_id, u32 engine_subid, bool fake_fault) { diff --git a/drivers/gpu/nvgpu/common/fifo/fifo.c b/drivers/gpu/nvgpu/common/fifo/fifo.c index a0c3f64bd..c925f6d42 100644 --- a/drivers/gpu/nvgpu/common/fifo/fifo.c +++ b/drivers/gpu/nvgpu/common/fifo/fifo.c @@ -48,7 +48,7 @@ void nvgpu_fifo_cleanup_sw_common(struct gk20a *g) nvgpu_engine_cleanup_sw(g); nvgpu_pbdma_cleanup_sw(g); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER f->deferred_reset_pending = false; nvgpu_mutex_destroy(&f->deferred_reset_mutex); #endif @@ -80,7 +80,7 @@ int nvgpu_fifo_setup_sw_common(struct gk20a *g) nvgpu_mutex_init(&f->intr.isr.mutex); nvgpu_mutex_init(&f->engines_reset_mutex); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_mutex_init(&f->deferred_reset_mutex); #endif diff --git a/drivers/gpu/nvgpu/common/fifo/runlist.c b/drivers/gpu/nvgpu/common/fifo/runlist.c index 6be0cd295..eab8ecd9d 100644 --- a/drivers/gpu/nvgpu/common/fifo/runlist.c +++ b/drivers/gpu/nvgpu/common/fifo/runlist.c @@ -29,7 +29,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif @@ -447,14 +447,14 @@ int nvgpu_runlist_update_locked(struct gk20a *g, u32 runlist_id, return ret; } -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING /* trigger host to expire current timeslice and reschedule runlist from front */ int nvgpu_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next, bool wait_preempt) { struct gk20a *g = ch->g; struct nvgpu_runlist_info *runlist; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU u32 token = PMU_INVALID_MUTEX_OWNER_ID; int mutex_ret = 0; #endif @@ -464,7 +464,7 @@ int nvgpu_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next, if (nvgpu_mutex_tryacquire(&runlist->runlist_lock) == 0) { return -EBUSY; } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU mutex_ret = nvgpu_pmu_lock_acquire( g, g->pmu, PMU_MUTEX_ID_FIFO, &token); #endif @@ -483,7 +483,7 @@ int nvgpu_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next, nvgpu_err(g, "wait pending failed for runlist %u", ch->runlist_id); } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (mutex_ret == 0) { if (nvgpu_pmu_lock_release(g, g->pmu, PMU_MUTEX_ID_FIFO, &token) != 0) { @@ -507,7 +507,7 @@ static int nvgpu_runlist_update(struct gk20a *g, u32 runlist_id, { struct nvgpu_runlist_info *runlist = NULL; struct nvgpu_fifo *f = &g->fifo; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU u32 token = PMU_INVALID_MUTEX_OWNER_ID; int mutex_ret = 0; #endif @@ -518,13 +518,13 @@ static int nvgpu_runlist_update(struct gk20a *g, u32 runlist_id, runlist = f->runlist_info[runlist_id]; nvgpu_mutex_acquire(&runlist->runlist_lock); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); #endif ret = nvgpu_runlist_update_locked(g, runlist_id, ch, add, wait_for_finish); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (mutex_ret == 0) { if (nvgpu_pmu_lock_release(g, g->pmu, PMU_MUTEX_ID_FIFO, &token) != 0) { @@ -610,19 +610,19 @@ const char *nvgpu_runlist_interleave_level_name(u32 interleave_level) void nvgpu_fifo_runlist_set_state(struct gk20a *g, u32 runlists_mask, u32 runlist_state) { -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU u32 token = PMU_INVALID_MUTEX_OWNER_ID; int mutex_ret = 0; #endif nvgpu_log(g, gpu_dbg_info, "runlist mask = 0x%08x state = 0x%08x", runlists_mask, runlist_state); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); #endif g->ops.runlist.write_state(g, runlists_mask, runlist_state); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (mutex_ret == 0) { if (nvgpu_pmu_lock_release(g, g->pmu, PMU_MUTEX_ID_FIFO, &token) != 0) { diff --git a/drivers/gpu/nvgpu/common/fifo/submit.c b/drivers/gpu/nvgpu/common/fifo/submit.c index 0a5061bae..6b5c6e68a 100644 --- a/drivers/gpu/nvgpu/common/fifo/submit.c +++ b/drivers/gpu/nvgpu/common/fifo/submit.c @@ -406,7 +406,7 @@ static int nvgpu_submit_channel_gpfifo(struct nvgpu_channel *c, && !c->deterministic) || !skip_buffer_refcounting); -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT need_job_tracking = need_job_tracking || c->wdt.enabled; #endif @@ -444,7 +444,7 @@ static int nvgpu_submit_channel_gpfifo(struct nvgpu_channel *c, need_sync_framework || !skip_buffer_refcounting; -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT need_deferred_cleanup = need_deferred_cleanup || c->wdt.enabled; #endif diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index ae2ad7364..378c4fd05 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c @@ -215,7 +215,7 @@ int nvgpu_tsg_unbind_channel_common(struct nvgpu_tsg *tsg, g->ops.channel.disable(ch); nvgpu_rwsem_up_write(&tsg->ch_list_lock); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER if (ch->mmu_debug_mode_enabled) { err = nvgpu_tsg_set_mmu_debug_mode(tsg, ch, false); if (err != 0) { @@ -300,7 +300,7 @@ static void nvgpu_tsg_destroy(struct gk20a *g, struct nvgpu_tsg *tsg) nvgpu_mutex_destroy(&tsg->event_id_list_lock); } -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL /* force reset tsg that the channel is bound to */ int nvgpu_tsg_force_reset_ch(struct nvgpu_channel *ch, u32 err_code, bool verbose) @@ -521,7 +521,7 @@ bool nvgpu_tsg_check_ctxsw_timeout(struct nvgpu_tsg *tsg, return recover; } -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING int nvgpu_tsg_set_interleave(struct nvgpu_tsg *tsg, u32 level) { struct gk20a *g = tsg->g; @@ -863,7 +863,7 @@ void nvgpu_tsg_reset_faulted_eng_pbdma(struct gk20a *g, struct nvgpu_tsg *tsg, nvgpu_rwsem_up_read(&tsg->ch_list_lock); } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER int nvgpu_tsg_set_mmu_debug_mode(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch, bool enable) { diff --git a/drivers/gpu/nvgpu/common/fifo/userd.c b/drivers/gpu/nvgpu/common/fifo/userd.c index fb6fcf199..2ff3df8aa 100644 --- a/drivers/gpu/nvgpu/common/fifo/userd.c +++ b/drivers/gpu/nvgpu/common/fifo/userd.c @@ -31,7 +31,7 @@ #include #include -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD int nvgpu_userd_init_slabs(struct gk20a *g) { struct nvgpu_fifo *f = &g->fifo; @@ -76,7 +76,7 @@ void nvgpu_userd_free_slabs(struct gk20a *g) int nvgpu_userd_init_channel(struct gk20a *g, struct nvgpu_channel *c) { -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD struct nvgpu_fifo *f = &g->fifo; struct nvgpu_mem *mem; u32 slab = c->chid / f->num_channels_per_slab; @@ -124,7 +124,7 @@ done: int nvgpu_userd_setup_sw(struct gk20a *g) { -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD struct nvgpu_fifo *f = &g->fifo; int err; u32 size, num_pages; @@ -159,7 +159,7 @@ clean_up: void nvgpu_userd_cleanup_sw(struct gk20a *g) { -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD struct nvgpu_fifo *f = &g->fifo; if (f->userd_gpu_va != 0ULL) { diff --git a/drivers/gpu/nvgpu/common/gr/ctx.c b/drivers/gpu/nvgpu/common/gr/ctx.c index 9ba39e049..ab9c29081 100644 --- a/drivers/gpu/nvgpu/common/gr/ctx.c +++ b/drivers/gpu/nvgpu/common/gr/ctx.c @@ -353,7 +353,7 @@ int nvgpu_gr_ctx_map_global_ctx_buffers(struct gk20a *g, g_bfr_index = &gr_ctx->global_ctx_buffer_index[0]; /* Circular Buffer */ -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR if (vpr && nvgpu_gr_global_ctx_buffer_ready(global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR)) { gpu_va = nvgpu_gr_global_ctx_buffer_map(global_ctx_buffer, @@ -366,7 +366,7 @@ int nvgpu_gr_ctx_map_global_ctx_buffers(struct gk20a *g, NVGPU_GR_GLOBAL_CTX_CIRCULAR, vm, NVGPU_VM_MAP_CACHEABLE, true); g_bfr_index[NVGPU_GR_CTX_CIRCULAR_VA] = NVGPU_GR_GLOBAL_CTX_CIRCULAR; -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR } #endif if (gpu_va == 0ULL) { @@ -376,7 +376,7 @@ int nvgpu_gr_ctx_map_global_ctx_buffers(struct gk20a *g, g_bfr_va[NVGPU_GR_CTX_CIRCULAR_VA] = gpu_va; /* Attribute Buffer */ -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR if (vpr && nvgpu_gr_global_ctx_buffer_ready(global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_ATTRIBUTE_VPR)) { gpu_va = nvgpu_gr_global_ctx_buffer_map(global_ctx_buffer, @@ -389,7 +389,7 @@ int nvgpu_gr_ctx_map_global_ctx_buffers(struct gk20a *g, NVGPU_GR_GLOBAL_CTX_ATTRIBUTE, vm, NVGPU_VM_MAP_CACHEABLE, false); g_bfr_index[NVGPU_GR_CTX_ATTRIBUTE_VA] = NVGPU_GR_GLOBAL_CTX_ATTRIBUTE; -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR } #endif if (gpu_va == 0ULL) { @@ -399,7 +399,7 @@ int nvgpu_gr_ctx_map_global_ctx_buffers(struct gk20a *g, g_bfr_va[NVGPU_GR_CTX_ATTRIBUTE_VA] = gpu_va; /* Page Pool */ -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR if (vpr && nvgpu_gr_global_ctx_buffer_ready(global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_PAGEPOOL_VPR)) { gpu_va = nvgpu_gr_global_ctx_buffer_map(global_ctx_buffer, @@ -412,7 +412,7 @@ int nvgpu_gr_ctx_map_global_ctx_buffers(struct gk20a *g, NVGPU_GR_GLOBAL_CTX_PAGEPOOL, vm, NVGPU_VM_MAP_CACHEABLE, true); g_bfr_index[NVGPU_GR_CTX_PAGEPOOL_VA] = NVGPU_GR_GLOBAL_CTX_PAGEPOOL; -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR } #endif if (gpu_va == 0ULL) { @@ -432,7 +432,7 @@ int nvgpu_gr_ctx_map_global_ctx_buffers(struct gk20a *g, g_bfr_va[NVGPU_GR_CTX_PRIV_ACCESS_MAP_VA] = gpu_va; g_bfr_index[NVGPU_GR_CTX_PRIV_ACCESS_MAP_VA] = NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP; -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE /* FECS trace buffer */ if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_VA)) { gpu_va = nvgpu_gr_global_ctx_buffer_map(global_ctx_buffer, @@ -704,7 +704,7 @@ u32 nvgpu_gr_ctx_get_ctx_id(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx) return gr_ctx->ctx_id; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void nvgpu_gr_ctx_set_zcull_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, u32 mode, u64 gpu_va) { @@ -969,7 +969,7 @@ u32 nvgpu_gr_ctx_read_ctx_id(struct nvgpu_gr_ctx *gr_ctx) return gr_ctx->ctx_id; } -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING void nvgpu_gr_ctx_set_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx, bool boost) { gr_ctx->boosted_ctx = boost; diff --git a/drivers/gpu/nvgpu/common/gr/fs_state.c b/drivers/gpu/nvgpu/common/gr/fs_state.c index d7c01b429..b0649a0fb 100644 --- a/drivers/gpu/nvgpu/common/gr/fs_state.c +++ b/drivers/gpu/nvgpu/common/gr/fs_state.c @@ -119,7 +119,7 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config) g->ops.gr.init.pd_tpc_per_gpc(g, config); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS /* gr__setup_pd_mapping */ g->ops.gr.init.rop_mapping(g, config); #endif diff --git a/drivers/gpu/nvgpu/common/gr/global_ctx.c b/drivers/gpu/nvgpu/common/gr/global_ctx.c index f9739e110..c52f5f62e 100644 --- a/drivers/gpu/nvgpu/common/gr/global_ctx.c +++ b/drivers/gpu/nvgpu/common/gr/global_ctx.c @@ -103,7 +103,7 @@ static int nvgpu_gr_global_ctx_buffer_alloc_sys(struct gk20a *g, return err; } -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR static int nvgpu_gr_global_ctx_buffer_alloc_vpr(struct gk20a *g, struct nvgpu_gr_global_ctx_buffer_desc *desc, u32 index) @@ -137,7 +137,7 @@ int nvgpu_gr_global_ctx_buffer_alloc(struct gk20a *g, if (desc[NVGPU_GR_GLOBAL_CTX_CIRCULAR].size == 0U || desc[NVGPU_GR_GLOBAL_CTX_PAGEPOOL].size == 0U || desc[NVGPU_GR_GLOBAL_CTX_ATTRIBUTE].size == 0U || -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR desc[NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR].size == 0U || desc[NVGPU_GR_GLOBAL_CTX_PAGEPOOL_VPR].size == 0U || desc[NVGPU_GR_GLOBAL_CTX_ATTRIBUTE_VPR].size == 0U || @@ -185,7 +185,7 @@ int nvgpu_gr_global_ctx_buffer_alloc(struct gk20a *g, goto clean_up; } } -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR err = nvgpu_gr_global_ctx_buffer_alloc_vpr(g, desc, NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR); if (err != 0) { diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 8fe8dad67..66b759af0 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -28,7 +28,7 @@ #include #include #include -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include #include #endif @@ -57,7 +57,7 @@ static int gr_alloc_global_ctx_buffers(struct gk20a *g) nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_CIRCULAR, size); -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR, size); #endif @@ -67,7 +67,7 @@ static int gr_alloc_global_ctx_buffers(struct gk20a *g) nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_PAGEPOOL, size); -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_PAGEPOOL_VPR, size); #endif @@ -78,7 +78,7 @@ static int gr_alloc_global_ctx_buffers(struct gk20a *g) nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_ATTRIBUTE, size); -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_ATTRIBUTE_VPR, size); #endif @@ -88,7 +88,7 @@ static int gr_alloc_global_ctx_buffers(struct gk20a *g) nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP, size); -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE size = nvgpu_gr_fecs_trace_buffer_size(g); nvgpu_log_info(g, "fecs_trace_buffer_size : %d", size); @@ -192,12 +192,12 @@ static int gr_init_setup_hw(struct gk20a *g) /* load gr floorsweeping registers */ g->ops.gr.init.pes_vsc_stream(g); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS err = nvgpu_gr_zcull_init_hw(g, gr->zcull, gr->config); if (err != 0) { goto out; } -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ if (g->ops.priv_ring.set_ppriv_timeout_settings != NULL) { g->ops.priv_ring.set_ppriv_timeout_settings(g); @@ -232,12 +232,12 @@ static int gr_init_setup_hw(struct gk20a *g) /* reset and enable exceptions */ g->ops.gr.intr.enable_exceptions(g, gr->config, true); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS err = nvgpu_gr_zbc_load_table(g, gr->zbc); if (err != 0) { goto out; } -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ /* * Disable both surface and LG coalesce. @@ -284,7 +284,7 @@ static void gr_remove_support(struct gk20a *g) nvgpu_netlist_deinit_ctx_vars(g); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_gr_hwpm_map_deinit(g, gr->hwpm_map); #endif @@ -294,10 +294,10 @@ static void gr_remove_support(struct gk20a *g) nvgpu_gr_intr_remove_support(g, gr->intr); gr->intr = NULL; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_gr_zbc_deinit(g, gr->zbc); nvgpu_gr_zcull_deinit(g, gr->zcull); -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ nvgpu_gr_obj_ctx_deinit(g, gr->golden_image); } @@ -404,7 +404,7 @@ static int gr_init_setup_sw(struct gk20a *g) goto clean_up; } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER err = nvgpu_gr_hwpm_map_init(g, &g->gr->hwpm_map, nvgpu_gr_falcon_get_pm_ctxsw_image_size(g->gr->falcon)); if (err != 0) { @@ -413,7 +413,7 @@ static int gr_init_setup_sw(struct gk20a *g) } #endif -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS err = nvgpu_gr_config_init_map_tiles(g, gr->config); if (err != 0) { goto clean_up; @@ -425,7 +425,7 @@ static int gr_init_setup_sw(struct gk20a *g) if (err != 0) { goto clean_up; } -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ gr->gr_ctx_desc = nvgpu_gr_ctx_desc_alloc(g); if (gr->gr_ctx_desc == NULL) { @@ -450,12 +450,12 @@ static int gr_init_setup_sw(struct gk20a *g) goto clean_up; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS err = nvgpu_gr_zbc_init(g, &gr->zbc); if (err != 0) { goto clean_up; } -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ gr->intr = nvgpu_gr_intr_init_support(g); if (gr->intr == NULL) { @@ -733,7 +733,7 @@ int nvgpu_gr_disable_ctxsw(struct gk20a *g) gr->ctxsw_disable_count++; if (gr->ctxsw_disable_count == 1) { -#ifdef NVGPU_FEATURE_POWER_PG +#ifdef CONFIG_NVGPU_POWER_PG err = nvgpu_pg_elpg_disable(g); if (err != 0) { nvgpu_err(g, @@ -780,7 +780,7 @@ int nvgpu_gr_enable_ctxsw(struct gk20a *g) if (err != 0) { nvgpu_err(g, "failed to start fecs ctxsw"); } -#ifdef NVGPU_FEATURE_POWER_PG +#ifdef CONFIG_NVGPU_POWER_PG else { if (nvgpu_pg_elpg_enable(g) != 0) { nvgpu_err(g, diff --git a/drivers/gpu/nvgpu/common/gr/gr_config.c b/drivers/gpu/nvgpu/common/gr/gr_config.c index 136f77781..658caee6f 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_config.c +++ b/drivers/gpu/nvgpu/common/gr/gr_config.c @@ -102,7 +102,7 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g) temp2 = nvgpu_safe_mult_u64((size_t)config->max_gpc_count, sizeof(u32)); config->gpc_tpc_count = nvgpu_kzalloc(g, gpc_size); config->gpc_tpc_mask = nvgpu_kzalloc(g, temp2); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS config->max_zcull_per_gpc_count = nvgpu_get_litter_value(g, GPU_LIT_NUM_ZCULL_BANKS); @@ -117,7 +117,7 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g) config->gpc_skip_mask = nvgpu_kzalloc(g, temp3); if ((config->gpc_tpc_count == NULL) || (config->gpc_tpc_mask == NULL) || -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS (config->gpc_zcb_count == NULL) || #endif (config->gpc_ppc_count == NULL) || @@ -143,7 +143,7 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g) config->ppc_count = 0; config->tpc_count = 0; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS config->zcb_count = 0; #endif for (gpc_index = 0; gpc_index < config->gpc_count; gpc_index++) { @@ -153,7 +153,7 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g) config->tpc_count = nvgpu_safe_add_u32(config->tpc_count, config->gpc_tpc_count[gpc_index]); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS config->gpc_zcb_count[gpc_index] = g->ops.gr.config.get_zcull_count_in_gpc(g, config, gpc_index); @@ -220,7 +220,7 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g) nvgpu_log_info(g, "max_gpc_count: %d", config->max_gpc_count); nvgpu_log_info(g, "max_tpc_per_gpc_count: %d", config->max_tpc_per_gpc_count); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_log_info(g, "max_zcull_per_gpc_count: %d", config->max_zcull_per_gpc_count); #endif nvgpu_log_info(g, "max_tpc_count: %d", config->max_tpc_count); @@ -233,7 +233,7 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g) nvgpu_log_info(g, "gpc_tpc_count[%d] : %d", gpc_index, config->gpc_tpc_count[gpc_index]); } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS for (gpc_index = 0; gpc_index < config->gpc_count; gpc_index++) { nvgpu_log_info(g, "gpc_zcb_count[%d] : %d", gpc_index, config->gpc_zcb_count[gpc_index]); @@ -274,7 +274,7 @@ clean_up: return NULL; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS static u32 prime_set[18] = { 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61 }; @@ -519,7 +519,7 @@ void nvgpu_gr_config_deinit(struct gk20a *g, struct nvgpu_gr_config *config) nvgpu_kfree(g, config->gpc_ppc_count); nvgpu_kfree(g, config->gpc_skip_mask); nvgpu_kfree(g, config->gpc_tpc_mask); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_kfree(g, config->gpc_zcb_count); nvgpu_kfree(g, config->map_tiles); #endif diff --git a/drivers/gpu/nvgpu/common/gr/gr_config_priv.h b/drivers/gpu/nvgpu/common/gr/gr_config_priv.h index f66415880..898ea59e3 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_config_priv.h +++ b/drivers/gpu/nvgpu/common/gr/gr_config_priv.h @@ -58,7 +58,7 @@ struct nvgpu_gr_config { u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC]; u32 *gpc_skip_mask; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS u32 max_zcull_per_gpc_count; u32 zcb_count; u32 *gpc_zcb_count; diff --git a/drivers/gpu/nvgpu/common/gr/gr_falcon.c b/drivers/gpu/nvgpu/common/gr/gr_falcon.c index 4157613df..05b425399 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_falcon.c +++ b/drivers/gpu/nvgpu/common/gr/gr_falcon.c @@ -30,11 +30,11 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #include #endif -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU #include #endif #include @@ -74,7 +74,7 @@ void nvgpu_gr_falcon_remove_support(struct gk20a *g, int nvgpu_gr_falcon_bind_fecs_elpg(struct gk20a *g) { -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU struct nvgpu_pmu *pmu = g->pmu; struct mm_gk20a *mm = &g->mm; struct vm_gk20a *vm = mm->pmu.vm; @@ -188,7 +188,7 @@ u32 nvgpu_gr_falcon_get_preempt_image_size(struct nvgpu_gr_falcon *falcon) return falcon->sizes.preempt_image_size; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS u32 nvgpu_gr_falcon_get_zcull_image_size(struct nvgpu_gr_falcon *falcon) { return falcon->sizes.zcull_image_size; @@ -551,14 +551,14 @@ int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g, /* this must be recovery so bootstrap fecs and gpccs */ if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { nvgpu_gr_falcon_load_gpccs_with_bootloader(g, falcon); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU err = nvgpu_pmu_lsfm_bootstrap_ls_falcon(g, g->pmu, g->pmu->lsfm, BIT32(FALCON_ID_FECS)); #endif } else { /* bind WPR VA inst block */ nvgpu_gr_falcon_bind_instblk(g, falcon); -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2, FALCON_ID_FECS); @@ -566,7 +566,7 @@ int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g, &g->sec2, FALCON_ID_GPCCS); } else #endif -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (g->support_ls_pmu) { err = nvgpu_pmu_lsfm_bootstrap_ls_falcon(g, g->pmu, g->pmu->lsfm, @@ -604,7 +604,7 @@ int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g, falcon_id_mask |= BIT8(FALCON_ID_GPCCS); } -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2, FALCON_ID_FECS); @@ -612,7 +612,7 @@ int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g, &g->sec2, FALCON_ID_GPCCS); } else #endif -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (g->support_ls_pmu) { err = nvgpu_pmu_lsfm_bootstrap_ls_falcon(g, g->pmu, g->pmu->lsfm, diff --git a/drivers/gpu/nvgpu/common/gr/gr_intr.c b/drivers/gpu/nvgpu/common/gr/gr_intr.c index 4eb5578cd..b6802e1b4 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_intr.c +++ b/drivers/gpu/nvgpu/common/gr/gr_intr.c @@ -28,7 +28,7 @@ #include #include #include -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) #include #endif @@ -132,7 +132,7 @@ static int gr_intr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, return ret; } -#if defined(NVGPU_FEATURE_CHANNEL_TSG_CONTROL) && defined(NVGPU_DEBUGGER) +#if defined(CONFIG_NVGPU_CHANNEL_TSG_CONTROL) && defined(CONFIG_NVGPU_DEBUGGER) static void gr_intr_post_bpt_events(struct gk20a *g, struct nvgpu_tsg *tsg, u32 global_esr) { @@ -351,7 +351,7 @@ int nvgpu_gr_intr_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, nvgpu_gr_tpc_offset(g, tpc)); u32 global_esr, warp_esr, global_mask; u64 hww_warp_esr_pc = 0; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER bool sm_debugger_attached; bool do_warp_sync = false, early_exit = false, ignore_debugger = false; bool disable_sm_exceptions = true; @@ -384,7 +384,7 @@ int nvgpu_gr_intr_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, nvgpu_safe_cast_u32_to_s32( g->ops.gr.intr.record_sm_error_state(g, gpc, tpc, sm, fault_ch))); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER sm_debugger_attached = g->ops.gr.sm_debugger_attached(g); if (!sm_debugger_attached) { nvgpu_err(g, "sm hww global 0x%08x warp 0x%08x", @@ -495,7 +495,7 @@ int nvgpu_gr_intr_handle_fecs_error(struct gk20a *g, struct nvgpu_channel *ch, } else if (fecs_host_intr.ctxsw_intr0 != 0U) { mailbox_value = g->ops.gr.falcon.read_fecs_ctxsw_mailbox(g, mailbox_id); -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE if (mailbox_value == g->ops.gr.fecs_trace.get_buffer_full_mailbox_val()) { nvgpu_info(g, "ctxsw intr0 set by ucode, " @@ -632,7 +632,7 @@ void nvgpu_gr_intr_handle_notify_pending(struct gk20a *g, nvgpu_log_fn(g, " "); -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) nvgpu_cyclestats_exec(g, ch, isr_data->data_lo); #endif @@ -656,7 +656,7 @@ void nvgpu_gr_intr_handle_semaphore_pending(struct gk20a *g, if (tsg != NULL) { int err; -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL g->ops.tsg.post_event_id(tsg, NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN); #endif @@ -811,7 +811,7 @@ int nvgpu_gr_intr_stall_isr(struct gk20a *g) need_reset = true; } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER /* signal clients waiting on an event */ if (g->ops.gr.sm_debugger_attached(g) && post_event && (fault_ch != NULL)) { @@ -853,7 +853,7 @@ int nvgpu_gr_intr_stall_isr(struct gk20a *g) /* Enable fifo access */ g->ops.gr.init.fifo_access(g, true); -#if defined(NVGPU_FEATURE_CHANNEL_TSG_CONTROL) && defined(NVGPU_DEBUGGER) +#if defined(CONFIG_NVGPU_CHANNEL_TSG_CONTROL) && defined(CONFIG_NVGPU_DEBUGGER) /* Posting of BPT events should be the last thing in this function */ if ((global_esr != 0U) && (tsg != NULL) && (need_reset == false)) { gr_intr_post_bpt_events(g, tsg, global_esr); diff --git a/drivers/gpu/nvgpu/common/gr/gr_priv.h b/drivers/gpu/nvgpu/common/gr/gr_priv.h index 2833b0198..f3c3deb23 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_priv.h +++ b/drivers/gpu/nvgpu/common/gr/gr_priv.h @@ -30,7 +30,7 @@ struct nvgpu_gr_ctx_desc; struct nvgpu_gr_global_ctx_buffer_desc; struct nvgpu_gr_obj_ctx_golden_image; struct nvgpu_gr_config; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_gr_zbc; struct nvgpu_gr_zcull; #endif @@ -51,11 +51,11 @@ struct nvgpu_gr { struct nvgpu_gr_config *config; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER struct nvgpu_gr_hwpm_map *hwpm_map; #endif -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_gr_zcull *zcull; struct nvgpu_gr_zbc *zbc; diff --git a/drivers/gpu/nvgpu/common/gr/gr_setup.c b/drivers/gpu/nvgpu/common/gr/gr_setup.c index 149e85411..5a344f798 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_setup.c +++ b/drivers/gpu/nvgpu/common/gr/gr_setup.c @@ -25,7 +25,7 @@ #include #include #include -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include #endif #include @@ -34,7 +34,7 @@ #include "gr_priv.h" -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS static int nvgpu_gr_setup_zcull(struct gk20a *g, struct nvgpu_channel *c, struct nvgpu_gr_ctx *gr_ctx) { @@ -166,7 +166,7 @@ int nvgpu_gr_setup_alloc_obj_ctx(struct nvgpu_channel *c, u32 class_num, c->subctx, nvgpu_gr_ctx_get_ctx_mem(gr_ctx)->gpu_va); } -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE if (g->ops.gr.fecs_trace.bind_channel && !c->vpr) { err = g->ops.gr.fecs_trace.bind_channel(g, &c->inst_block, c->subctx, gr_ctx, tsg->tgid, 0); @@ -222,7 +222,7 @@ void nvgpu_gr_setup_free_subctx(struct nvgpu_channel *c) } } -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL int nvgpu_gr_setup_set_preemption_mode(struct nvgpu_channel *ch, u32 graphics_preempt_mode, u32 compute_preempt_mode) diff --git a/drivers/gpu/nvgpu/common/gr/gr_utils.c b/drivers/gpu/nvgpu/common/gr/gr_utils.c index 0fbffc9f8..62dc8dc48 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_utils.c +++ b/drivers/gpu/nvgpu/common/gr/gr_utils.c @@ -49,7 +49,7 @@ void nvgpu_gr_reset_golden_image_ptr(struct gk20a *g) g->gr->golden_image = NULL; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_gr_zcull *nvgpu_gr_get_zcull_ptr(struct gk20a *g) { return g->gr->zcull; @@ -66,7 +66,7 @@ struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g) return g->gr->config; } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER struct nvgpu_gr_hwpm_map *nvgpu_gr_get_hwpm_map_ptr(struct gk20a *g) { return g->gr->hwpm_map; @@ -78,7 +78,7 @@ struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g) return g->gr->intr; } -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE struct nvgpu_gr_global_ctx_buffer_desc *nvgpu_gr_get_global_ctx_buffer_ptr( struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c index 08d34ea7b..7d6369132 100644 --- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c +++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c @@ -24,7 +24,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif #include @@ -507,7 +507,7 @@ restore_fe_go_idle: goto clean_up; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS err = nvgpu_gr_ctx_init_zcull(g, gr_ctx); if (err != 0) { goto clean_up; @@ -531,7 +531,7 @@ restore_fe_go_idle: } golden_image->ready = true; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU nvgpu_pmu_set_golden_image_initialized(g, true); #endif g->ops.gr.falcon.set_current_ctx_invalid(g); @@ -726,7 +726,7 @@ void nvgpu_gr_obj_ctx_deinit(struct gk20a *g, golden_image->local_golden_image); golden_image->local_golden_image = NULL; } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU nvgpu_pmu_set_golden_image_initialized(g, false); #endif golden_image->ready = false; diff --git a/drivers/gpu/nvgpu/common/gr/subctx.c b/drivers/gpu/nvgpu/common/gr/subctx.c index 4d877f21f..ac29ac41c 100644 --- a/drivers/gpu/nvgpu/common/gr/subctx.c +++ b/drivers/gpu/nvgpu/common/gr/subctx.c @@ -104,7 +104,7 @@ void nvgpu_gr_subctx_load_ctx_header(struct gk20a *g, g->ops.gr.ctxsw_prog.set_pm_ptr(g, ctxheader, nvgpu_gr_ctx_get_pm_ctx_mem(gr_ctx)->gpu_va); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS g->ops.gr.ctxsw_prog.set_zcull_ptr(g, ctxheader, nvgpu_gr_ctx_get_zcull_ctx_va(gr_ctx)); #endif @@ -114,7 +114,7 @@ void nvgpu_gr_subctx_load_ctx_header(struct gk20a *g, g->ops.gr.ctxsw_prog.set_type_per_veid_header(g, ctxheader); } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void nvgpu_gr_subctx_zcull_setup(struct gk20a *g, struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx) { diff --git a/drivers/gpu/nvgpu/common/gr/zbc.c b/drivers/gpu/nvgpu/common/gr/zbc.c index eee352dba..b3b2cdc55 100644 --- a/drivers/gpu/nvgpu/common/gr/zbc.c +++ b/drivers/gpu/nvgpu/common/gr/zbc.c @@ -25,7 +25,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif @@ -39,7 +39,7 @@ static int nvgpu_gr_zbc_add(struct gk20a *g, struct nvgpu_gr_zbc *zbc, u32 i; int ret = -ENOSPC; bool added = false; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU u32 entries; #endif @@ -134,7 +134,7 @@ static int nvgpu_gr_zbc_add(struct gk20a *g, struct nvgpu_gr_zbc *zbc, goto err_mutex; } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (!added && ret == 0) { /* update zbc for elpg only when new entry is added */ entries = max(zbc->max_used_color_index, diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 63a89dd28..8d19a5a35 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -48,7 +48,7 @@ #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif @@ -100,14 +100,14 @@ int gk20a_prepare_poweroff(struct gk20a *g) } } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU /* disable elpg before gr or fifo suspend */ if (g->support_ls_pmu) { ret = nvgpu_pmu_destroy(g, g->pmu); } #endif -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { tmp_ret = nvgpu_sec2_destroy(g); if ((tmp_ret != 0) && (ret == 0)) { @@ -134,11 +134,11 @@ int gk20a_prepare_poweroff(struct gk20a *g) nvgpu_falcon_sw_free(g, FALCON_ID_SEC2); nvgpu_falcon_sw_free(g, FALCON_ID_PMU); -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE nvgpu_ce_suspend(g); #endif -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU /* deinit the bios */ nvgpu_bios_sw_deinit(g, g->bios); #endif @@ -197,7 +197,7 @@ int gk20a_finalize_poweron(struct gk20a *g) goto exit; } -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU err = nvgpu_falcon_sw_init(g, FALCON_ID_SEC2); if (err != 0) { nvgpu_err(g, "failed to sw init FALCON_ID_SEC2"); @@ -208,7 +208,7 @@ int gk20a_finalize_poweron(struct gk20a *g) err = nvgpu_falcon_sw_init(g, FALCON_ID_NVDEC); if (err != 0) { nvgpu_err(g, "failed to sw init FALCON_ID_NVDEC"); -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU goto done_sec2; #else goto done_pmu; @@ -231,7 +231,7 @@ int gk20a_finalize_poweron(struct gk20a *g) goto done; } -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { err = nvgpu_init_sec2_setup_sw(g, &g->sec2); if (err != 0) { @@ -249,7 +249,7 @@ int gk20a_finalize_poweron(struct gk20a *g) } } -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU err = nvgpu_bios_sw_init(g, &g->bios); if (err != 0) { nvgpu_err(g, "BIOS SW init failed %d", err); @@ -350,7 +350,7 @@ int gk20a_finalize_poweron(struct gk20a *g) nvgpu_mutex_acquire(&g->tpc_pg_lock); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER if (g->can_tpc_powergate) { if (g->ops.gr.powergate_tpc != NULL) { g->ops.gr.powergate_tpc(g); @@ -382,7 +382,7 @@ int gk20a_finalize_poweron(struct gk20a *g) } } -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { err = nvgpu_init_sec2_support(g); if (err != 0) { @@ -393,7 +393,7 @@ int gk20a_finalize_poweron(struct gk20a *g) } #endif -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU err = nvgpu_pmu_init(g, g->pmu); if (err != 0) { nvgpu_err(g, "failed to init gk20a pmu"); @@ -425,7 +425,7 @@ int gk20a_finalize_poweron(struct gk20a *g) nvgpu_mutex_release(&g->tpc_pg_lock); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { err = nvgpu_pmu_pstate_sw_setup(g); if (err != 0) { @@ -475,7 +475,7 @@ int gk20a_finalize_poweron(struct gk20a *g) /* Restore the debug setting */ g->ops.fb.set_debug_mode(g, g->mmu_debug_ctrl); -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE err = nvgpu_ce_init_support(g); if (err != 0) { nvgpu_err(g, "failed to init ce"); @@ -529,7 +529,7 @@ done_gsp: nvgpu_falcon_sw_free(g, FALCON_ID_GSPLITE); done_nvdec: nvgpu_falcon_sw_free(g, FALCON_ID_NVDEC); -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU done_sec2: nvgpu_falcon_sw_free(g, FALCON_ID_SEC2); #endif @@ -630,7 +630,7 @@ void gk20a_init_gpu_characteristics(struct gk20a *g) g->ops.gr.init.detect_sm_arch(g); -#ifdef CONFIG_GK20A_CYCLE_STATS +#ifdef CONFIG_NVGPU_CYCLESTATS if (g->ops.gr.init_cyclestats != NULL) { g->ops.gr.init_cyclestats(g); } @@ -652,7 +652,7 @@ static void gk20a_free_cb(struct nvgpu_ref *refcount) nvgpu_log(g, gpu_dbg_shutdown, "Freeing GK20A struct!"); -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE nvgpu_ce_destroy(g); #endif diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c index de05dd1e6..0c3a1d146 100644 --- a/drivers/gpu/nvgpu/common/mm/mm.c +++ b/drivers/gpu/nvgpu/common/mm/mm.c @@ -109,7 +109,7 @@ static int nvgpu_alloc_sysmem_flush(struct gk20a *g) return nvgpu_dma_alloc_sys(g, SZ_4K, &g->mm.sysmem_flush); } -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE static void nvgpu_remove_mm_ce_support(struct mm_gk20a *mm) { struct gk20a *g = gk20a_from_mm(mm); @@ -292,7 +292,7 @@ static int nvgpu_init_mmu_debug(struct mm_gk20a *mm) return -ENOMEM; } -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE void nvgpu_init_mm_ce_context(struct gk20a *g) { #if defined(CONFIG_GK20A_VIDMEM) @@ -509,7 +509,7 @@ static int nvgpu_init_mm_setup_sw(struct gk20a *g) } mm->remove_support = nvgpu_remove_mm_support; -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE mm->remove_ce_support = nvgpu_remove_mm_ce_support; #endif diff --git a/drivers/gpu/nvgpu/common/mm/vidmem.c b/drivers/gpu/nvgpu/common/mm/vidmem.c index ce5d193b2..8ca95c445 100644 --- a/drivers/gpu/nvgpu/common/mm/vidmem.c +++ b/drivers/gpu/nvgpu/common/mm/vidmem.c @@ -103,7 +103,7 @@ static int nvgpu_vidmem_do_clear_all(struct gk20a *g) vidmem_dbg(g, "Clearing all VIDMEM:"); -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE err = nvgpu_ce_execute_ops(g, mm->vidmem.ce_ctx_id, 0, @@ -462,7 +462,7 @@ int nvgpu_vidmem_clear(struct gk20a *g, struct nvgpu_mem *mem) nvgpu_fence_put(last_fence); } -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE err = nvgpu_ce_execute_ops(g, g->mm.vidmem.ce_ctx_id, 0, @@ -479,7 +479,7 @@ int nvgpu_vidmem_clear(struct gk20a *g, struct nvgpu_mem *mem) #endif if (err != 0) { -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE nvgpu_err(g, "Failed nvgpu_ce_execute_ops[%d]", err); #endif diff --git a/drivers/gpu/nvgpu/common/netlist/netlist.c b/drivers/gpu/nvgpu/common/netlist/netlist.c index e3875d6db..2de5fa371 100644 --- a/drivers/gpu/nvgpu/common/netlist/netlist.c +++ b/drivers/gpu/nvgpu/common/netlist/netlist.c @@ -267,7 +267,7 @@ static int nvgpu_netlist_init_ctx_vars_fw(struct gk20a *g) goto clean_up; } break; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS case NETLIST_REGIONID_CTXREG_ZCULL_GPC: nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ZCULL_GPC"); err = nvgpu_netlist_alloc_load_aiv_list(g, @@ -484,7 +484,7 @@ clean_up: nvgpu_kfree(g, netlist_vars->ctxsw_regs.sys.l); nvgpu_kfree(g, netlist_vars->ctxsw_regs.gpc.l); nvgpu_kfree(g, netlist_vars->ctxsw_regs.tpc.l); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_kfree(g, netlist_vars->ctxsw_regs.zcull_gpc.l); #endif nvgpu_kfree(g, netlist_vars->ctxsw_regs.ppc.l); @@ -556,7 +556,7 @@ void nvgpu_netlist_deinit_ctx_vars(struct gk20a *g) nvgpu_kfree(g, netlist_vars->ctxsw_regs.sys.l); nvgpu_kfree(g, netlist_vars->ctxsw_regs.gpc.l); nvgpu_kfree(g, netlist_vars->ctxsw_regs.tpc.l); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_kfree(g, netlist_vars->ctxsw_regs.zcull_gpc.l); #endif nvgpu_kfree(g, netlist_vars->ctxsw_regs.ppc.l); @@ -708,7 +708,7 @@ struct netlist_aiv_list *nvgpu_netlist_get_tpc_ctxsw_regs(struct gk20a *g) return &g->netlist_vars->ctxsw_regs.tpc; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct netlist_aiv_list *nvgpu_netlist_get_zcull_gpc_ctxsw_regs(struct gk20a *g) { return &g->netlist_vars->ctxsw_regs.zcull_gpc; diff --git a/drivers/gpu/nvgpu/common/netlist/netlist_priv.h b/drivers/gpu/nvgpu/common/netlist/netlist_priv.h index 4e731d90b..3f68bd245 100644 --- a/drivers/gpu/nvgpu/common/netlist/netlist_priv.h +++ b/drivers/gpu/nvgpu/common/netlist/netlist_priv.h @@ -109,7 +109,7 @@ struct nvgpu_netlist_vars { struct netlist_aiv_list sys; struct netlist_aiv_list gpc; struct netlist_aiv_list tpc; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct netlist_aiv_list zcull_gpc; #endif struct netlist_aiv_list ppc; diff --git a/drivers/gpu/nvgpu/common/nvlink/init/device_reginit.c b/drivers/gpu/nvgpu/common/nvlink/init/device_reginit.c index 131ded7ea..e541a3e02 100644 --- a/drivers/gpu/nvgpu/common/nvlink/init/device_reginit.c +++ b/drivers/gpu/nvgpu/common/nvlink/init/device_reginit.c @@ -23,7 +23,7 @@ #include #include -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK int nvgpu_nvlink_reg_init(struct gk20a *g) { int err; diff --git a/drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.c b/drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.c index 5b55e2191..9c3fce0ef 100644 --- a/drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.c +++ b/drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.c @@ -25,7 +25,7 @@ #include #include "device_reginit_gv100.h" -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK struct nvlink_reginit { u32 addr; u32 value; @@ -177,4 +177,4 @@ int gv100_nvlink_reg_init(struct gk20a *g) } return 0; } -#endif /* CONFIG_TEGRA_NVLINK */ +#endif /* CONFIG_NVGPU_NVLINK */ diff --git a/drivers/gpu/nvgpu/common/nvlink/intr_and_err_handling_gv100.c b/drivers/gpu/nvgpu/common/nvlink/intr_and_err_handling_gv100.c index 15b1594ad..ab3dae423 100644 --- a/drivers/gpu/nvgpu/common/nvlink/intr_and_err_handling_gv100.c +++ b/drivers/gpu/nvgpu/common/nvlink/intr_and_err_handling_gv100.c @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK #include #include @@ -508,4 +508,4 @@ void gv100_nvlink_isr(struct gk20a *g) return; } -#endif /* CONFIG_TEGRA_NVLINK */ +#endif /* CONFIG_NVGPU_NVLINK */ diff --git a/drivers/gpu/nvgpu/common/nvlink/link_mode_transitions.c b/drivers/gpu/nvgpu/common/nvlink/link_mode_transitions.c index a475a270f..c6bae9a92 100644 --- a/drivers/gpu/nvgpu/common/nvlink/link_mode_transitions.c +++ b/drivers/gpu/nvgpu/common/nvlink/link_mode_transitions.c @@ -24,7 +24,7 @@ #include #include -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK /* * WAR: use this function to find detault link, as only one is supported * on the library for now diff --git a/drivers/gpu/nvgpu/common/nvlink/minion.c b/drivers/gpu/nvgpu/common/nvlink/minion.c index a9e77938a..7a5c5421c 100644 --- a/drivers/gpu/nvgpu/common/nvlink/minion.c +++ b/drivers/gpu/nvgpu/common/nvlink/minion.c @@ -25,7 +25,7 @@ #include #include -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK /* Extract a WORD from the MINION ucode */ u32 nvgpu_nvlink_minion_extract_word(struct nvgpu_firmware *fw, u32 idx) diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink.c b/drivers/gpu/nvgpu/common/nvlink/nvlink.c index 155a60737..154bbf4d4 100644 --- a/drivers/gpu/nvgpu/common/nvlink/nvlink.c +++ b/drivers/gpu/nvgpu/common/nvlink/nvlink.c @@ -25,7 +25,7 @@ #include #include -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK int nvgpu_nvlink_speed_config(struct gk20a *g) { @@ -82,7 +82,7 @@ int nvgpu_nvlink_dev_shutdown(struct gk20a *g) int nvgpu_nvlink_remove(struct gk20a *g) { -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK int err; if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK)) { diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c index e5c6578cf..030759556 100644 --- a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK #include #include @@ -915,4 +915,4 @@ int gv100_nvlink_speed_config(struct gk20a *g) return 0; } -#endif /* CONFIG_TEGRA_NVLINK */ +#endif /* CONFIG_NVGPU_NVLINK */ diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.c b/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.c index 8d5897aab..8304e1cdc 100644 --- a/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.c +++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.c @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK #include #include @@ -122,4 +122,4 @@ int tu104_nvlink_speed_config(struct gk20a *g) return ret; } -#endif /* CONFIG_TEGRA_NVLINK */ +#endif /* CONFIG_NVGPU_NVLINK */ diff --git a/drivers/gpu/nvgpu/common/nvlink/probe.c b/drivers/gpu/nvgpu/common/nvlink/probe.c index f46558bd7..4d0ae2e44 100644 --- a/drivers/gpu/nvgpu/common/nvlink/probe.c +++ b/drivers/gpu/nvgpu/common/nvlink/probe.c @@ -26,7 +26,7 @@ int nvgpu_nvlink_probe(struct gk20a *g) { -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK int err; err = nvgpu_nvlink_setup_ndev(g); diff --git a/drivers/gpu/nvgpu/common/pmu/lsfm/lsfm.c b/drivers/gpu/nvgpu/common/pmu/lsfm/lsfm.c index 9d78fea74..9a531c826 100644 --- a/drivers/gpu/nvgpu/common/pmu/lsfm/lsfm.c +++ b/drivers/gpu/nvgpu/common/pmu/lsfm/lsfm.c @@ -29,7 +29,7 @@ #include "lsfm_sw_gm20b.h" #include "lsfm_sw_gp10b.h" -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU #include "lsfm_sw_gv100.h" #include "lsfm_sw_tu104.h" #endif @@ -153,7 +153,7 @@ int nvgpu_pmu_lsfm_init(struct gk20a *g, struct nvgpu_pmu_lsfm **lsfm) case NVGPU_GPUID_GV11B: nvgpu_gp10b_lsfm_sw_init(g, *lsfm); break; -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU case NVGPU_GPUID_GV100: nvgpu_gv100_lsfm_sw_init(g, *lsfm); break; diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index 264423ecd..69df3b962 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c @@ -30,7 +30,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #include #include @@ -43,11 +43,11 @@ #include #endif -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU #include #endif -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU /* PMU locks used to sync with PMU-RTOS */ int nvgpu_pmu_lock_acquire(struct gk20a *g, struct nvgpu_pmu *pmu, u32 id, u32 *token) @@ -227,7 +227,7 @@ int nvgpu_pmu_init(struct gk20a *g, struct nvgpu_pmu *pmu) } if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { /* Reset PMU engine */ err = nvgpu_falcon_reset(g->pmu->flcn); @@ -323,7 +323,7 @@ int nvgpu_pmu_early_init(struct gk20a *g, struct nvgpu_pmu **pmu_p) nvgpu_set_enabled(g, NVGPU_PMU_PERFMON, false); goto exit; } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU nvgpu_mutex_init(&pmu->isr_mutex); /* Allocate memory for pmu_perfmon */ @@ -380,7 +380,7 @@ exit: void nvgpu_pmu_remove_support(struct gk20a *g, struct nvgpu_pmu *pmu) { if(pmu != NULL) { -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (pmu->remove_support != NULL) { pmu->remove_support(g->pmu); } @@ -440,7 +440,7 @@ static int pmu_enable(struct nvgpu_pmu *pmu, bool enable) if (!enable) { if (!g->ops.pmu.is_engine_in_reset(g)) { -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU g->ops.pmu.pmu_enable_irq(pmu, false); #endif pmu_enable_hw(pmu, false); diff --git a/drivers/gpu/nvgpu/common/power_features/pg/pg.c b/drivers/gpu/nvgpu/common/power_features/pg/pg.c index aa232100e..dd1f68fda 100644 --- a/drivers/gpu/nvgpu/common/power_features/pg/pg.c +++ b/drivers/gpu/nvgpu/common/power_features/pg/pg.c @@ -21,7 +21,7 @@ */ #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #include #endif @@ -42,7 +42,7 @@ bool nvgpu_pg_elpg_is_enabled(struct gk20a *g) int nvgpu_pg_elpg_enable(struct gk20a *g) { int err = 0; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU nvgpu_log_fn(g, " "); if (!g->can_elpg) { @@ -63,7 +63,7 @@ int nvgpu_pg_elpg_enable(struct gk20a *g) int nvgpu_pg_elpg_disable(struct gk20a *g) { int err = 0; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU nvgpu_log_fn(g, " "); if (!g->can_elpg) { @@ -109,7 +109,7 @@ int nvgpu_pg_elpg_set_elpg_enabled(struct gk20a *g, bool enable) if (!change_mode) { goto done; } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU err = nvgpu_pmu_pg_global_enable(g, enable); #endif done: diff --git a/drivers/gpu/nvgpu/common/power_features/power_features.c b/drivers/gpu/nvgpu/common/power_features/power_features.c index fc849ee5e..ec4d5c16e 100644 --- a/drivers/gpu/nvgpu/common/power_features/power_features.c +++ b/drivers/gpu/nvgpu/common/power_features/power_features.c @@ -33,7 +33,7 @@ int nvgpu_cg_pg_disable(struct gk20a *g) g->ops.gr.init.wait_initialized(g); -#ifdef NVGPU_FEATURE_POWER_PG +#ifdef CONFIG_NVGPU_POWER_PG /* disable elpg before clock gating */ err = nvgpu_pg_elpg_disable(g); if (err != 0) { @@ -63,7 +63,7 @@ int nvgpu_cg_pg_enable(struct gk20a *g) nvgpu_cg_slcg_gr_perf_ltc_load_enable(g); -#ifdef NVGPU_FEATURE_POWER_PG +#ifdef CONFIG_NVGPU_POWER_PG err = nvgpu_pg_elpg_enable(g); if (err != 0) { nvgpu_err(g, "failed to set enable elpg"); diff --git a/drivers/gpu/nvgpu/common/rc/rc.c b/drivers/gpu/nvgpu/common/rc/rc.c index 36a3cba64..7ca665907 100644 --- a/drivers/gpu/nvgpu/common/rc/rc.c +++ b/drivers/gpu/nvgpu/common/rc/rc.c @@ -63,7 +63,7 @@ void nvgpu_rc_ctxsw_timeout(struct gk20a *g, u32 eng_bitmask, nvgpu_tsg_set_error_notifier(g, tsg, NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT /* * Cancel all channels' wdt since ctxsw timeout might * trigger multiple watchdogs at a time @@ -194,7 +194,7 @@ void nvgpu_rc_tsg_and_related_engines(struct gk20a *g, struct nvgpu_tsg *tsg, * changing until engine status is checked to make sure tsg * being recovered is not loaded on the engines */ -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER err = g->ops.gr.disable_ctxsw(g); #endif @@ -206,7 +206,7 @@ void nvgpu_rc_tsg_and_related_engines(struct gk20a *g, struct nvgpu_tsg *tsg, eng_bitmask = g->ops.engine.get_mask_on_id(g, tsg->tsgid, true); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER /* * it is ok to enable ctxsw before tsg is recovered. If engines * is 0, no engine recovery is needed and if it is non zero, diff --git a/drivers/gpu/nvgpu/common/sim/sim_netlist.c b/drivers/gpu/nvgpu/common/sim/sim_netlist.c index 278bd53c0..338d73605 100644 --- a/drivers/gpu/nvgpu/common/sim/sim_netlist.c +++ b/drivers/gpu/nvgpu/common/sim/sim_netlist.c @@ -40,7 +40,7 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) struct netlist_aiv_list *sys_ctxsw_regs; struct netlist_aiv_list *gpc_ctxsw_regs; struct netlist_aiv_list *tpc_ctxsw_regs; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct netlist_aiv_list *zcull_gpc_ctxsw_regs; #endif struct netlist_aiv_list *pm_sys_ctxsw_regs; @@ -73,7 +73,7 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) sys_ctxsw_regs = nvgpu_netlist_get_sys_ctxsw_regs(g); gpc_ctxsw_regs = nvgpu_netlist_get_gpc_ctxsw_regs(g); tpc_ctxsw_regs = nvgpu_netlist_get_tpc_ctxsw_regs(g); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS zcull_gpc_ctxsw_regs = nvgpu_netlist_get_zcull_gpc_ctxsw_regs(g); #endif pm_sys_ctxsw_regs = nvgpu_netlist_get_pm_sys_ctxsw_regs(g); @@ -121,7 +121,7 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) &gpc_ctxsw_regs->count); g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0, &tpc_ctxsw_regs->count); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0, &zcull_gpc_ctxsw_regs->count); #endif @@ -177,7 +177,7 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) if (nvgpu_netlist_alloc_aiv_list(g, tpc_ctxsw_regs) == NULL) { goto fail; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS if (nvgpu_netlist_alloc_aiv_list(g, zcull_gpc_ctxsw_regs) == NULL) { goto fail; } @@ -312,7 +312,7 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) i, &l[i].value); } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS for (i = 0; i < zcull_gpc_ctxsw_regs->count; i++) { struct netlist_aiv *l = zcull_gpc_ctxsw_regs->l; g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR", @@ -392,7 +392,7 @@ fail: nvgpu_kfree(g, sys_ctxsw_regs->l); nvgpu_kfree(g, gpc_ctxsw_regs->l); nvgpu_kfree(g, tpc_ctxsw_regs->l); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_kfree(g, zcull_gpc_ctxsw_regs->l); #endif nvgpu_kfree(g, ppc_ctxsw_regs->l); diff --git a/drivers/gpu/nvgpu/common/vgpu/fifo/userd_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/fifo/userd_vgpu.c index cad454947..add7c00a8 100644 --- a/drivers/gpu/nvgpu/common/vgpu/fifo/userd_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/fifo/userd_vgpu.c @@ -31,7 +31,7 @@ int vgpu_userd_setup_sw(struct gk20a *g) { -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD struct nvgpu_fifo *f = &g->fifo; f->userd_entry_size = g->ops.userd.entry_size(g); @@ -44,7 +44,7 @@ int vgpu_userd_setup_sw(struct gk20a *g) void vgpu_userd_cleanup_sw(struct gk20a *g) { -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD nvgpu_userd_free_slabs(g); #endif } diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 5d9d7ff59..fefd6d52e 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -103,10 +103,10 @@ static const struct gpu_ops vgpu_gp10b_ops = { .ltc = { .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zbc_color_entry = NULL, .set_zbc_depth_entry = NULL, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .init_fs_state = vgpu_ltc_init_fs_state, .flush = NULL, .set_enabled = NULL, @@ -133,7 +133,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_num_pce = vgpu_ce_get_num_pce, }, .gr = { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .set_alpha_circular_buffer_size = NULL, .set_circular_buffer_size = NULL, .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, @@ -197,7 +197,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr, .set_zcull = gm20b_ctxsw_prog_set_zcull, .set_zcull_mode_no_ctxsw = @@ -237,7 +237,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, .hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag, @@ -261,14 +261,14 @@ static const struct gpu_ops vgpu_gp10b_ops = { .init_sm_id_table = vgpu_gr_init_sm_id_table, }, .setup = { -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, #endif .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, .free_gr_ctx = vgpu_gr_free_gr_ctx, .set_preemption_mode = vgpu_gr_set_preemption_mode, }, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .zbc = { .add_color = NULL, .add_depth = NULL, @@ -282,12 +282,12 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_zcull_info = vgpu_gr_get_zcull_info, .program_zcull_mapping = NULL, }, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .falcon = { .init_ctx_state = vgpu_gr_init_ctx_state, .load_ctxsw_ucode = NULL, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .fecs_trace = { .alloc_user_buffer = vgpu_alloc_user_buffer, .free_user_buffer = vgpu_free_user_buffer, @@ -308,7 +308,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_buffer_full_mailbox_val = gm20b_fecs_trace_get_buffer_full_mailbox_val, }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ +#endif /* CONFIG_NVGPU_FECS_TRACE */ .init = { .get_no_of_sm = nvgpu_gr_get_no_of_sm, .fs_state = vgpu_gr_init_fs_state, @@ -527,7 +527,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .userd = { .setup_sw = vgpu_userd_setup_sw, .cleanup_sw = vgpu_userd_cleanup_sw, -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD .init_mem = gk20a_userd_init_mem, .gp_get = gk20a_userd_gp_get, .gp_put = gk20a_userd_gp_put, @@ -611,7 +611,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .init_blcg_mode = NULL, .elcg_init_idle_filters = NULL, }, -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU .pmu = { .pmu_setup_elpg = NULL, .pmu_get_queue_head = NULL, @@ -652,7 +652,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb, .clk_arb_cleanup = gp10b_clk_arb_cleanup, }, -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .regops = { .exec_regops = vgpu_exec_regops, .get_global_whitelist_ranges = @@ -695,7 +695,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .debug = { .show_dump = NULL, }, -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .debugger = { .post_events = nvgpu_dbg_gpu_post_events, .dbg_set_powergate = vgpu_dbg_set_powergate, @@ -727,7 +727,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .read_ptimer = vgpu_read_ptimer, .get_timestamps_zipper = vgpu_get_timestamps_zipper, }, -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) .css = { .enable_snapshot = vgpu_css_enable_snapshot_buffer, .disable_snapshot = vgpu_css_release_snapshot_buffer, @@ -799,13 +799,13 @@ int vgpu_gp10b_init_hal(struct gk20a *g) gops->mm = vgpu_gp10b_ops.mm; gops->pramin = vgpu_gp10b_ops.pramin; gops->therm = vgpu_gp10b_ops.therm; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU gops->pmu = vgpu_gp10b_ops.pmu; #endif gops->clk_arb = vgpu_gp10b_ops.clk_arb; gops->mc = vgpu_gp10b_ops.mc; gops->debug = vgpu_gp10b_ops.debug; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER gops->debugger = vgpu_gp10b_ops.debugger; gops->regops = vgpu_gp10b_ops.regops; gops->perf = vgpu_gp10b_ops.perf; @@ -813,7 +813,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g) #endif gops->bus = vgpu_gp10b_ops.bus; gops->ptimer = vgpu_gp10b_ops.ptimer; -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) gops->css = vgpu_gp10b_ops.css; #endif gops->falcon = vgpu_gp10b_ops.falcon; diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c index 8ceb0dfb3..256e937ed 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c @@ -293,7 +293,7 @@ int vgpu_gr_map_global_ctx_buffers(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, g_bfr_va[NVGPU_GR_CTX_PRIV_ACCESS_MAP_VA] = gpu_va; /* FECS trace Buffer */ -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE gpu_va = nvgpu_vm_alloc_va(ch_vm, nvgpu_gr_global_ctx_get_size(global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_FECS_TRACE_BUFFER), @@ -311,7 +311,7 @@ int vgpu_gr_map_global_ctx_buffers(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, p->attr_va = g_bfr_va[NVGPU_GR_CTX_ATTRIBUTE_VA]; p->page_pool_va = g_bfr_va[NVGPU_GR_CTX_PAGEPOOL_VA]; p->priv_access_map_va = g_bfr_va[NVGPU_GR_CTX_PRIV_ACCESS_MAP_VA]; -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE p->fecs_trace_va = g_bfr_va[NVGPU_GR_CTX_FECS_TRACE_BUFFER_VA]; #endif err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/fecs_trace_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/fecs_trace_vgpu.c index 16862dc92..9390d884e 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/fecs_trace_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/gr/fecs_trace_vgpu.c @@ -163,7 +163,7 @@ int vgpu_free_user_buffer(struct gk20a *g) } -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE int vgpu_fecs_trace_max_entries(struct gk20a *g, struct nvgpu_gpu_ctxsw_trace_filter *filter) { @@ -189,4 +189,4 @@ int vgpu_fecs_trace_set_filter(struct gk20a *g, return err; } -#endif /* CONFIG_GK20A_CTXSW_TRACE */ +#endif /* CONFIG_NVGPU_FECS_TRACE */ diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c index 00d7afb6e..33171e8c4 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c @@ -39,7 +39,7 @@ #include #include #include -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include #include #endif @@ -60,7 +60,7 @@ #include "common/gr/gr_falcon_priv.h" #include "common/gr/gr_intr_priv.h" #include "common/gr/ctx_priv.h" -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include "common/gr/zcull_priv.h" #include "common/gr/zbc_priv.h" #endif @@ -155,7 +155,7 @@ int vgpu_gr_init_ctx_state(struct gk20a *g, return -ENXIO; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS sizes->zcull_image_size = priv->constants.zcull_ctx_size; if (sizes->zcull_image_size == 0U) { return -ENXIO; @@ -209,7 +209,7 @@ int vgpu_gr_alloc_global_ctx_buffers(struct gk20a *g) nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP, size); -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE size = nvgpu_gr_fecs_trace_buffer_size(g); nvgpu_log_info(g, "fecs_trace_buffer_size : %d", size); @@ -314,7 +314,7 @@ int vgpu_gr_alloc_obj_ctx(struct nvgpu_channel *c, u32 class_num, u32 flags) nvgpu_err(g, "fail to commit gr ctx buffer"); goto out; } -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE /* for fecs bind channel */ err = nvgpu_pg_elpg_protected_call(g, vgpu_gr_load_golden_ctx_image(g, c->virt_ctx)); @@ -478,7 +478,7 @@ cleanup: return err; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS static int vgpu_gr_init_gr_zcull(struct gk20a *g, struct nvgpu_gr *gr, u32 size) { @@ -582,7 +582,7 @@ u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g) return priv->constants.max_lts_per_ltc; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS int vgpu_gr_add_zbc(struct gk20a *g, struct nvgpu_gr_zbc *zbc, struct nvgpu_gr_zbc_entry *zbc_val) { @@ -671,7 +671,7 @@ static void vgpu_remove_gr_support(struct gk20a *g) nvgpu_gr_config_deinit(gr->g, gr->config); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_gr_zcull_deinit(gr->g, gr->zcull); #endif } @@ -722,7 +722,7 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g) goto clean_up; } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER err = nvgpu_gr_hwpm_map_init(g, &g->gr->hwpm_map, nvgpu_gr_falcon_get_pm_ctxsw_image_size(g->gr->falcon)); if (err != 0) { @@ -731,7 +731,7 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g) } #endif -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS err = vgpu_gr_init_gr_zcull(g, gr, nvgpu_gr_falcon_get_zcull_image_size(g->gr->falcon)); if (err) { @@ -822,7 +822,7 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) g->ops.channel.set_error_notifier(ch, NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); break; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER case TEGRA_VGPU_GR_INTR_SM_EXCEPTION: g->ops.debugger.post_events(ch); break; @@ -1220,7 +1220,7 @@ int vgpu_gr_update_pc_sampling(struct nvgpu_channel *ch, bool enable) void vgpu_gr_init_cyclestats(struct gk20a *g) { -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) bool snapshots_supported = true; u32 max_css_buffer_size; diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h index 9af033ed5..fb7d7417a 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h +++ b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h @@ -28,7 +28,7 @@ struct gk20a; struct nvgpu_channel; struct gr_gk20a; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_gr_zcull_info; struct nvgpu_gr_zcull; struct nvgpu_gr_zbc; @@ -55,7 +55,7 @@ u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, struct nvgpu_gr_config *config, u32 vgpu_gr_get_max_fbps_count(struct gk20a *g); u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g); u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct nvgpu_channel *c, u64 zcull_va, u32 mode); int vgpu_gr_get_zcull_info(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index 4354f0a30..acbaf5f9a 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -52,7 +52,7 @@ #include "hal/therm/therm_gp10b.h" #include "hal/therm/therm_gv11b.h" #include "hal/gr/fecs_trace/fecs_trace_gv11b.h" -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include "hal/gr/zbc/zbc_gv11b.h" #endif #include "hal/gr/hwpm_map/hwpm_map_gv100.h" @@ -117,7 +117,7 @@ #include #include -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include #endif @@ -130,7 +130,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .ltc = { .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zbc_s_entry = NULL, .set_zbc_color_entry = NULL, .set_zbc_depth_entry = NULL, @@ -160,7 +160,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_num_pce = vgpu_ce_get_num_pce, }, .gr = { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .set_alpha_circular_buffer_size = NULL, .set_circular_buffer_size = NULL, .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, @@ -231,7 +231,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr, .set_zcull = gm20b_ctxsw_prog_set_zcull, .set_zcull_mode_no_ctxsw = @@ -273,7 +273,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, .hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag, @@ -305,7 +305,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .init_sm_id_table = vgpu_gr_init_sm_id_table, }, .setup = { -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, #endif .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, @@ -313,7 +313,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .free_subctx = vgpu_channel_free_ctx_header, .set_preemption_mode = vgpu_gr_set_preemption_mode, }, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .zbc = { .add_color = NULL, .add_depth = NULL, @@ -327,8 +327,8 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_zcull_info = vgpu_gr_get_zcull_info, .program_zcull_mapping = NULL, }, -#endif /* NVGPU_GRAPHICS */ -#ifdef NVGPU_DEBUGGER +#endif /* CONFIG_NVGPU_GRAPHICS */ +#ifdef CONFIG_NVGPU_DEBUGGER .hwpm_map = { .align_regs_perf_pma = gv100_gr_hwpm_map_align_regs_perf_pma, @@ -338,7 +338,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .init_ctx_state = vgpu_gr_init_ctx_state, .load_ctxsw_ucode = NULL, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .fecs_trace = { .alloc_user_buffer = vgpu_alloc_user_buffer, .free_user_buffer = vgpu_free_user_buffer, @@ -359,7 +359,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_buffer_full_mailbox_val = gv11b_fecs_trace_get_buffer_full_mailbox_val, }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ +#endif /* CONFIG_NVGPU_FECS_TRACE */ .init = { .get_no_of_sm = nvgpu_gr_get_no_of_sm, .get_nonpes_aware_tpc = @@ -613,7 +613,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .userd = { .setup_sw = vgpu_userd_setup_sw, .cleanup_sw = vgpu_userd_cleanup_sw, -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD .init_mem = gk20a_userd_init_mem, .gp_get = gv11b_userd_gp_get, .gp_put = gv11b_userd_gp_put, @@ -704,7 +704,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .init_blcg_mode = NULL, .elcg_init_idle_filters = NULL, }, -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU .pmu = { .pmu_setup_elpg = NULL, .pmu_get_queue_head = NULL, @@ -747,7 +747,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb, .clk_arb_cleanup = gp10b_clk_arb_cleanup, }, -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .regops = { .exec_regops = vgpu_exec_regops, .get_global_whitelist_ranges = @@ -791,7 +791,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .debug = { .show_dump = NULL, }, -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .debugger = { .post_events = nvgpu_dbg_gpu_post_events, .dbg_set_powergate = vgpu_dbg_set_powergate, @@ -823,7 +823,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .read_ptimer = vgpu_read_ptimer, .get_timestamps_zipper = vgpu_get_timestamps_zipper, }, -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) .css = { .enable_snapshot = vgpu_css_enable_snapshot_buffer, .disable_snapshot = vgpu_css_release_snapshot_buffer, @@ -894,13 +894,13 @@ int vgpu_gv11b_init_hal(struct gk20a *g) gops->netlist = vgpu_gv11b_ops.netlist; gops->mm = vgpu_gv11b_ops.mm; gops->therm = vgpu_gv11b_ops.therm; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU gops->pmu = vgpu_gv11b_ops.pmu; #endif gops->clk_arb = vgpu_gv11b_ops.clk_arb; gops->mc = vgpu_gv11b_ops.mc; gops->debug = vgpu_gv11b_ops.debug; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER gops->debugger = vgpu_gv11b_ops.debugger; gops->regops = vgpu_gv11b_ops.regops; gops->perf = vgpu_gv11b_ops.perf; @@ -908,7 +908,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g) #endif gops->bus = vgpu_gv11b_ops.bus; gops->ptimer = vgpu_gv11b_ops.ptimer; -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) gops->css = vgpu_gv11b_ops.css; #endif gops->falcon = vgpu_gv11b_ops.falcon; diff --git a/drivers/gpu/nvgpu/common/vgpu/init/init_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/init/init_vgpu.c index 8395bdcd6..dde7ff5f9 100644 --- a/drivers/gpu/nvgpu/common/vgpu/init/init_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/init/init_vgpu.c @@ -64,7 +64,7 @@ void vgpu_remove_support_common(struct gk20a *g) struct tegra_vgpu_intr_msg msg; int err; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER if (g->dbg_regops_tmp_buf) { nvgpu_kfree(g, g->dbg_regops_tmp_buf); } @@ -82,7 +82,7 @@ void vgpu_remove_support_common(struct gk20a *g) g->mm.remove_support(&g->mm); } -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) nvgpu_free_cyclestats_snapshot_data(g); #endif diff --git a/drivers/gpu/nvgpu/common/vgpu/intr/intr_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/intr/intr_vgpu.c index 64fa9fb80..2c2a4a03e 100644 --- a/drivers/gpu/nvgpu/common/vgpu/intr/intr_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/intr/intr_vgpu.c @@ -67,7 +67,7 @@ int vgpu_intr_thread(void *dev_id) vgpu_fifo_isr(g, &msg->info.fifo_intr); } break; -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE case TEGRA_VGPU_EVENT_FECS_TRACE: vgpu_fecs_trace_data_update(g); break; diff --git a/drivers/gpu/nvgpu/common/vgpu/vgpu.c b/drivers/gpu/nvgpu/common/vgpu/vgpu.c index bfced2e39..3994098b8 100644 --- a/drivers/gpu/nvgpu/common/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/vgpu.c @@ -187,7 +187,7 @@ int vgpu_intr_thread(void *dev_id) vgpu_fifo_isr(g, &msg->info.fifo_intr); } break; -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE case TEGRA_VGPU_EVENT_FECS_TRACE: vgpu_fecs_trace_data_update(g); break; @@ -230,7 +230,7 @@ void vgpu_remove_support_common(struct gk20a *g) struct tegra_vgpu_intr_msg msg; int err; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER if (g->dbg_regops_tmp_buf) { nvgpu_kfree(g, g->dbg_regops_tmp_buf); } diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c b/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c index c7b364223..e118dfe78 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c @@ -347,7 +347,7 @@ void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER g->ops.gr.set_debug_mode(g, enable); #endif } diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c b/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c index 7c5a4d3e8..b2c6320fa 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c @@ -53,7 +53,7 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) nvgpu_log(g, gpu_dbg_info, "nvlink soc credits init done by bpmp"); } else { #ifndef __NVGPU_POSIX__ -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK nvgpu_mss_nvlink_init_credits(g); #endif #endif diff --git a/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c index 063ef25e4..0f7239d8f 100644 --- a/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c @@ -258,7 +258,7 @@ bool gk20a_fifo_handle_mmu_fault_locked( fault_id = nvgpu_readl(g, fifo_intr_mmu_fault_id_r()); fake_fault = false; } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_mutex_acquire(&g->fifo.deferred_reset_mutex); g->fifo.deferred_reset_pending = false; nvgpu_mutex_release(&g->fifo.deferred_reset_mutex); @@ -290,7 +290,7 @@ bool gk20a_fifo_handle_mmu_fault_locked( if (ctxsw) { g->ops.gr.falcon.dump_stats(g); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_err(g, " gr_status_r: 0x%x", g->ops.gr.get_gr_status(g)); #endif @@ -340,7 +340,7 @@ bool gk20a_fifo_handle_mmu_fault_locked( /* check if engine reset should be deferred */ if (engine_id != NVGPU_INVALID_ENG_ID) { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER bool defer = nvgpu_engine_should_defer_reset(g, engine_id, mmfault_info.client_type, fake_fault); @@ -360,12 +360,12 @@ bool gk20a_fifo_handle_mmu_fault_locked( } else { #endif nvgpu_engine_reset(g, engine_id); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER } #endif } -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE if (tsg != NULL) { nvgpu_gr_fecs_trace_add_tsg_reset(g, tsg); } diff --git a/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c index 33c1139c1..cd216ee4a 100644 --- a/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c @@ -32,7 +32,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif @@ -101,7 +101,7 @@ int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id, int gk20a_fifo_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch) { int ret = 0; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU u32 token = PMU_INVALID_MUTEX_OWNER_ID; int mutex_ret = 0; #endif @@ -109,12 +109,12 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch) /* we have no idea which runlist we are using. lock all */ nvgpu_runlist_lock_active_runlists(g); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); #endif ret = gk20a_fifo_preempt_locked(g, ch->chid, ID_TYPE_CHANNEL); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (mutex_ret == 0) { if (nvgpu_pmu_lock_release(g, g->pmu, PMU_MUTEX_ID_FIFO, &token) != 0) { @@ -150,7 +150,7 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch) int gk20a_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) { int ret = 0; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU u32 token = PMU_INVALID_MUTEX_OWNER_ID; int mutex_ret = 0; #endif @@ -158,12 +158,12 @@ int gk20a_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) /* we have no idea which runlist we are using. lock all */ nvgpu_runlist_lock_active_runlists(g); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); #endif ret = gk20a_fifo_preempt_locked(g, tsg->tsgid, ID_TYPE_TSG); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (mutex_ret == 0) { if (nvgpu_pmu_lock_release(g, g->pmu, PMU_MUTEX_ID_FIFO, &token) != 0) { diff --git a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c index be4ed1e77..5167a3bdf 100644 --- a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c +++ b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c @@ -37,7 +37,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif @@ -88,7 +88,7 @@ void gv11b_fifo_preempt_runlists_for_rc(struct gk20a *g, u32 runlists_mask) { struct nvgpu_fifo *f = &g->fifo; struct nvgpu_runlist_info *runlist; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU u32 token = PMU_INVALID_MUTEX_OWNER_ID; int mutex_ret = 0; #endif @@ -96,7 +96,7 @@ void gv11b_fifo_preempt_runlists_for_rc(struct gk20a *g, u32 runlists_mask) /* runlist_lock are locked by teardown and sched are disabled too */ nvgpu_log_fn(g, "preempt runlists_mask:0x%08x", runlists_mask); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); #endif @@ -116,7 +116,7 @@ void gv11b_fifo_preempt_runlists_for_rc(struct gk20a *g, u32 runlists_mask) runlist->reset_eng_bitmask = runlist->eng_bitmask; } } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (mutex_ret == 0) { int err = nvgpu_pmu_lock_release(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); @@ -430,7 +430,7 @@ int gv11b_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) { struct nvgpu_fifo *f = &g->fifo; int ret = 0; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU u32 token = PMU_INVALID_MUTEX_OWNER_ID; int mutex_ret = 0; #endif @@ -448,12 +448,12 @@ int gv11b_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) /* WAR for Bug 2065990 */ nvgpu_tsg_disable_sched(g, tsg); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); #endif ret = gv11b_fifo_preempt_locked(g, tsg->tsgid, ID_TYPE_TSG); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (mutex_ret == 0) { int err = nvgpu_pmu_lock_release(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); diff --git a/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c b/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c index 15207379c..4ffe7af76 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c +++ b/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c @@ -44,7 +44,7 @@ int gv11b_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base, nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v()); -#ifdef NVGPU_REPLAYABLE_FAULT +#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT if ((flags & NVGPU_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE) != 0U) { replayable = true; } diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c index 7023069ac..8225836c9 100644 --- a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c @@ -35,7 +35,7 @@ #define FECS_MAILBOX_0_ACK_RESTORE 0x4U -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING int gk20a_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next) { return nvgpu_runlist_reschedule(ch, preempt_next, true); @@ -138,7 +138,7 @@ void gk20a_runlist_write_state(struct gk20a *g, u32 runlists_mask, nvgpu_writel(g, fifo_sched_disable_r(), reg_val); } -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING /* trigger host preempt of GR pending load ctx if that ctx is not for ch */ int gk20a_fifo_reschedule_preempt_next(struct nvgpu_channel *ch, bool wait_preempt) diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.h b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.h index c208bfc8e..9d7cbf940 100644 --- a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.h +++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.h @@ -29,7 +29,7 @@ struct nvgpu_channel; struct nvgpu_tsg; struct gk20a; -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING int gk20a_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next); int gk20a_fifo_reschedule_preempt_next(struct nvgpu_channel *ch, bool wait_preempt); diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv11b.c b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv11b.c index 5f7c614b8..7908b85ea 100644 --- a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv11b.c @@ -26,7 +26,7 @@ #include -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING int gv11b_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next) { /* diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv11b.h b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv11b.h index 9dc8bbda6..16ee1a5f7 100644 --- a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv11b.h @@ -27,7 +27,7 @@ struct nvgpu_channel; -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING int gv11b_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next); #endif u32 gv11b_runlist_count_max(void); diff --git a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.c b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.c index 50b25f5b8..3ec326808 100644 --- a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.c @@ -80,7 +80,7 @@ u32 gm20b_gr_config_get_tpc_count_in_gpc(struct gk20a *g, return gr_gpc0_fs_gpc_num_available_tpcs_v(tmp); } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS u32 gm20b_gr_config_get_zcull_count_in_gpc(struct gk20a *g, struct nvgpu_gr_config *config, u32 gpc_index) { diff --git a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h index 19ebdc852..6653f2b28 100644 --- a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h @@ -34,7 +34,7 @@ u32 gm20b_gr_config_get_gpc_tpc_mask(struct gk20a *g, struct nvgpu_gr_config *config, u32 gpc_index); u32 gm20b_gr_config_get_tpc_count_in_gpc(struct gk20a *g, struct nvgpu_gr_config *config, u32 gpc_index); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS u32 gm20b_gr_config_get_zcull_count_in_gpc(struct gk20a *g, struct nvgpu_gr_config *config, u32 gpc_index); #endif diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c index 4f9a88f09..aed540902 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c @@ -80,7 +80,7 @@ void gm20b_ctxsw_prog_set_patch_addr(struct gk20a *g, ctxsw_prog_main_image_patch_adr_hi_o(), u64_hi32(addr)); } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void gm20b_ctxsw_prog_set_zcull_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr) { @@ -275,7 +275,7 @@ u32 gm20b_ctxsw_prog_get_local_priv_register_ctl_offset(u32 *context) return ctxsw_prog_local_priv_register_ctl_offset_v(data); } -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE u32 gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp(void) { return ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(); diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h index 5c582c7e4..f2b7a9bb8 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h @@ -39,7 +39,7 @@ void gm20b_ctxsw_prog_set_patch_count(struct gk20a *g, struct nvgpu_mem *ctx_mem, u32 count); void gm20b_ctxsw_prog_set_patch_addr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void gm20b_ctxsw_prog_set_zcull_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); void gm20b_ctxsw_prog_set_zcull(struct gk20a *g, struct nvgpu_mem *ctx_mem, @@ -78,7 +78,7 @@ void gm20b_ctxsw_prog_get_extended_buffer_size_offset(u32 *context, u32 *size, u32 *offset); void gm20b_ctxsw_prog_get_ppc_info(u32 *context, u32 *num_ppcs, u32 *ppc_mask); u32 gm20b_ctxsw_prog_get_local_priv_register_ctl_offset(u32 *context); -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE u32 gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp(void); u32 gm20b_ctxsw_prog_hw_get_ts_tag(u64 ts); u64 gm20b_ctxsw_prog_hw_record_ts_timestamp(u64 ts); diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c index 98fc19145..97fc32ab8 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c @@ -696,7 +696,7 @@ int gm20b_gr_falcon_init_ctx_state(struct gk20a *g, "query golden image size failed"); return ret; } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER ret = gm20b_gr_falcon_ctrl_ctxsw(g, NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_PM_IMAGE_SIZE, 0, &sizes->pm_ctxsw_image_size); @@ -707,7 +707,7 @@ int gm20b_gr_falcon_init_ctx_state(struct gk20a *g, } #endif -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS ret = gm20b_gr_falcon_ctrl_ctxsw(g, NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE, 0, &sizes->zcull_image_size); @@ -851,7 +851,7 @@ int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method, fecs_method, data, ret_val); switch (fecs_method) { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER case NVGPU_GR_FALCON_METHOD_CTXSW_STOP: op.method.addr = gr_fecs_method_push_adr_stop_ctxsw_v(); @@ -892,7 +892,7 @@ int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method, gr_fecs_method_push_adr_discover_image_size_v(); op.mailbox.ret = ret_val; break; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS case NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE: op.method.addr = gr_fecs_method_push_adr_discover_zcull_image_size_v(); @@ -900,7 +900,7 @@ int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method, break; #endif -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER case NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_PM_IMAGE_SIZE: op.method.addr = gr_fecs_method_push_adr_discover_pm_image_size_v(); @@ -908,8 +908,11 @@ int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method, sleepduringwait = true; break; #endif -/* Replace NVGPU_GRAPHICS switch here with relevant power feature switch */ -#ifdef NVGPU_GRAPHICS +/* + * Replace CONFIG_NVGPU_GRAPHICS switch here with relevant + * power feature switch. + */ +#ifdef CONFIG_NVGPU_GRAPHICS case NVGPU_GR_FALCON_METHOD_REGLIST_DISCOVER_IMAGE_SIZE: op.method.addr = gr_fecs_method_push_adr_discover_reglist_image_size_v(); @@ -956,7 +959,7 @@ int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method, op.cond.fail = GR_IS_UCODE_OP_AND; sleepduringwait = true; break; -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE case NVGPU_GR_FALCON_METHOD_FECS_TRACE_FLUSH: op.method.addr = gr_fecs_method_push_adr_write_timestamp_record_v(); diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b.c index d28e5b00a..991bfe84c 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b.c @@ -40,7 +40,7 @@ int gp10b_gr_falcon_init_ctx_state(struct gk20a *g, if (err != 0) { return err; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS err = g->ops.gr.falcon.ctrl_ctxsw(g, NVGPU_GR_FALCON_METHOD_PREEMPT_IMAGE_SIZE, 0U, &sizes->preempt_image_size); @@ -58,7 +58,7 @@ int gp10b_gr_falcon_init_ctx_state(struct gk20a *g, int gp10b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method, u32 data, u32 *ret_val) { -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_fecs_method_op op = { .mailbox = { .id = 0U, .data = 0U, .ret = NULL, .clr = ~U32(0U), .ok = 0U, .fail = 0U}, @@ -73,7 +73,7 @@ int gp10b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method, fecs_method, data, ret_val); switch (fecs_method) { -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS case NVGPU_GR_FALCON_METHOD_PREEMPT_IMAGE_SIZE: op.method.addr = gr_fecs_method_push_adr_discover_preemption_image_size_v(); diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c index 080956774..6c1536059 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c @@ -438,7 +438,7 @@ int gr_gm20b_update_pc_sampling(struct nvgpu_channel *c, void gr_gm20b_init_cyclestats(struct gk20a *g) { -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT, true); #else diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c index c3c958f6e..9b34826de 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c @@ -471,7 +471,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, nvgpu_gr_ctx_set_cilp_preempt_pending(gr_ctx, true); g->gr->cilp_preempt_pending_chid = fault_ch->chid; -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL g->ops.tsg.post_event_id(tsg, NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED); #endif @@ -487,7 +487,7 @@ int gr_gp10b_pre_process_sm_exception(struct gk20a *g, bool sm_debugger_attached, struct nvgpu_channel *fault_ch, bool *early_exit, bool *ignore_debugger) { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER bool cilp_enabled = false; struct nvgpu_tsg *tsg; @@ -757,7 +757,7 @@ clean_up: return err; } -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING int gr_gp10b_set_boosted_ctx(struct nvgpu_channel *ch, bool boost) { diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.h index 4eb62ed3c..44e608353 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.h +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.h @@ -55,7 +55,7 @@ u32 get_ecc_override_val(struct gk20a *g); int gr_gp10b_suspend_contexts(struct gk20a *g, struct dbg_session_gk20a *dbg_s, int *ctx_resident_ch_fd); -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING int gr_gp10b_set_boosted_ctx(struct nvgpu_channel *ch, bool boost); #endif diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c index 4878b6520..b3eee7395 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c @@ -454,7 +454,7 @@ void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, fuse_val); } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER static int gr_gv11b_handle_warp_esr_error_mmu_nack(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 warp_esr_error, @@ -628,7 +628,7 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g, bool sm_debugger_attached, struct nvgpu_channel *fault_ch, bool *early_exit, bool *ignore_debugger) { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER int ret; bool cilp_enabled = false; u32 warp_esr_error = gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(warp_esr); diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c index 060c6ebea..18398b641 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c @@ -258,7 +258,7 @@ void gm20b_gr_init_tpc_mask(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask) nvgpu_writel(g, gr_fe_tpc_fs_r(), pes_tpc_mask); } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void gm20b_gr_init_rop_mapping(struct gk20a *g, struct nvgpu_gr_config *gr_config) { diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h index d117c4d33..075306f87 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h @@ -48,7 +48,7 @@ u32 gm20b_gr_init_get_sm_id_size(void); int gm20b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id, struct nvgpu_gr_config *gr_config); void gm20b_gr_init_tpc_mask(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void gm20b_gr_init_rop_mapping(struct gk20a *g, struct nvgpu_gr_config *gr_config); #endif diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c index 9202c44a1..22c589d91 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c @@ -474,7 +474,7 @@ void gv11b_gr_init_tpc_mask(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask) nvgpu_writel(g, gr_fe_tpc_fs_r(gpc_index), pes_tpc_mask); } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void gv11b_gr_init_rop_mapping(struct gk20a *g, struct nvgpu_gr_config *gr_config) { diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h index 5784a2bfb..835f000d0 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h @@ -42,7 +42,7 @@ void gv11b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid, int gv11b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id, struct nvgpu_gr_config *gr_config); void gv11b_gr_init_tpc_mask(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void gv11b_gr_init_rop_mapping(struct gk20a *g, struct nvgpu_gr_config *gr_config); #endif diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c index f50ae5f53..6282d5d41 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c @@ -64,7 +64,7 @@ int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, goto fail; } -#if defined(NVGPU_DEBUGGER) && defined(NVGPU_GRAPHICS) +#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) if (class_num == MAXWELL_B) { switch (offset << 2) { case NVB197_SET_SHADER_EXCEPTIONS: diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c index d3ba83962..ce58aa8b3 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c @@ -111,7 +111,7 @@ int gp10b_gr_intr_handle_fecs_error(struct gk20a *g, struct nvgpu_channel *ch; u32 chid = NVGPU_INVALID_CHANNEL_ID; int ret = 0; -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL struct nvgpu_tsg *tsg; #endif struct nvgpu_fecs_host_intr_status fecs_host_intr; @@ -156,12 +156,12 @@ int gp10b_gr_intr_handle_fecs_error(struct gk20a *g, goto clean_up; } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER /* Post events to UMD */ g->ops.debugger.post_events(ch); #endif -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL tsg = &g->fifo.tsg[ch->tsgid]; g->ops.tsg.post_event_id(tsg, NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE); @@ -219,7 +219,7 @@ int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, goto fail; } -#if defined(NVGPU_DEBUGGER) && defined(NVGPU_GRAPHICS) +#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) if (class_num == PASCAL_A) { switch (offset << 2) { case NVC097_SET_SHADER_EXCEPTIONS: diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c index 8660e3f4d..84109b718 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c @@ -199,7 +199,7 @@ int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, goto fail; } -#if defined(NVGPU_DEBUGGER) && defined(NVGPU_GRAPHICS) +#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) if (class_num == VOLTA_A) { switch (offset << 2) { case NVC397_SET_SHADER_EXCEPTIONS: diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c index 8d711ddd3..5bcda8c7c 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c @@ -91,7 +91,7 @@ int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, goto fail; } -#if defined(NVGPU_DEBUGGER) && defined(NVGPU_GRAPHICS) +#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) if (class_num == TURING_A) { switch (offset << 2) { case NVC597_SET_SHADER_EXCEPTIONS: diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 98c72dcfe..71641addf 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -33,14 +33,14 @@ #include #include #include -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include #endif #include #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif #include @@ -83,7 +83,7 @@ #include "hal/fifo/mmu_fault_gk20a.h" #include "hal/fifo/mmu_fault_gm20b.h" #include "hal/rc/rc_gk20a.h" -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include "hal/gr/zbc/zbc_gm20b.h" #include "hal/gr/zcull/zcull_gm20b.h" #endif @@ -107,7 +107,7 @@ #include "hal/fifo/channel_gk20a.h" #include "hal/fifo/channel_gm20b.h" -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include "common/pmu/pg/pg_sw_gm20b.h" #endif @@ -121,10 +121,10 @@ static const struct gpu_ops gm20b_ops = { .ltc = { .determine_L2_size_bytes = gm20b_determine_L2_size_bytes, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, -#endif /*NVGPU_GRAPHICS */ +#endif /*CONFIG_NVGPU_GRAPHICS */ .init_fs_state = gm20b_ltc_init_fs_state, .flush = gm20b_flush_ltc, .set_enabled = gm20b_ltc_set_enabled, @@ -150,7 +150,7 @@ static const struct gpu_ops gm20b_ops = { .isr_nonstall = gk20a_ce2_nonstall_isr, }, .gr = { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .get_gr_status = gr_gm20b_get_gr_status, .set_alpha_circular_buffer_size = gr_gm20b_set_alpha_circular_buffer_size, @@ -196,7 +196,7 @@ static const struct gpu_ops gm20b_ops = { .esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events, .disable_ctxsw = nvgpu_gr_disable_ctxsw, .enable_ctxsw = nvgpu_gr_enable_ctxsw, -#endif /* NVGPU_DEBUGGER */ +#endif /* CONFIG_NVGPU_DEBUGGER */ .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, @@ -213,14 +213,14 @@ static const struct gpu_ops gm20b_ops = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr, .set_zcull = gm20b_ctxsw_prog_set_zcull, .set_zcull_mode_no_ctxsw = gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw, .is_zcull_mode_separate_buffer = gm20b_ctxsw_prog_is_zcull_mode_separate_buffer, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .set_pm_ptr = gm20b_ctxsw_prog_set_pm_ptr, .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, @@ -249,7 +249,7 @@ static const struct gpu_ops gm20b_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, .hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag, @@ -268,16 +268,16 @@ static const struct gpu_ops gm20b_ops = { .get_gpc_tpc_mask = gm20b_gr_config_get_gpc_tpc_mask, .get_tpc_count_in_gpc = gm20b_gr_config_get_tpc_count_in_gpc, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .get_zcull_count_in_gpc = gm20b_gr_config_get_zcull_count_in_gpc, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask, .get_pd_dist_skip_table_size = gm20b_gr_config_get_pd_dist_skip_table_size, .init_sm_id_table = gm20b_gr_config_init_sm_id_table, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .fecs_trace = { .alloc_user_buffer = nvgpu_gr_fecs_trace_ring_alloc, .free_user_buffer = nvgpu_gr_fecs_trace_ring_free, @@ -300,15 +300,15 @@ static const struct gpu_ops gm20b_ops = { .get_write_index = gm20b_fecs_trace_get_write_index, .set_read_index = gm20b_fecs_trace_set_read_index, }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ +#endif /* CONFIG_NVGPU_FECS_TRACE */ .setup = { -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .alloc_obj_ctx = nvgpu_gr_setup_alloc_obj_ctx, .free_gr_ctx = nvgpu_gr_setup_free_gr_ctx, }, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .zbc = { .add_color = gm20b_gr_zbc_add_color, .add_depth = gm20b_gr_zbc_add_depth, @@ -323,7 +323,7 @@ static const struct gpu_ops gm20b_ops = { .get_zcull_info = gm20b_gr_get_zcull_info, .program_zcull_mapping = gm20b_gr_program_zcull_mapping, }, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .init = { .get_no_of_sm = nvgpu_gr_get_no_of_sm, .wait_initialized = nvgpu_gr_wait_initialized, @@ -338,7 +338,7 @@ static const struct gpu_ops gm20b_ops = { .sm_id_config = gm20b_gr_init_sm_id_config, .sm_id_numbering = gm20b_gr_init_sm_id_numbering, .tpc_mask = gm20b_gr_init_tpc_mask, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .rop_mapping = gm20b_gr_init_rop_mapping, #endif .fs_state = gm20b_gr_init_fs_state, @@ -719,7 +719,7 @@ static const struct gpu_ops gm20b_ops = { .userd = { .setup_sw = nvgpu_userd_setup_sw, .cleanup_sw = nvgpu_userd_cleanup_sw, -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD .init_mem = gk20a_userd_init_mem, .gp_get = gk20a_userd_gp_get, .gp_put = gk20a_userd_gp_put, @@ -756,11 +756,11 @@ static const struct gpu_ops gm20b_ops = { nvgpu_tsg_unbind_channel_check_ctx_reload, .unbind_channel_check_eng_faulted = NULL, .check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout, -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL .force_reset = nvgpu_tsg_force_reset_ch, .post_event_id = nvgpu_tsg_post_event_id, #endif -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING .set_timeslice = nvgpu_tsg_set_timeslice, #endif .default_timeslice_us = nvgpu_tsg_default_timeslice_us, @@ -802,7 +802,7 @@ static const struct gpu_ops gm20b_ops = { .idle_slowdown_enable = gm20b_therm_idle_slowdown_enable, .idle_slowdown_disable = gm20b_therm_idle_slowdown_disable, }, -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU .pmu = { .is_pmu_supported = gm20b_is_pmu_supported, .falcon_base_addr = gk20a_pmu_falcon_base_addr, @@ -853,7 +853,7 @@ static const struct gpu_ops gm20b_ops = { .pll_reg_write = gm20b_clk_pll_reg_write, .get_pll_debug_data = gm20b_clk_get_pll_debug_data, }, -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .regops = { .exec_regops = exec_regops_gk20a, .get_global_whitelist_ranges = @@ -897,7 +897,7 @@ static const struct gpu_ops gm20b_ops = { .debug = { .show_dump = gk20a_debug_show_dump, }, -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .debugger = { .post_events = nvgpu_dbg_gpu_post_events, .dbg_set_powergate = nvgpu_dbg_set_powergate, @@ -935,7 +935,7 @@ static const struct gpu_ops gm20b_ops = { .read_ptimer = gk20a_read_ptimer, .get_timestamps_zipper = nvgpu_get_timestamps_zipper, }, -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) .css = { .enable_snapshot = nvgpu_css_enable_snapshot, .disable_snapshot = nvgpu_css_disable_snapshot, @@ -1038,7 +1038,7 @@ int gm20b_init_hal(struct gk20a *g) gops->netlist = gm20b_ops.netlist; gops->mm = gm20b_ops.mm; gops->therm = gm20b_ops.therm; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU gops->pmu = gm20b_ops.pmu; #endif /* @@ -1056,7 +1056,7 @@ int gm20b_init_hal(struct gk20a *g) gops->mc = gm20b_ops.mc; gops->debug = gm20b_ops.debug; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER gops->debugger = gm20b_ops.debugger; gops->regops = gm20b_ops.regops; gops->perf = gm20b_ops.perf; @@ -1064,7 +1064,7 @@ int gm20b_init_hal(struct gk20a *g) #endif gops->bus = gm20b_ops.bus; gops->ptimer = gm20b_ops.ptimer; -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) gops->css = gm20b_ops.css; #endif gops->falcon = gm20b_ops.falcon; @@ -1098,7 +1098,7 @@ int gm20b_init_hal(struct gk20a *g) nvgpu_gr_falcon_load_secure_ctxsw_ucode; } else { /* Inherit from gk20a */ -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU gops->pmu.setup_apertures = gm20b_pmu_ns_setup_apertures; #endif diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 3f3b81fd5..efae07a95 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -33,7 +33,7 @@ #include #include #include -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include #endif #include @@ -41,7 +41,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif @@ -99,7 +99,7 @@ #include "hal/gr/ecc/ecc_gp10b.h" #include "hal/gr/fecs_trace/fecs_trace_gm20b.h" #include "hal/gr/config/gr_config_gm20b.h" -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include "hal/gr/zbc/zbc_gp10b.h" #endif #include "hal/gr/zcull/zcull_gm20b.h" @@ -114,7 +114,7 @@ #include "hal/gr/gr/gr_gk20a.h" #include "hal/gr/gr/gr_gp10b.h" #include "hal/gr/gr/gr_gm20b.h" -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include "hal/pmu/pmu_gk20a.h" #include "hal/pmu/pmu_gm20b.h" #include "hal/pmu/pmu_gp10b.h" @@ -127,7 +127,7 @@ #include "hal/top/top_gm20b.h" #include "hal/top/top_gp10b.h" #include "hal/pramin/pramin_init.h" -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include "common/pmu/pg/pg_sw_gm20b.h" #include "common/pmu/pg/pg_sw_gp10b.h" #endif @@ -150,10 +150,10 @@ static void gp10b_init_gpu_characteristics(struct gk20a *g) static const struct gpu_ops gp10b_ops = { .ltc = { .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .init_fs_state = gp10b_ltc_init_fs_state, .flush = gm20b_flush_ltc, .set_enabled = gp10b_ltc_set_enabled, @@ -179,7 +179,7 @@ static const struct gpu_ops gp10b_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, }, .gr = { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .get_gr_status = gr_gm20b_get_gr_status, .set_alpha_circular_buffer_size = gr_gp10b_set_alpha_circular_buffer_size, @@ -215,7 +215,7 @@ static const struct gpu_ops gp10b_ops = { .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down, .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING .set_boosted_ctx = gr_gp10b_set_boosted_ctx, #endif .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception, @@ -230,7 +230,7 @@ static const struct gpu_ops gp10b_ops = { .esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events, .disable_ctxsw = nvgpu_gr_disable_ctxsw, .enable_ctxsw = nvgpu_gr_enable_ctxsw, -#endif /* NVGPU_DEBUGGER */ +#endif /* CONFIG_NVGPU_DEBUGGER */ .ecc = { .detect = gp10b_ecc_detect_enabled_units, .init = gp10b_ecc_init, @@ -251,14 +251,14 @@ static const struct gpu_ops gp10b_ops = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr, .set_zcull = gm20b_ctxsw_prog_set_zcull, .set_zcull_mode_no_ctxsw = gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw, .is_zcull_mode_separate_buffer = gm20b_ctxsw_prog_is_zcull_mode_separate_buffer, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .set_pm_ptr = gm20b_ctxsw_prog_set_pm_ptr, .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, @@ -291,7 +291,7 @@ static const struct gpu_ops gp10b_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, .hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag, @@ -315,16 +315,16 @@ static const struct gpu_ops gp10b_ops = { .get_gpc_tpc_mask = gm20b_gr_config_get_gpc_tpc_mask, .get_tpc_count_in_gpc = gm20b_gr_config_get_tpc_count_in_gpc, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .get_zcull_count_in_gpc = gm20b_gr_config_get_zcull_count_in_gpc, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask, .get_pd_dist_skip_table_size = gm20b_gr_config_get_pd_dist_skip_table_size, .init_sm_id_table = gm20b_gr_config_init_sm_id_table, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .fecs_trace = { .alloc_user_buffer = nvgpu_gr_fecs_trace_ring_alloc, .free_user_buffer = nvgpu_gr_fecs_trace_ring_free, @@ -347,18 +347,18 @@ static const struct gpu_ops gp10b_ops = { .get_write_index = gm20b_fecs_trace_get_write_index, .set_read_index = gm20b_fecs_trace_set_read_index, }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ +#endif /* CONFIG_NVGPU_FECS_TRACE */ .setup = { -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .alloc_obj_ctx = nvgpu_gr_setup_alloc_obj_ctx, .free_gr_ctx = nvgpu_gr_setup_free_gr_ctx, -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL .set_preemption_mode = nvgpu_gr_setup_set_preemption_mode, #endif }, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .zbc = { .add_color = gp10b_gr_zbc_add_color, .add_depth = gp10b_gr_zbc_add_depth, @@ -375,7 +375,7 @@ static const struct gpu_ops gp10b_ops = { .get_zcull_info = gm20b_gr_get_zcull_info, .program_zcull_mapping = gm20b_gr_program_zcull_mapping, }, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .init = { .get_no_of_sm = nvgpu_gr_get_no_of_sm, .wait_initialized = nvgpu_gr_wait_initialized, @@ -390,7 +390,7 @@ static const struct gpu_ops gp10b_ops = { .sm_id_config = gp10b_gr_init_sm_id_config, .sm_id_numbering = gm20b_gr_init_sm_id_numbering, .tpc_mask = gm20b_gr_init_tpc_mask, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .rop_mapping = gm20b_gr_init_rop_mapping, #endif .fs_state = gp10b_gr_init_fs_state, @@ -784,7 +784,7 @@ static const struct gpu_ops gp10b_ops = { .set_eng_method_buffer = NULL, }, .runlist = { -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING .reschedule = gk20a_runlist_reschedule, .reschedule_preempt_next_locked = gk20a_fifo_reschedule_preempt_next, #endif @@ -802,7 +802,7 @@ static const struct gpu_ops gp10b_ops = { .userd = { .setup_sw = nvgpu_userd_setup_sw, .cleanup_sw = nvgpu_userd_cleanup_sw, -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD .init_mem = gk20a_userd_init_mem, .gp_get = gk20a_userd_gp_get, .gp_put = gk20a_userd_gp_put, @@ -840,11 +840,11 @@ static const struct gpu_ops gp10b_ops = { nvgpu_tsg_unbind_channel_check_ctx_reload, .unbind_channel_check_eng_faulted = NULL, .check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout, -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL .force_reset = nvgpu_tsg_force_reset_ch, .post_event_id = nvgpu_tsg_post_event_id, #endif -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING .set_timeslice = nvgpu_tsg_set_timeslice, #endif .default_timeslice_us = nvgpu_tsg_default_timeslice_us, @@ -884,7 +884,7 @@ static const struct gpu_ops gp10b_ops = { .init_blcg_mode = gm20b_therm_init_blcg_mode, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, }, -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU .pmu = { .is_pmu_supported = gp10b_is_pmu_supported, .falcon_base_addr = gk20a_pmu_falcon_base_addr, @@ -937,7 +937,7 @@ static const struct gpu_ops gp10b_ops = { .clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb, .clk_arb_cleanup = gp10b_clk_arb_cleanup, }, -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .regops = { .exec_regops = exec_regops_gk20a, .get_global_whitelist_ranges = @@ -981,7 +981,7 @@ static const struct gpu_ops gp10b_ops = { .debug = { .show_dump = gk20a_debug_show_dump, }, -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .debugger = { .post_events = nvgpu_dbg_gpu_post_events, .dbg_set_powergate = nvgpu_dbg_set_powergate, @@ -1020,7 +1020,7 @@ static const struct gpu_ops gp10b_ops = { .read_ptimer = gk20a_read_ptimer, .get_timestamps_zipper = nvgpu_get_timestamps_zipper, }, -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) .css = { .enable_snapshot = nvgpu_css_enable_snapshot, .disable_snapshot = nvgpu_css_disable_snapshot, @@ -1129,13 +1129,13 @@ int gp10b_init_hal(struct gk20a *g) gops->netlist = gp10b_ops.netlist; gops->mm = gp10b_ops.mm; gops->therm = gp10b_ops.therm; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU gops->pmu = gp10b_ops.pmu; #endif gops->clk_arb = gp10b_ops.clk_arb; gops->mc = gp10b_ops.mc; gops->debug = gp10b_ops.debug; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER gops->debugger = gp10b_ops.debugger; gops->regops = gp10b_ops.regops; gops->perf = gp10b_ops.perf; @@ -1143,7 +1143,7 @@ int gp10b_init_hal(struct gk20a *g) #endif gops->bus = gp10b_ops.bus; gops->ptimer = gp10b_ops.ptimer; -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) gops->css = gp10b_ops.css; #endif gops->falcon = gp10b_ops.falcon; @@ -1177,7 +1177,7 @@ int gp10b_init_hal(struct gk20a *g) nvgpu_gr_falcon_load_secure_ctxsw_ucode; } else { /* Inherit from gk20a */ -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU gops->pmu.setup_apertures = gm20b_pmu_ns_setup_apertures; #endif diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 07b0d977f..5c23c0f07 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -28,7 +28,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif @@ -106,7 +106,7 @@ #include "hal/gr/falcon/gr_falcon_gp10b.h" #include "hal/gr/falcon/gr_falcon_gv11b.h" #include "hal/gr/config/gr_config_gm20b.h" -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include "hal/gr/zbc/zbc_gp10b.h" #include "hal/gr/zbc/zbc_gv11b.h" #include "hal/gr/zcull/zcull_gm20b.h" @@ -126,7 +126,7 @@ #include "hal/gr/gr/gr_gp10b.h" #include "hal/gr/gr/gr_gv100.h" #include "hal/gr/gr/gr_gv11b.h" -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include "hal/pmu/pmu_gk20a.h" #include "hal/pmu/pmu_gm20b.h" #endif @@ -141,7 +141,7 @@ #include "hal/top/top_gp10b.h" #include "hal/top/top_gv11b.h" -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include "common/pmu/pg/pg_sw_gm20b.h" #include "common/pmu/pg/pg_sw_gp106.h" #include "common/pmu/pg/pg_sw_gv11b.h" @@ -174,7 +174,7 @@ static void gv11b_init_gpu_characteristics(struct gk20a *g) g->ops.gr.ecc.detect(g); nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true); -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true); #endif nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true); @@ -187,11 +187,11 @@ static const struct gpu_ops gv11b_ops = { .get_ltc_err_desc = gv11b_ltc_get_err_desc, .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .init_fs_state = gv11b_ltc_init_fs_state, .flush = gm20b_flush_ltc, .set_enabled = gp10b_ltc_set_enabled, @@ -220,7 +220,7 @@ static const struct gpu_ops gv11b_ops = { gv11b_ce_mthd_buffer_fault_in_bar2_fault, }, .gr = { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .get_gr_status = gr_gm20b_get_gr_status, .set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size, @@ -259,7 +259,7 @@ static const struct gpu_ops gv11b_ops = { .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING .set_boosted_ctx = gr_gp10b_set_boosted_ctx, #endif .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, @@ -283,7 +283,7 @@ static const struct gpu_ops gv11b_ops = { .esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events, .disable_ctxsw = nvgpu_gr_disable_ctxsw, .enable_ctxsw = nvgpu_gr_enable_ctxsw, -#endif /* NVGPU_DEBUGGER */ +#endif /* CONFIG_NVGPU_DEBUGGER */ .ecc = { .detect = gv11b_ecc_detect_enabled_units, .init = gv11b_ecc_init, @@ -314,7 +314,7 @@ static const struct gpu_ops gv11b_ops = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr, .set_zcull = gm20b_ctxsw_prog_set_zcull, .set_zcull_mode_no_ctxsw = @@ -356,7 +356,7 @@ static const struct gpu_ops gv11b_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, .hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag, @@ -388,7 +388,7 @@ static const struct gpu_ops gv11b_ops = { .get_gpc_tpc_mask = gm20b_gr_config_get_gpc_tpc_mask, .get_tpc_count_in_gpc = gm20b_gr_config_get_tpc_count_in_gpc, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .get_zcull_count_in_gpc = gm20b_gr_config_get_zcull_count_in_gpc, #endif @@ -397,7 +397,7 @@ static const struct gpu_ops gv11b_ops = { gm20b_gr_config_get_pd_dist_skip_table_size, .init_sm_id_table = gv100_gr_config_init_sm_id_table, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .fecs_trace = { .alloc_user_buffer = nvgpu_gr_fecs_trace_ring_alloc, .free_user_buffer = nvgpu_gr_fecs_trace_ring_free, @@ -420,19 +420,19 @@ static const struct gpu_ops gv11b_ops = { .get_write_index = gm20b_fecs_trace_get_write_index, .set_read_index = gm20b_fecs_trace_set_read_index, }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ +#endif /* CONFIG_NVGPU_FECS_TRACE */ .setup = { -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull, #endif .alloc_obj_ctx = nvgpu_gr_setup_alloc_obj_ctx, .free_gr_ctx = nvgpu_gr_setup_free_gr_ctx, .free_subctx = nvgpu_gr_setup_free_subctx, -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL .set_preemption_mode = nvgpu_gr_setup_set_preemption_mode, #endif }, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .zbc = { .add_color = gp10b_gr_zbc_add_color, .add_depth = gp10b_gr_zbc_add_depth, @@ -449,8 +449,8 @@ static const struct gpu_ops gv11b_ops = { .get_zcull_info = gm20b_gr_get_zcull_info, .program_zcull_mapping = gv11b_gr_program_zcull_mapping, }, -#endif /* NVGPU_GRAPHICS */ -#ifdef NVGPU_DEBUGGER +#endif /* CONFIG_NVGPU_GRAPHICS */ +#ifdef CONFIG_NVGPU_DEBUGGER .hwpm_map = { .align_regs_perf_pma = gv100_gr_hwpm_map_align_regs_perf_pma, @@ -472,7 +472,7 @@ static const struct gpu_ops gv11b_ops = { .sm_id_config = gv11b_gr_init_sm_id_config, .sm_id_numbering = gv11b_gr_init_sm_id_numbering, .tpc_mask = gv11b_gr_init_tpc_mask, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .rop_mapping = gv11b_gr_init_rop_mapping, #endif .fs_state = gv11b_gr_init_fs_state, @@ -935,7 +935,7 @@ static const struct gpu_ops gv11b_ops = { .userd = { .setup_sw = nvgpu_userd_setup_sw, .cleanup_sw = nvgpu_userd_cleanup_sw, -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD .init_mem = gk20a_userd_init_mem, .gp_get = gv11b_userd_gp_get, .gp_put = gv11b_userd_gp_put, @@ -979,11 +979,11 @@ static const struct gpu_ops gv11b_ops = { .unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted, .check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout, -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL .force_reset = nvgpu_tsg_force_reset_ch, .post_event_id = nvgpu_tsg_post_event_id, #endif -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING .set_timeslice = nvgpu_tsg_set_timeslice, #endif .default_timeslice_us = nvgpu_tsg_default_timeslice_us, @@ -1059,7 +1059,7 @@ static const struct gpu_ops gv11b_ops = { gv11b_clear_pmu_bar0_host_err_status, .bar0_error_status = gv11b_pmu_bar0_error_status, .validate_mem_integrity = gv11b_pmu_validate_mem_integrity, -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU /* ISR */ .pmu_enable_irq = gk20a_pmu_enable_irq, .get_irqdest = gv11b_pmu_get_irqdest, @@ -1106,7 +1106,7 @@ static const struct gpu_ops gv11b_ops = { .clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb, .clk_arb_cleanup = gp10b_clk_arb_cleanup, }, -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .regops = { .exec_regops = exec_regops_gk20a, .get_global_whitelist_ranges = @@ -1153,7 +1153,7 @@ static const struct gpu_ops gv11b_ops = { .debug = { .show_dump = gk20a_debug_show_dump, }, -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .debugger = { .post_events = nvgpu_dbg_gpu_post_events, .dbg_set_powergate = nvgpu_dbg_set_powergate, @@ -1192,7 +1192,7 @@ static const struct gpu_ops gv11b_ops = { .read_ptimer = gk20a_read_ptimer, .get_timestamps_zipper = nvgpu_get_timestamps_zipper, }, -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) .css = { .enable_snapshot = nvgpu_css_enable_snapshot, .disable_snapshot = nvgpu_css_disable_snapshot, @@ -1306,7 +1306,7 @@ int gv11b_init_hal(struct gk20a *g) gops->pmu = gv11b_ops.pmu; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER gops->debugger = gv11b_ops.debugger; gops->regops = gv11b_ops.regops; gops->perf = gv11b_ops.perf; @@ -1314,7 +1314,7 @@ int gv11b_init_hal(struct gk20a *g) #endif gops->bus = gv11b_ops.bus; gops->ptimer = gv11b_ops.ptimer; -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) gops->css = gv11b_ops.css; #endif gops->falcon = gv11b_ops.falcon; @@ -1342,7 +1342,7 @@ int gv11b_init_hal(struct gk20a *g) gops->gr.falcon.load_ctxsw_ucode = nvgpu_gr_falcon_load_secure_ctxsw_ucode; } else { -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU /* non-secure boot */ gops->pmu.setup_apertures = gm20b_pmu_ns_setup_apertures; diff --git a/drivers/gpu/nvgpu/hal/init/hal_init.c b/drivers/gpu/nvgpu/hal/init/hal_init.c index bda459ce4..df945e111 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_init.c +++ b/drivers/gpu/nvgpu/hal/init/hal_init.c @@ -31,7 +31,7 @@ #include "hal_gm20b.h" #include "hal_gp10b.h" #include "hal_gv11b.h" -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU #include "hal_tu104.h" #endif @@ -63,7 +63,7 @@ int nvgpu_init_hal(struct gk20a *g) return -ENODEV; } break; -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU #if defined(CONFIG_NVGPU_SUPPORT_TURING) case NVGPU_GPUID_TU104: if (tu104_init_hal(g) != 0) { diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 05e8480d3..a4cfdf92b 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -114,7 +114,7 @@ #include "hal/gr/falcon/gr_falcon_gv11b.h" #include "hal/gr/config/gr_config_gm20b.h" #include "hal/gr/config/gr_config_gv100.h" -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include "hal/gr/zbc/zbc_gp10b.h" #include "hal/gr/zbc/zbc_gv11b.h" #include "hal/gr/zcull/zcull_gm20b.h" @@ -147,7 +147,7 @@ #include "hal/nvdec/nvdec_tu104.h" #include "hal/gsp/gsp_gv100.h" #include "hal/perf/perf_gv11b.h" -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU #include "hal/sec2/sec2_tu104.h" #endif #include "hal/sync/syncpt_cmdbuf_gv11b.h" @@ -194,7 +194,7 @@ #include #include #include -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include #endif #include @@ -229,11 +229,11 @@ static const struct gpu_ops tu104_ops = { }, .ltc = { .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ .init_fs_state = ltc_tu104_init_fs_state, .flush = gm20b_flush_ltc, .set_enabled = gp10b_ltc_set_enabled, @@ -264,7 +264,7 @@ static const struct gpu_ops tu104_ops = { gv11b_ce_mthd_buffer_fault_in_bar2_fault, }, .gr = { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .get_gr_status = gr_gm20b_get_gr_status, .set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size, @@ -303,7 +303,7 @@ static const struct gpu_ops tu104_ops = { .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING .set_boosted_ctx = gr_gp10b_set_boosted_ctx, #endif .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, @@ -326,7 +326,7 @@ static const struct gpu_ops tu104_ops = { .esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events, .disable_ctxsw = nvgpu_gr_disable_ctxsw, .enable_ctxsw = nvgpu_gr_enable_ctxsw, -#endif /* NVGPU_DEBUGGER */ +#endif /* CONFIG_NVGPU_DEBUGGER */ .ecc = { .detect = NULL, .init = tu104_ecc_init, @@ -347,7 +347,7 @@ static const struct gpu_ops tu104_ops = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr, .set_zcull = gm20b_ctxsw_prog_set_zcull, .set_zcull_mode_no_ctxsw = @@ -389,7 +389,7 @@ static const struct gpu_ops tu104_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, .hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag, @@ -422,7 +422,7 @@ static const struct gpu_ops tu104_ops = { .get_gpc_tpc_mask = gm20b_gr_config_get_gpc_tpc_mask, .get_tpc_count_in_gpc = gm20b_gr_config_get_tpc_count_in_gpc, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .get_zcull_count_in_gpc = gm20b_gr_config_get_zcull_count_in_gpc, #endif @@ -431,7 +431,7 @@ static const struct gpu_ops tu104_ops = { gm20b_gr_config_get_pd_dist_skip_table_size, .init_sm_id_table = gv100_gr_config_init_sm_id_table, }, -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE .fecs_trace = { .alloc_user_buffer = nvgpu_gr_fecs_trace_ring_alloc, .free_user_buffer = nvgpu_gr_fecs_trace_ring_free, @@ -454,19 +454,19 @@ static const struct gpu_ops tu104_ops = { .get_write_index = gm20b_fecs_trace_get_write_index, .set_read_index = gm20b_fecs_trace_set_read_index, }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ +#endif /* CONFIG_NVGPU_FECS_TRACE */ .setup = { -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull, #endif .alloc_obj_ctx = nvgpu_gr_setup_alloc_obj_ctx, .free_gr_ctx = nvgpu_gr_setup_free_gr_ctx, .free_subctx = nvgpu_gr_setup_free_subctx, -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL .set_preemption_mode = nvgpu_gr_setup_set_preemption_mode, #endif }, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .zbc = { .add_color = gp10b_gr_zbc_add_color, .add_depth = gp10b_gr_zbc_add_depth, @@ -483,8 +483,8 @@ static const struct gpu_ops tu104_ops = { .get_zcull_info = gm20b_gr_get_zcull_info, .program_zcull_mapping = gv11b_gr_program_zcull_mapping, }, -#endif /* NVGPU_GRAPHICS */ -#ifdef NVGPU_DEBUGGER +#endif /* CONFIG_NVGPU_GRAPHICS */ +#ifdef CONFIG_NVGPU_DEBUGGER .hwpm_map = { .align_regs_perf_pma = gv100_gr_hwpm_map_align_regs_perf_pma, @@ -508,7 +508,7 @@ static const struct gpu_ops tu104_ops = { .sm_id_config = gv11b_gr_init_sm_id_config, .sm_id_numbering = gv11b_gr_init_sm_id_numbering, .tpc_mask = gv11b_gr_init_tpc_mask, -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS .rop_mapping = gv11b_gr_init_rop_mapping, #endif .fs_state = gv11b_gr_init_fs_state, @@ -976,7 +976,7 @@ static const struct gpu_ops tu104_ops = { .userd = { .setup_sw = nvgpu_userd_setup_sw, .cleanup_sw = nvgpu_userd_cleanup_sw, -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD .init_mem = gk20a_userd_init_mem, .gp_get = gv11b_userd_gp_get, .gp_put = gv11b_userd_gp_put, @@ -1020,11 +1020,11 @@ static const struct gpu_ops tu104_ops = { .unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted, .check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout, -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL .force_reset = nvgpu_tsg_force_reset_ch, .post_event_id = nvgpu_tsg_post_event_id, #endif -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING .set_timeslice = nvgpu_tsg_set_timeslice, #endif .default_timeslice_us = nvgpu_tsg_default_timeslice_us, @@ -1076,14 +1076,14 @@ static const struct gpu_ops tu104_ops = { .init_elcg_mode = gv11b_therm_init_elcg_mode, .init_blcg_mode = gm20b_therm_init_blcg_mode, .elcg_init_idle_filters = NULL, -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU .get_internal_sensor_curr_temp = gp106_get_internal_sensor_curr_temp, .get_internal_sensor_limits = gp106_get_internal_sensor_limits, #endif }, -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU .pmu = { .falcon_base_addr = gp106_pmu_falcon_base_addr, .pmu_queue_tail = gk20a_pmu_queue_tail, @@ -1144,7 +1144,7 @@ static const struct gpu_ops tu104_ops = { .stop_clk_arb_threads = gv100_stop_clk_arb_threads, }, #endif -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .regops = { .exec_regops = exec_regops_gk20a, .get_global_whitelist_ranges = @@ -1193,7 +1193,7 @@ static const struct gpu_ops tu104_ops = { .debug = { .show_dump = gk20a_debug_show_dump, }, -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER .debugger = { .post_events = nvgpu_dbg_gpu_post_events, .dbg_set_powergate = nvgpu_dbg_set_powergate, @@ -1234,7 +1234,7 @@ static const struct gpu_ops tu104_ops = { .read_ptimer = gk20a_read_ptimer, .get_timestamps_zipper = nvgpu_get_timestamps_zipper, }, -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) .css = { .enable_snapshot = nvgpu_css_enable_snapshot, .disable_snapshot = nvgpu_css_disable_snapshot, @@ -1306,7 +1306,7 @@ static const struct gpu_ops tu104_ops = { .read_vin_cal_gain_offset_fuse = gp106_fuse_read_vin_cal_gain_offset_fuse, }, -#if defined(CONFIG_TEGRA_NVLINK) +#if defined(CONFIG_NVGPU_NVLINK) .nvlink = { .get_link_reset_mask = gv100_nvlink_get_link_reset_mask, .discover_ioctrl = gv100_nvlink_discover_ioctrl, @@ -1358,7 +1358,7 @@ static const struct gpu_ops tu104_ops = { } }, #endif -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU .sec2 = { .secured_sec2_start = tu104_start_sec2_secure, .enable_irq = tu104_sec2_enable_irq, @@ -1436,12 +1436,12 @@ int tu104_init_hal(struct gk20a *g) gops->netlist = tu104_ops.netlist; gops->mm = tu104_ops.mm; gops->therm = tu104_ops.therm; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU gops->pmu = tu104_ops.pmu; #endif gops->mc = tu104_ops.mc; gops->debug = tu104_ops.debug; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER gops->debugger = tu104_ops.debugger; gops->regops = tu104_ops.regops; gops->perf = tu104_ops.perf; @@ -1449,7 +1449,7 @@ int tu104_init_hal(struct gk20a *g) #endif gops->bus = tu104_ops.bus; gops->ptimer = tu104_ops.ptimer; -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) gops->css = tu104_ops.css; #endif gops->xve = tu104_ops.xve; @@ -1457,7 +1457,7 @@ int tu104_init_hal(struct gk20a *g) gops->priv_ring = tu104_ops.priv_ring; gops->fuse = tu104_ops.fuse; gops->nvlink = tu104_ops.nvlink; -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU gops->sec2 = tu104_ops.sec2; #endif gops->gsp = tu104_ops.gsp; @@ -1505,7 +1505,7 @@ int tu104_init_hal(struct gk20a *g) gops->pmu_perf.support_vfe = true; gops->clk.support_vf_point = true; gops->clk.lut_num_entries = CTRL_CLK_LUT_NUM_ENTRIES_GV10x; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU gops->clk.perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35; #endif nvgpu_pramin_ops_init(g); diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c index 9870b485f..0effca402 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c @@ -207,7 +207,7 @@ u64 gm20b_determine_L2_size_bytes(struct gk20a *g) return cache_size; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS /* * Sets the ZBC color for the passed index. */ @@ -242,7 +242,7 @@ void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), depth_val); } -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled) { diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.h b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.h index a49af5a48..012c91d5e 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.h +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.h @@ -31,14 +31,14 @@ struct gk20a; struct gr_gk20a; u64 gm20b_determine_L2_size_bytes(struct gk20a *g); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void gm20b_ltc_set_zbc_color_entry(struct gk20a *g, u32 *color_l2, u32 index); void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, u32 depth_val, u32 index); -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled); void gm20b_ltc_init_fs_state(struct gk20a *g); void gm20b_flush_ltc(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c index dc914cdb2..3e11bbc69 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c @@ -75,7 +75,7 @@ int gv11b_ltc_inject_ecc_error(struct gk20a *g, return 0; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS /* * Sets the ZBC stencil for the passed index. */ @@ -90,7 +90,7 @@ void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(), stencil_depth); } -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ void gv11b_ltc_init_fs_state(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.h b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.h index ea66e066b..7ca5459c9 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.h +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.h @@ -30,11 +30,11 @@ struct gk20a; struct nvgpu_hw_err_inject_info; struct nvgpu_hw_err_inject_info_desc; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, u32 stencil_depth, u32 index); -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ void gv11b_ltc_init_fs_state(struct gk20a *g); struct nvgpu_hw_err_inject_info_desc * gv11b_ltc_get_err_desc(struct gk20a *g); int gv11b_ltc_inject_ecc_error(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c index 1460a6c24..ba0b66b33 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c @@ -74,7 +74,7 @@ void gm20b_mc_isr_stall(struct gk20a *g) if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) { g->ops.fifo.intr_0_isr(g); } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { g->ops.pmu.pmu_isr(g); } diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c index 6e2a53e2f..738c8c638 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c @@ -134,7 +134,7 @@ void mc_gp10b_isr_stall(struct gk20a *g) if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) { g->ops.fifo.intr_0_isr(g); } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { g->ops.pmu.pmu_isr(g); } diff --git a/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b.c b/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b.c index 25116f702..faef0485f 100644 --- a/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b.c +++ b/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b.c @@ -46,7 +46,7 @@ #include "hal/fb/fb_mmu_fault_gv11b.h" #include "hal/mm/mmu_fault/mmu_fault_gv11b.h" -#ifdef NVGPU_REPLAYABLE_FAULT +#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT static int gv11b_fb_fix_page_fault(struct gk20a *g, struct mmu_fault_info *mmufault); #endif @@ -307,7 +307,7 @@ void gv11b_mm_mmu_fault_handle_mmu_fault_common(struct gk20a *g, gmmu_fault_mmu_eng_id_ce0_v() + num_lce)) { /* CE page faults are not reported as replayable */ nvgpu_log(g, gpu_dbg_intr, "CE Faulted"); -#ifdef NVGPU_REPLAYABLE_FAULT +#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT err = gv11b_fb_fix_page_fault(g, mmufault); #else err = -EINVAL; @@ -407,7 +407,7 @@ void gv11b_mm_mmu_fault_handle_mmu_fault_common(struct gk20a *g, } else { if (mmufault->fault_type == gmmu_fault_type_pte_v()) { nvgpu_log(g, gpu_dbg_intr, "invalid pte! try to fix"); -#ifdef NVGPU_REPLAYABLE_FAULT +#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT err = gv11b_fb_fix_page_fault(g, mmufault); #else err = -EINVAL; @@ -550,7 +550,7 @@ void gv11b_mm_mmu_fault_handle_other_fault_notify(struct gk20a *g, } } -#ifdef NVGPU_REPLAYABLE_FAULT +#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT static int gv11b_fb_fix_page_fault(struct gk20a *g, struct mmu_fault_info *mmufault) { diff --git a/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_gv100.c b/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_gv100.c index 924eefb76..567377f44 100644 --- a/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_gv100.c +++ b/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_gv100.c @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK #include #include @@ -757,4 +757,4 @@ u32 gv100_nvlink_link_get_rx_sublink_state(struct gk20a *g, u32 link_id) return nvl_sl1_slsm_status_rx_primary_state_v(reg); } -#endif /* CONFIG_TEGRA_NVLINK */ +#endif /* CONFIG_NVGPU_NVLINK */ diff --git a/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_tu104.c b/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_tu104.c index d98f9d37a..357657084 100644 --- a/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_tu104.c +++ b/drivers/gpu/nvgpu/hal/nvlink/link_mode_transitions_tu104.c @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK #include #include @@ -194,4 +194,4 @@ int tu104_nvlink_data_ready_en(struct gk20a *g, } return ret; } -#endif /* CONFIG_TEGRA_NVLINK */ +#endif /* CONFIG_NVGPU_NVLINK */ diff --git a/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c b/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c index 9036df151..9f7d385c2 100644 --- a/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c +++ b/drivers/gpu/nvgpu/hal/nvlink/minion_gv100.c @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK #include #include @@ -408,4 +408,4 @@ void gv100_nvlink_minion_isr(struct gk20a *g) { return; } -#endif /* CONFIG_TEGRA_NVLINK */ +#endif /* CONFIG_NVGPU_NVLINK */ diff --git a/drivers/gpu/nvgpu/hal/nvlink/minion_tu104.c b/drivers/gpu/nvgpu/hal/nvlink/minion_tu104.c index 45287657d..61fe41b9a 100644 --- a/drivers/gpu/nvgpu/hal/nvlink/minion_tu104.c +++ b/drivers/gpu/nvgpu/hal/nvlink/minion_tu104.c @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK #include @@ -60,4 +60,4 @@ u32 tu104_nvlink_minion_get_dlcmd_ordinal(struct gk20a *g, return dlcmd_ordinal; } -#endif /* CONFIG_TEGRA_NVLINK */ +#endif /* CONFIG_NVGPU_NVLINK */ diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gp106.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gp106.c index b3cf07cf9..7784a8d50 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gp106.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gp106.c @@ -61,7 +61,7 @@ int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset) return 0; } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU void gp106_pmu_setup_apertures(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c index ea783d74c..c61d2c197 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c @@ -29,7 +29,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif @@ -74,7 +74,7 @@ int gv11b_pmu_inject_ecc_error(struct gk20a *g, return 0; } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU /* PROD settings for ELPG sequencing registers*/ static struct pg_init_sequence_list _pginitseq_gv11b[] = { {0x0010e0a8U, 0x00000000U} , @@ -618,7 +618,7 @@ void gv11b_secured_pmu_start(struct gk20a *g) bool gv11b_is_pmu_supported(struct gk20a *g) { -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU return true; #else /* set to false to disable LS PMU ucode support */ diff --git a/drivers/gpu/nvgpu/hal/pramin/pramin_init.c b/drivers/gpu/nvgpu/hal/pramin/pramin_init.c index 8e33d04a1..72efe93df 100644 --- a/drivers/gpu/nvgpu/hal/pramin/pramin_init.c +++ b/drivers/gpu/nvgpu/hal/pramin/pramin_init.c @@ -24,7 +24,7 @@ #include "pramin_init.h" #include "pramin_gp10b.h" -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU #include "pramin_gv100.h" #include "pramin_tu104.h" #endif @@ -37,7 +37,7 @@ void nvgpu_pramin_ops_init(struct gk20a *g) case NVGPU_GPUID_GP10B: g->ops.pramin.data032_r = gp10b_pramin_data032_r; break; -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU case NVGPU_GPUID_GV100: g->ops.pramin.data032_r = gv100_pramin_data032_r; break; diff --git a/drivers/gpu/nvgpu/hal/rc/rc_gv11b.c b/drivers/gpu/nvgpu/hal/rc/rc_gv11b.c index 5274e70f0..3d07b9c97 100644 --- a/drivers/gpu/nvgpu/hal/rc/rc_gv11b.c +++ b/drivers/gpu/nvgpu/hal/rc/rc_gv11b.c @@ -38,7 +38,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #endif @@ -54,7 +54,7 @@ static void gv11b_fifo_locked_abort_runlist_active_tsgs(struct gk20a *g, struct nvgpu_tsg *tsg = NULL; unsigned long tsgid; struct nvgpu_runlist_info *runlist = NULL; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU u32 token = PMU_INVALID_MUTEX_OWNER_ID; int mutex_ret = 0; #endif @@ -63,7 +63,7 @@ static void gv11b_fifo_locked_abort_runlist_active_tsgs(struct gk20a *g, nvgpu_err(g, "abort active tsgs of runlists set in " "runlists_mask: 0x%08x", runlists_mask); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU /* runlist_lock are locked by teardown */ mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); @@ -92,10 +92,10 @@ static void gv11b_fifo_locked_abort_runlist_active_tsgs(struct gk20a *g, nvgpu_tsg_reset_faulted_eng_pbdma(g, tsg, true, true); -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE nvgpu_gr_fecs_trace_add_tsg_reset(g, tsg); #endif -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER if (!g->fifo.deferred_reset_pending) { #endif if (rc_type == RC_TYPE_MMU_FAULT) { @@ -106,7 +106,7 @@ static void gv11b_fifo_locked_abort_runlist_active_tsgs(struct gk20a *g, */ (void) nvgpu_tsg_mark_error(g, tsg); } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER } #endif @@ -126,7 +126,7 @@ static void gv11b_fifo_locked_abort_runlist_active_tsgs(struct gk20a *g, nvgpu_log(g, gpu_dbg_info, "aborted tsg id %lu", tsgid); } } -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU if (mutex_ret == 0) { err = nvgpu_pmu_lock_release(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); @@ -150,7 +150,7 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask, struct nvgpu_runlist_info *runlist = NULL; u32 engine_id; struct nvgpu_fifo *f = &g->fifo; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER u32 client_type = ~U32(0U); bool deferred_reset_pending = false; #endif @@ -197,7 +197,7 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask, if (rc_type == RC_TYPE_MMU_FAULT) { gk20a_debug_dump(g); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER client_type = mmufault->client_type; #endif nvgpu_tsg_reset_faulted_eng_pbdma(g, tsg, true, true); @@ -225,7 +225,7 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask, nvgpu_preempt_poll_tsg_on_pbdma(g, tsg); } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_mutex_acquire(&f->deferred_reset_mutex); g->fifo.deferred_reset_pending = false; nvgpu_mutex_release(&f->deferred_reset_mutex); @@ -246,7 +246,7 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask, engine_id = U32(bit); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER if ((tsg != NULL) && nvgpu_engine_should_defer_reset(g, engine_id, client_type, false)) { @@ -265,18 +265,18 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask, } else { #endif nvgpu_engine_reset(g, engine_id); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER } #endif } } -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE if (tsg != NULL) nvgpu_gr_fecs_trace_add_tsg_reset(g, tsg); #endif if (tsg != NULL) { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER if (deferred_reset_pending) { g->ops.tsg.disable(tsg); } else { @@ -286,7 +286,7 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask, } (void)nvgpu_tsg_mark_error(g, tsg); nvgpu_tsg_abort(g, tsg, false); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER } #endif } else { diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h index d32dd1ad3..b6726deb3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h @@ -211,7 +211,7 @@ struct nvgpu_channel_joblist { struct nvgpu_mutex cleanup_lock; }; -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT struct nvgpu_channel_wdt { /* lock protects the running timer state */ @@ -322,7 +322,7 @@ struct nvgpu_channel { struct nvgpu_cond notifier_wq; struct nvgpu_cond semaphore_wq; -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT /* kernel watchdog to kill stuck jobs */ struct nvgpu_channel_wdt wdt; #endif @@ -330,7 +330,7 @@ struct nvgpu_channel { /* for job cleanup handling in the background worker */ struct nvgpu_list_node worker_item; -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) struct { void *cyclestate_buffer; u32 cyclestate_buffer_size; @@ -382,7 +382,7 @@ struct nvgpu_channel { bool has_os_fence_framework_support; bool is_privileged_channel; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER bool mmu_debug_mode_enabled; #endif }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/fifo.h b/drivers/gpu/nvgpu/include/nvgpu/fifo.h index 23ce2539f..963053302 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/fifo.h +++ b/drivers/gpu/nvgpu/include/nvgpu/fifo.h @@ -119,7 +119,7 @@ struct nvgpu_fifo { } intr; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER unsigned long deferred_fault_engines; bool deferred_reset_pending; struct nvgpu_mutex deferred_reset_mutex; diff --git a/drivers/gpu/nvgpu/include/nvgpu/fifo/userd.h b/drivers/gpu/nvgpu/include/nvgpu/fifo/userd.h index 2adeea5ff..83368072f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/fifo/userd.h +++ b/drivers/gpu/nvgpu/include/nvgpu/fifo/userd.h @@ -32,7 +32,7 @@ int nvgpu_userd_setup_sw(struct gk20a *g); void nvgpu_userd_cleanup_sw(struct gk20a *g); int nvgpu_userd_init_channel(struct gk20a *g, struct nvgpu_channel *c); -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD int nvgpu_userd_init_slabs(struct gk20a *g); void nvgpu_userd_free_slabs(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 257808893..d66363fc0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -47,7 +47,7 @@ struct nvgpu_gpu_ctxsw_trace_entry; struct nvgpu_cpu_time_correlation_sample; struct nvgpu_warpstate; struct nvgpu_clk_arb; -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE struct nvgpu_gpu_ctxsw_trace_filter; #endif struct priv_cmd_entry; @@ -62,7 +62,7 @@ struct nvgpu_sgt; struct nvgpu_sgl; struct nvgpu_device_info; struct nvgpu_gr_subctx; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_gr_zbc; struct nvgpu_gr_zbc_entry; struct nvgpu_gr_zbc_query_params; @@ -217,7 +217,7 @@ struct gpu_ops { u64 (*determine_L2_size_bytes)(struct gk20a *gk20a); struct nvgpu_hw_err_inject_info_desc * (*get_ltc_err_desc) (struct gk20a *g); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void (*set_zbc_color_entry)(struct gk20a *g, u32 *color_val_l2, u32 index); @@ -263,7 +263,7 @@ struct gpu_ops { void (*mthd_buffer_fault_in_bar2_fault)(struct gk20a *g); } ce; struct { -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER u32 (*get_gr_status)(struct gk20a *g); void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset); void (*set_alpha_circular_buffer_size)(struct gk20a *g, @@ -344,7 +344,7 @@ struct gpu_ops { struct vm_gk20a *vm, u32 class, u32 graphics_preempt_mode, u32 compute_preempt_mode); -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING int (*set_boosted_ctx)(struct nvgpu_channel *ch, bool boost); #endif int (*trigger_suspend)(struct gk20a *g); @@ -423,7 +423,7 @@ struct gpu_ops { struct nvgpu_mem *ctx_mem, u32 count); void (*set_patch_addr)(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void (*set_zcull_ptr)(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); void (*set_zcull)(struct gk20a *g, @@ -468,7 +468,7 @@ struct gpu_ops { void (*get_ppc_info)(u32 *context, u32 *num_ppcs, u32 *ppc_mask); u32 (*get_local_priv_register_ctl_offset)(u32 *context); -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE u32 (*hw_get_ts_tag_invalid_timestamp)(void); u32 (*hw_get_ts_tag)(u64 ts); u64 (*hw_record_ts_timestamp)(u64 ts); @@ -504,7 +504,7 @@ struct gpu_ops { struct nvgpu_gr_config *config, u32 gpc_index); u32 (*get_tpc_count_in_gpc)(struct gk20a *g, struct nvgpu_gr_config *config, u32 gpc_index); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS u32 (*get_zcull_count_in_gpc)(struct gk20a *g, struct nvgpu_gr_config *config, u32 gpc_index); #endif @@ -576,7 +576,7 @@ struct gpu_ops { u32 (*read_fecs_ctxsw_status1)(struct gk20a *g); } falcon; -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE struct { int (*init)(struct gk20a *g); int (*max_entries)(struct gk20a *, @@ -613,7 +613,7 @@ struct gpu_ops { #endif struct { -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS int (*bind_ctxsw_zcull)(struct gk20a *g, struct nvgpu_channel *c, u64 zcull_va, @@ -625,13 +625,13 @@ struct gpu_ops { struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx); void (*free_subctx)(struct nvgpu_channel *c); -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL int (*set_preemption_mode)(struct nvgpu_channel *ch, u32 graphics_preempt_mode, u32 compute_preempt_mode); #endif } setup; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct { int (*add_color)(struct gk20a *g, struct nvgpu_gr_zbc_entry *color_val, @@ -665,9 +665,9 @@ struct gpu_ops { u32 zcull_alloc_num, u32 *zcull_map_tiles); } zcull; -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER struct { void (*align_regs_perf_pma)(u32 *offset); u32 (*get_active_fbpa_mask)(struct gk20a *g); @@ -696,10 +696,10 @@ struct gpu_ops { struct nvgpu_gr_config *gr_config); void (*tpc_mask)(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void (*rop_mapping)(struct gk20a *g, struct nvgpu_gr_config *gr_config); -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ int (*fs_state)(struct gk20a *g); void (*pd_tpc_per_gpc)(struct gk20a *g, struct nvgpu_gr_config *gr_config); @@ -1228,7 +1228,7 @@ struct gpu_ops { struct nvgpu_channel_hw_state *state); bool (*check_ctxsw_timeout)(struct nvgpu_tsg *tsg, bool *verbose, u32 *ms); -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL int (*force_reset)(struct nvgpu_channel *ch, u32 err_code, bool verbose); void (*post_event_id)(struct nvgpu_tsg *tsg, @@ -1366,7 +1366,7 @@ struct gpu_ops { void (*secured_pmu_start)(struct gk20a *g); void (*flcn_setup_boot_config)(struct gk20a *g); bool (*validate_mem_integrity)(struct gk20a *g); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU /* ISR */ void (*pmu_enable_irq)(struct nvgpu_pmu *pmu, bool enable); bool (*pmu_is_interrupted)(struct nvgpu_pmu *pmu); @@ -1480,7 +1480,7 @@ struct gpu_ops { bool support_changeseq; bool support_vfe; } pmu_perf; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER struct { int (*exec_regops)(struct gk20a *g, struct nvgpu_channel *ch, @@ -1533,7 +1533,7 @@ struct gpu_ops { void (*show_dump)(struct gk20a *g, struct nvgpu_debug_context *o); } debug; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER struct { void (*post_events)(struct nvgpu_channel *ch); int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, @@ -1592,7 +1592,7 @@ struct gpu_ops { u32 (*get_aon_secure_scratch_reg)(struct gk20a *g, u32 i); } bios; -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) struct { int (*enable_snapshot)(struct nvgpu_channel *ch, struct gk20a_cs_snapshot_client *client); @@ -1955,13 +1955,13 @@ struct gk20a { /*refcount for timeout disable */ nvgpu_atomic_t timeouts_disabled_refcount; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER /* must have dbg_sessions_lock before use */ struct nvgpu_dbg_reg_op *dbg_regops_tmp_buf; u32 dbg_regops_tmp_buf_ops; #endif -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) struct nvgpu_mutex cs_lock; struct gk20a_cs_snapshot *cs_data; #endif @@ -2025,7 +2025,7 @@ struct gk20a { struct nvgpu_channel_worker { struct nvgpu_worker worker; -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT u32 watchdog_interval; struct nvgpu_timeout timeout; #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/config.h b/drivers/gpu/nvgpu/include/nvgpu/gr/config.h index 6c8f4718a..072be1356 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/config.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/config.h @@ -40,7 +40,7 @@ u32 nvgpu_gr_config_get_gpc_count(struct nvgpu_gr_config *config); u32 nvgpu_gr_config_get_tpc_count(struct nvgpu_gr_config *config); u32 nvgpu_gr_config_get_ppc_count(struct nvgpu_gr_config *config); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS int nvgpu_gr_config_init_map_tiles(struct gk20a *g, struct nvgpu_gr_config *config); u32 nvgpu_gr_config_get_map_row_offset(struct nvgpu_gr_config *config); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h index 551a59103..863bcdd32 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h @@ -52,7 +52,7 @@ struct patch_desc; struct pm_ctx_desc; struct nvgpu_gr_ctx_desc; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct zcull_ctx_desc; #endif @@ -175,7 +175,7 @@ void nvgpu_gr_ctx_set_patch_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, u32 nvgpu_gr_ctx_get_ctx_id(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void nvgpu_gr_ctx_set_zcull_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, u32 mode, u64 gpu_va); @@ -229,7 +229,7 @@ void nvgpu_gr_ctx_set_cilp_preempt_pending(struct nvgpu_gr_ctx *gr_ctx, u32 nvgpu_gr_ctx_read_ctx_id(struct nvgpu_gr_ctx *gr_ctx); -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING void nvgpu_gr_ctx_set_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx, bool boost); bool nvgpu_gr_ctx_get_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/global_ctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/global_ctx.h index e9c49ca86..640510da3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/global_ctx.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/global_ctx.h @@ -39,7 +39,7 @@ typedef void (*global_ctx_mem_destroy_fn)(struct gk20a *g, #define NVGPU_GR_GLOBAL_CTX_PAGEPOOL 1U #define NVGPU_GR_GLOBAL_CTX_ATTRIBUTE 2U -#ifdef NVGPU_VPR +#ifdef CONFIG_NVGPU_VPR #define NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR 3U #define NVGPU_GR_GLOBAL_CTX_PAGEPOOL_VPR 4U #define NVGPU_GR_GLOBAL_CTX_ATTRIBUTE_VPR 5U diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h index a56c70e70..238943adc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h @@ -109,7 +109,7 @@ u32 nvgpu_gr_falcon_get_golden_image_size(struct nvgpu_gr_falcon *falcon); u32 nvgpu_gr_falcon_get_pm_ctxsw_image_size(struct nvgpu_gr_falcon *falcon); u32 nvgpu_gr_falcon_get_preempt_image_size(struct nvgpu_gr_falcon *falcon); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS u32 nvgpu_gr_falcon_get_zcull_image_size(struct nvgpu_gr_falcon *falcon); #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h index b5e33d1e8..2c585afbe 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h @@ -28,7 +28,7 @@ struct nvgpu_gr_falcon; struct nvgpu_gr_obj_ctx_golden_image; struct nvgpu_gr_config; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_gr_zbc; struct nvgpu_gr_zcull; #endif @@ -40,16 +40,16 @@ struct nvgpu_gr_global_ctx_buffer_desc; struct nvgpu_gr_falcon *nvgpu_gr_get_falcon_ptr(struct gk20a *g); struct nvgpu_gr_obj_ctx_golden_image *nvgpu_gr_get_golden_image_ptr( struct gk20a *g); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_gr_zcull *nvgpu_gr_get_zcull_ptr(struct gk20a *g); struct nvgpu_gr_zbc *nvgpu_gr_get_zbc_ptr(struct gk20a *g); #endif struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER struct nvgpu_gr_hwpm_map *nvgpu_gr_get_hwpm_map_ptr(struct gk20a *g); #endif struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g); -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE struct nvgpu_gr_global_ctx_buffer_desc *nvgpu_gr_get_global_ctx_buffer_ptr( struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h b/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h index 4689f334b..2ba25d767 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h @@ -29,7 +29,7 @@ struct nvgpu_channel; struct vm_gk20a; struct nvgpu_gr_ctx; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS int nvgpu_gr_setup_bind_ctxsw_zcull(struct gk20a *g, struct nvgpu_channel *c, u64 zcull_va, u32 mode); #endif @@ -40,7 +40,7 @@ void nvgpu_gr_setup_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx); void nvgpu_gr_setup_free_subctx(struct nvgpu_channel *c); -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL int nvgpu_gr_setup_set_preemption_mode(struct nvgpu_channel *ch, u32 graphics_preempt_mode, u32 compute_preempt_mode); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h index ce6d42e49..5014e9639 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h @@ -40,7 +40,7 @@ void nvgpu_gr_subctx_load_ctx_header(struct gk20a *g, struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx, u64 gpu_va); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS void nvgpu_gr_subctx_zcull_setup(struct gk20a *g, struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx); #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/mm.h b/drivers/gpu/nvgpu/include/nvgpu/mm.h index 0b2567168..1cf94122a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/mm.h @@ -104,7 +104,7 @@ struct mm_gk20a { struct nvgpu_mem hw_fault_buf[NVGPU_MMU_FAULT_TYPE_NUM]; struct mmu_fault_info fault_info[NVGPU_MMU_FAULT_TYPE_NUM]; struct nvgpu_mutex hub_isr_mutex; -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE /* * Separate function to cleanup the CE since it requires a channel to * be closed which must happen before fifo cleanup. @@ -178,7 +178,7 @@ static inline u64 nvgpu_gmmu_va_small_page_limit(void) return ((u64)SZ_1G * 56U); } -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE void nvgpu_init_mm_ce_context(struct gk20a *g); #endif int nvgpu_init_mm_support(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/netlist.h b/drivers/gpu/nvgpu/include/nvgpu/netlist.h index 480f231dc..3e2437f30 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/netlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/netlist.h @@ -104,7 +104,7 @@ struct netlist_u32_list *nvgpu_netlist_get_gpccs_data(struct gk20a *g); struct netlist_aiv_list *nvgpu_netlist_get_sys_ctxsw_regs(struct gk20a *g); struct netlist_aiv_list *nvgpu_netlist_get_gpc_ctxsw_regs(struct gk20a *g); struct netlist_aiv_list *nvgpu_netlist_get_tpc_ctxsw_regs(struct gk20a *g); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct netlist_aiv_list *nvgpu_netlist_get_zcull_gpc_ctxsw_regs( struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index c0dc733d8..a96c20e1a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -31,7 +31,7 @@ #include #include #include -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU #include #include #include @@ -89,7 +89,7 @@ struct nvgpu_clk_pmupstate; /* pmu load const defines */ #define PMU_BUSY_CYCLES_NORM_MAX (1000U) -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU struct rpc_handler_payload { void *rpc_buff; bool is_mem_free_set; @@ -154,7 +154,7 @@ struct nvgpu_pmu { bool isr_enabled; struct nvgpu_mutex isr_mutex; struct nvgpu_falcon *flcn; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU struct nvgpu_allocator dmem; struct nvgpu_mem trace_buf; struct pmu_sha1_gid gid_info; @@ -179,7 +179,7 @@ struct nvgpu_pmu { #endif }; -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU /*! * Structure/object which single register write need to be done during PG init * sequence to set PROD values. @@ -199,7 +199,7 @@ int nvgpu_pmu_lock_release(struct gk20a *g, struct nvgpu_pmu *pmu, /* PMU RTOS init/setup functions */ int nvgpu_pmu_early_init(struct gk20a *g, struct nvgpu_pmu **pmu_p); -#ifdef NVGPU_FEATURE_LS_PMU +#ifdef CONFIG_NVGPU_LS_PMU int nvgpu_pmu_init(struct gk20a *g, struct nvgpu_pmu *pmu); int nvgpu_pmu_destroy(struct gk20a *g, struct nvgpu_pmu *pmu); #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/power_features/pg.h b/drivers/gpu/nvgpu/include/nvgpu/power_features/pg.h index 388ae5399..674adb7f5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/power_features/pg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/power_features/pg.h @@ -28,7 +28,7 @@ struct gk20a; -#ifdef NVGPU_FEATURE_POWER_PG +#ifdef CONFIG_NVGPU_POWER_PG #define nvgpu_pg_elpg_protected_call(g, func) \ ({ \ int err = 0; \ diff --git a/drivers/gpu/nvgpu/include/nvgpu/runlist.h b/drivers/gpu/nvgpu/include/nvgpu/runlist.h index 1951f3359..2047c5e8d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/runlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/runlist.h @@ -74,7 +74,7 @@ int nvgpu_runlist_update_locked(struct gk20a *g, u32 runlist_id, struct nvgpu_channel *ch, bool add, bool wait_for_finish); -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING int nvgpu_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next, bool wait_preempt); #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/tsg.h b/drivers/gpu/nvgpu/include/nvgpu/tsg.h index 0956ea7be..71438eae0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/tsg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/tsg.h @@ -117,7 +117,7 @@ int nvgpu_tsg_unbind_channel_check_hw_state(struct nvgpu_tsg *tsg, void nvgpu_tsg_unbind_channel_check_ctx_reload(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch, struct nvgpu_channel_hw_state *hw_state); -#ifdef NVGPU_FEATURE_CHANNEL_TSG_CONTROL +#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL int nvgpu_tsg_force_reset_ch(struct nvgpu_channel *ch, u32 err_code, bool verbose); #endif @@ -130,7 +130,7 @@ bool nvgpu_tsg_mark_error(struct gk20a *g, struct nvgpu_tsg *tsg); bool nvgpu_tsg_check_ctxsw_timeout(struct nvgpu_tsg *tsg, bool *debug_dump, u32 *ms); int nvgpu_tsg_set_runlist_interleave(struct nvgpu_tsg *tsg, u32 level); -#ifdef NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING int nvgpu_tsg_set_timeslice(struct nvgpu_tsg *tsg, u32 timeslice_us); u32 nvgpu_tsg_get_timeslice(struct nvgpu_tsg *tsg); int nvgpu_tsg_set_priority(struct gk20a *g, struct nvgpu_tsg *tsg, @@ -174,7 +174,7 @@ void nvgpu_tsg_set_ctxsw_timeout_accumulated_ms(struct nvgpu_tsg *tsg, u32 ms); void nvgpu_tsg_abort(struct gk20a *g, struct nvgpu_tsg *tsg, bool preempt); void nvgpu_tsg_reset_faulted_eng_pbdma(struct gk20a *g, struct nvgpu_tsg *tsg, bool eng, bool pbdma); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER int nvgpu_tsg_set_mmu_debug_mode(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch, bool enable); #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index e30e08fad..70bd97cef 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h @@ -240,7 +240,7 @@ struct tegra_vgpu_golden_ctx_params { u32 size; }; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct tegra_vgpu_zcull_bind_params { u64 handle; u64 zcull_va; @@ -643,7 +643,7 @@ struct tegra_vgpu_cmd_msg { struct tegra_vgpu_cache_maint_params cache_maint; struct tegra_vgpu_runlist_params runlist; struct tegra_vgpu_golden_ctx_params golden_ctx; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct tegra_vgpu_zcull_bind_params zcull_bind; struct tegra_vgpu_zcull_info_params zcull_info; struct tegra_vgpu_zbc_set_table_params zbc_set_table; diff --git a/drivers/gpu/nvgpu/os/linux/cde.c b/drivers/gpu/nvgpu/os/linux/cde.c index 67e46ae86..a2903f74d 100644 --- a/drivers/gpu/nvgpu/os/linux/cde.c +++ b/drivers/gpu/nvgpu/os/linux/cde.c @@ -1338,7 +1338,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx) goto err_get_gk20a_channel; } -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT ch->wdt.enabled = false; #endif diff --git a/drivers/gpu/nvgpu/os/linux/debug_fecs_trace.h b/drivers/gpu/nvgpu/os/linux/debug_fecs_trace.h index 54ebaaf9f..d4f32d8bd 100644 --- a/drivers/gpu/nvgpu/os/linux/debug_fecs_trace.h +++ b/drivers/gpu/nvgpu/os/linux/debug_fecs_trace.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,7 +19,7 @@ struct gk20a; -#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_GK20A_CTXSW_TRACE) +#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_NVGPU_FECS_TRACE) int nvgpu_fecs_trace_init_debugfs(struct gk20a *g); #else static int nvgpu_fecs_trace_init_debugfs(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/os/linux/driver_common.c b/drivers/gpu/nvgpu/os/linux/driver_common.c index aa1250e4b..fb4643a13 100644 --- a/drivers/gpu/nvgpu/os/linux/driver_common.c +++ b/drivers/gpu/nvgpu/os/linux/driver_common.c @@ -67,7 +67,7 @@ static void nvgpu_init_vars(struct gk20a *g) nvgpu_mutex_init(&g->tpc_pg_lock); nvgpu_mutex_init(&g->clk_arb_enable_lock); nvgpu_mutex_init(&g->cg_pg_lock); -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) nvgpu_mutex_init(&g->cs_lock); #endif @@ -290,7 +290,7 @@ int nvgpu_probe(struct gk20a *g, nvgpu_create_sysfs(dev); gk20a_debug_init(g, debugfs_symlink); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K); if (!g->dbg_regops_tmp_buf) { nvgpu_err(g, "couldn't allocate regops tmp buf"); diff --git a/drivers/gpu/nvgpu/os/linux/ioctl.c b/drivers/gpu/nvgpu/os/linux/ioctl.c index d716a9007..1efd7e671 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl.c @@ -101,7 +101,7 @@ static const struct file_operations gk20a_tsg_ops = { .unlocked_ioctl = nvgpu_ioctl_tsg_dev_ioctl, }; -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE static const struct file_operations gk20a_ctxsw_ops = { .owner = THIS_MODULE, .release = gk20a_ctxsw_dev_release, @@ -271,7 +271,7 @@ int gk20a_user_init(struct device *dev, const char *interface_name, if (err) goto fail; -#if defined(CONFIG_GK20A_CTXSW_TRACE) +#if defined(CONFIG_NVGPU_FECS_TRACE) err = gk20a_create_device(dev, devno++, interface_name, "-ctxsw", &l->ctxsw.cdev, &l->ctxsw.node, &gk20a_ctxsw_ops, diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c index 6f274db85..f5162e8c6 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c @@ -113,7 +113,7 @@ struct channel_priv { struct nvgpu_channel *c; }; -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) void gk20a_channel_free_cycle_stats_buffer(struct nvgpu_channel *ch) { @@ -285,7 +285,7 @@ int gk20a_channel_free_cycle_stats_snapshot(struct nvgpu_channel *ch) static int gk20a_channel_set_wdt_status(struct nvgpu_channel *ch, struct nvgpu_channel_wdt_args *args) { -#ifdef NVGPU_CHANNEL_WDT +#ifdef CONFIG_NVGPU_CHANNEL_WDT u32 status = args->wdt_status & (NVGPU_IOCTL_CHANNEL_DISABLE_WDT | NVGPU_IOCTL_CHANNEL_ENABLE_WDT); @@ -760,7 +760,7 @@ notif_clean_up: return ret; } -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS static int gk20a_channel_zcull_bind(struct nvgpu_channel *ch, struct nvgpu_zcull_bind_args *args) { @@ -1228,7 +1228,7 @@ long gk20a_channel_ioctl(struct file *filp, gk20a_idle(ch->g); break; -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS case NVGPU_IOCTL_CHANNEL_ZCULL_BIND: err = gk20a_busy(ch->g); if (err) { diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index e10f47864..7894f2518 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c @@ -35,7 +35,7 @@ #include #include #include -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS #include #include #endif @@ -334,7 +334,7 @@ gk20a_ctrl_ioctl_gpu_characteristics( gpu.dma_copy_class = g->ops.get_litter_value(g, GPU_LIT_DMA_COPY_CLASS); -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU gpu.vbios_version = nvgpu_bios_get_vbios_version(g); gpu.vbios_oem_version = nvgpu_bios_get_vbios_oem_version(g); #else @@ -1667,7 +1667,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg struct gk20a *g = priv->g; u8 buf[NVGPU_GPU_IOCTL_MAX_ARG_SIZE]; struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g); -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_gpu_zcull_get_ctx_size_args *get_ctx_size_args; struct nvgpu_gpu_zcull_get_info_args *get_info_args; struct nvgpu_gr_zcull_info *zcull_info; @@ -1678,7 +1678,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg struct nvgpu_gpu_zbc_set_table_args *set_table_args; struct nvgpu_gpu_zbc_query_table_args *query_table_args; u32 i; -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ int err = 0; nvgpu_log_fn(g, "start %d", _IOC_NR(cmd)); @@ -1705,7 +1705,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg nvgpu_speculation_barrier(); switch (cmd) { -#ifdef NVGPU_GRAPHICS +#ifdef CONFIG_NVGPU_GRAPHICS case NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE: get_ctx_size_args = (struct nvgpu_gpu_zcull_get_ctx_size_args *)buf; @@ -1822,7 +1822,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg if (zbc_tbl) nvgpu_kfree(g, zbc_tbl); break; -#endif /* NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_GRAPHICS */ case NVGPU_GPU_IOCTL_GET_CHARACTERISTICS: err = gk20a_ctrl_ioctl_gpu_characteristics( g, (struct nvgpu_gpu_get_characteristics *)buf); diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index efbecee60..0c3fdcf14 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c @@ -590,7 +590,7 @@ static int dbg_unbind_all_channels_gk20a(struct dbg_session_gk20a *dbg_s) return 0; } -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER /* * Convert common regops op values of the form of NVGPU_DBG_REG_OP_* * into linux regops op values of the form of NVGPU_DBG_GPU_REG_OP_* @@ -935,7 +935,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, return err; } -#endif /* NVGPU_DEBUGGER */ +#endif /* CONFIG_NVGPU_DEBUGGER */ static int nvgpu_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s, struct nvgpu_dbg_gpu_powergate_args *args) @@ -1906,7 +1906,7 @@ static int nvgpu_dbg_gpu_set_sm_exception_type_mask(struct dbg_session_gk20a *db return err; } -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) static int nvgpu_dbg_gpu_cycle_stats(struct dbg_session_gk20a *dbg_s, struct nvgpu_dbg_gpu_cycle_stats_args *args) { @@ -2038,7 +2038,7 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, (struct nvgpu_dbg_gpu_bind_channel_args *)buf); break; -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER case NVGPU_DBG_GPU_IOCTL_REG_OPS: err = nvgpu_ioctl_channel_reg_ops(dbg_s, (struct nvgpu_dbg_gpu_exec_reg_ops_args *)buf); @@ -2145,7 +2145,7 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, (struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *)buf); break; -#ifdef CONFIG_GK20A_CYCLE_STATS +#ifdef CONFIG_NVGPU_CYCLESTATS case NVGPU_DBG_GPU_IOCTL_CYCLE_STATS: err = nvgpu_dbg_gpu_cycle_stats(dbg_s, (struct nvgpu_dbg_gpu_cycle_stats_args *)buf); diff --git a/drivers/gpu/nvgpu/os/linux/linux-channel.c b/drivers/gpu/nvgpu/os/linux/linux-channel.c index 7562edf2c..cc277be6b 100644 --- a/drivers/gpu/nvgpu/os/linux/linux-channel.c +++ b/drivers/gpu/nvgpu/os/linux/linux-channel.c @@ -274,7 +274,7 @@ static void nvgpu_channel_close_linux(struct nvgpu_channel *ch, bool force) { nvgpu_channel_work_completion_clear(ch); -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) gk20a_channel_free_cycle_stats_buffer(ch); gk20a_channel_free_cycle_stats_snapshot(ch); #endif diff --git a/drivers/gpu/nvgpu/os/linux/module.c b/drivers/gpu/nvgpu/os/linux/module.c index 7b89fc1cd..e1b718bff 100644 --- a/drivers/gpu/nvgpu/os/linux/module.c +++ b/drivers/gpu/nvgpu/os/linux/module.c @@ -217,7 +217,7 @@ int nvgpu_finalize_poweron_linux(struct nvgpu_os_linux *l) return err; } -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE err = gk20a_ctxsw_trace_init(g); if (err != 0) nvgpu_warn(g, "could not initialize ctxsw tracing"); @@ -431,7 +431,7 @@ int gk20a_pm_finalize_poweron(struct device *dev) if (err) goto done; -#ifdef NVGPU_FEATURE_CE +#ifdef CONFIG_NVGPU_CE nvgpu_init_mm_ce_context(g); #endif @@ -833,7 +833,7 @@ void gk20a_remove_support(struct gk20a *g) tegra_unregister_idle_unidle(gk20a_do_idle); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_kfree(g, g->dbg_regops_tmp_buf); #endif @@ -864,7 +864,7 @@ void gk20a_remove_support(struct gk20a *g) sim_linux->remove_support_linux(g); } -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) nvgpu_free_cyclestats_snapshot_data(g); #endif @@ -1546,7 +1546,7 @@ int nvgpu_remove(struct device *dev, struct class *class) gk20a_cde_destroy(l); #endif -#ifdef CONFIG_GK20A_CTXSW_TRACE +#ifdef CONFIG_NVGPU_FECS_TRACE gk20a_ctxsw_trace_cleanup(g); #endif diff --git a/drivers/gpu/nvgpu/os/linux/nvlink.c b/drivers/gpu/nvgpu/os/linux/nvlink.c index b388f0307..81f502a2f 100644 --- a/drivers/gpu/nvgpu/os/linux/nvlink.c +++ b/drivers/gpu/nvgpu/os/linux/nvlink.c @@ -15,7 +15,7 @@ */ #include -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK #include #endif @@ -25,7 +25,7 @@ #include #include -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK int nvgpu_nvlink_enumerate(struct gk20a *g) { struct nvlink_device *ndev = (struct nvlink_device *) g->nvlink.priv; @@ -286,11 +286,11 @@ void nvgpu_mss_nvlink_init_credits(struct gk20a *g) val = readl_relaxed(soc4 + 4); writel_relaxed(val, soc4 + 4); } -#endif /* CONFIG_TEGRA_NVLINK */ +#endif /* CONFIG_NVGPU_NVLINK */ int nvgpu_nvlink_deinit(struct gk20a *g) { -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK struct nvlink_device *ndev = g->nvlink.priv; int err; diff --git a/drivers/gpu/nvgpu/os/linux/nvlink_probe.c b/drivers/gpu/nvgpu/os/linux/nvlink_probe.c index 90c7b6578..dee776e15 100644 --- a/drivers/gpu/nvgpu/os/linux/nvlink_probe.c +++ b/drivers/gpu/nvgpu/os/linux/nvlink_probe.c @@ -15,7 +15,7 @@ */ #include -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK #include #endif @@ -27,7 +27,7 @@ #include #include -#ifdef CONFIG_TEGRA_NVLINK +#ifdef CONFIG_NVGPU_NVLINK int nvgpu_nvlink_read_dt_props(struct gk20a *g) { struct device_node *np; @@ -476,5 +476,5 @@ int nvgpu_nvlink_unregister_link(struct gk20a *g) return nvlink_unregister_link(&ndev->link); } -#endif /* CONFIG_TEGRA_NVLINK */ +#endif /* CONFIG_NVGPU_NVLINK */ diff --git a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c index 25b317a2a..370d0c695 100644 --- a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c +++ b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c @@ -134,13 +134,13 @@ static int vgpu_init_support(struct platform_device *pdev) nvgpu_mutex_init(&g->dbg_sessions_lock); nvgpu_mutex_init(&g->client_lock); -#if defined(CONFIG_GK20A_CYCLE_STATS) +#if defined(CONFIG_NVGPU_CYCLESTATS) nvgpu_mutex_init(&g->cs_lock); #endif nvgpu_init_list_node(&g->profiler_objects); -#ifdef NVGPU_DEBUGGER +#ifdef CONFIG_NVGPU_DEBUGGER g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K); if (!g->dbg_regops_tmp_buf) { nvgpu_err(g, "couldn't allocate regops tmp buf"); diff --git a/userspace/units/fifo/nvgpu-fifo.c b/userspace/units/fifo/nvgpu-fifo.c index 484cdf0a4..8e38f592e 100644 --- a/userspace/units/fifo/nvgpu-fifo.c +++ b/userspace/units/fifo/nvgpu-fifo.c @@ -83,7 +83,7 @@ static u32 stub_gv11b_gr_init_get_no_of_sm(struct gk20a *g) return 8; } -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD static int stub_userd_setup_sw(struct gk20a *g) { struct nvgpu_fifo *f = &g->fifo; @@ -115,7 +115,7 @@ int test_fifo_init_support(struct unit_module *m, struct gk20a *g, void *args) g->ops.gr.init.get_no_of_sm = stub_gv11b_gr_init_get_no_of_sm; g->ops.tsg.init_eng_method_buffers = NULL; -#ifdef NVGPU_USERD +#ifdef CONFIG_NVGPU_USERD /* * Regular USERD init requires bar1.vm to be initialized * Use a stub in unit tests, since it will be disabled in diff --git a/userspace/units/fuse/nvgpu-fuse.c b/userspace/units/fuse/nvgpu-fuse.c index 5dee347b8..acbbffc82 100644 --- a/userspace/units/fuse/nvgpu-fuse.c +++ b/userspace/units/fuse/nvgpu-fuse.c @@ -31,7 +31,7 @@ #include "nvgpu-fuse-priv.h" #include "nvgpu-fuse-gp10b.h" #include "nvgpu-fuse-gm20b.h" -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU #include "nvgpu-fuse-tu104.h" #endif @@ -182,7 +182,7 @@ struct unit_module_test fuse_tests[] = { UNIT_TEST(fuse_gm20b_cleanup, test_fuse_device_common_cleanup, &gm20b_init_args, 0), -#ifdef NVGPU_DGPU_SUPPORT +#ifdef CONFIG_NVGPU_DGPU UNIT_TEST(fuse_tu104_init, test_fuse_device_common_init, &tu104_init_args, 0), UNIT_TEST(fuse_tu104_vin_cal_rev, test_fuse_tu104_vin_cal_rev, NULL, 0),