diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 4c23455d0..4984af46b 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -19,6 +19,8 @@ #include #include +#include + #include "gk20a/gr_gk20a.h" #include "gk20a/semaphore_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" @@ -1049,7 +1051,7 @@ static bool gr_activity_empty_or_preempted(u32 val) return true; } -static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long end_jiffies, +static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, u32 expect_delay) { u32 delay = expect_delay; @@ -1058,9 +1060,12 @@ static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long end_jiffies, bool gr_busy; u32 gr_status; u32 activity0, activity1, activity2, activity4; + struct nvgpu_timeout timeout; gk20a_dbg_fn(""); + nvgpu_timeout_init(g, &timeout, duration_ms, NVGPU_TIMER_CPU_TIMER); + do { /* fmodel: host gets fifo_engine_status(gr) from gr only when gr_status is read */ @@ -1089,8 +1094,7 @@ static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long end_jiffies, usleep_range(delay, delay * 2); delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); - } while (time_before(jiffies, end_jiffies) - || !tegra_platform_is_silicon()); + } while (!nvgpu_timeout_expired(&timeout)); gk20a_err(dev_from_gk20a(g), "timeout, ctxsw busy : %d, gr busy : %d, %08x, %08x, %08x, %08x", @@ -1634,8 +1638,6 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) u32 j; u32 num_subctx = nvgpu_get_litter_value(g, GPU_LIT_NUM_SUBCTX); u32 err = 0; - unsigned long end_jiffies = jiffies + - msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); for (j = 0; j < num_subctx; j++) { @@ -1643,8 +1645,8 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) sw_veid_bundle_init->l[index].addr | gr_pipe_bundle_address_veid_f(j)); - err = gr_gk20a_wait_fe_idle(g, end_jiffies, - GR_IDLE_CHECK_DEFAULT); + err = gr_gk20a_wait_fe_idle(g, gk20a_get_gr_idle_timeout(g), + GR_IDLE_CHECK_DEFAULT); } } @@ -1655,8 +1657,6 @@ static int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) u32 i; u32 last_bundle_data = 0; u32 err = 0; - unsigned long end_jiffies = jiffies + - msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); gk20a_dbg_fn(""); for (i = 0; i < sw_veid_bundle_init->count; i++) { @@ -1672,8 +1672,9 @@ static int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) sw_veid_bundle_init->l[i].addr) == GR_GO_IDLE_BUNDLE) { gk20a_writel(g, gr_pipe_bundle_address_r(), sw_veid_bundle_init->l[i].addr); - err |= gr_gk20a_wait_idle(g, end_jiffies, - GR_IDLE_CHECK_DEFAULT); + err |= gr_gk20a_wait_idle(g, + gk20a_get_gr_idle_timeout(g), + GR_IDLE_CHECK_DEFAULT); } else gv11b_write_bundle_veid_state(g, i);