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gpu: nvgpu: Add nvgpu_early_poweron() support

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1) NvGpu dev node needs to be created in gpu power on
early stage to avoid latency introduced by udevd.
For creating dev node, device and grmgr init
needs to move to early stage of GPU power on.
After grmgr init, NvGpu can identify the number of MIG
instance required for each physical GPU.
For that, added a new API nvgpu_early_poweron() to handle
early init which is required for before dev node creation.

2) Removed fifo dependency in nvgpu_init_gr_manager()

3) Used get_max_subctx_count() directly to query
the veid/subctx count.

JIRA NVGPU-6633

Change-Id: Ib9d7c3e184c71237b0da9305515ccd8ceda1d5ad
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2517173
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Lakshmanan M
2021-04-19 22:56:18 +05:30
committed by mobile promotions
parent 3648fe4655
commit 3f8c562004
4 changed files with 63 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/nvgpu/common/grmgr/grmgr.c
View File

@@ -88,7 +88,18 @@ int nvgpu_init_gr_manager(struct gk20a *g)
}
nvgpu_assert(local_gpc_mask == 0U);
}
if (g->ops.gr.init.get_max_subctx_count != NULL) {
gr_syspipe->max_veid_count_per_tsg =
g->ops.gr.init.get_max_subctx_count();
} else {
/*
* For vgpu, NvGpu has to rely on chip constant
* queried from nvgpu server.
* For legacy chips, g->fifo.max_subctx_count should be 0U.
*/
gr_syspipe->max_veid_count_per_tsg = g->fifo.max_subctx_count;
}
gr_syspipe->veid_start_offset = 0U;
gpu_instance->num_lce = nvgpu_device_get_copies(g, gpu_instance->lce_devs,

40
drivers/gpu/nvgpu/common/init/nvgpu_init.c
View File

@@ -42,6 +42,7 @@
#include <nvgpu/gr/gr.h>
#include <nvgpu/pm_reservation.h>
#include <nvgpu/netlist.h>
#include <nvgpu/hal_init.h>
#ifdef CONFIG_NVGPU_LS_PMU
#include <nvgpu/pmu/pmu_pstate.h>
@@ -585,6 +586,38 @@ static bool needs_init(struct gk20a *g, nvgpu_init_func_t func, u32 enable_flag)
nvgpu_is_enabled(g, enable_flag)) && (func != NULL);
}
int nvgpu_early_poweron(struct gk20a *g)
{
int err = 0;
err = nvgpu_detect_chip(g);
if (err != 0) {
nvgpu_err(g, "nvgpu_detect_chip failed[%d]", err);
goto done;
}
/*
* Initialize the GPU's device list. Needed before NVLINK
* init since the NVLINK IOCTRL block is enumerated in the
* device list.
*/
err = nvgpu_device_init(g);
if (err != 0) {
nvgpu_err(g, "nvgpu_device_init failed[%d]", err);
goto done;
}
err = g->ops.grmgr.init_gr_manager(g);
if (err != 0) {
nvgpu_device_cleanup(g);
nvgpu_err(g, "g->ops.grmgr.init_gr_manager failed[%d]", err);
goto done;
}
done:
return err;
}
int nvgpu_finalize_poweron(struct gk20a *g)
{
int err = 0;
@@ -610,12 +643,6 @@ int nvgpu_finalize_poweron(struct gk20a *g)
NVGPU_INIT_TABLE_ENTRY(&nvgpu_falcons_sw_init, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(g->ops.pmu.pmu_early_init, NO_FLAG),
/*
* Initialize the GPU's device list. Needed before NVLINK
* init since the NVLINK IOCTRL block is enumerated in the
* device list.
*/
NVGPU_INIT_TABLE_ENTRY(&nvgpu_device_init, NO_FLAG),
#ifdef CONFIG_NVGPU_DGPU
NVGPU_INIT_TABLE_ENTRY(g->ops.sec2.init_sec2_setup_sw,
NVGPU_SUPPORT_SEC2_RTOS),
@@ -665,7 +692,6 @@ int nvgpu_finalize_poweron(struct gk20a *g)
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_acquire_tpc_pg_lock, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_power_gate_gr, NO_FLAG),
#endif
NVGPU_INIT_TABLE_ENTRY(g->ops.grmgr.init_gr_manager, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(&nvgpu_netlist_init_ctx_vars, NO_FLAG),
/* prepare portion of sw required for enable hw */
NVGPU_INIT_TABLE_ENTRY(&nvgpu_gr_alloc, NO_FLAG),

14
drivers/gpu/nvgpu/include/nvgpu/nvgpu_init.h
View File

@@ -79,6 +79,20 @@ struct nvgpu_ref;
* + nvgpu_check_gpu_state() - Restart if the state is invalid.
*/
/**
* @brief Initial driver initialization
*
* @param g [in] The GPU
*
* Initializes device and grmgr subunits in the early stage of
* GPU power on sequence. This separate routine is required to create
* the GPU dev node in the early stage of GPU power on sequence.
* Each sub-unit is responsible for HW initialization.
*
* @return 0 in case of success, < 0 in case of failure.
*/
int nvgpu_early_poweron(struct gk20a *g);
/**
* @brief Final driver initialization
*

11
drivers/gpu/nvgpu/os/linux/module.c
View File

@@ -41,7 +41,6 @@
#include <soc/tegra/fuse.h>
#endif /* CONFIG_NVGPU_TEGRA_FUSE */
#include <nvgpu/hal_init.h>
#include <nvgpu/dma.h>
#include <nvgpu/kmem.h>
#include <nvgpu/nvgpu_common.h>
@@ -434,14 +433,12 @@ int gk20a_pm_finalize_poweron(struct device *dev)
nvgpu_restore_usermode_for_poweron(g);
err = nvgpu_detect_chip(g);
if (err)
err = nvgpu_early_poweron(g);
if (err != 0) {
nvgpu_err(g, "nvgpu_early_poweron failed[%d]", err);
goto done;
}
/**
* TODO: Need to add nvgpu_early_poweron() sequence before
* creating device nodes.
*/
if (!l->dev_nodes_created) {
err = gk20a_user_init(dev);
if (err) {