From 3fe70bf86e4bf18f5816f6603fef7355a5b89ec3 Mon Sep 17 00:00:00 2001 From: Tejal Kudav Date: Fri, 18 Feb 2022 02:31:07 +0000 Subject: [PATCH] gpu: nvgpu: Update CE Intr code as per Orin HSIs Below CE interrupts do not have any users(usecases) on safety build; disable them only on safety build. 1. BLOCKPIPE stall intr: Not used by GFX(VKSC) and CUDA on safety. 2. NONBLOCK_PIPE nonstall intr: Non-stall intrs are not supported on safety build. Also, this one is not used by GFX(VKSC) and CUDA. 3. STALLING_DEBUG intr: Added in Orin tree. It is only needed for debugging. Disable on safety build as there is no current usage in driver. 4. POISON_ERROR intr: Poison is a fault containment and not supported on GA10b. 5. INVALID_CONFIG intr: Floor sweeping not supported on functional safety SKU. Bug 3548082 Change-Id: I8d97ccb38f138b2c04a780e1c255a64d28723405 Signed-off-by: Tejal Kudav Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2671927 Tested-by: mobile promotions Reviewed-by: mobile promotions --- arch/nvgpu-hal-new.yaml | 1 + drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/Makefile.sources | 1 + drivers/gpu/nvgpu/common/ce/ce.c | 2 + drivers/gpu/nvgpu/hal/ce/ce2_gk20a.c | 1 - drivers/gpu/nvgpu/hal/ce/ce_ga10b.h | 5 +- drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c | 54 +++++++++++-------- drivers/gpu/nvgpu/hal/ce/ce_gp10b.c | 53 ++++++++++++++++++ drivers/gpu/nvgpu/hal/ce/ce_gp10b.h | 4 +- drivers/gpu/nvgpu/hal/ce/ce_gp10b_fusa.c | 22 -------- drivers/gpu/nvgpu/hal/ce/ce_gv11b_fusa.c | 2 + .../gpu/nvgpu/hal/cic/mon/lut_ga10b_fusa.c | 31 ++++++----- drivers/gpu/nvgpu/hal/init/hal_ga100.c | 3 ++ drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 4 +- drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 2 + drivers/gpu/nvgpu/hal/init/hal_tu104.c | 2 + drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c | 2 + drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c | 5 +- .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c | 2 + .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c | 4 +- drivers/gpu/nvgpu/include/nvgpu/gops/ce.h | 27 +++++----- drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h | 11 ++-- libs/dgpu/libnvgpu-drv-dgpu_safe.export | 1 - libs/igpu/libnvgpu-drv-igpu_safe.export | 1 - userspace/required_tests.ini | 1 - userspace/units/ce/nvgpu-ce.c | 54 +------------------ userspace/units/ce/nvgpu-ce.h | 30 +---------- userspace/units/mc/nvgpu-mc.c | 9 +++- 28 files changed, 170 insertions(+), 165 deletions(-) create mode 100644 drivers/gpu/nvgpu/hal/ce/ce_gp10b.c diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index dde3fad78..cfceaec80 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -569,6 +569,7 @@ ce: owner: Thomas F sources: [ hal/ce/ce2_gk20a.c, hal/ce/ce2_gk20a.h, + hal/ce/ce_gp10b.c, hal/ce/ce_tu104.c, hal/ce/ce_tu104.h ] diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index b7a3c9d39..6e714e25c 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -805,6 +805,7 @@ nvgpu-y += \ nvgpu-$(CONFIG_NVGPU_HAL_NON_FUSA) += \ hal/ce/ce_tu104.o \ + hal/ce/ce_gp10b.o \ hal/clk/clk_gm20b.o \ hal/init/hal_gm20b.o \ hal/init/hal_gm20b_litter.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 5fe179f40..328920e57 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -315,6 +315,7 @@ srcs += hal/init/hal_gm20b.c \ hal/priv_ring/priv_ring_gm20b.c \ hal/power_features/cg/gm20b_gating_reglist.c \ hal/ce/ce2_gk20a.c \ + hal/ce/ce_gp10b.c \ hal/therm/therm_gm20b.c \ hal/therm/therm_gp10b.c \ hal/ltc/ltc_gm20b.c \ diff --git a/drivers/gpu/nvgpu/common/ce/ce.c b/drivers/gpu/nvgpu/common/ce/ce.c index 2258c81f9..056d2d865 100644 --- a/drivers/gpu/nvgpu/common/ce/ce.c +++ b/drivers/gpu/nvgpu/common/ce/ce.c @@ -65,9 +65,11 @@ int nvgpu_ce_init_support(struct gk20a *g) g->ops.ce.init_prod_values(g); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR if (g->ops.ce.init_hw != NULL) { g->ops.ce.init_hw(g); } +#endif if (g->ops.ce.intr_enable != NULL) { g->ops.ce.intr_enable(g, true); diff --git a/drivers/gpu/nvgpu/hal/ce/ce2_gk20a.c b/drivers/gpu/nvgpu/hal/ce/ce2_gk20a.c index d5e1ee599..175a96d8c 100644 --- a/drivers/gpu/nvgpu/hal/ce/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/hal/ce/ce2_gk20a.c @@ -53,7 +53,6 @@ void gk20a_ce2_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) nvgpu_log(g, gpu_dbg_intr, "ce2 blocking pipe interrupt"); clear_intr |= ce2_intr_status_blockpipe_pending_f(); } - if ((ce2_intr & ce2_intr_status_launcherr_pending_f()) != 0U) { nvgpu_log(g, gpu_dbg_intr, "ce2 launch error interrupt"); clear_intr |= ce2_intr_status_launcherr_pending_f(); diff --git a/drivers/gpu/nvgpu/hal/ce/ce_ga10b.h b/drivers/gpu/nvgpu/hal/ce/ce_ga10b.h index 2f66ea7e4..accca449d 100644 --- a/drivers/gpu/nvgpu/hal/ce/ce_ga10b.h +++ b/drivers/gpu/nvgpu/hal/ce/ce_ga10b.h @@ -1,7 +1,7 @@ /* * Ampere GPU series copy engine * - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -25,8 +25,9 @@ #define NVGPU_CE_GA10B_H struct gk20a; - +#ifdef CONFIG_NVGPU_NONSTALL_INTR void ga10b_ce_init_hw(struct gk20a *g); +#endif void ga10b_ce_intr_enable(struct gk20a *g, bool enable); void ga10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); void ga10b_ce_intr_retrigger(struct gk20a *g, u32 inst_id); diff --git a/drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c index c02f719ba..6db5ee996 100644 --- a/drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c @@ -1,7 +1,7 @@ /* * Ampere GPU series Copy Engine. * - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -35,16 +35,21 @@ #include -static u32 ce_lce_stall_intr_mask(void) +static u32 ce_lce_intr_mask(void) { - u32 mask = ce_lce_intr_en_blockpipe_m() | - ce_lce_intr_en_launcherr_m() | + /* Note: Poison error(fault containment) is not supported on GA10b. */ + u32 mask = ce_lce_intr_en_launcherr_m() | +#ifdef CONFIG_NVGPU_HAL_NON_FUSA + ce_lce_intr_en_stalling_debug_m() | + ce_lce_intr_en_blockpipe_m() | ce_lce_intr_en_invalid_config_m() | +#endif +#ifdef CONFIG_NVGPU_NONSTALL_INTR + ce_lce_intr_en_nonblockpipe_m() | +#endif ce_lce_intr_en_mthd_buffer_fault_m() | ce_lce_intr_en_fbuf_crc_fail_m() | - ce_lce_intr_en_fbuf_magic_chk_fail_m() | - ce_lce_intr_en_poison_error_m() | - ce_lce_intr_en_stalling_debug_m(); + ce_lce_intr_en_fbuf_magic_chk_fail_m(); return mask; } @@ -62,15 +67,20 @@ static void ga10b_ce_intr_stall_nonstall_enable(struct gk20a *g, intr_ctrl = nvgpu_readl(g, ce_lce_intr_ctrl_r(inst_id)); intr_notify_ctrl = nvgpu_readl(g, ce_lce_intr_notify_ctrl_r(inst_id)); - /* * The copy engine interrupts are enabled using a single enable * register: ce_lce_intr_en_r. The interrupts generated by the * CE engine are grouped into two: * Stall: - * - Represented by: ce_lce_stall_intr_mask(). + * ce_lce_intr_en_launcherr_m() + * ce_lce_intr_en_stalling_debug_m() + * ce_lce_intr_en_blockpipe_m() + * ce_lce_intr_en_invalid_config_m() + * ce_lce_intr_en_mthd_buffer_fault_m() + * ce_lce_intr_en_fbuf_crc_fail_m() + * ce_lce_intr_en_fbuf_magic_chk_fail_m() * Non-Stall: - * - Represented by: ce_lce_intr_en_nonblockpipe_m(). + * ce_lce_intr_en_nonblockpipe_m(). * Stalling interrupts are routed either to the cpu/gsp using * the POR value of vector_id in register: ce_lce_intr_ctrl_r. * This vector aligns with the intr_id field in device info. @@ -89,8 +99,7 @@ static void ga10b_ce_intr_stall_nonstall_enable(struct gk20a *g, * are reported to CPU on the POR values of vector_ids. * In addition, disable reporting to GSP. */ - intr_en_mask = ce_lce_stall_intr_mask() | - ce_lce_intr_en_nonblockpipe_m(); + intr_en_mask = ce_lce_intr_mask(); intr_ctrl_msk = ce_lce_intr_ctrl_cpu_enable_f() | ce_lce_intr_ctrl_gsp_disable_f(); intr_notify_ctrl_msk = @@ -110,6 +119,13 @@ static void ga10b_ce_intr_stall_nonstall_enable(struct gk20a *g, ce_lce_intr_notify_ctrl_gsp_disable_f(); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR + /* Disable nonstalling CE interrupts on safety build */ + intr_notify_ctrl_msk = + ce_lce_intr_notify_ctrl_cpu_disable_f() | + ce_lce_intr_notify_ctrl_gsp_disable_f(); +#endif + intr_ctrl = set_field(intr_ctrl, ce_lce_intr_ctrl_cpu_m() | ce_lce_intr_ctrl_gsp_m(), intr_ctrl_msk); @@ -129,6 +145,7 @@ static void ga10b_ce_intr_stall_nonstall_enable(struct gk20a *g, nvgpu_writel(g, ce_lce_intr_en_r(inst_id), intr_en_mask); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR void ga10b_ce_init_hw(struct gk20a *g) { u32 nonstall_vectorid_tree[NVGPU_CIC_INTR_VECTORID_SIZE_MAX]; @@ -156,6 +173,7 @@ void ga10b_ce_init_hw(struct gk20a *g) nvgpu_cic_mon_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_CE, nonstall_vectorid_tree, num_nonstall_vectors); } +#endif void ga10b_ce_intr_enable(struct gk20a *g, bool enable) { @@ -194,16 +212,7 @@ void ga10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) clear_intr |= ce_intr_status_fbuf_magic_chk_fail_reset_f(); } - /* - * The poison error indicates that the data returned from the memory - * subsytem is corrupted due to an uncorrectable ecc error. - */ - if ((ce_intr & ce_intr_status_poison_error_pending_f()) != 0U) { - nvgpu_err(g, "ce: inst %d: poison error, uncorrected ecc error", - inst_id); - clear_intr |= ce_intr_status_poison_error_reset_f(); - } - +#ifdef CONFIG_NVGPU_HAL_NON_FUSA /* * The stalling_debug error interrupt is triggered when SW writes TRUE * to NV_CE_LCE_OPT_EXT_DEBUG_TRIGGER_STALLING. @@ -212,6 +221,7 @@ void ga10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) nvgpu_err(g, "ce: inst %d: stalling debug interrupt", inst_id); clear_intr |= ce_intr_status_stalling_debug_pending_f(); } +#endif nvgpu_writel(g, ce_intr_status_r(inst_id), clear_intr); diff --git a/drivers/gpu/nvgpu/hal/ce/ce_gp10b.c b/drivers/gpu/nvgpu/hal/ce/ce_gp10b.c new file mode 100644 index 000000000..d85e86bae --- /dev/null +++ b/drivers/gpu/nvgpu/hal/ce/ce_gp10b.c @@ -0,0 +1,53 @@ +/* + * Pascal GPU series Copy Engine. + * + * Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "ce_gp10b.h" + +#include + +u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) +{ + u32 nonstall_ops = 0U; + u32 ce_intr = nvgpu_readl(g, ce_intr_status_r(inst_id)); + + (void)pri_base; + + nvgpu_log(g, gpu_dbg_intr, "ce nonstall isr %08x %08x", + ce_intr, inst_id); + + if ((ce_intr & ce_intr_status_nonblockpipe_pending_f()) != 0U) { + nvgpu_writel(g, ce_intr_status_r(inst_id), + ce_intr_status_nonblockpipe_pending_f()); + nonstall_ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE | + NVGPU_CIC_NONSTALL_OPS_POST_EVENTS); + } + + return nonstall_ops; +} diff --git a/drivers/gpu/nvgpu/hal/ce/ce_gp10b.h b/drivers/gpu/nvgpu/hal/ce/ce_gp10b.h index 54ef19f1d..711a3e238 100644 --- a/drivers/gpu/nvgpu/hal/ce/ce_gp10b.h +++ b/drivers/gpu/nvgpu/hal/ce/ce_gp10b.h @@ -1,7 +1,7 @@ /* * Pascal GPU series Copy Engine. * - * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,6 +29,8 @@ struct gk20a; void gp10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); +#ifdef CONFIG_NVGPU_NONSTALL_INTR u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); +#endif /* NVGPU_HAL_NON_FUSA */ #endif /* NVGPU_CE_GP10B_H */ diff --git a/drivers/gpu/nvgpu/hal/ce/ce_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/ce/ce_gp10b_fusa.c index 6f91bc37c..5be799744 100644 --- a/drivers/gpu/nvgpu/hal/ce/ce_gp10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/ce/ce_gp10b_fusa.c @@ -43,8 +43,6 @@ void gp10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) /* clear blocking interrupts: they exibit broken behavior */ if ((ce_intr & ce_intr_status_blockpipe_pending_f()) != 0U) { - nvgpu_report_err_to_sdl(g, NVGPU_ERR_MODULE_CE, - GPU_CE_BLOCK_PIPE); nvgpu_err(g, "ce blocking pipe interrupt"); clear_intr |= ce_intr_status_blockpipe_pending_f(); } @@ -59,23 +57,3 @@ void gp10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) nvgpu_writel(g, ce_intr_status_r(inst_id), clear_intr); return; } - -u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) -{ - u32 nonstall_ops = 0U; - u32 ce_intr = nvgpu_readl(g, ce_intr_status_r(inst_id)); - - (void)pri_base; - - nvgpu_log(g, gpu_dbg_intr, "ce nonstall isr %08x %08x", - ce_intr, inst_id); - - if ((ce_intr & ce_intr_status_nonblockpipe_pending_f()) != 0U) { - nvgpu_writel(g, ce_intr_status_r(inst_id), - ce_intr_status_nonblockpipe_pending_f()); - nonstall_ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE | - NVGPU_CIC_NONSTALL_OPS_POST_EVENTS); - } - - return nonstall_ops; -} diff --git a/drivers/gpu/nvgpu/hal/ce/ce_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/ce/ce_gv11b_fusa.c index 48ad26004..7ef9920e5 100644 --- a/drivers/gpu/nvgpu/hal/ce/ce_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/ce/ce_gv11b_fusa.c @@ -54,6 +54,7 @@ void gv11b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) nvgpu_log(g, gpu_dbg_intr, "ce isr 0x%08x 0x%08x", ce_intr, inst_id); +#ifdef CONFIG_NVGPU_HAL_NON_FUSA /* * An INVALID_CONFIG interrupt will be generated if a floorswept * PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG @@ -66,6 +67,7 @@ void gv11b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) nvgpu_err(g, "ce: inst %d: invalid config", inst_id); clear_intr |= ce_intr_status_invalid_config_reset_f(); } +#endif /* * A MTHD_BUFFER_FAULT interrupt will be triggered if any access diff --git a/drivers/gpu/nvgpu/hal/cic/mon/lut_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/cic/mon/lut_ga10b_fusa.c index 53302d3ff..99fedd559 100644 --- a/drivers/gpu/nvgpu/hal/cic/mon/lut_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/cic/mon/lut_ga10b_fusa.c @@ -572,25 +572,28 @@ struct nvgpu_err_hw_module ga10b_err_lut[] = { INJECT_SW, NULL, NULL, NULL, NULL, 0, 0), - GPU_CRITERR("ce_block_pipe", - GPU_CE_BLOCK_PIPE, - INJECT_SW, - NULL, NULL, - NULL, NULL, 0, 0), - GPU_NONCRITERR("ce_nonblock_pipe", - 0, INJECT_NONE, - NULL, NULL, - NULL, NULL, 0, 0), - GPU_CRITERR("ce_invalid_config", - GPU_CE_INVALID_CONFIG, - INJECT_SW, - NULL, NULL, - NULL, NULL, 0, 0), GPU_CRITERR("ce_method_buffer_fault", GPU_CE_METHOD_BUFFER_FAULT, INJECT_SW, NULL, NULL, NULL, NULL, 0, 0), + GPU_CRITERR("ce_fbuf_crc_fail", + GPU_CE_FBUF_CRC_FAIL, + INJECT_NONE, + NULL, NULL, + NULL, NULL, 0, 0), + GPU_CRITERR("ce_fbuf_magic_chk_fail", + GPU_CE_FBUF_MAGIC_CHK_FAIL, + INJECT_NONE, + NULL, NULL, + NULL, NULL, 0, 0), +#ifdef CONFIG_NVGPU_NON_FUSA + GPU_CRITERR("ce_invalid_config", + GPU_CE_INVALID_CONFIG, + INJECT_SW, + NULL, NULL, + NULL, NULL, 0, 0), +#endif }, }, }; diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index 2caa1d381..ad9d30521 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -422,7 +422,10 @@ static const struct gops_ce ga100_ops_ce = { #endif .set_pce2lce_mapping = NULL, .isr_stall = gv11b_ce_stall_isr, +#ifdef CONFIG_NVGPU_NONSTALL_INTR .isr_nonstall = NULL, + .init_hw = NULL, +#endif .get_num_pce = gv11b_ce_get_num_pce, .mthd_buffer_fault_in_bar2_fault = gv11b_ce_mthd_buffer_fault_in_bar2_fault, .init_prod_values = gv11b_ce_init_prod_values, diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index a8a0f7719..c3b7d4de2 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -393,11 +393,13 @@ static const struct gops_ce ga10b_ops_ce = { .ce_app_suspend = nvgpu_ce_app_suspend, .ce_app_destroy = nvgpu_ce_app_destroy, #endif - .init_hw = ga10b_ce_init_hw, .intr_enable = ga10b_ce_intr_enable, .isr_stall = ga10b_ce_stall_isr, .intr_retrigger = ga10b_ce_intr_retrigger, +#ifdef CONFIG_NVGPU_NONSTALL_INTR .isr_nonstall = NULL, + .init_hw = ga10b_ce_init_hw, +#endif .get_num_pce = gv11b_ce_get_num_pce, .mthd_buffer_fault_in_bar2_fault = gv11b_ce_mthd_buffer_fault_in_bar2_fault, .init_prod_values = gv11b_ce_init_prod_values, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 4f2c781d5..38bc3ba7e 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -310,7 +310,9 @@ static const struct gops_ce gv11b_ops_ce = { .ce_app_destroy = nvgpu_ce_app_destroy, #endif .isr_stall = gv11b_ce_stall_isr, +#ifdef CONFIG_NVGPU_NONSTALL_INTR .isr_nonstall = gp10b_ce_nonstall_isr, +#endif .get_num_pce = gv11b_ce_get_num_pce, .mthd_buffer_fault_in_bar2_fault = gv11b_ce_mthd_buffer_fault_in_bar2_fault, .init_prod_values = gv11b_ce_init_prod_values, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 9b1847b51..2f9297e9e 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -359,7 +359,9 @@ static const struct gops_ce tu104_ops_ce = { #endif .set_pce2lce_mapping = tu104_ce_set_pce2lce_mapping, .isr_stall = gv11b_ce_stall_isr, +#ifdef CONFIG_NVGPU_NONSTALL_INTR .isr_nonstall = NULL, +#endif .get_num_pce = gv11b_ce_get_num_pce, .mthd_buffer_fault_in_bar2_fault = gv11b_ce_mthd_buffer_fault_in_bar2_fault, .init_prod_values = gv11b_ce_init_prod_values, diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c index c1049d96d..e24dfe49f 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c @@ -84,6 +84,7 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g) nonstall_ops |= g->ops.gr.intr.nonstall_isr(g); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR /* CE Engine */ if (nvgpu_device_is_ce(g, dev) && (g->ops.ce.isr_nonstall != NULL)) { @@ -91,6 +92,7 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g) dev->inst_id, dev->pri_base); } +#endif } return nonstall_ops; diff --git a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c index 98703d545..8946a0ebc 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c @@ -280,6 +280,7 @@ u32 ga10b_intr_isr_host2soc_0(struct gk20a *g) handled_subtree_mask |= unit_subtree_mask; } +#ifdef CONFIG_NVGPU_NONSTALL_INTR if (ga10b_intr_is_unit_pending(g, NVGPU_CIC_INTR_UNIT_CE, intr_leaf0, intr_leaf1, &unit_subtree_mask) == true) { ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask); @@ -287,7 +288,7 @@ u32 ga10b_intr_isr_host2soc_0(struct gk20a *g) NVGPU_CIC_NONSTALL_OPS_POST_EVENTS); handled_subtree_mask |= unit_subtree_mask; } - +#endif ga10b_intr_subtree_clear_unhandled(g, subtree, intr_leaf0, intr_leaf1, handled_subtree_mask); return ops; @@ -397,10 +398,12 @@ bool ga10b_mc_intr_get_unit_info(struct gk20a *g, u32 unit) intr_unit_info->valid = true; return true; /* CE NONSTALL interrupts */ +#ifdef CONFIG_NVGPU_NONSTALL_INTR case NVGPU_CIC_INTR_UNIT_CE: /* vectorids are setup in ce.init_hw */ nvgpu_log(g, gpu_dbg_intr, "CE NONSTALL interrupt"); break; +#endif case NVGPU_CIC_INTR_UNIT_GR_STALL: reg_val = nvgpu_readl(g, ctrl_legacy_engine_stall_intr_base_vectorid_r()); diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c index e0715ba80..e6339416e 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c @@ -271,7 +271,9 @@ static const struct gops_ce vgpu_ga10b_ops_ce = { .ce_app_destroy = NULL, #endif .isr_stall = NULL, +#ifdef CONFIG_NVGPU_NONSTALL_INTR .isr_nonstall = NULL, +#endif .get_num_pce = vgpu_ce_get_num_pce, }; diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c index 07a5d86ab..35b223792 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -244,7 +244,9 @@ static const struct gops_ce vgpu_gv11b_ops_ce = { .ce_app_destroy = NULL, #endif .isr_stall = NULL, +#ifdef CONFIG_NVGPU_NONSTALL_INTR .isr_nonstall = NULL, +#endif .get_num_pce = vgpu_ce_get_num_pce, }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h index ed4e50e6b..e7d88e8c0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -60,6 +60,7 @@ struct gops_ce { */ void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base); +#ifdef CONFIG_NVGPU_NONSTALL_INTR /** * @brief Handler for CE non-stalling interrupts. * @@ -82,6 +83,19 @@ struct gops_ce { */ u32 (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base); + /* + * @brief Get non-stall vectors from hw. + * + * @param g [in] The GPU driver struct. + * + * Steps: + * - Get a list of non-stall vectors used by the engine + * from the hw register POR values. + */ + void (*init_hw)(struct gk20a *g); + +#endif + /** * @brief Get number of PCEs (Physical Copy Engines). * @@ -120,17 +134,6 @@ struct gops_ce { void (*init_prod_values)(struct gk20a *g); void (*request_idle)(struct gk20a *g); - /* - * @brief Get non-stall vectors from hw. - * - * @param g [in] The GPU driver struct. - * - * Steps: - * - Get a list of non-stall vectors used by the engine - * from the hw register POR values. - */ - void (*init_hw)(struct gk20a *g); - /* * @brief Enable/disable ce interrupts. * diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h index 98be9f2b3..c0b2f4c30 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h @@ -274,10 +274,13 @@ struct mmu_fault_info; * Macros used to assign unique index to errors reported from the CE unit. * @{ */ -#define GPU_CE_LAUNCH_ERROR (0U) -#define GPU_CE_BLOCK_PIPE (1U) -#define GPU_CE_INVALID_CONFIG (3U) -#define GPU_CE_METHOD_BUFFER_FAULT (4U) +#define GPU_CE_LAUNCH_ERROR (0x0) +#define GPU_CE_METHOD_BUFFER_FAULT (0x1) +#define GPU_CE_FBUF_CRC_FAIL (0x2) +#define GPU_CE_FBUF_MAGIC_CHK_FAIL (0x3) +#ifdef CONFIG_NVGPU_NON_FUSA +#define GPU_CE_INVALID_CONFIG (0x4) +#endif /** * @} */ diff --git a/libs/dgpu/libnvgpu-drv-dgpu_safe.export b/libs/dgpu/libnvgpu-drv-dgpu_safe.export index 889c8255f..eb6cf09ea 100644 --- a/libs/dgpu/libnvgpu-drv-dgpu_safe.export +++ b/libs/dgpu/libnvgpu-drv-dgpu_safe.export @@ -81,7 +81,6 @@ gm20b_gr_falcon_submit_fecs_method_op gm20b_gr_falcon_ctrl_ctxsw gm20b_bus_bar1_bind gp10b_bus_bar2_bind -gp10b_ce_nonstall_isr gp10b_get_max_page_table_levels gp10b_mm_get_default_va_sizes gp10b_mm_get_iommu_bit diff --git a/libs/igpu/libnvgpu-drv-igpu_safe.export b/libs/igpu/libnvgpu-drv-igpu_safe.export index 0b7c7e91d..3e98a6599 100644 --- a/libs/igpu/libnvgpu-drv-igpu_safe.export +++ b/libs/igpu/libnvgpu-drv-igpu_safe.export @@ -81,7 +81,6 @@ gm20b_gr_falcon_submit_fecs_method_op gm20b_gr_falcon_ctrl_ctxsw gm20b_bus_bar1_bind gp10b_bus_bar2_bind -gp10b_ce_nonstall_isr gp10b_get_max_page_table_levels gp10b_mm_get_default_va_sizes gp10b_mm_get_iommu_bit diff --git a/userspace/required_tests.ini b/userspace/required_tests.ini index 0a275c3a0..0a4fc4e63 100644 --- a/userspace/required_tests.ini +++ b/userspace/required_tests.ini @@ -98,7 +98,6 @@ test_init_hw.bus_init_hw=0 [ce] test_ce_free_env.ce_free_env=0 test_ce_init_support.ce_init_support=0 -test_ce_nonstall_isr.ce_nonstall_isr=0 test_ce_setup_env.ce_setup_env=0 test_ce_stall_isr.ce_stall_isr=0 test_get_num_pce.ce_get_num_pce=0 diff --git a/userspace/units/ce/nvgpu-ce.c b/userspace/units/ce/nvgpu-ce.c index 841539704..512017cfb 100644 --- a/userspace/units/ce/nvgpu-ce.c +++ b/userspace/units/ce/nvgpu-ce.c @@ -207,7 +207,8 @@ int test_ce_stall_isr(struct unit_module *m, struct gk20a *g, void *args) g->ops.ce.isr_stall = gv11b_ce_stall_isr; for (inst_id = 0; inst_id < NUM_INST; inst_id++) { intr_status_written[inst_id] = 0; - intr_val = 0x1f; /* all intr sources */ + /* all intr sources except (non)blockpipe as they are not supported on safety */ + intr_val = 0x14; nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id), intr_val); g->ops.ce.isr_stall(g, inst_id, 0); @@ -236,56 +237,6 @@ done: return ret; } -int test_ce_nonstall_isr(struct unit_module *m, struct gk20a *g, void *args) -{ - int ret = UNIT_SUCCESS; - int inst_id; - u32 intr_val; - u32 val; - - g->ops.ce.isr_nonstall = gp10b_ce_nonstall_isr; - for (inst_id = 0; inst_id < NUM_INST; inst_id++) { - intr_status_written[inst_id] = 0; - intr_val = 0x1f; /* all intr sources */ - nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id), - intr_val); - val = g->ops.ce.isr_nonstall(g, inst_id, 0); - if (val != (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE | - NVGPU_CIC_NONSTALL_OPS_POST_EVENTS)) { - ret = UNIT_FAIL; - unit_err(m, "incorrect ops returned 0x%08x\n", val); - goto done; - } - if (intr_status_written[inst_id] != - ce_intr_status_nonblockpipe_pending_f()) { - ret = UNIT_FAIL; - unit_err(m, "intr_status not cleared properly, only 0x%08x\n", - intr_status_written[inst_id]); - goto done; - } - - intr_status_written[inst_id] = 0; - intr_val = 0x0; - nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id), - intr_val); - val = g->ops.ce.isr_nonstall(g, inst_id, 0); - if (val != 0U) { - ret = UNIT_FAIL; - unit_err(m, "incorrect ops returned 0x%08x\n", val); - goto done; - } - if (intr_status_written[inst_id] != intr_val) { - ret = UNIT_FAIL; - unit_err(m, "intr_status not cleared, only 0x%08x\n", - intr_status_written[inst_id]); - goto done; - } - } - -done: - return ret; -} - static u32 mock_get_num_lce(struct gk20a *g) { return NUM_INST; @@ -383,7 +334,6 @@ struct unit_module_test ce_tests[] = { UNIT_TEST(ce_setup_env, test_ce_setup_env, NULL, 0), UNIT_TEST(ce_init_support, test_ce_init_support, NULL, 0), UNIT_TEST(ce_stall_isr, test_ce_stall_isr, NULL, 0), - UNIT_TEST(ce_nonstall_isr, test_ce_nonstall_isr, NULL, 0), UNIT_TEST(mthd_buffer_fault_in_bar2_fault, test_mthd_buffer_fault_in_bar2_fault, NULL, 0), UNIT_TEST(ce_get_num_pce, test_get_num_pce, NULL, 0), UNIT_TEST(ce_init_prod_values, test_init_prod_values, NULL, 0), diff --git a/userspace/units/ce/nvgpu-ce.h b/userspace/units/ce/nvgpu-ce.h index f2a3214f2..ba4c475af 100644 --- a/userspace/units/ce/nvgpu-ce.h +++ b/userspace/units/ce/nvgpu-ce.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -115,32 +115,6 @@ int test_ce_init_support(struct unit_module *m, struct gk20a *g, void *args); */ int test_ce_stall_isr(struct unit_module *m, struct gk20a *g, void *args); -/** - * Test specification for: test_ce_nonstall_isr - * - * Description: Validate nonstall interrupt handler functionality. - * - * Test Type: Feature - * - * Targets: gops_ce.isr_nonstall, gp10b_ce_nonstall_isr - * - * Input: test_ce_setup_env must have been run. - * - * Steps: - * - Set all CE interrupt sources pending in the interrupt status reg for each - * instance. - * - Call gops_ce.isr_nonstall. - * - Verify only the nonstall interrupt is cleared and the expected ops are - * returned. - * - Set no CE interrupt sources pending in the interrupt status reg for each - * instance. - * - Call gops_ce.isr_nonstall. - * - Verify no interrupts are cleared and no ops are returned. - * - * Output: Returns PASS if expected result is met, FAIL otherwise. - */ -int test_ce_nonstall_isr(struct unit_module *m, struct gk20a *g, void *args); - /** * Test specification for: test_mthd_buffer_fault_in_bar2_fault * @@ -209,4 +183,4 @@ int test_get_num_pce(struct unit_module *m, struct gk20a *g, void *args); */ int test_init_prod_values(struct unit_module *m, struct gk20a *g, void *args); -#endif /* UNIT_NVGPU_CE_H */ \ No newline at end of file +#endif /* UNIT_NVGPU_CE_H */ diff --git a/userspace/units/mc/nvgpu-mc.c b/userspace/units/mc/nvgpu-mc.c index df638c77b..5cf0d2edd 100644 --- a/userspace/units/mc/nvgpu-mc.c +++ b/userspace/units/mc/nvgpu-mc.c @@ -176,11 +176,13 @@ static void mock_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) u.ce_isr = true; } +#ifdef CONFIG_NVGPU_NONSTALL_INTR static u32 mock_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) { u.ce_isr = true; return u.ce_isr_return; } +#endif static void mock_fb_isr(struct gk20a *g, u32 intr_unit_bitmask) { @@ -254,7 +256,9 @@ int test_mc_setup_env(struct unit_module *m, /* override HALs */ g->ops.bus.isr = mock_bus_isr; g->ops.ce.isr_stall = mock_ce_stall_isr; +#ifdef CONFIG_NVGPU_NONSTALL_INTR g->ops.ce.isr_nonstall = mock_ce_nonstall_isr; +#endif g->ops.fb.intr.isr = mock_fb_isr; g->ops.fifo.intr_0_isr = mock_fifo_stall_isr; g->ops.fifo.intr_1_isr = mock_fifo_nonstall_isr; @@ -671,15 +675,18 @@ int test_isr_nonstall(struct unit_module *m, struct gk20a *g, void *args) } /* for branch coverage set this HAL to NULL */ +#ifdef CONFIG_NVGPU_NONSTALL_INTR g->ops.ce.isr_nonstall = NULL; +#endif for (i = 0; i < NUM_MC_UNITS; i++) { intrs_pending |= mc_units[i].bit; } nvgpu_posix_io_writel_reg_space(g, NONSTALL_PENDING_REG, intrs_pending); reset_ctx(); g->ops.mc.isr_nonstall(g); +#ifdef CONFIG_NVGPU_NONSTALL_INTR g->ops.ce.isr_nonstall = mock_ce_nonstall_isr; - +#endif return UNIT_SUCCESS; }