From 4034de5756ceb1b84a0b28ff9492c3b0350c7ef6 Mon Sep 17 00:00:00 2001 From: dt Date: Fri, 6 Aug 2021 09:55:16 +0000 Subject: [PATCH] gpu: nvgpu: Fix for smid programming As number of available tpc/gpc is more than 4 in new dgpu, this fix is needed for correct sm_id config programming. After CONFIG_UBSAN kernel compilation flag to know any shifting cause overflow or not enablement , this is identified where the shift is overflowing u32 when number of available TPCs is more than four. Bug 200727116 Change-Id: I9169a00614e4a648afe4a2d2f8e76c178e8c19eb Signed-off-by: dt Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2571823 Reviewed-by: Deepak Nibade Reviewed-by: Vaibhav Kachore Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc_kernel_abi Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c index 0b61c5465..abd11ae8d 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c @@ -510,7 +510,7 @@ int gv11b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id, index = nvgpu_safe_add_u32(gpc_index, index); tpc_sm_id[index] |= (tpc_id << nvgpu_safe_mult_u32( - tpc_index, + (tpc_index & 3U), bit_stride)); } nvgpu_gr_ctx_patch_write(g, gr_ctx,