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gpu: nvgpu: update CBC init sequence

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At present, for each resume cycle the driver sends the
"nvgpu_cbc_op_clear" command to L2 cache controller, this causes the
contents of the compression bit backing store to be cleared, and results
in corrupting the metadata for all the compressible surfaces already allocated.
Fix this by updating cbc.init function to be aware of resume state and
not clear the compression bit backing store, instead issue
"nvgpu_cbc_op_invalide" command, this should leave the backing store in a
consistent state across suspend/resume cycles.

The updated cbc.init HAL for gv11b is reusable acrosss multiple chips, hence
remove unnecessary chip specific cbc.init HALs.

Bug 3483688

Change-Id: I2de848a083436bc085ee98e438874214cb61261f
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2660075
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2022-01-27 02:35:13 +00:00
committed by mobile promotions
parent 29a0a146ac
commit 40397ac0c4
13 changed files with 43 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/nvgpu/common/cbc/cbc.c
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@@ -62,9 +62,15 @@ int nvgpu_cbc_init_support(struct gk20a *g)
{
int err = 0;
struct nvgpu_cbc *cbc = g->cbc;
bool is_resume = true;
nvgpu_log_fn(g, " ");
/*
* If cbc == NULL, the device is being powered-on for the first
* time and hence nvgpu_cbc_init_support is not called as part of
* suspend/resume cycle, so set is_resume to false.
*/
if (cbc == NULL) {
cbc = nvgpu_kzalloc(g, sizeof(*cbc));
if (cbc == NULL) {
@@ -81,10 +87,11 @@ int nvgpu_cbc_init_support(struct gk20a *g)
return err;
}
}
is_resume = false;
}
if (g->ops.cbc.init != NULL) {
g->ops.cbc.init(g, g->cbc);
g->ops.cbc.init(g, g->cbc, is_resume);
}
return err;