From 40a58a7c06e3c852135e4bf4255f837a2dea8939 Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Mon, 15 Jul 2019 08:42:25 -0700 Subject: [PATCH] gpu: nvgpu: fix MISRA errors common.fifo.engines Rule 15.7 needs if-elseif constructs to be terminated with else statement. Rule 17.7 requires function return value to be checked for error information. This patch fixes MISRA errors mentioned above. Jira NVGPU-3809 Change-Id: I201497c3fb679514268d06ff2b3e9cf378591c5b Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/2153554 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Philip Elcan GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/engines.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index 8f9db31f5..9e2c75d54 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -321,6 +321,8 @@ int nvgpu_engine_disable_activity(struct gk20a *g, } else if (nvgpu_pbdma_status_is_chsw_load(&pbdma_status) || nvgpu_pbdma_status_is_chsw_switch(&pbdma_status)) { pbdma_chid = pbdma_status.next_id; + } else { + /* Nothing to do here */ } if (pbdma_chid != NVGPU_INVALID_CHANNEL_ID) { @@ -343,6 +345,8 @@ int nvgpu_engine_disable_activity(struct gk20a *g, } else if (nvgpu_engine_status_is_ctxsw_switch(&engine_status) || nvgpu_engine_status_is_ctxsw_load(&engine_status)) { engine_chid = engine_status.ctx_next_id; + } else { + /* Nothing to do here */ } if (engine_chid != NVGPU_INVALID_ENG_ID && engine_chid != pbdma_chid) { @@ -417,7 +421,7 @@ int nvgpu_engine_wait_for_idle(struct gk20a *g) { struct nvgpu_timeout timeout; u32 delay = POLL_DELAY_MIN_US; - int ret = 0; + int ret = 0, err = 0; u32 i, host_num_engines; struct nvgpu_engine_status_info engine_status; @@ -426,8 +430,11 @@ int nvgpu_engine_wait_for_idle(struct gk20a *g) host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES); - nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g), + err = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g), NVGPU_TIMER_CPU_TIMER); + if (err != 0) { + return -EINVAL; + } for (i = 0; i < host_num_engines; i++) { ret = -ETIMEDOUT;