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gpu: nvgpu: use a separate big vm for cde

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Allocate a separate VM for CDE channels instead of using the system
(PMU) vm, and make it much bigger than the PMU's to fit the maximum
number of CDE channels there.

Bug 1566740

Change-Id: I4f487c40c9ec79cc9ffb880b0ecd3f47eb450336
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/815149
Reviewed-by: Automatic_Commit_Validation_User
This commit is contained in:
Konsta Holtta
2015-10-09 13:36:08 +03:00
parent 8452348539
commit 411c3a9a4f
3 changed files with 24 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/gk20a/cde_gk20a.c
View File

@@ -1194,8 +1194,8 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
}
/* bind the channel to the vm */
gk20a_vm_get(&g->mm.pmu.vm);
ch->vm = &g->mm.pmu.vm;
gk20a_vm_get(&g->mm.cde.vm);
ch->vm = &g->mm.cde.vm;
err = channel_gk20a_commit_va(ch);
if (err) {
gk20a_warn(&cde_ctx->pdev->dev, "cde: could not bind vm");

19
drivers/gpu/nvgpu/gk20a/mm_gk20a.c
View File

@@ -105,6 +105,7 @@ static int update_gmmu_ptes_locked(struct vm_gk20a *vm,
static int __must_check gk20a_init_system_vm(struct mm_gk20a *mm);
static int __must_check gk20a_init_bar1_vm(struct mm_gk20a *mm);
static int __must_check gk20a_init_hwpm(struct mm_gk20a *mm);
static int __must_check gk20a_init_cde_vm(struct mm_gk20a *mm);
struct gk20a_dmabuf_priv {
@@ -344,6 +345,7 @@ static void gk20a_remove_mm_support(struct mm_gk20a *mm)
gk20a_remove_vm(&mm->bar1.vm, &mm->bar1.inst_block);
gk20a_remove_vm(&mm->pmu.vm, &mm->pmu.inst_block);
gk20a_free_inst_block(gk20a_from_mm(mm), &mm->hwpm.inst_block);
gk20a_vm_remove_support_nofree(&mm->cde.vm);
}
int gk20a_init_mm_setup_sw(struct gk20a *g)
@@ -386,6 +388,10 @@ int gk20a_init_mm_setup_sw(struct gk20a *g)
if (err)
return err;
err = gk20a_init_cde_vm(mm);
if (err)
return err;
/* set vm_alloc_share op here as gk20a_as_alloc_share needs it */
g->ops.mm.vm_alloc_share = gk20a_vm_alloc_share;
mm->remove_support = gk20a_remove_mm_support;
@@ -3268,6 +3274,19 @@ static int gk20a_init_hwpm(struct mm_gk20a *mm)
return 0;
}
static int gk20a_init_cde_vm(struct mm_gk20a *mm)
{
struct vm_gk20a *vm = &mm->cde.vm;
struct gk20a *g = gk20a_from_mm(mm);
u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size;
return gk20a_init_vm(mm, vm, big_page_size,
SZ_4K * 16,
NV_MM_DEFAULT_KERNEL_SIZE,
NV_MM_DEFAULT_KERNEL_SIZE + NV_MM_DEFAULT_USER_SIZE,
false, "cde");
}
void gk20a_mm_init_pdb(struct gk20a *g, void *inst_ptr, u64 pdb_addr)
{
u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());

3
drivers/gpu/nvgpu/gk20a/mm_gk20a.h
View File

@@ -318,6 +318,9 @@ struct mm_gk20a {
struct mem_desc inst_block;
} hwpm;
struct {
struct vm_gk20a vm;
} cde;
struct mutex l2_op_lock;
#ifdef CONFIG_ARCH_TEGRA_18x_SOC