From 4222052a53182e34c21b1ebdc9fd47293cdf920d Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Thu, 2 May 2019 14:29:29 -0400 Subject: [PATCH] gpu: nvgpu: gmmu: fix MISRA 16.x violations in gmmu.h MISRA rules 16.x enforce specific switch statement formats including always having a break. Fix MISRA 16.x violations in gmmu.h. JIRA NVGPU-3340 Change-Id: Ic03878265e84a571c128c59ba5eee6c83a725a67 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2110596 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/gmmu.h | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h index d93ee6d7a..8cc6d09fb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h @@ -114,16 +114,23 @@ struct gk20a_mmu_level { static inline const char *nvgpu_gmmu_perm_str(enum gk20a_mem_rw_flag p) { + const char *str; + switch (p) { case gk20a_mem_flag_none: - return "RW"; + str = "RW"; + break; case gk20a_mem_flag_write_only: - return "WO"; + str = "WO"; + break; case gk20a_mem_flag_read_only: - return "RO"; + str = "RO"; + break; default: - return "??"; + str = "??"; + break; } + return str; } int nvgpu_gmmu_init_page_table(struct vm_gk20a *vm);