From 42440a161a4f7284c1be18a8535d6975e322d759 Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Fri, 12 Jul 2019 15:35:47 -0700 Subject: [PATCH] gpu: nvgpu: fix MISRA violations common.gr.ctx Rule 10.6 forbids assignment of an 32-bit expression to a 64-bit target. This patch fixes MISRA 10.6 errors in common/gr/ctx.c Jira NVGPU-3808 Change-Id: I02bc42040e494b230d51aa5c3ae035dd5e3ad9aa Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/2152643 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/ctx.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/ctx.c b/drivers/gpu/nvgpu/common/gr/ctx.c index 611ace08a..c7a601ab6 100644 --- a/drivers/gpu/nvgpu/common/gr/ctx.c +++ b/drivers/gpu/nvgpu/common/gr/ctx.c @@ -467,8 +467,10 @@ void nvgpu_gr_ctx_patch_write(struct gk20a *g, return; } - nvgpu_mem_wr32(g, &gr_ctx->patch_ctx.mem, patch_slot, addr); - nvgpu_mem_wr32(g, &gr_ctx->patch_ctx.mem, patch_slot + 1U, data); + nvgpu_mem_wr32(g, &gr_ctx->patch_ctx.mem, + (u64)patch_slot, addr); + nvgpu_mem_wr32(g, &gr_ctx->patch_ctx.mem, + (u64)patch_slot + 1ULL, data); gr_ctx->patch_ctx.data_count = nvgpu_safe_add_u32( gr_ctx->patch_ctx.data_count, 1U); nvgpu_log(g, gpu_dbg_info,