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gpu: nvgpu: fifo MISRA fix for Rule 10.1

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JIRA NVGPU-3383

Change-Id: I18ab3ebd4728ff798c0cc47f6cb84d1dda225b53
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116729
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-05-09 12:02:16 -07:00
committed by mobile promotions
parent 8d34edfee0
commit 42c2ea552d
1 changed files with 9 additions and 3 deletions
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12
drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c
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@@ -364,7 +364,7 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
u32 pbdma_id;
u32 act_eng_id;
u32 runlist_id;
int ret = 0;
int err, ret = 0;
u32 tsgid;
if (id_type == ID_TYPE_TSG) {
@@ -382,17 +382,23 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
for_each_set_bit(bit, &runlist_served_pbdmas, f->num_pbdma) {
pbdma_id = U32(bit);
ret |= gv11b_fifo_preempt_poll_pbdma(g, tsgid,
err = gv11b_fifo_preempt_poll_pbdma(g, tsgid,
pbdma_id);
if (err != 0) {
ret = err;
}
}
f->runlist_info[runlist_id]->reset_eng_bitmask = 0U;
for_each_set_bit(bit, &runlist_served_engines, f->max_engines) {
act_eng_id = U32(bit);
ret |= gv11b_fifo_preempt_poll_eng(g,
err = gv11b_fifo_preempt_poll_eng(g,
tsgid, act_eng_id,
&f->runlist_info[runlist_id]->reset_eng_bitmask);
if (err != 0 && ret == 0) {
ret = err;
}
}
return ret;
}