From 42f5a2d806ad007002efa9a10a61372cec8e43eb Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Thu, 1 Aug 2019 10:54:10 -0400 Subject: [PATCH] gpu: nvgpu: fb: fix CERT-C violations CERT-C Rule INT30-C Requires that unsigned integer operations do not wrap. Fix these violations by using the safe ops. JIRA NVGPU-3868 Change-Id: I51e8ee212777232b6d7c033078bea9b9c77ff898 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2166259 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Nitin Kumbhar Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c | 2 +- .../hal/fb/intr/fb_intr_ecc_gv11b_fusa.c | 36 ++++++++++++------- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c index 6b20b0b12..423a78b4c 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c @@ -308,5 +308,5 @@ void gm20b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size) (val << WPR_INFO_ADDR_ALIGNMENT)); *wpr_base = wpr_start; - *wpr_size = (wpr_end - wpr_start); + *wpr_size = nvgpu_safe_sub_u64(wpr_end, wpr_start); } diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c index f0512e59c..e871e18f1 100644 --- a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c @@ -146,10 +146,14 @@ static void gv11b_fb_intr_handle_ecc_l2tlb(struct gk20a *g, u32 ecc_status) BIT32(fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s()); } - g->ecc.fb.mmu_l2tlb_ecc_corrected_err_count[0].counter += - corrected_delta; - g->ecc.fb.mmu_l2tlb_ecc_uncorrected_err_count[0].counter += - uncorrected_delta; + g->ecc.fb.mmu_l2tlb_ecc_corrected_err_count[0].counter = + nvgpu_safe_add_u32( + g->ecc.fb.mmu_l2tlb_ecc_corrected_err_count[0].counter, + corrected_delta); + g->ecc.fb.mmu_l2tlb_ecc_uncorrected_err_count[0].counter = + nvgpu_safe_add_u32( + g->ecc.fb.mmu_l2tlb_ecc_uncorrected_err_count[0].counter, + uncorrected_delta); if ((ecc_status & fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()) @@ -224,10 +228,14 @@ static void gv11b_fb_intr_handle_ecc_hubtlb(struct gk20a *g, u32 ecc_status) BIT32(fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s()); } - g->ecc.fb.mmu_hubtlb_ecc_corrected_err_count[0].counter += - corrected_delta; - g->ecc.fb.mmu_hubtlb_ecc_uncorrected_err_count[0].counter += - uncorrected_delta; + g->ecc.fb.mmu_hubtlb_ecc_corrected_err_count[0].counter = + nvgpu_safe_add_u32( + g->ecc.fb.mmu_hubtlb_ecc_corrected_err_count[0].counter, + corrected_delta); + g->ecc.fb.mmu_hubtlb_ecc_uncorrected_err_count[0].counter = + nvgpu_safe_add_u32( + g->ecc.fb.mmu_hubtlb_ecc_uncorrected_err_count[0].counter, + uncorrected_delta); if ((ecc_status & fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()) != 0U) { @@ -301,10 +309,14 @@ static void gv11b_fb_intr_handle_ecc_fillunit(struct gk20a *g, u32 ecc_status) BIT32(fb_mmu_fillunit_ecc_uncorrected_err_count_total_s()); } - g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter += - corrected_delta; - g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter += - uncorrected_delta; + g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter = + nvgpu_safe_add_u32( + g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter, + corrected_delta); + g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter = + nvgpu_safe_add_u32( + g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter, + uncorrected_delta); if ((ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()) != 0U) {