diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
index c5afc33e9..a3acd6ec5 100644
--- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c
+++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
@@ -400,6 +400,12 @@ void nvgpu_gr_obj_ctx_commit_global_ctx_buffers(struct gk20a *g,
 	}
 #endif
 
+#ifdef CONFIG_NVGPU_GRAPHICS
+	if (g->ops.gr.init.commit_rops_crop_override != NULL) {
+		g->ops.gr.init.commit_rops_crop_override(g, gr_ctx, patch);
+	}
+#endif
+
 	if (patch) {
 		nvgpu_gr_ctx_patch_write_end(g, gr_ctx, false);
 	}
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c
index 1bcf0af17..05b093cfc 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c
@@ -25,6 +25,7 @@
 #include <nvgpu/soc.h>
 #include <nvgpu/log.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/gr/ctx.h>
 #include <nvgpu/static_analysis.h>
 
 #include "gr_init_ga10b.h"
@@ -58,6 +59,19 @@ u32 ga10b_gr_init_get_ctx_betacb_size(struct gk20a *g)
 			gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()));
 }
 
+void ga10b_gr_init_commit_rops_crop_override(struct gk20a *g,
+				struct nvgpu_gr_ctx *gr_ctx, bool patch)
+{
+	if (g->emulate_mode) {
+		u32 data = 0U;
+		data = nvgpu_readl(g, gr_pri_gpcs_rops_crop_debug1_r());
+		data = set_field(data,
+			gr_pri_gpcs_rops_crop_debug1_crd_cond_read_m(),
+			gr_pri_gpcs_rops_crop_debug1_crd_cond_read_disable_f());
+		nvgpu_gr_ctx_patch_write(g, gr_ctx,
+			gr_pri_gpcs_rops_crop_debug1_r(), data, patch);
+	}
+}
 #endif
 
 #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h
index 982d92f8f..b98c7b6b9 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h
@@ -61,6 +61,8 @@ u32 ga10b_gr_init_get_attrib_cb_gfxp_size(struct gk20a *g);
 
 u32 ga10b_gr_init_get_ctx_spill_size(struct gk20a *g);
 u32 ga10b_gr_init_get_ctx_betacb_size(struct gk20a *g);
+void ga10b_gr_init_commit_rops_crop_override(struct gk20a *g,
+			struct nvgpu_gr_ctx *gr_ctx, bool patch);
 
 #endif /* CONFIG_NVGPU_GRAPHICS */
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index cf1db7628..ca4b5482e 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -628,6 +628,7 @@ static const struct gops_gr_init ga10b_ops_gr_init = {
 	.rop_mapping = gv11b_gr_init_rop_mapping,
 	.get_rtv_cb_size = tu104_gr_init_get_rtv_cb_size,
 	.commit_rtv_cb = tu104_gr_init_commit_rtv_cb,
+	.commit_rops_crop_override = ga10b_gr_init_commit_rops_crop_override,
 #endif /* CONFIG_NVGPU_GRAPHICS */
 #ifdef CONFIG_NVGPU_GFXP
 	.preemption_state = gv11b_gr_init_preemption_state,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
index 24b594c8f..b23863af6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
@@ -840,6 +840,8 @@ struct gops_gr_init {
 	u32 (*get_rtv_cb_size)(struct gk20a *g);
 	void (*commit_rtv_cb)(struct gk20a *g, u64 addr,
 			      struct nvgpu_gr_ctx *gr_ctx, bool patch);
+	void (*commit_rops_crop_override)(struct gk20a *g,
+			      struct nvgpu_gr_ctx *gr_ctx, bool patch);
 #endif
 #ifdef CONFIG_NVGPU_GFXP
 	int (*preemption_state)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
index 419a39fcd..c1bbcd168 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
@@ -1089,6 +1089,9 @@
 #define gr_egpc0_etpc0_sm0_dsm_perf_counter5_r()                   (0x00584618U)
 #define gr_egpc0_etpc0_sm0_dsm_perf_counter6_r()                   (0x0058461cU)
 #define gr_egpc0_etpc0_sm0_dsm_perf_counter7_r()                   (0x00584620U)
+#define gr_pri_gpcs_rops_crop_debug1_r()                           (0x0041bc80U)
+#define gr_pri_gpcs_rops_crop_debug1_crd_cond_read_m()         (U32(0x3U) << 0U)
+#define gr_pri_gpcs_rops_crop_debug1_crd_cond_read_disable_f()            (0x1U)
 #define gr_pri_gpcs_rops_crop_debug4_r()                           (0x0041bc8cU)
 #define gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_s()                     (1U)
 #define gr_pri_gpcs_rops_crop_debug4_clamp_fp_blend_m()       (U32(0x1U) << 18U)