From 43d6dc82c90ad1045b19efc5ab44269dea913cfb Mon Sep 17 00:00:00 2001 From: Divya Singhatwaria Date: Fri, 8 Mar 2019 16:29:44 +0530 Subject: [PATCH] gpu: nvgpu: Re-structure nvgpu_pmu struct - Make a new structure: nvgpu_pmu_pg for PG unit - This new struct combines all PG unit variables like elpg_stat, elpg_refcnt, pg_init etc. into one structure as a part of PG unit refactoring. - Use pmu_pg struct to access all PG variables. - Eg: &pmu->pmu_pg.elpg_mutex, &pmu->pmu_pg.pg_mutex and so on. NVGPU-1973 Change-Id: I9973072826f4089f6315827bce49fa30dbcbcdda Signed-off-by: Divya Singhatwaria Reviewed-on: https://git-master.nvidia.com/r/2071306 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c | 8 +- drivers/gpu/nvgpu/common/pmu/pg/pmu_aelpg.c | 10 +- drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c | 97 ++++++++++---------- drivers/gpu/nvgpu/common/pmu/pmu.c | 14 ++- drivers/gpu/nvgpu/common/pmu/pmu_debug.c | 4 +- drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 12 +-- drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c | 16 ++-- drivers/gpu/nvgpu/common/pmu/pmu_gp106.c | 2 +- drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c | 2 +- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 8 +- drivers/gpu/nvgpu/include/nvgpu/pmu.h | 23 +---- drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h | 18 ++++ drivers/gpu/nvgpu/os/linux/debug_pmu.c | 8 +- drivers/gpu/nvgpu/os/linux/driver_common.c | 10 +- drivers/gpu/nvgpu/os/linux/sysfs.c | 8 +- 15 files changed, 120 insertions(+), 120 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c b/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c index 9482aa883..a24ab673b 100644 --- a/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c +++ b/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c @@ -380,7 +380,7 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock) if (pstate_lock) { nvgpu_clk_arb_pstate_change_lock(g, true); } - nvgpu_mutex_acquire(&pmu->pg_mutex); + nvgpu_mutex_acquire(&pmu->pmu_pg.pg_mutex); present_pstate = nvgpu_clk_arb_get_current_pstate(g); @@ -400,7 +400,7 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock) } } - nvgpu_mutex_release(&pmu->pg_mutex); + nvgpu_mutex_release(&pmu->pmu_pg.pg_mutex); if (pstate_lock) { nvgpu_clk_arb_pstate_change_lock(g, false); } @@ -421,7 +421,7 @@ int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock) if (pstate_lock) { nvgpu_clk_arb_pstate_change_lock(g, true); } - nvgpu_mutex_acquire(&pmu->pg_mutex); + nvgpu_mutex_acquire(&pmu->pmu_pg.pg_mutex); present_pstate = nvgpu_clk_arb_get_current_pstate(g); @@ -445,7 +445,7 @@ int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock) } exit_unlock: - nvgpu_mutex_release(&pmu->pg_mutex); + nvgpu_mutex_release(&pmu->pmu_pg.pg_mutex); if (pstate_lock) { nvgpu_clk_arb_pstate_change_lock(g, false); } diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pmu_aelpg.c b/drivers/gpu/nvgpu/common/pmu/pg/pmu_aelpg.c index a65567968..670716ecf 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pmu_aelpg.c +++ b/drivers/gpu/nvgpu/common/pmu/pg/pmu_aelpg.c @@ -34,7 +34,7 @@ int nvgpu_aelpg_init(struct gk20a *g) union pmu_ap_cmd ap_cmd; ap_cmd.init.cmd_id = PMU_AP_CMD_ID_INIT; - ap_cmd.init.pg_sampling_period_us = g->pmu.aelpg_param[0]; + ap_cmd.init.pg_sampling_period_us = g->pmu.pmu_pg.aelpg_param[0]; status = nvgpu_pmu_ap_send_command(g, &ap_cmd, false); return status; @@ -48,13 +48,13 @@ int nvgpu_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id) ap_cmd.init_and_enable_ctrl.cmd_id = PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL; ap_cmd.init_and_enable_ctrl.ctrl_id = ctrl_id; ap_cmd.init_and_enable_ctrl.params.min_idle_filter_us = - g->pmu.aelpg_param[1]; + g->pmu.pmu_pg.aelpg_param[1]; ap_cmd.init_and_enable_ctrl.params.min_target_saving_us = - g->pmu.aelpg_param[2]; + g->pmu.pmu_pg.aelpg_param[2]; ap_cmd.init_and_enable_ctrl.params.power_break_even_us = - g->pmu.aelpg_param[3]; + g->pmu.pmu_pg.aelpg_param[3]; ap_cmd.init_and_enable_ctrl.params.cycles_per_sample_max = - g->pmu.aelpg_param[4]; + g->pmu.pmu_pg.aelpg_param[4]; switch (ctrl_id) { case PMU_AP_CTRL_ID_GRAPHICS: diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c index e6b3bc09f..1fc02c902 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c +++ b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c @@ -57,12 +57,12 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) nvgpu_log_fn(g, " "); - pmu->initialized = true; + pmu->pmu_pg.initialized = true; nvgpu_pmu_state_change(g, PMU_STATE_STARTED, false); if (nvgpu_is_enabled(g, NVGPU_PMU_ZBC_SAVE)) { /* Save zbc table after PMU is initialized. */ - pmu->zbc_ready = true; + pmu->pmu_pg.zbc_ready = true; g->ops.pmu.save_zbc(g, 0xf); } @@ -107,7 +107,7 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg, if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { pmu->mscg_transition_state = PMU_ELPG_STAT_ON; } else { - pmu->elpg_stat = PMU_ELPG_STAT_ON; + pmu->pmu_pg.elpg_stat = PMU_ELPG_STAT_ON; } break; case PMU_PG_ELPG_MSG_DISALLOW_ACK: @@ -117,7 +117,7 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg, if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { pmu->mscg_transition_state = PMU_ELPG_STAT_OFF; } else { - pmu->elpg_stat = PMU_ELPG_STAT_OFF; + pmu->pmu_pg.elpg_stat = PMU_ELPG_STAT_OFF; } if (pmu->pmu_state == PMU_STATE_ELPG_BOOTING) { @@ -125,7 +125,7 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg, g->ops.pmu.pmu_pg_engines_feature_list(g, PMU_PG_ELPG_ENGINE_ID_GRAPHICS) != NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) { - pmu->initialized = true; + pmu->pmu_pg.initialized = true; nvgpu_pmu_state_change(g, PMU_STATE_STARTED, true); WRITE_ONCE(pmu->mscg_stat, PMU_MSCG_DISABLED); @@ -205,7 +205,7 @@ static int pmu_enable_elpg_locked(struct gk20a *g, u8 pg_engine_id) * pending to sync with follow up ELPG disable */ if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { - pmu->elpg_stat = PMU_ELPG_STAT_ON_PENDING; + pmu->pmu_pg.elpg_stat = PMU_ELPG_STAT_ON_PENDING; } else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { pmu->mscg_transition_state = PMU_ELPG_STAT_ON_PENDING; } @@ -240,18 +240,18 @@ int nvgpu_pmu_enable_elpg(struct gk20a *g) return ret; } - nvgpu_mutex_acquire(&pmu->elpg_mutex); + nvgpu_mutex_acquire(&pmu->pmu_pg.elpg_mutex); - pmu->elpg_refcnt++; - if (pmu->elpg_refcnt <= 0) { + pmu->pmu_pg.elpg_refcnt++; + if (pmu->pmu_pg.elpg_refcnt <= 0) { goto exit_unlock; } /* something is not right if we end up in following code path */ - if (unlikely(pmu->elpg_refcnt > 1)) { + if (unlikely(pmu->pmu_pg.elpg_refcnt > 1)) { nvgpu_warn(g, "%s(): possible elpg refcnt mismatch. elpg refcnt=%d", - __func__, pmu->elpg_refcnt); + __func__, pmu->pmu_pg.elpg_refcnt); WARN_ON(true); } @@ -263,7 +263,7 @@ int nvgpu_pmu_enable_elpg(struct gk20a *g) } /* return if ELPG is already on or on_pending or off_on_pending */ - if (pmu->elpg_stat != PMU_ELPG_STAT_OFF) { + if (pmu->pmu_pg.elpg_stat != PMU_ELPG_STAT_OFF) { goto exit_unlock; } @@ -286,7 +286,7 @@ int nvgpu_pmu_enable_elpg(struct gk20a *g) } exit_unlock: - nvgpu_mutex_release(&pmu->elpg_mutex); + nvgpu_mutex_release(&pmu->pmu_pg.elpg_mutex); nvgpu_log_fn(g, "done"); return ret; } @@ -312,33 +312,33 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g) pg_engine_id_list = g->ops.pmu.pmu_pg_supported_engines_list(g); } - nvgpu_mutex_acquire(&pmu->elpg_mutex); + nvgpu_mutex_acquire(&pmu->pmu_pg.elpg_mutex); - pmu->elpg_refcnt--; - if (pmu->elpg_refcnt > 0) { + pmu->pmu_pg.elpg_refcnt--; + if (pmu->pmu_pg.elpg_refcnt > 0) { nvgpu_warn(g, "%s(): possible elpg refcnt mismatch. elpg refcnt=%d", - __func__, pmu->elpg_refcnt); + __func__, pmu->pmu_pg.elpg_refcnt); WARN_ON(true); ret = 0; goto exit_unlock; } /* cancel off_on_pending and return */ - if (pmu->elpg_stat == PMU_ELPG_STAT_OFF_ON_PENDING) { - pmu->elpg_stat = PMU_ELPG_STAT_OFF; + if (pmu->pmu_pg.elpg_stat == PMU_ELPG_STAT_OFF_ON_PENDING) { + pmu->pmu_pg.elpg_stat = PMU_ELPG_STAT_OFF; ret = 0; goto exit_reschedule; } /* wait if on_pending */ - else if (pmu->elpg_stat == PMU_ELPG_STAT_ON_PENDING) { + else if (pmu->pmu_pg.elpg_stat == PMU_ELPG_STAT_ON_PENDING) { pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g), - &pmu->elpg_stat, PMU_ELPG_STAT_ON); + &pmu->pmu_pg.elpg_stat, PMU_ELPG_STAT_ON); - if (pmu->elpg_stat != PMU_ELPG_STAT_ON) { + if (pmu->pmu_pg.elpg_stat != PMU_ELPG_STAT_ON) { nvgpu_err(g, "ELPG_ALLOW_ACK failed, elpg_stat=%d", - pmu->elpg_stat); + pmu->pmu_pg.elpg_stat); nvgpu_pmu_dump_elpg_stats(pmu); nvgpu_pmu_dump_falcon_stats(pmu); ret = -EBUSY; @@ -346,7 +346,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g) } } /* return if ELPG is already off */ - else if (pmu->elpg_stat != PMU_ELPG_STAT_ON) { + else if (pmu->pmu_pg.elpg_stat != PMU_ELPG_STAT_ON) { ret = 0; goto exit_reschedule; } @@ -372,13 +372,13 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g) cmd.cmd.pg.elpg_cmd.cmd = PMU_PG_ELPG_CMD_DISALLOW; if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { - pmu->elpg_stat = PMU_ELPG_STAT_OFF_PENDING; + pmu->pmu_pg.elpg_stat = PMU_ELPG_STAT_OFF_PENDING; } else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { pmu->mscg_transition_state = PMU_ELPG_STAT_OFF_PENDING; } if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { - ptr = &pmu->elpg_stat; + ptr = &pmu->pmu_pg.elpg_stat; } else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { ptr = &pmu->mscg_transition_state; } @@ -387,6 +387,11 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g) ret = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, pmu, &seq); + if (ret != 0) { + nvgpu_err(g, "PMU_PG_ELPG_CMD_DISALLOW \ + cmd post failed"); + goto exit_unlock; + } pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g), @@ -403,7 +408,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g) exit_reschedule: exit_unlock: - nvgpu_mutex_release(&pmu->elpg_mutex); + nvgpu_mutex_release(&pmu->pmu_pg.elpg_mutex); nvgpu_log_fn(g, "done"); return ret; } @@ -424,7 +429,7 @@ static void pmu_handle_pg_stat_msg(struct gk20a *g, struct pmu_msg *msg, switch (msg->msg.pg.stat.sub_msg_id) { case PMU_PG_STAT_MSG_RESP_DMEM_OFFSET: nvgpu_pmu_dbg(g, "ALLOC_DMEM_OFFSET is acknowledged from PMU"); - pmu->stat_dmem_offset[msg->msg.pg.stat.engine_id] = + pmu->pmu_pg.stat_dmem_offset[msg->msg.pg.stat.engine_id] = msg->msg.pg.stat.data; break; default: @@ -468,7 +473,7 @@ static int pmu_pg_init_send(struct gk20a *g, u8 pg_engine_id) } /* alloc dmem for powergating state log */ - pmu->stat_dmem_offset[pg_engine_id] = 0; + pmu->pmu_pg.stat_dmem_offset[pg_engine_id] = 0; (void) memset(&cmd, 0, sizeof(struct pmu_cmd)); cmd.hdr.unit_id = PMU_UNIT_PG; tmp = PMU_CMD_HDR_SIZE + sizeof(struct pmu_pg_cmd_stat); @@ -491,7 +496,7 @@ static int pmu_pg_init_send(struct gk20a *g, u8 pg_engine_id) */ /* set for wait_event PMU_ELPG_STAT_OFF */ if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { - pmu->elpg_stat = PMU_ELPG_STAT_OFF; + pmu->pmu_pg.elpg_stat = PMU_ELPG_STAT_OFF; } else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { pmu->mscg_transition_state = PMU_ELPG_STAT_OFF; } @@ -569,8 +574,8 @@ static void pmu_handle_pg_buf_config_msg(struct gk20a *g, struct pmu_msg *msg, return; } - pmu->buf_loaded = (eng_buf_stat->status == PMU_PG_MSG_ENG_BUF_LOADED); - if ((!pmu->buf_loaded) && + pmu->pmu_pg.buf_loaded = (eng_buf_stat->status == PMU_PG_MSG_ENG_BUF_LOADED); + if ((!pmu->pmu_pg.buf_loaded) && (pmu->pmu_state == PMU_STATE_LOADING_PG_BUF)) { nvgpu_err(g, "failed to load PGENG buffer"); } else { @@ -601,15 +606,15 @@ int nvgpu_pmu_init_bind_fecs(struct gk20a *g) g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx(&cmd.cmd.pg, PMU_PGENG_GR_BUFFER_IDX_FECS); g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size(&cmd.cmd.pg, - pmu->pg_buf.size); + pmu->pmu_pg.pg_buf.size); g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base(&cmd.cmd.pg, - u64_lo32(pmu->pg_buf.gpu_va)); + u64_lo32(pmu->pmu_pg.pg_buf.gpu_va)); g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset(&cmd.cmd.pg, - (u8)(pmu->pg_buf.gpu_va & 0xFFU)); + (u8)(pmu->pmu_pg.pg_buf.gpu_va & 0xFFU)); g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx(&cmd.cmd.pg, PMU_DMAIDX_VIRT); - pmu->buf_loaded = false; + pmu->pmu_pg.buf_loaded = false; nvgpu_pmu_dbg(g, "cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_FECS"); nvgpu_pmu_state_change(g, PMU_STATE_LOADING_PG_BUF, false); err = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, @@ -650,7 +655,7 @@ void nvgpu_pmu_setup_hw_load_zbc(struct gk20a *g) g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx(&cmd.cmd.pg, PMU_DMAIDX_VIRT); - pmu->buf_loaded = false; + pmu->pmu_pg.buf_loaded = false; nvgpu_pmu_dbg(g, "cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_ZBC"); nvgpu_pmu_state_change(g, PMU_STATE_LOADING_ZBC, false); err = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, @@ -668,7 +673,7 @@ int nvgpu_pmu_get_pg_stats(struct gk20a *g, u32 pg_engine_id, u32 pg_engine_id_list = 0; int err = 0; - if (!pmu->initialized) { + if (!pmu->pmu_pg.initialized) { pg_stat_data->ingating_time = 0; pg_stat_data->ungating_time = 0; pg_stat_data->gating_cnt = 0; @@ -695,12 +700,12 @@ int nvgpu_init_task_pg_init(struct gk20a *g) nvgpu_log_fn(g, " "); - nvgpu_cond_init(&pmu->pg_init.wq); + nvgpu_cond_init(&pmu->pmu_pg.pg_init.wq); (void) snprintf(thread_name, sizeof(thread_name), "nvgpu_pg_init_%s", g->name); - err = nvgpu_thread_create(&pmu->pg_init.state_task, g, + err = nvgpu_thread_create(&pmu->pmu_pg.pg_init.state_task, g, nvgpu_pg_init_task, thread_name); if (err != 0) { nvgpu_err(g, "failed to start nvgpu_pg_init thread"); @@ -714,25 +719,25 @@ void nvgpu_kill_task_pg_init(struct gk20a *g) struct nvgpu_timeout timeout; /* make sure the pending operations are finished before we continue */ - if (nvgpu_thread_is_running(&pmu->pg_init.state_task)) { + if (nvgpu_thread_is_running(&pmu->pmu_pg.pg_init.state_task)) { /* post PMU_STATE_EXIT to exit PMU state machine loop */ nvgpu_pmu_state_change(g, PMU_STATE_EXIT, true); /* Make thread stop*/ - nvgpu_thread_stop(&pmu->pg_init.state_task); + nvgpu_thread_stop(&pmu->pmu_pg.pg_init.state_task); /* wait to confirm thread stopped */ nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); do { - if (!nvgpu_thread_is_running(&pmu->pg_init.state_task)) { + if (!nvgpu_thread_is_running(&pmu->pmu_pg.pg_init.state_task)) { break; } nvgpu_udelay(2); } while (nvgpu_timeout_expired_msg(&timeout, "timeout - waiting PMU state machine thread stop") == 0); } else { - nvgpu_thread_join(&pmu->pg_init.state_task); + nvgpu_thread_join(&pmu->pmu_pg.pg_init.state_task); } } @@ -740,7 +745,7 @@ int nvgpu_pg_init_task(void *arg) { struct gk20a *g = (struct gk20a *)arg; struct nvgpu_pmu *pmu = &g->pmu; - struct nvgpu_pg_init *pg_init = &pmu->pg_init; + struct nvgpu_pg_init *pg_init = &pmu->pmu_pg.pg_init; u32 pmu_state = 0; nvgpu_log_fn(g, "thread start"); @@ -750,7 +755,7 @@ int nvgpu_pg_init_task(void *arg) NVGPU_COND_WAIT_INTERRUPTIBLE(&pg_init->wq, (pg_init->state_change == true), 0U); - pmu->pg_init.state_change = false; + pmu->pmu_pg.pg_init.state_change = false; pmu_state = NV_ACCESS_ONCE(pmu->pmu_state); if (pmu_state == PMU_STATE_EXIT) { diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index 3d668839c..0fd89a524 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c @@ -149,11 +149,10 @@ static int nvgpu_init_pmu_setup_sw(struct gk20a *g) nvgpu_log_fn(g, " "); /* start with elpg disabled until first enable call */ - pmu->elpg_refcnt = 0; + pmu->pmu_pg.elpg_refcnt = 0; /* Create thread to handle PMU state machine */ nvgpu_init_task_pg_init(g); - if (pmu->sw_ready) { for (i = 0; i < pmu->mutex_cnt; i++) { pmu->mutex[i].id = i; @@ -252,7 +251,7 @@ int nvgpu_init_pmu_support(struct gk20a *g) nvgpu_log_fn(g, " "); - if (pmu->initialized) { + if (pmu->pmu_pg.initialized) { return 0; } @@ -535,8 +534,8 @@ void nvgpu_pmu_state_change(struct gk20a *g, u32 pmu_state, pmu->pmu_state = pmu_state; if (post_change_event) { - pmu->pg_init.state_change = true; - nvgpu_cond_signal(&pmu->pg_init.wq); + pmu->pmu_pg.pg_init.state_change = true; + nvgpu_cond_signal(&pmu->pmu_pg.pg_init.wq); } /* make status visible */ @@ -554,7 +553,6 @@ int nvgpu_pmu_destroy(struct gk20a *g) if (!g->support_ls_pmu) { return 0; } - nvgpu_kill_task_pg_init(g); nvgpu_pmu_get_pg_stats(g, @@ -563,7 +561,7 @@ int nvgpu_pmu_destroy(struct gk20a *g) if (nvgpu_pmu_disable_elpg(g) != 0) { nvgpu_err(g, "failed to set disable elpg"); } - pmu->initialized = false; + pmu->pmu_pg.initialized = false; /* update the s/w ELPG residency counters */ g->pg_ingating_time_us += (u64)pg_stat_data.ingating_time; @@ -582,7 +580,7 @@ int nvgpu_pmu_destroy(struct gk20a *g) nvgpu_pmu_state_change(g, PMU_STATE_OFF, false); pmu->pmu_ready = false; pmu->perfmon_ready = false; - pmu->zbc_ready = false; + pmu->pmu_pg.zbc_ready = false; g->pmu_lsf_pmu_wpr_init_done = false; nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_debug.c b/drivers/gpu/nvgpu/common/pmu/pmu_debug.c index a4ba65836..f9736ae73 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_debug.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_debug.c @@ -35,7 +35,7 @@ void nvgpu_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu) /* Print PG stats */ nvgpu_err(g, "Print PG stats"); nvgpu_falcon_print_dmem(&pmu->flcn, - pmu->stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_GRAPHICS], + pmu->pmu_pg.stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_GRAPHICS], (u32)sizeof(struct pmu_pg_stats_v2)); g->ops.pmu.pmu_dump_elpg_stats(pmu); @@ -49,7 +49,7 @@ void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu) g->ops.pmu.pmu_dump_falcon_stats(pmu); nvgpu_err(g, "pmu state: %d", pmu->pmu_state); - nvgpu_err(g, "elpg state: %d", pmu->elpg_stat); + nvgpu_err(g, "elpg state: %d", pmu->pmu_pg.elpg_stat); /* PMU may crash due to FECS crash. Dump FECS status */ g->ops.gr.dump_gr_falcon_stats(g); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index d2110c0de..80fd33970 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c @@ -1677,8 +1677,8 @@ static void nvgpu_remove_pmu_support(struct nvgpu_pmu *pmu) nvgpu_dma_unmap_free(vm, &pmu->super_surface_buf); } - nvgpu_mutex_destroy(&pmu->elpg_mutex); - nvgpu_mutex_destroy(&pmu->pg_mutex); + nvgpu_mutex_destroy(&pmu->pmu_pg.elpg_mutex); + nvgpu_mutex_destroy(&pmu->pmu_pg.pg_mutex); nvgpu_mutex_destroy(&pmu->isr_mutex); nvgpu_mutex_destroy(&pmu->pmu_copy_lock); nvgpu_mutex_destroy(&pmu->pmu_seq_lock); @@ -1776,12 +1776,12 @@ int nvgpu_early_init_pmu_sw(struct gk20a *g, struct nvgpu_pmu *pmu) goto exit; } - err = nvgpu_mutex_init(&pmu->elpg_mutex); + err = nvgpu_mutex_init(&pmu->pmu_pg.elpg_mutex); if (err != 0) { return err; } - err = nvgpu_mutex_init(&pmu->pg_mutex); + err = nvgpu_mutex_init(&pmu->pmu_pg.pg_mutex); if (err != 0) { goto fail_elpg; } @@ -1817,9 +1817,9 @@ fail_pmu_copy: fail_isr: nvgpu_mutex_destroy(&pmu->isr_mutex); fail_pg: - nvgpu_mutex_destroy(&pmu->pg_mutex); + nvgpu_mutex_destroy(&pmu->pmu_pg.pg_mutex); fail_elpg: - nvgpu_mutex_destroy(&pmu->elpg_mutex); + nvgpu_mutex_destroy(&pmu->pmu_pg.elpg_mutex); exit: return err; } diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c index f0dceed98..039e5e881 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c @@ -289,7 +289,7 @@ int gk20a_pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token) struct pmu_mutex *mutex; u32 data, owner, max_retry; - if (!pmu->initialized) { + if (!pmu->pmu_pg.initialized) { return -EINVAL; } @@ -359,7 +359,7 @@ int gk20a_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token) struct pmu_mutex *mutex; u32 owner, data; - if (!pmu->initialized) { + if (!pmu->pmu_pg.initialized) { return -EINVAL; } @@ -548,7 +548,7 @@ static void pmu_handle_zbc_msg(struct gk20a *g, struct pmu_msg *msg, { struct nvgpu_pmu *pmu = param; gk20a_dbg_pmu(g, "reply ZBC_TABLE_UPDATE"); - pmu->zbc_save_done = true; + pmu->pmu_pg.zbc_save_done = true; } void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) @@ -558,7 +558,7 @@ void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) u32 seq; size_t tmp_size; - if (!pmu->pmu_ready || (entries == 0U) || !pmu->zbc_ready) { + if (!pmu->pmu_ready || (entries == 0U) || !pmu->pmu_pg.zbc_ready) { return; } @@ -570,14 +570,14 @@ void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) cmd.cmd.zbc.cmd_type = g->pmu_ver_cmd_id_zbc_table_update; cmd.cmd.zbc.entry_mask = ZBC_MASK(entries); - pmu->zbc_save_done = false; + pmu->pmu_pg.zbc_save_done = false; gk20a_dbg_pmu(g, "cmd post ZBC_TABLE_UPDATE"); nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, pmu_handle_zbc_msg, pmu, &seq); pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g), - &pmu->zbc_save_done, 1); - if (!pmu->zbc_save_done) { + &pmu->pmu_pg.zbc_save_done, 1); + if (!pmu->pmu_pg.zbc_save_done) { nvgpu_err(g, "ZBC save timeout"); } } @@ -872,7 +872,7 @@ int gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, int err; err = nvgpu_falcon_copy_from_dmem(&pmu->flcn, - pmu->stat_dmem_offset[pg_engine_id], + pmu->pmu_pg.stat_dmem_offset[pg_engine_id], (u8 *)&stats, (u32)sizeof(struct pmu_pg_stats), 0); if (err != 0) { nvgpu_err(g, "PMU falcon DMEM copy failed"); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c index 5573c0353..5b567e21a 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c @@ -169,7 +169,7 @@ int gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, int err; err = nvgpu_falcon_copy_from_dmem(&pmu->flcn, - pmu->stat_dmem_offset[pg_engine_id], + pmu->pmu_pg.stat_dmem_offset[pg_engine_id], (u8 *)&stats, (u32)sizeof(struct pmu_pg_stats_v2), 0); if (err != 0) { nvgpu_err(g, "PMU falcon DMEM copy failed"); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c b/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c index 17a1d37a7..cd27e2897 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c @@ -272,7 +272,7 @@ int gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, int err; err = nvgpu_falcon_copy_from_dmem(&pmu->flcn, - pmu->stat_dmem_offset[pg_engine_id], + pmu->pmu_pg.stat_dmem_offset[pg_engine_id], (u8 *)&stats, (u32)sizeof(struct pmu_pg_stats_v1), 0); if (err != 0) { nvgpu_err(g, "PMU falcon DMEM copy failed"); diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 5de181e3c..272f637cc 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -2704,8 +2704,8 @@ static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g) return err; } - if (pmu->pg_buf.cpu_va == NULL) { - err = nvgpu_dma_alloc_map_sys(vm, size, &pmu->pg_buf); + if (pmu->pmu_pg.pg_buf.cpu_va == NULL) { + err = nvgpu_dma_alloc_map_sys(vm, size, &pmu->pmu_pg.pg_buf); if (err != 0) { nvgpu_err(g, "failed to allocate memory"); return -ENOMEM; @@ -2720,7 +2720,7 @@ static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g) return err; } - err = gr_gk20a_fecs_set_reglist_virtual_addr(g, pmu->pg_buf.gpu_va); + err = gr_gk20a_fecs_set_reglist_virtual_addr(g, pmu->pmu_pg.pg_buf.gpu_va); if (err != 0) { nvgpu_err(g, "fail to set pg buffer pmu va"); @@ -2916,7 +2916,7 @@ int gk20a_gr_reset(struct gk20a *g) return err; } - err = gr_gk20a_fecs_set_reglist_virtual_addr(g, g->pmu.pg_buf.gpu_va); + err = gr_gk20a_fecs_set_reglist_virtual_addr(g, g->pmu.pmu_pg.pg_buf.gpu_va); if (err != 0) { nvgpu_err(g, "fail to set pg buffer pmu va"); diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index c7dd79695..747e3977b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -24,7 +24,6 @@ #define NVGPU_PMU_H #include -#include #include #include #include @@ -318,8 +317,6 @@ struct nvgpu_pmu { struct nvgpu_mem ucode; - struct nvgpu_mem pg_buf; - /* TBD: remove this if ZBC seq is fixed */ struct nvgpu_mem seq_buf; struct nvgpu_mem trace_buf; @@ -331,8 +328,6 @@ struct nvgpu_pmu { struct nv_pmu_super_surface_member_descriptor ssmd_get_status[NV_PMU_SUPER_SURFACE_MEMBER_DESCRIPTOR_COUNT]; - bool buf_loaded; - struct pmu_sha1_gid gid_info; struct nvgpu_engine_mem_queue *queue[PMU_QUEUE_COUNT]; @@ -356,31 +351,17 @@ struct nvgpu_pmu { u32 perfmon_query; - bool zbc_save_done; - - u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE]; - - u32 elpg_stat; - u32 mscg_stat; u32 mscg_transition_state; u32 pmu_state; -#define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC 1U /* msec */ - struct nvgpu_pg_init pg_init; - struct nvgpu_mutex pg_mutex; /* protect pg-RPPG/MSCG enable/disable */ - struct nvgpu_mutex elpg_mutex; /* protect elpg enable/disable */ - /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */ - int elpg_refcnt; - + struct nvgpu_pmu_pg pmu_pg; union { struct pmu_perfmon_counter_v2 perfmon_counter_v2; }; u8 perfmon_state_id[PMU_DOMAIN_GROUP_NUM]; - bool initialized; - void (*remove_support)(struct nvgpu_pmu *pmu); bool sw_ready; bool perfmon_ready; @@ -393,7 +374,6 @@ struct nvgpu_pmu { struct nvgpu_mutex isr_mutex; bool isr_enabled; - bool zbc_ready; union { struct pmu_cmdline_args_v3 args_v3; struct pmu_cmdline_args_v4 args_v4; @@ -402,7 +382,6 @@ struct nvgpu_pmu { }; unsigned long perfmon_events_cnt; bool perfmon_sampling_enabled; - u32 aelpg_param[5]; u32 override_done; }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h index 67381dbf1..d8d97417d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h @@ -31,6 +31,7 @@ #include #include #include +#include struct nvgpu_pg_init { bool state_change; @@ -38,6 +39,23 @@ struct nvgpu_pg_init { struct nvgpu_thread state_task; }; +struct nvgpu_pmu_pg { + u32 elpg_stat; +#define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC 1U /* msec */ + struct nvgpu_pg_init pg_init; + struct nvgpu_mutex pg_mutex; /* protect pg-RPPG/MSCG enable/disable */ + struct nvgpu_mutex elpg_mutex; /* protect elpg enable/disable */ + /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */ + int elpg_refcnt; + u32 aelpg_param[5]; + bool zbc_ready; + bool zbc_save_done; + bool buf_loaded; + struct nvgpu_mem pg_buf; + bool initialized; + u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE]; +}; + /*PG defines used by nvpgu-pmu*/ struct pmu_pg_stats_data { u32 gating_cnt; diff --git a/drivers/gpu/nvgpu/os/linux/debug_pmu.c b/drivers/gpu/nvgpu/os/linux/debug_pmu.c index 7c4db50c9..6028e533d 100644 --- a/drivers/gpu/nvgpu/os/linux/debug_pmu.c +++ b/drivers/gpu/nvgpu/os/linux/debug_pmu.c @@ -36,16 +36,16 @@ static int lpwr_debug_show(struct seq_file *s, void *data) "MSCG pstate state: %u\n" "MSCG transition state: %u\n", g->ops.clk_arb.get_current_pstate(g), - g->elpg_enabled, g->pmu.elpg_refcnt, - g->pmu.elpg_stat, g->mscg_enabled, + g->elpg_enabled, g->pmu.pmu_pg.elpg_refcnt, + g->pmu.pmu_pg.elpg_stat, g->mscg_enabled, g->pmu.mscg_stat, g->pmu.mscg_transition_state); } else seq_printf(s, "ELPG Enabled: %u\n" "ELPG ref count: %u\n" "ELPG state: %u\n", - g->elpg_enabled, g->pmu.elpg_refcnt, - g->pmu.elpg_stat); + g->elpg_enabled, g->pmu.pmu_pg.elpg_refcnt, + g->pmu.pmu_pg.elpg_stat); return 0; diff --git a/drivers/gpu/nvgpu/os/linux/driver_common.c b/drivers/gpu/nvgpu/os/linux/driver_common.c index e890d0e49..30d844447 100644 --- a/drivers/gpu/nvgpu/os/linux/driver_common.c +++ b/drivers/gpu/nvgpu/os/linux/driver_common.c @@ -196,11 +196,11 @@ static void nvgpu_init_pm_vars(struct gk20a *g) nvgpu_set_enabled(g, NVGPU_PMU_PERFMON, platform->enable_perfmon); /* set default values to aelpg parameters */ - g->pmu.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US; - g->pmu.aelpg_param[1] = APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US; - g->pmu.aelpg_param[2] = APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US; - g->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US; - g->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT; + g->pmu.pmu_pg.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US; + g->pmu.pmu_pg.aelpg_param[1] = APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US; + g->pmu.pmu_pg.aelpg_param[2] = APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US; + g->pmu.pmu_pg.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US; + g->pmu.pmu_pg.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT; } nvgpu_set_enabled(g, NVGPU_SUPPORT_ASPM, !platform->disable_aspm); diff --git a/drivers/gpu/nvgpu/os/linux/sysfs.c b/drivers/gpu/nvgpu/os/linux/sysfs.c index 95f312012..7c060e9d9 100644 --- a/drivers/gpu/nvgpu/os/linux/sysfs.c +++ b/drivers/gpu/nvgpu/os/linux/sysfs.c @@ -579,7 +579,7 @@ static ssize_t aelpg_param_store(struct device *dev, struct gk20a *g = get_gk20a(dev); int status = 0; union pmu_ap_cmd ap_cmd; - int *paramlist = (int *)g->pmu.aelpg_param; + int *paramlist = (int *)g->pmu.pmu_pg.aelpg_param; u32 defaultparam[5] = { APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US, APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US, @@ -622,9 +622,9 @@ static ssize_t aelpg_param_read(struct device *dev, struct gk20a *g = get_gk20a(dev); return snprintf(buf, PAGE_SIZE, - "%d %d %d %d %d\n", g->pmu.aelpg_param[0], - g->pmu.aelpg_param[1], g->pmu.aelpg_param[2], - g->pmu.aelpg_param[3], g->pmu.aelpg_param[4]); + "%d %d %d %d %d\n", g->pmu.pmu_pg.aelpg_param[0], + g->pmu.pmu_pg.aelpg_param[1], g->pmu.pmu_pg.aelpg_param[2], + g->pmu.pmu_pg.aelpg_param[3], g->pmu.pmu_pg.aelpg_param[4]); } static DEVICE_ATTR(aelpg_param, ROOTRW,