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gpu: nvgpu: add debugger flag for regops support

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Add NVGPU_DEBUGGER flag for regops API and hals

Jira NVGPU-3505

Change-Id: I9f2b850c881bf05f8ba5b6ef1f59f0d73a948cde
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130146
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-05-23 15:36:40 +05:30
committed by mobile promotions
parent 3d318e1d1d
commit 455b0da253
14 changed files with 43 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -141,7 +141,6 @@ srcs += common/utils/enabled.c \
common/fifo/pbdma_status.c \
common/fifo/userd.c \
common/mc/mc.c \
common/regops/regops.c \
common/clk_arb/clk_arb.c \
common/clk_arb/clk_arb_gp10b.c \
common/fence/fence.c \
@@ -205,9 +204,6 @@ srcs += common/utils/enabled.c \
hal/cbc/cbc_gp10b.c \
hal/cbc/cbc_gv11b.c \
hal/ptimer/ptimer_gk20a.c \
hal/regops/regops_gm20b.c \
hal/regops/regops_gp10b.c \
hal/regops/regops_gv11b.c \
hal/ce/ce2_gk20a.c \
hal/ce/ce_gp10b.c \
hal/ce/ce_gv11b.c \
@@ -313,7 +309,13 @@ srcs += common/gr/zbc.c \
endif
ifeq ($(NVGPU_DEBUGGER),1)
srcs += common/debugger.c
srcs += common/debugger.c \
common/regops/regops.c \
hal/regops/regops_gm20b.c \
hal/regops/regops_gp10b.c \
hal/regops/regops_gv11b.c \
hal/regops/regops_gv100.c \
hal/regops/regops_tu104.c
endif
ifeq ($(NVGPU_FEATURE_CE),1)
@@ -502,8 +504,6 @@ srcs += common/sec2/sec2.c \
hal/power_features/cg/gv100_gating_reglist.c \
hal/power_features/cg/tu104_gating_reglist.c \
hal/cbc/cbc_tu104.c \
hal/regops/regops_gv100.c \
hal/regops/regops_tu104.c \
hal/ltc/ltc_tu104.c \
hal/fb/fb_gv100.c \
hal/fb/fb_tu104.c \

4
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -654,6 +654,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
.clk_arb_cleanup = gp10b_clk_arb_cleanup,
},
#ifdef NVGPU_DEBUGGER
.regops = {
.exec_regops = vgpu_exec_regops,
.get_global_whitelist_ranges =
@@ -670,6 +671,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.get_qctl_whitelist = gp10b_get_qctl_whitelist,
.get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
},
#endif
.mc = {
.intr_mask = NULL,
.intr_enable = NULL,
@@ -800,11 +802,11 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
gops->pmu = vgpu_gp10b_ops.pmu;
#endif
gops->clk_arb = vgpu_gp10b_ops.clk_arb;
gops->regops = vgpu_gp10b_ops.regops;
gops->mc = vgpu_gp10b_ops.mc;
gops->debug = vgpu_gp10b_ops.debug;
#ifdef NVGPU_DEBUGGER
gops->debugger = vgpu_gp10b_ops.debugger;
gops->regops = vgpu_gp10b_ops.regops;
#endif
gops->perfbuf = vgpu_gp10b_ops.perfbuf;
gops->bus = vgpu_gp10b_ops.bus;

4
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -747,6 +747,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
.clk_arb_cleanup = gp10b_clk_arb_cleanup,
},
#ifdef NVGPU_DEBUGGER
.regops = {
.exec_regops = vgpu_exec_regops,
.get_global_whitelist_ranges =
@@ -763,6 +764,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.get_qctl_whitelist = gv11b_get_qctl_whitelist,
.get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count,
},
#endif
.mc = {
.intr_mask = NULL,
.intr_enable = NULL,
@@ -893,11 +895,11 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
gops->pmu = vgpu_gv11b_ops.pmu;
#endif
gops->clk_arb = vgpu_gv11b_ops.clk_arb;
gops->regops = vgpu_gv11b_ops.regops;
gops->mc = vgpu_gv11b_ops.mc;
gops->debug = vgpu_gv11b_ops.debug;
#ifdef NVGPU_DEBUGGER
gops->debugger = vgpu_gv11b_ops.debugger;
gops->regops = vgpu_gv11b_ops.regops;
#endif
gops->perfbuf = vgpu_gv11b_ops.perfbuf;
gops->bus = vgpu_gv11b_ops.bus;

2
drivers/gpu/nvgpu/common/vgpu/init/init_vgpu.c
View File

@@ -64,9 +64,11 @@ void vgpu_remove_support_common(struct gk20a *g)
struct tegra_vgpu_intr_msg msg;
int err;
#ifdef NVGPU_DEBUGGER
if (g->dbg_regops_tmp_buf) {
nvgpu_kfree(g, g->dbg_regops_tmp_buf);
}
#endif
nvgpu_gr_remove_support(g);

2
drivers/gpu/nvgpu/common/vgpu/vgpu.c
View File

@@ -230,9 +230,11 @@ void vgpu_remove_support_common(struct gk20a *g)
struct tegra_vgpu_intr_msg msg;
int err;
#ifdef NVGPU_DEBUGGER
if (g->dbg_regops_tmp_buf) {
nvgpu_kfree(g, g->dbg_regops_tmp_buf);
}
#endif
if (g->gr->remove_support) {
g->gr->remove_support(g);

4
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -851,6 +851,7 @@ static const struct gpu_ops gm20b_ops = {
.pll_reg_write = gm20b_clk_pll_reg_write,
.get_pll_debug_data = gm20b_clk_get_pll_debug_data,
},
#ifdef NVGPU_DEBUGGER
.regops = {
.exec_regops = exec_regops_gk20a,
.get_global_whitelist_ranges =
@@ -867,6 +868,7 @@ static const struct gpu_ops gm20b_ops = {
.get_qctl_whitelist = gm20b_get_qctl_whitelist,
.get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count,
},
#endif
.mc = {
.intr_mask = gm20b_mc_intr_mask,
.intr_enable = gm20b_mc_intr_enable,
@@ -1050,13 +1052,13 @@ int gm20b_init_hal(struct gk20a *g)
gops->clk.pll_reg_write = gm20b_ops.clk.pll_reg_write;
gops->clk.get_pll_debug_data = gm20b_ops.clk.get_pll_debug_data;
gops->regops = gm20b_ops.regops;
gops->mc = gm20b_ops.mc;
gops->perf = gm20b_ops.perf;
gops->perfbuf = gm20b_ops.perfbuf;
gops->debug = gm20b_ops.debug;
#ifdef NVGPU_DEBUGGER
gops->debugger = gm20b_ops.debugger;
gops->regops = gm20b_ops.regops;
#endif
gops->bus = gm20b_ops.bus;
gops->ptimer = gm20b_ops.ptimer;

4
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -935,6 +935,7 @@ static const struct gpu_ops gp10b_ops = {
.clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
.clk_arb_cleanup = gp10b_clk_arb_cleanup,
},
#ifdef NVGPU_DEBUGGER
.regops = {
.exec_regops = exec_regops_gk20a,
.get_global_whitelist_ranges =
@@ -951,6 +952,7 @@ static const struct gpu_ops gp10b_ops = {
.get_qctl_whitelist = gp10b_get_qctl_whitelist,
.get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
},
#endif
.mc = {
.intr_mask = mc_gp10b_intr_mask,
.intr_enable = mc_gp10b_intr_enable,
@@ -1129,11 +1131,11 @@ int gp10b_init_hal(struct gk20a *g)
gops->pmu = gp10b_ops.pmu;
#endif
gops->clk_arb = gp10b_ops.clk_arb;
gops->regops = gp10b_ops.regops;
gops->mc = gp10b_ops.mc;
gops->debug = gp10b_ops.debug;
#ifdef NVGPU_DEBUGGER
gops->debugger = gp10b_ops.debugger;
gops->regops = gp10b_ops.regops;
#endif
gops->perf = gp10b_ops.perf;
gops->perfbuf = gp10b_ops.perfbuf;

4
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -1102,6 +1102,7 @@ static const struct gpu_ops gv11b_ops = {
.clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
.clk_arb_cleanup = gp10b_clk_arb_cleanup,
},
#ifdef NVGPU_DEBUGGER
.regops = {
.exec_regops = exec_regops_gk20a,
.get_global_whitelist_ranges =
@@ -1118,6 +1119,7 @@ static const struct gpu_ops gv11b_ops = {
.get_qctl_whitelist = gv11b_get_qctl_whitelist,
.get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count,
},
#endif
.mc = {
.intr_mask = mc_gp10b_intr_mask,
.intr_enable = mc_gv11b_intr_enable,
@@ -1298,11 +1300,11 @@ int gv11b_init_hal(struct gk20a *g)
gops->mm = gv11b_ops.mm;
gops->therm = gv11b_ops.therm;
gops->pmu = gv11b_ops.pmu;
gops->regops = gv11b_ops.regops;
gops->mc = gv11b_ops.mc;
gops->debug = gv11b_ops.debug;
#ifdef NVGPU_DEBUGGER
gops->debugger = gv11b_ops.debugger;
gops->regops = gv11b_ops.regops;
#endif
gops->perf = gv11b_ops.perf;
gops->perfbuf = gv11b_ops.perfbuf;

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1140,6 +1140,7 @@ static const struct gpu_ops tu104_ops = {
.stop_clk_arb_threads = gv100_stop_clk_arb_threads,
},
#endif
#ifdef NVGPU_DEBUGGER
.regops = {
.exec_regops = exec_regops_gk20a,
.get_global_whitelist_ranges =
@@ -1156,6 +1157,7 @@ static const struct gpu_ops tu104_ops = {
.get_qctl_whitelist = tu104_get_qctl_whitelist,
.get_qctl_whitelist_count = tu104_get_qctl_whitelist_count,
},
#endif
.mc = {
.intr_enable = intr_tu104_enable,
.intr_mask = intr_tu104_mask,
@@ -1433,11 +1435,11 @@ int tu104_init_hal(struct gk20a *g)
#ifdef NVGPU_FEATURE_LS_PMU
gops->pmu = tu104_ops.pmu;
#endif
gops->regops = tu104_ops.regops;
gops->mc = tu104_ops.mc;
gops->debug = tu104_ops.debug;
#ifdef NVGPU_DEBUGGER
gops->debugger = tu104_ops.debugger;
gops->regops = tu104_ops.regops;
#endif
gops->perf = tu104_ops.perf;
gops->perfbuf = tu104_ops.perfbuf;

4
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1473,6 +1473,7 @@ struct gpu_ops {
bool support_changeseq;
bool support_vfe;
} pmu_perf;
#ifdef NVGPU_DEBUGGER
struct {
int (*exec_regops)(struct gk20a *g,
struct nvgpu_channel *ch,
@@ -1491,6 +1492,7 @@ struct gpu_ops {
const u32* (*get_qctl_whitelist)(void);
u64 (*get_qctl_whitelist_count)(void);
} regops;
#endif
struct {
void (*intr_mask)(struct gk20a *g);
void (*intr_enable)(struct gk20a *g);
@@ -1946,9 +1948,11 @@ struct gk20a {
/*refcount for timeout disable */
nvgpu_atomic_t timeouts_disabled_refcount;
#ifdef NVGPU_DEBUGGER
/* must have dbg_sessions_lock before use */
struct nvgpu_dbg_reg_op *dbg_regops_tmp_buf;
u32 dbg_regops_tmp_buf_ops;
#endif
#if defined(CONFIG_GK20A_CYCLE_STATS)
struct nvgpu_mutex cs_lock;

2
drivers/gpu/nvgpu/os/linux/driver_common.c
View File

@@ -290,6 +290,7 @@ int nvgpu_probe(struct gk20a *g,
nvgpu_create_sysfs(dev);
gk20a_debug_init(g, debugfs_symlink);
#ifdef NVGPU_DEBUGGER
g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K);
if (!g->dbg_regops_tmp_buf) {
nvgpu_err(g, "couldn't allocate regops tmp buf");
@@ -297,6 +298,7 @@ int nvgpu_probe(struct gk20a *g,
}
g->dbg_regops_tmp_buf_ops =
SZ_4K / sizeof(g->dbg_regops_tmp_buf[0]);
#endif
g->remove_support = gk20a_remove_support;

4
drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
View File

@@ -590,6 +590,7 @@ static int dbg_unbind_all_channels_gk20a(struct dbg_session_gk20a *dbg_s)
return 0;
}
#ifdef NVGPU_DEBUGGER
/*
* Convert common regops op values of the form of NVGPU_DBG_REG_OP_*
* into linux regops op values of the form of NVGPU_DBG_GPU_REG_OP_*
@@ -934,6 +935,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
return err;
}
#endif /* NVGPU_DEBUGGER */
static int nvgpu_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_powergate_args *args)
@@ -2036,10 +2038,12 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd,
(struct nvgpu_dbg_gpu_bind_channel_args *)buf);
break;
#ifdef NVGPU_DEBUGGER
case NVGPU_DBG_GPU_IOCTL_REG_OPS:
err = nvgpu_ioctl_channel_reg_ops(dbg_s,
(struct nvgpu_dbg_gpu_exec_reg_ops_args *)buf);
break;
#endif
case NVGPU_DBG_GPU_IOCTL_POWERGATE:
err = nvgpu_ioctl_powergate_gk20a(dbg_s,

2
drivers/gpu/nvgpu/os/linux/module.c
View File

@@ -833,7 +833,9 @@ void gk20a_remove_support(struct gk20a *g)
tegra_unregister_idle_unidle(gk20a_do_idle);
#ifdef NVGPU_DEBUGGER
nvgpu_kfree(g, g->dbg_regops_tmp_buf);
#endif
nvgpu_channel_remove_support_linux(l);

2
drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c
View File

@@ -140,6 +140,7 @@ static int vgpu_init_support(struct platform_device *pdev)
nvgpu_init_list_node(&g->profiler_objects);
#ifdef NVGPU_DEBUGGER
g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K);
if (!g->dbg_regops_tmp_buf) {
nvgpu_err(g, "couldn't allocate regops tmp buf");
@@ -147,6 +148,7 @@ static int vgpu_init_support(struct platform_device *pdev)
}
g->dbg_regops_tmp_buf_ops =
SZ_4K / sizeof(g->dbg_regops_tmp_buf[0]);
#endif
err = nvgpu_gr_alloc(g);
if (err != 0) {