gpu: nvgpu: unit: traceability for fifo

Fix 'Targets:' statements and/or add explicit tests for:
- gops_fifo.fifo_init_support
- gops_fifo.fifo_suspend
- gv11b_tsg_unbind_channel_check_eng_faulted
- nvgpu_tsg_from_ch
- nvgpu_tsg_alloc_sm_error_states_mem
- nvgpu_tsg_cleanup_sw
- nvgpu_tsg_set_error_notifier
- nvgpu_tsg_enable_sched
- nvgpu_tsg_default_timeslice_us
- nvgpu_tsg_get_from_id
- nvgpu_tsg_disable_sched
- nvgpu_tsg_release_common
- nvgpu_tsg_check_and_get_from_id
- nvgpu_tsg_open_common
- gv11b_pbdma_config_userd_writeback_enable
- gv11b_tsg_deinit_eng_method_buffers

Jira NVGPU-4890

Change-Id: I298b9f18318105cee8dc882767e30729e7106ccc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280134
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

userspace/required_tests.json

@@ -2987,6 +2987,12 @@
         "unit": "nvgpu_pbdma_gm20b",
         "test_level": 0
     },
+    {
+        "test": "test_gm20b_pbdma_get_ctrl_hce_priv_mode_yes",
+        "case": "pbdma_get_ctrl_hce_priv_mode_yes",
+        "unit": "nvgpu_pbdma_gm20b",
+        "test_level": 0
+    },
     {
         "test": "test_gm20b_pbdma_get_fc_subdevice",
         "case": "pbdma_get_fc_subdevice",
@@ -3131,7 +3137,7 @@
         "unit": "nvgpu_pbdma_gv11b",
         "test_level": 0
     },
-        {
+    {
         "test": "test_preempt_get_timeout",
         "case": "get_timeout",
         "unit": "nvgpu_preempt",
@@ -3401,6 +3407,12 @@
         "unit": "nvgpu_tsg",
         "test_level": 0
     },
+    {
+        "test": "test_tsg_enable_sched",
+        "case": "enable_disable_sched",
+        "unit": "nvgpu_tsg",
+        "test_level": 0
+    },
     {
         "test": "test_tsg_check_and_get_from_id",
         "case": "get_from_id",

userspace/units/fifo/fifo/nvgpu-fifo.h

@@ -39,7 +39,8 @@ struct gk20a;
  *
  * Test Type: Feature based
  *
- * Targets: nvgpu_fifo_init_support, nvgpu_fifo_setup_sw,
+ * Targets: gops_fifo.fifo_init_support, nvgpu_fifo_init_support,
+ *          gops_fifo.setup_sw, nvgpu_fifo_setup_sw,
  *          nvgpu_fifo_setup_sw_common, nvgpu_fifo_cleanup_sw,
  *          nvgpu_fifo_cleanup_sw_common
  *
@@ -84,7 +85,7 @@ int test_decode_pbdma_ch_eng_status(struct unit_module *m, struct gk20a *g,
  *
  * Test Type: Feature based
  *
- * Targets: nvgpu_fifo_suspend
+ * Targets: gops_fifo.fifo_suspend, nvgpu_fifo_suspend
  *
  * Input: None
  *

userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.h

@@ -210,7 +210,7 @@ int test_gv11b_pbdma_set_channel_info_veid(struct unit_module *m,
  *
  * Test Type: Feature
  *
- * Targets: gops_pbdma.config_userd_writeback_enable
+ * Targets: gops_pbdma.config_userd_writeback_enable,
  *          gv11b_pbdma_config_userd_writeback_enable
  *
  * Input: test_fifo_init_support() run for this GPU

userspace/units/fifo/tsg/gv11b/nvgpu-tsg-gv11b.h

@@ -41,7 +41,9 @@ struct gk20a;
  * Test Type: Feature
  *
  * Targets: gops_tsg.init_eng_method_buffers,
- *          gv11b_tsg_init_eng_method_buffers
+ *          gv11b_tsg_init_eng_method_buffers,
+ *          gops_tsg.deinit_eng_method_buffers,
+ *          gv11b_tsg_deinit_eng_method_buffers,
  *
  * Input: test_fifo_init_support() run for this GPU
  *
@@ -106,7 +108,7 @@ int test_gv11b_tsg_bind_channel_eng_method_buffers(struct unit_module *m,
  *
  * Test Type: Feature
  *
- * Targets: gops_tsg.unbind_channel_check_eng_faulted
+ * Targets: gops_tsg.unbind_channel_check_eng_faulted,
  *          gv11b_tsg_unbind_channel_check_eng_faulted
  *
  * Input: test_fifo_init_support() run for this GPU

userspace/units/fifo/tsg/nvgpu-tsg.c

@@ -73,6 +73,8 @@ struct stub_ctx {
 	u32 count;
 	u32 chid;
 	u32 tsgid;
+	u32 runlist_mask;
+	u32 runlist_state;
 };
 
 struct stub_ctx stub[MAX_STUB];
@@ -163,6 +165,12 @@ int test_tsg_open(struct unit_module *m,
 
 	kmem_fi = nvgpu_kmem_get_fault_injection();
 
+	unit_assert(nvgpu_tsg_default_timeslice_us(g) ==
+		NVGPU_TSG_TIMESLICE_DEFAULT_US, goto done);
+
+	unit_assert(nvgpu_tsg_check_and_get_from_id(g, NVGPU_INVALID_TSG_ID) ==
+		NULL, goto done);
+
 	for (branches = 0U; branches < F_TSG_OPEN_LAST; branches++) {
 
 		if (pruned(branches, prune)) {
@@ -224,6 +232,10 @@ int test_tsg_open(struct unit_module *m,
 			unit_assert(tsg == NULL, goto done);
 		} else {
 			unit_assert(tsg != NULL, goto done);
+			unit_assert(nvgpu_tsg_get_from_id(g, tsg->tsgid) ==
+				tsg, goto done);
+			unit_assert(nvgpu_tsg_check_and_get_from_id(g,
+				tsg->tsgid) == tsg, goto done);
 			nvgpu_ref_put(&tsg->refcount, nvgpu_tsg_release);
 			tsg = NULL;
 		}
@@ -349,11 +361,16 @@ int test_tsg_bind_channel(struct unit_module *m,
 		err = nvgpu_tsg_bind_channel(tsg, ch);
 
 		if (branches & fail) {
+			if (!(branches & F_TSG_BIND_CHANNEL_CH_BOUND)) {
+				unit_assert(nvgpu_tsg_from_ch(ch) == NULL,
+					goto done);
+			}
 			unit_assert(err != 0, goto done);
 		} else {
 			unit_assert(err == 0, goto done);
 			unit_assert(!nvgpu_list_empty(&tsg->ch_list),
 				goto done);
+			unit_assert(nvgpu_tsg_from_ch(ch) == tsg, goto done);
 
 			err = nvgpu_tsg_unbind_channel(tsg, ch);
 			unit_assert(err == 0, goto done);
@@ -1041,6 +1058,55 @@ done:
 	return ret;
 }
 
+static void stub_runlist_write_state(struct gk20a *g,
+	u32 runlists_mask, u32 runlist_state)
+{
+	stub[0].runlist_mask = runlists_mask;
+	stub[0].runlist_state = runlist_state;
+}
+
+int test_tsg_enable_sched(struct unit_module *m,
+		struct gk20a *g, void *args)
+{
+	struct gpu_ops gops = g->ops;
+	struct nvgpu_tsg *tsg = NULL;
+	struct nvgpu_channel *ch = NULL;
+	int ret = UNIT_FAIL;
+	int err;
+
+	g->ops.runlist.write_state = stub_runlist_write_state;
+
+	tsg = nvgpu_tsg_open(g, getpid());
+	unit_assert(tsg != NULL, goto done);
+
+	ch = nvgpu_channel_open_new(g, ~0U, false, getpid(), getpid());
+	unit_assert(ch != NULL, goto done);
+
+	err = nvgpu_tsg_bind_channel(tsg, ch);
+	unit_assert(err == 0, goto done);
+
+	memset(stub, 0, sizeof(stub));
+	nvgpu_tsg_enable_sched(g, tsg);
+	unit_assert(stub[0].runlist_mask == BIT(tsg->runlist_id), goto done);
+	unit_assert(stub[0].runlist_state == RUNLIST_ENABLED, goto done);
+
+	memset(stub, 0, sizeof(stub));
+	nvgpu_tsg_disable_sched(g, tsg);
+	unit_assert(stub[0].runlist_mask == BIT(tsg->runlist_id), goto done);
+	unit_assert(stub[0].runlist_state == RUNLIST_DISABLED, goto done);
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ch != NULL) {
+		nvgpu_channel_close(ch);
+	}
+	if (tsg != NULL) {
+		nvgpu_ref_put(&tsg->refcount, nvgpu_tsg_release);
+	}
+	g->ops = gops;
+	return ret;
+}
+
 int test_tsg_check_and_get_from_id(struct unit_module *m,
 		struct gk20a *g, void *args)
 {
@@ -1473,6 +1539,7 @@ struct unit_module_test nvgpu_tsg_tests[] = {
 	UNIT_TEST(unbind_channel_check_ctx_reload,
 		test_tsg_unbind_channel_check_ctx_reload, &unit_ctx, 0),
 	UNIT_TEST(enable_disable, test_tsg_enable, &unit_ctx, 0),
+	UNIT_TEST(enable_disable_sched, test_tsg_enable_sched, &unit_ctx, 0),
 	UNIT_TEST(abort, test_tsg_abort, &unit_ctx, 0),
 	UNIT_TEST(mark_error, test_tsg_mark_error, &unit_ctx, 0),
 	UNIT_TEST(set_ctx_mmu_error, test_tsg_set_ctx_mmu_error, &unit_ctx, 0),

userspace/units/fifo/tsg/nvgpu-tsg.h

@@ -40,14 +40,24 @@ struct gk20a;
  *
  * Test Type: Feature
  *
- * Targets: nvgpu_tsg_open
+ * Targets: nvgpu_tsg_open, nvgpu_tsg_open_common,
+ *          nvgpu_tsg_alloc_sm_error_states_mem,
+ *          nvgpu_tsg_default_timeslice_us,
+ *          nvgpu_tsg_get_from_id,
+ *          nvgpu_tsg_check_and_get_from_id
  *
  * Input: test_fifo_init_support() run for this GPU
  *
  * Steps:
+ * - Check that nvgpu_tsg_default_timeslice_us returns
+ *   NVGPU_TSG_TIMESLICE_DEFAULT_US.
+ * - Check that nvgpu_tsg_check_and_get_from_id return NULL for
+ *   NVGPU_INVALID_TSG_ID.
  * - Check that TSG can be allocated with nvgpu_tsg_open.
  *    - Check that nvgpu_tsg_open returns a non NULL value.
- *    - Decrement ref_count in order to invoke nvgpu_tsg_releases.
+ *    - Check that tsg can be retrieved from tsgid with nvgpu_tsg_get_from_id.
+ *    - Check that nvgpu_tsg_check_and_get_from_id return tsg from its id.
+ *    - Decrement ref_count in order to invoke nvgpu_tsg_release.
  * - Check TSG allocation failures cases:
  *   - failure to acquire unused TSG (by forcing f->num_channels to 0).
  *   - failure to allocate sm error state:
@@ -71,7 +81,7 @@ int test_tsg_open(struct unit_module *m,
  *
  * Test Type: Feature
  *
- * Targets: nvgpu_tsg_bind_channel
+ * Targets: nvgpu_tsg_bind_channel, nvgpu_tsg_from_ch
  *
  * Input: test_fifo_init_support() run for this GPU
  *
@@ -83,6 +93,7 @@ int test_tsg_open(struct unit_module *m,
  *   - Check that TSG's list of channel is not empty.
  *   - Unbind channel with nvgpu_tsg_unbind_channel.
  *   - Check that ch->tsgid is now invalid.
+ *   - Check that tsg can be retrieved from ch using nvgpu_tsg_from_ch.
  * - Check TSG bind failure cases:
  *   - Attempt to bind an already bound channel (by binding a channel to a
  *     TSG, then attempting to bind it to another TSG).
@@ -90,6 +101,8 @@ int test_tsg_open(struct unit_module *m,
  *     TSG's runlist_id to a different value).
  *   - Attempt to bind a channel that is already active (by forcing related
  *     bit in the runlist->active_channels bitmask).
+ *   - Check that nvgpu_tsg_from_ch return NULL when bind failed.
+
  *   In negative testing case, original state is restored after checking
  *   that test_tsg_bind_channel failed.
  * - Additionally, the following cases are checked:
@@ -153,7 +166,7 @@ int test_tsg_unbind_channel(struct unit_module *m,
  *
  * Test Type: Feature
  *
- * Targets: nvgpu_tsg_release
+ * Targets: nvgpu_tsg_release, nvgpu_tsg_release_common
  *
  * Input: test_fifo_init_support() run for this GPU
  *
@@ -261,6 +274,31 @@ int test_tsg_unbind_channel_check_ctx_reload(struct unit_module *m,
 int test_tsg_enable(struct unit_module *m,
 		struct gk20a *g, void *args);
 
+/**
+ * Test specification for: test_tsg_enable_sched
+ *
+ * Description: Enable/disable TSG scheduling
+ *
+ * Test Type: Feature
+ *
+ * Targets: nvgpu_tsg_enable_sched, nvgpu_tsg_disable_sched
+ *
+ * Input: test_fifo_init_support() run for this GPU
+ *
+ * Steps:
+ * - Create a TSG with a bound channel.
+ * - Use stub for g->ops.runlist.write_state to store runlist_mask
+ *   and runlist_state.
+ * - Call nvgpu_tsg_enable_sched and check that runlist_mask matches
+ *   TSG's runlist_id and runlist_state is RUNLIST_ENABLED.
+ * - Call nvgpu_tsg_diable_sched and check that runlist_mask matches
+ *   TSG's runlist_id and runlist_state is RUNLIST_DISABLED.
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_tsg_enable_sched(struct unit_module *m,
+		struct gk20a *g, void *args);
+
 /**
  * Test specification for: test_tsg_check_and_get_from_id
  *
@@ -318,7 +356,7 @@ int test_tsg_abort(struct unit_module *m,
  *
  * Test Type: Feature
  *
- * Targets: nvgpu_tsg_setup_sw
+ * Targets: nvgpu_tsg_setup_sw, nvgpu_tsg_cleanup_sw
  *
  * Input: None
  *
@@ -340,7 +378,7 @@ int test_tsg_setup_sw(struct unit_module *m,
  *
  * Test Type: Feature
  *
- * Targets: nvgpu_tsg_mark_error
+ * Targets: nvgpu_tsg_mark_error, nvgpu_tsg_set_error_notifier
  *
  * Input: None
  *