From 45ee7baab1d5a4e3250aa68f56bf8a8ee76c33c9 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Wed, 6 Mar 2019 23:10:14 +0530 Subject: [PATCH] gpu: nvgpu: move mailbox0 write to engine bl_bootstrap Semantics of the engine bootloader bootstrap are to set falcon mailbox0 register to non-zero value and verify that it is cleared to ascertain successful completion of bootstrap. Read was done in the engine bl_bootstrap related functions. Hence move the write as well to those functions. JIRA NVGPU-1993 Change-Id: I6d04148fbf1d517f0af8b4cfc2ee144d38704647 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2034511 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/falcon/falcon.c | 2 -- drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c | 2 ++ drivers/gpu/nvgpu/gp106/sec2_gp106.c | 2 ++ drivers/gpu/nvgpu/gv100/gsp_gv100.c | 2 ++ drivers/gpu/nvgpu/tu104/sec2_tu104.c | 2 ++ 5 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index 490f43ec5..f21cc5f4d 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c @@ -656,8 +656,6 @@ int nvgpu_falcon_bl_bootstrap(struct nvgpu_falcon *flcn, goto exit; } - nvgpu_falcon_mailbox_write(flcn, FALCON_MAILBOX_0, 0xDEADA5A5U); - virt_addr = bl_info->bl_start_tag << 8; err = nvgpu_falcon_bootstrap(flcn, virt_addr); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c index d2d088283..b63505ab6 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c @@ -374,6 +374,8 @@ static int gm20b_bl_bootstrap(struct gk20a *g, pwr_pmu_new_instblk_target_sys_coh_f() : pwr_pmu_new_instblk_target_sys_ncoh_f())) ; + nvgpu_falcon_mailbox_write(g->pmu.flcn, FALCON_MAILBOX_0, 0xDEADA5A5U); + return nvgpu_falcon_bl_bootstrap(g->pmu.flcn, bl_info); } diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 0e1c87233..4c68fb0a7 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c @@ -77,6 +77,8 @@ static int sec2_flcn_bl_bootstrap(struct gk20a *g, data |= BIT32(3); gk20a_writel(g, psec_falcon_engctl_r(), data); + nvgpu_falcon_mailbox_write(g->sec2.flcn, FALCON_MAILBOX_0, 0xDEADA5A5U); + err = nvgpu_falcon_bl_bootstrap(g->sec2.flcn, bl_info); return err; diff --git a/drivers/gpu/nvgpu/gv100/gsp_gv100.c b/drivers/gpu/nvgpu/gv100/gsp_gv100.c index a0a7af2f9..ff0b19a90 100644 --- a/drivers/gpu/nvgpu/gv100/gsp_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gsp_gv100.c @@ -68,6 +68,8 @@ static int gsp_flcn_bl_bootstrap(struct gk20a *g, data |= pgsp_falcon_engctl_switch_context_true_f(); gk20a_writel(g, pgsp_falcon_engctl_r(), data); + nvgpu_falcon_mailbox_write(g->gsp_flcn, FALCON_MAILBOX_0, 0xDEADA5A5U); + status = nvgpu_falcon_bl_bootstrap(g->gsp_flcn, bl_info); return status; diff --git a/drivers/gpu/nvgpu/tu104/sec2_tu104.c b/drivers/gpu/nvgpu/tu104/sec2_tu104.c index 1719da4bb..dcc821d42 100644 --- a/drivers/gpu/nvgpu/tu104/sec2_tu104.c +++ b/drivers/gpu/nvgpu/tu104/sec2_tu104.c @@ -202,6 +202,8 @@ static int tu104_sec2_flcn_bl_bootstrap(struct gk20a *g, data |= (1U << 3U); gk20a_writel(g, psec_falcon_engctl_r(), data); + nvgpu_falcon_mailbox_write(g->sec2.flcn, FALCON_MAILBOX_0, 0xDEADA5A5U); + return nvgpu_falcon_bl_bootstrap(g->sec2.flcn, bl_info); }