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gpu: nvgpu: fix TSG enable sequence

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Due to a h/w bug in Maxwell and Pascal we first need to enable all channels with
NEXT and CTX_RELOAD set in a TSG, and then rest of the channels should be
enabled
Add this sequence to gk20a_tsg_enable()

Add new APIs to enable/disable scheduling of TSG runlist
gk20a_fifo_enable_tsg_sched()
gk20a_fifo_disble_tsg_sched()

Add new APIs to check if channel has NEXT or CTX_RELOAD set
gk20a_fifo_channel_status_is_next()
gk20a_fifo_channel_status_is_ctx_reload()

Bug 1739362

Change-Id: I4891cbd7f22ebc1e0bf32c52801002cdc259dbe1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560636
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2017-09-13 05:41:52 -07:00
committed by mobile promotions
parent 7d6d040531
commit 460951ed09
7 changed files with 208 additions and 6 deletions
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6
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
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@@ -248,6 +248,9 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g,
bool wait_for_idle);
int gk20a_fifo_disable_all_engine_activity(struct gk20a *g,
bool wait_for_idle);
void gk20a_fifo_enable_tsg_sched(struct gk20a *g, struct tsg_gk20a *tsg);
void gk20a_fifo_disable_tsg_sched(struct gk20a *g, struct tsg_gk20a *tsg);
u32 gk20a_fifo_engines_on_ch(struct gk20a *g, u32 chid);
int gk20a_fifo_reschedule_runlist(struct gk20a *g, u32 runlist_id);
@@ -362,6 +365,9 @@ const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index);
void gk20a_fifo_enable_channel(struct channel_gk20a *ch);
void gk20a_fifo_disable_channel(struct channel_gk20a *ch);
bool gk20a_fifo_channel_status_is_next(struct gk20a *g, u32 chid);
bool gk20a_fifo_channel_status_is_ctx_reload(struct gk20a *g, u32 chid);
struct channel_gk20a *gk20a_refch_from_inst_ptr(struct gk20a *g, u64 inst_ptr);
void gk20a_fifo_channel_unbind(struct channel_gk20a *ch_gk20a);