From 4688c596e2de997b008520a34be0d84f1f7ae683 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 12 Nov 2018 15:35:46 -0800 Subject: [PATCH] gpu: nvgpu: unit: Add pd_cache unit test for VC C1 Add a unit test that executes the verification criteria C1. JIRA NVGPU-1323 Change-Id: I7a14076c4084e54c38f514590eb8ccd9a5f9327b Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1949209 Reviewed-by: svc-mobile-coverity Reviewed-by: Philip Elcan GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/libnvgpu-drv.export | 2 + userspace/include/unit/unit-requirement-ids.h | 5 ++ userspace/units/mm/pd_cache/pd_cache.c | 77 +++++++++++++++++++ 3 files changed, 84 insertions(+) diff --git a/drivers/gpu/nvgpu/libnvgpu-drv.export b/drivers/gpu/nvgpu/libnvgpu-drv.export index cfa81047d..a5cd2a3ac 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv.export @@ -73,6 +73,8 @@ nvgpu_pd_alloc nvgpu_pd_cache_fini nvgpu_pd_cache_init nvgpu_pd_free +nvgpu_mem_rd32 +nvgpu_mem_wr32 nvgpu_mutex_acquire nvgpu_mutex_release nvgpu_posix_cleanup diff --git a/userspace/include/unit/unit-requirement-ids.h b/userspace/include/unit/unit-requirement-ids.h index 24f36198b..703f4e35a 100644 --- a/userspace/include/unit/unit-requirement-ids.h +++ b/userspace/include/unit/unit-requirement-ids.h @@ -23,4 +23,9 @@ #ifndef __UNIT_UNIT_REQUIREMENT_IDS_H__ #define __UNIT_UNIT_REQUIREMENT_IDS_H__ +/* + * Unit requirement test specification unique IDs. + */ +#define PD_CACHE_REQ1_UID "6439202" + #endif diff --git a/userspace/units/mm/pd_cache/pd_cache.c b/userspace/units/mm/pd_cache/pd_cache.c index 62714c049..fda8ddc6d 100644 --- a/userspace/units/mm/pd_cache/pd_cache.c +++ b/userspace/units/mm/pd_cache/pd_cache.c @@ -22,6 +22,7 @@ #include #include +#include #include #include @@ -557,6 +558,76 @@ static int test_pd_cache_fini(struct unit_module *m, return UNIT_SUCCESS; } +/* + * Requirement NVGPU-RQCD-68.C1 + * Requirement NVGPU-RQCD-68.C2 + * + * Valid/Invalid: The pd_cache does/does not allocate a suitable DMA'able + * buffer of memory. + * Valid/Invalid: The allocated PD is/is not sufficiently aligned for use by + * the GMMU. + */ +static int test_pd_cache_valid_alloc(struct unit_module *m, + struct gk20a *g, void *args) +{ + u32 bytes; + int err; + struct vm_gk20a vm; + struct nvgpu_gmmu_pd pd; + + err = init_pd_cache(m, g, &vm); + if (err != UNIT_SUCCESS) { + return err; + } + + /* + * Allocate a PD of each valid PD size and ensure they are properly + * populated with nvgpu_mem data. This tests read/write and alignment. + * This covers the VCs 1 and 2. + */ + bytes = 256; /* 256 bytes is the min PD size. */ + while (bytes <= PAGE_SIZE) { + + err = nvgpu_pd_alloc(&vm, &pd, bytes); + if (err) { + goto fail; + } + + /* + * Do a write to the zeroth word and then verify this made it to + * the nvgpu_mem. Using the zeroth word makes it easy to read + * back. + */ + pd_write(g, &pd, 0, 0x12345678); + + if (0x12345678 != + nvgpu_mem_rd32(g, pd.mem, pd.mem_offs / sizeof(u32))) { + nvgpu_pd_free(&vm, &pd); + goto fail; + } + + /* + * Check alignment is at least as much as the size. + */ + if ((pd.mem_offs & (bytes - 1)) != 0) { + nvgpu_pd_free(&vm, &pd); + goto fail; + } + + nvgpu_pd_free(&vm, &pd); + + bytes <<= 1; + } + + nvgpu_pd_cache_fini(g); + return UNIT_SUCCESS; + +fail: + nvgpu_pd_cache_fini(g); + return err; +} + + /* * Init the global env - just make sure we don't try and allocate from VIDMEM * when doing dma allocs. @@ -574,6 +645,12 @@ struct unit_module_test pd_cache_tests[] = { UNIT_TEST(init, test_pd_cache_init, NULL), UNIT_TEST(fini, test_pd_cache_fini, NULL), + /* + * Requirement verification tests. + */ + UNIT_TEST_REQ("NVGPU-RQCD-68.C1,2", PD_CACHE_REQ1_UID, "V4", + valid_alloc, test_pd_cache_valid_alloc, NULL), + /* * Direct allocs. */