diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 078a71581..04695d113 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -279,7 +279,7 @@ int gk20a_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
 	return ret;
 }
 
-static int init_engine_info(struct fifo_gk20a *f)
+int gk20a_fifo_init_engine_info(struct fifo_gk20a *f)
 {
 	struct gk20a *g = f->g;
 	struct device *d = dev_from_gk20a(g);
@@ -796,7 +796,7 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g)
 	for (i = 0; i < f->num_pbdma; ++i)
 		f->pbdma_map[i] = gk20a_readl(g, fifo_pbdma_map_r(i));
 
-	init_engine_info(f);
+	g->ops.fifo.init_engine_info(f);
 
 	init_runlist(g, f);
 
@@ -3082,4 +3082,5 @@ void gk20a_init_fifo(struct gpu_ops *gops)
 	/* gk20a doesn't support device_info_data packet parsing */
 	gops->fifo.device_info_data_parse = NULL;
 	gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
+	gops->fifo.init_engine_info = gk20a_fifo_init_engine_info;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index e6ae0bdcd..3473bc78b 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -250,4 +250,7 @@ bool gk20a_fifo_is_valid_runlist_id(struct gk20a *g, u32 runlist_id);
 
 int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 hw_chid,
 		bool add, bool wait_for_finish);
+
+int gk20a_fifo_init_engine_info(struct fifo_gk20a *f);
+
 #endif /*__GR_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 74ffab610..997da125d 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -352,6 +352,7 @@ struct gpu_ops {
 				struct channel_gk20a *ch);
 		int (*tsg_unbind_channel)(struct channel_gk20a *ch);
 		u32 (*eng_runlist_base_size)(void);
+		int (*init_engine_info)(struct fifo_gk20a *f);
 	} fifo;
 	struct pmu_v {
 		/*used for change of enum zbc update cmd id from ver 0 to ver1*/
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index 031c5bae4..00db510a3 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -155,4 +155,5 @@ void gm20b_init_fifo(struct gpu_ops *gops)
 	gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type;
 	gops->fifo.device_info_data_parse = gm20b_device_info_data_parse;
 	gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
+	gops->fifo.init_engine_info = gk20a_fifo_init_engine_info;
 }
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 11f389fbc..ffa16cd37 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -160,22 +160,29 @@ static int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
 	return (err || msg.ret) ? -ENOMEM : 0;
 }
 
-static int init_engine_info(struct fifo_gk20a *f)
+static int vgpu_fifo_init_engine_info(struct fifo_gk20a *f)
 {
 	struct fifo_engine_info_gk20a *gr_info;
+	struct fifo_engine_info_gk20a *ce_info;
 	const u32 gr_sw_id = ENGINE_GR_GK20A;
+	const u32 ce_sw_id = ENGINE_GRCE_GK20A;
 
 	gk20a_dbg_fn("");
 
-	/* all we really care about finding is the graphics entry    */
-	/* especially early on in sim it probably thinks it has more */
-	f->num_engines = 1;
+	f->num_engines = 2;
 
-	gr_info = f->engine_info + gr_sw_id;
+	gr_info = &f->engine_info[0];
 
 	/* FIXME: retrieve this from server */
 	gr_info->runlist_id = 0;
-	f->active_engines_list[0] = gr_sw_id;
+	gr_info->engine_enum = gr_sw_id;
+	f->active_engines_list[0] = 0;
+
+	ce_info = &f->engine_info[1];
+	ce_info->runlist_id = 0;
+	ce_info->inst_id = 2;
+	ce_info->engine_enum = ce_sw_id;
+	f->active_engines_list[1] = 1;
 
 	return 0;
 }
@@ -292,7 +299,7 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g)
 	}
 	memset(f->active_engines_list, 0xff, (f->max_engines * sizeof(u32)));
 
-	init_engine_info(f);
+	g->ops.fifo.init_engine_info(f);
 
 	init_runlist(g, f);
 
@@ -778,4 +785,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops)
 	gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave;
 	gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice;
 	gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch;
+	gops->fifo.init_engine_info = vgpu_fifo_init_engine_info;
 }