From 47c3d4582c2ec0e57e9ab22534ee02b35f8e4af7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Konsta=20H=C3=B6ltt=C3=A4?= Date: Fri, 3 Apr 2020 17:20:42 +0300 Subject: [PATCH] gpu: nvgpu: hide priv cmdbuf gva and size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an accessor function in the priv cmdbuf object for gva and size to be written in a gpfifo entry once the cmdbuf build is finished. This helps in eventually hiding the struct priv_cmd_entry as an implementation detail. Add a sanity check to verify that the buffer has been filled exactly to the requested size. The cmdbufs are used to hold wait and increment commands for syncpoints or gpu semaphores. A prefence buffer can hold a number of wait commands of equal size, and the postfence buffer holds exactly one increment. Jira NVGPU-4548 Change-Id: I83132bf6de52794ecc419e033e9f4599e488fd68 Signed-off-by: Konsta Hölttä Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325102 (cherry picked from commit d1831463a487666017c4c80fab0292a0b85c7d83) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2331339 Reviewed-by: automaticguardword Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Alex Waterman Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c | 22 +++++++++++++++++++ drivers/gpu/nvgpu/common/fifo/submit.c | 13 ++++------- drivers/gpu/nvgpu/include/nvgpu/priv_cmdbuf.h | 3 +++ 3 files changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c b/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c index 2868ba370..5555c6b9e 100644 --- a/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c +++ b/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c @@ -30,6 +30,7 @@ #include #include #include +#include struct priv_cmd_queue { struct nvgpu_mem mem; @@ -256,3 +257,24 @@ void nvgpu_priv_cmdbuf_append_zeros(struct gk20a *g, struct priv_cmd_entry *e, 0, entries * sizeof(u32)); e->fill_off += entries; } + +void nvgpu_priv_cmdbuf_finish(struct gk20a *g, struct priv_cmd_entry *e, + u64 *gva, u32 *size) +{ + /* + * The size is written to the pushbuf entry, so make sure this buffer + * is complete at this point. The responsibility of the channel sync is + * to be consistent in allocation and usage, and the matching size and + * add gops (e.g., get_wait_cmd_size, add_wait_cmd) help there. + */ + nvgpu_assert(e->fill_off == e->size); + +#ifdef CONFIG_NVGPU_TRACE + if (e->mem->aperture == APERTURE_SYSMEM) { + trace_gk20a_push_cmdbuf(g->name, 0, e->size, 0, + (u32 *)e->mem->cpu_va + e->off); + } +#endif + *gva = e->gva; + *size = e->size; +} diff --git a/drivers/gpu/nvgpu/common/fifo/submit.c b/drivers/gpu/nvgpu/common/fifo/submit.c index a6d0888b6..09885128a 100644 --- a/drivers/gpu/nvgpu/common/fifo/submit.c +++ b/drivers/gpu/nvgpu/common/fifo/submit.c @@ -199,21 +199,16 @@ static void nvgpu_submit_append_priv_cmdbuf(struct nvgpu_channel *c, struct gk20a *g = c->g; struct nvgpu_mem *gpfifo_mem = &c->gpfifo.mem; struct nvgpu_gpfifo_entry gpfifo_entry; + u64 gva; + u32 size; - g->ops.pbdma.format_gpfifo_entry(g, &gpfifo_entry, - cmd->gva, cmd->size); + nvgpu_priv_cmdbuf_finish(g, cmd, &gva, &size); + g->ops.pbdma.format_gpfifo_entry(g, &gpfifo_entry, gva, size); nvgpu_mem_wr_n(g, gpfifo_mem, c->gpfifo.put * (u32)sizeof(gpfifo_entry), &gpfifo_entry, (u32)sizeof(gpfifo_entry)); -#ifdef CONFIG_NVGPU_TRACE - if (cmd->mem->aperture == APERTURE_SYSMEM) { - trace_gk20a_push_cmdbuf(g->name, 0, cmd->size, 0, - (u32 *)cmd->mem->cpu_va + cmd->off); - } -#endif - c->gpfifo.put = (c->gpfifo.put + 1U) & (c->gpfifo.entry_num - 1U); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/priv_cmdbuf.h b/drivers/gpu/nvgpu/include/nvgpu/priv_cmdbuf.h index 4d9b06d4e..f06954dac 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/priv_cmdbuf.h +++ b/drivers/gpu/nvgpu/include/nvgpu/priv_cmdbuf.h @@ -54,4 +54,7 @@ void nvgpu_priv_cmdbuf_append(struct gk20a *g, struct priv_cmd_entry *e, void nvgpu_priv_cmdbuf_append_zeros(struct gk20a *g, struct priv_cmd_entry *e, u32 entries); +void nvgpu_priv_cmdbuf_finish(struct gk20a *g, struct priv_cmd_entry *e, + u64 *gva, u32 *size); + #endif