From 47dc015b86e5db0efc9a53718e1ce9e8877a17d2 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 9 Sep 2020 11:02:40 +0530 Subject: [PATCH] gpu: nvgpu: Add physical gpu instance support This patch added the physical gpu intance support when MIG is enabled. JIRA NVGPU-5647 Change-Id: Ic642b88ebc70ea6114e63c2287db8bca00860c67 Signed-off-by: Lakshmanan M Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2410698 Reviewed-by: automaticguardword Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Deepak Nibade Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/grmgr/grmgr.c | 64 ++++++++++++++++--------- drivers/gpu/nvgpu/include/nvgpu/grmgr.h | 7 +++ drivers/gpu/nvgpu/include/nvgpu/mig.h | 12 ++++- 3 files changed, 59 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nvgpu/common/grmgr/grmgr.c b/drivers/gpu/nvgpu/common/grmgr/grmgr.c index 2abf3bdeb..ccff57d0b 100644 --- a/drivers/gpu/nvgpu/common/grmgr/grmgr.c +++ b/drivers/gpu/nvgpu/common/grmgr/grmgr.c @@ -43,6 +43,7 @@ int nvgpu_init_gr_manager(struct gk20a *g) gpu_instance->gpu_instance_id = 0U; gpu_instance->is_memory_partition_supported = false; + gpu_instance->gpu_instance_type = NVGPU_MIG_TYPE_PHYSICAL; gr_syspipe->gr_instance_id = 0U; gr_syspipe->gr_syspipe_id = 0U; @@ -79,7 +80,7 @@ int nvgpu_init_gr_manager(struct gk20a *g) g->mig.current_gr_syspipe_id = NVGPU_MIG_INVALID_GR_SYSPIPE_ID; nvgpu_log(g, gpu_dbg_mig, - "[non MIG boot] gpu_instance_id[%u] gr_instance_id[%u] " + "[Physical device] gpu_instance_id[%u] gr_instance_id[%u] " "gr_syspipe_id[%u] num_gpc[%u] gr_engine_id[%u] " "max_veid_count_per_tsg[%u] veid_start_offset[%u] " "is_memory_partition_support[%d] num_lce[%u] ", @@ -250,47 +251,66 @@ u32 nvgpu_grmgr_get_num_gr_instances(struct gk20a *g) return g->mig.num_gr_sys_pipes_enabled; } +static inline u32 nvgpu_grmgr_get_gpu_instance_id(struct gk20a *g, + u32 gr_instance_id) +{ + u32 gpu_instance_id = 0U; + + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { + /* 0th entry is physical device gpu instance */ + gpu_instance_id = nvgpu_safe_add_u32(gr_instance_id, 1U); + + if (gpu_instance_id >= g->mig.num_gpu_instances) { + nvgpu_err(g, + "gpu_instance_id[%u] > num_gpu_instances[%u]", + gpu_instance_id, g->mig.num_gpu_instances); + nvgpu_assert( + gpu_instance_id < g->mig.num_gpu_instances); + gpu_instance_id = 0U; + } + } + + nvgpu_log(g, gpu_dbg_mig, "gr_instance_id[%u] gpu_instance_id[%u]", + gr_instance_id, gpu_instance_id); + + return gpu_instance_id; +} + u32 nvgpu_grmgr_get_gr_syspipe_id(struct gk20a *g, u32 gr_instance_id) { struct nvgpu_gpu_instance *gpu_instance; struct nvgpu_gr_syspipe *gr_syspipe; + u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id( + g, gr_instance_id); - if (gr_instance_id < g->mig.num_gpu_instances) { - gpu_instance = &g->mig.gpu_instance[gr_instance_id]; - gr_syspipe = &gpu_instance->gr_syspipe; + gpu_instance = &g->mig.gpu_instance[gpu_instance_id]; + gr_syspipe = &gpu_instance->gr_syspipe; - return gr_syspipe->gr_syspipe_id; - } - - return U32_MAX; + return gr_syspipe->gr_syspipe_id; } u32 nvgpu_grmgr_get_gr_num_gpcs(struct gk20a *g, u32 gr_instance_id) { struct nvgpu_gpu_instance *gpu_instance; struct nvgpu_gr_syspipe *gr_syspipe; + u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id( + g, gr_instance_id); - if (gr_instance_id < g->mig.num_gpu_instances) { - gpu_instance = &g->mig.gpu_instance[gr_instance_id]; - gr_syspipe = &gpu_instance->gr_syspipe; + gpu_instance = &g->mig.gpu_instance[gpu_instance_id]; + gr_syspipe = &gpu_instance->gr_syspipe; - return gr_syspipe->num_gpc; - } - - return U32_MAX; + return gr_syspipe->num_gpc; } u32 nvgpu_grmgr_get_gr_gpc_phys_id(struct gk20a *g, u32 gr_instance_id, u32 gpc_local_id) { struct nvgpu_gpu_instance *gpu_instance; struct nvgpu_gr_syspipe *gr_syspipe; + u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id( + g, gr_instance_id); - if (gr_instance_id < g->mig.num_gpu_instances) { - gpu_instance = &g->mig.gpu_instance[gr_instance_id]; - gr_syspipe = &gpu_instance->gr_syspipe; + gpu_instance = &g->mig.gpu_instance[gpu_instance_id]; + gr_syspipe = &gpu_instance->gr_syspipe; - return gr_syspipe->gpcs[gpc_local_id].physical_id; - } - - return U32_MAX; + return gr_syspipe->gpcs[gpc_local_id].physical_id; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/grmgr.h b/drivers/gpu/nvgpu/include/nvgpu/grmgr.h index a5a1511c9..b65a2955c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/grmgr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/grmgr.h @@ -26,6 +26,7 @@ #define NVGPU_GRMGR_H #include +#include struct gk20a; @@ -38,4 +39,10 @@ u32 nvgpu_grmgr_get_gr_syspipe_id(struct gk20a *g, u32 gr_instance_id); u32 nvgpu_grmgr_get_gr_num_gpcs(struct gk20a *g, u32 gr_instance_id); u32 nvgpu_grmgr_get_gr_gpc_phys_id(struct gk20a *g, u32 gr_instance_id, u32 gpc_local_id); +static inline bool nvgpu_grmgr_is_mig_type_gpu_instance( + struct nvgpu_gpu_instance *gpu_instance) +{ + return (gpu_instance->gpu_instance_type == NVGPU_MIG_TYPE_MIG); +} + #endif /* NVGPU_GRMGR_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/mig.h b/drivers/gpu/nvgpu/include/nvgpu/mig.h index b9874eff1..48e7b4ba7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mig.h +++ b/drivers/gpu/nvgpu/include/nvgpu/mig.h @@ -29,8 +29,8 @@ /** Maximum GPC group supported by HW. */ #define NVGPU_MIG_MAX_GPCGRP 2U -/** Maximum gpu instances count. */ -#define NVGPU_MIG_MAX_GPU_INSTANCES 8U +/** Maximum gpu instances count (1 Physical + 8 MIGs). */ +#define NVGPU_MIG_MAX_GPU_INSTANCES 9U /** Maximum mig config count. */ #define NVGPU_MIG_MAX_MIG_CONFIG_COUNT 16U @@ -47,6 +47,12 @@ /** Maximum number of GPC count. */ #define NVGPU_MIG_MAX_GPCS 32U +/** Enumerated type used to identify various gpu instance types */ +enum nvgpu_mig_gpu_instance_type { + NVGPU_MIG_TYPE_PHYSICAL = 0, + NVGPU_MIG_TYPE_MIG +}; + /** * @brief GPC Id information. * This struct describes the logical, physical and gpcgrp id of each GPC. @@ -108,6 +114,8 @@ struct nvgpu_gpu_instance { const struct nvgpu_device *lce_devs[NVGPU_MIG_MAX_ENGINES]; /* Flag to indicate whether memory partition is supported or not. */ bool is_memory_partition_supported; + /** Enumerated type used to identify various gpu instance types */ + enum nvgpu_mig_gpu_instance_type gpu_instance_type; }; /**