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gpu: nvgpu: fix engine reset in FECS trace
In virtualization case, VM server is the only one allowed to write to ctxsw ring buffer. It will also generate an event in case of engine reset. Only generate a tracepoint on Guest OS side. EVLR-314 Change-Id: I2cb09780a9b41237fe196ef1f3515923f36a24a4 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1130743 (cherry picked from commit 4bbf9538e2a3375eb86b2feea6c605c3eec2ca40) Reviewed-on: http://git-master/r/1133614 (cherry picked from commit 2076d944db41b37143c27795b3cffd88e99e0b00) Reviewed-on: http://git-master/r/1150046 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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committed by
Terje Bergstrom
parent
4df6cd4a34
commit
47e3d2e905
@@ -885,11 +885,9 @@ static void gk20a_free_channel(struct channel_gk20a *ch)
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mutex_lock(&g->fifo.gr_reset_mutex);
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/* if lock is already taken, a reset is taking place
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so no need to repeat */
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if (!was_reset) {
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gk20a_ctxsw_trace_channel_reset(g, ch);
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if (!was_reset)
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gk20a_fifo_reset_engine(g,
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g->fifo.deferred_fault_engines);
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}
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mutex_unlock(&g->fifo.gr_reset_mutex);
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g->fifo.deferred_fault_engines = 0;
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g->fifo.deferred_reset_pending = false;
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