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gpu: nvgpu: fix engine reset in FECS trace

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In virtualization case, VM server is the only one
allowed to write to ctxsw ring buffer. It will
also generate an event in case of engine reset.
Only generate a tracepoint on Guest OS side.

EVLR-314

Change-Id: I2cb09780a9b41237fe196ef1f3515923f36a24a4
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1130743
(cherry picked from commit 4bbf9538e2a3375eb86b2feea6c605c3eec2ca40)
Reviewed-on: http://git-master/r/1133614
(cherry picked from commit 2076d944db41b37143c27795b3cffd88e99e0b00)
Reviewed-on: http://git-master/r/1150046
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Thomas Fleury
2016-04-21 16:35:44 -07:00
committed by Terje Bergstrom
parent 4df6cd4a34
commit 47e3d2e905
5 changed files with 14 additions and 15 deletions
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13
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -1082,15 +1082,16 @@ static bool gk20a_fifo_handle_mmu_fault(
mutex_lock(&g->fifo.gr_reset_mutex);
/* if lock is already taken, a reset is taking place
so no need to repeat */
if (!was_reset) {
if (ch)
gk20a_ctxsw_trace_channel_reset(g, ch);
else
gk20a_ctxsw_trace_tsg_reset(g, tsg);
if (!was_reset)
gk20a_fifo_reset_engine(g, engine_id);
}
mutex_unlock(&g->fifo.gr_reset_mutex);
}
if (ch)
gk20a_ctxsw_trace_channel_reset(g, ch);
else if (tsg)
gk20a_ctxsw_trace_tsg_reset(g, tsg);
/* disable the channel/TSG from hw and increment
* syncpoints */