From 4874bdfbacf1b9438d99b6d3a9a7700533d563f8 Mon Sep 17 00:00:00 2001 From: Divya Singhatwaria Date: Wed, 9 Jun 2021 13:34:28 +0530 Subject: [PATCH] gpu: nvgpu: Address DVR issues for common.power_features Fix the common.power_features DVR issues found as part of 5.2 SWUD Lite units design verification. 1.Add note about various *CG features. 2. nvgpu_cg_init_gr_load_gating_prod description fixed. JIRA NVGPU-6610 Change-Id: Id28eaa9d15a5481d28a5fd2cc407c82734a6c165 Signed-off-by: Divya Singhatwaria Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2541739 (cherry picked from commit d19e95407748689a26ae5b5920e6fb50f4399d1f) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2542078 Reviewed-by: svc_kernel_abi Reviewed-by: Sagar Kamble Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- .../gpu/nvgpu/include/nvgpu/power_features/cg.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h b/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h index 3a6cc11d9..781136509 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h @@ -35,6 +35,17 @@ * configuration for Second Level Clock Gating (SLCG), Block Level * Clock Gating (BLCG) and Engine Level Clock Gating (ELCG). * + * ELCG is supported for GR and CE. It is pure HW logic. + * ELCG is applicable to all units within an engine. + * + * BLCG controller is instanced in each unit. Each unit can decide + * BLCG entry/exit. BLCG entry/exit latency is small, + * so there are modes/states under which a unit can enter BLCG. + + * A second level clock gate is a clock gate that exists within the clock + * network between the BLCG/ELCG (1st-level) clock gate and flops/ICGs at the + * leaf-end of the clock network. + * * Chip specific clock gating register configurations are available * in the files, hal/power_features/cg/_gating_reglist.c. * @@ -179,12 +190,12 @@ struct gk20a; /** * @brief During nvgpu power-on, this function is called as part of GR - * HW initialization to load register configuration for ELCG and + * HW initialization to load register configuration for SLCG and * BLCG for GR related units. * * @param g [in] The GPU driver struct. * - * This function programs ELCG configuration for bus, chiplet, gr, perf, + * This function programs SLCG configuration for bus, chiplet, gr, perf, * xbar, hshub units and BLCG for bus, gr, xbar and hshub. This is * called in #nvgpu_gr_enable_hw after resetting GR engine. *