diff --git a/drivers/gpu/nvgpu/common/enabled.c b/drivers/gpu/nvgpu/common/enabled.c
index 11686610b..dc8c30a4f 100644
--- a/drivers/gpu/nvgpu/common/enabled.c
+++ b/drivers/gpu/nvgpu/common/enabled.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-18, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,7 +53,7 @@ bool nvgpu_is_enabled(struct gk20a *g, int flag)
 	return test_bit(flag, g->enabled_flags);
 }
 
-void __nvgpu_set_enabled(struct gk20a *g, int flag, bool state)
+void nvgpu_set_enabled(struct gk20a *g, int flag, bool state)
 {
 	if (state) {
 		set_bit(flag, g->enabled_flags);
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
index 67db3598e..22df9fa85 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * GM20B FUSE
  *
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,8 +39,8 @@ int gm20b_fuse_check_priv_security(struct gk20a *g)
 	bool is_auto_fetch_disable = false;
 
 	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-		__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-		__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
+		nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
+		nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
 		nvgpu_log(g, gpu_dbg_info, "priv sec is enabled in fmodel");
 		return 0;
 	}
@@ -50,7 +50,7 @@ int gm20b_fuse_check_priv_security(struct gk20a *g)
 		return -EINVAL;
 	}
 
-	__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
+	nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
 
 	if (gk20a_readl(g, fuse_opt_priv_sec_en_r()) != 0U) {
 		/*
@@ -59,7 +59,7 @@ int gm20b_fuse_check_priv_security(struct gk20a *g)
 		 * set to 0. In this case gmmu tries to pull wpr
 		 * and vpr settings from tegra mc
 		 */
-		__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
+		nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
 		is_wpr_enabled =
 			(gcplex_config & GCPLEX_CONFIG_WPR_ENABLED_MASK) != 0U;
 		is_auto_fetch_disable =
@@ -84,7 +84,7 @@ int gm20b_fuse_check_priv_security(struct gk20a *g)
 			return -EINVAL;
 		}
 	} else {
-		__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
+		nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
 		nvgpu_log(g, gpu_dbg_info,
 				"gcplex_config = 0x%08x, non secure mode",
 				gcplex_config);
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
index f9c557058..ec4f004f4 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
@@ -1,7 +1,7 @@
 /*
  * GP10B FUSE
  *
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -40,8 +40,8 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
 	bool is_auto_fetch_disable = false;
 
 	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-		__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-		__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
+		nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
+		nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
 		nvgpu_log(g, gpu_dbg_info, "priv sec is disabled in fmodel");
 		return 0;
 	}
@@ -58,8 +58,8 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
 		 * set to 0. In this case gmmu tries to pull wpr
 		 * and vpr settings from tegra mc
 		 */
-		__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-		__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
+		nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
+		nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
 		is_wpr_enabled =
 			(gcplex_config & GCPLEX_CONFIG_WPR_ENABLED_MASK) != 0U;
 		is_auto_fetch_disable =
@@ -85,8 +85,8 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
 			return -EINVAL;
 		}
 	} else {
-		__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-		__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
+		nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
+		nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
 		nvgpu_log(g, gpu_dbg_info,
 				"gcplex_config = 0x%08x, non secure mode",
 				gcplex_config);
diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
index 532bf9afd..972268179 100644
--- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c
+++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
@@ -504,11 +504,11 @@ int gk20a_wait_for_idle(struct gk20a *g)
 
 int gk20a_init_gpu_characteristics(struct gk20a *g)
 {
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, true);
 
 	if ((g->ops.mm.support_sparse != NULL) && g->ops.mm.support_sparse(g)) {
-		__nvgpu_set_enabled(g, NVGPU_SUPPORT_SPARSE_ALLOCS, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_SPARSE_ALLOCS, true);
 	}
 
 	/*
@@ -516,7 +516,7 @@ int gk20a_init_gpu_characteristics(struct gk20a *g)
 	 * anything that depends on job tracking. (Here, fast means strictly no
 	 * metadata, just the gpfifo contents are copied and gp_put updated).
 	 */
-	__nvgpu_set_enabled(g,
+	nvgpu_set_enabled(g,
 			NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING,
 			true);
 
@@ -527,16 +527,16 @@ int gk20a_init_gpu_characteristics(struct gk20a *g)
 	 * that depends on deferred cleanup.
 	 */
 	if (!nvgpu_channel_sync_needs_os_fence_framework(g)) {
-		__nvgpu_set_enabled(g,
+		nvgpu_set_enabled(g,
 				NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL,
 				true);
 	}
 
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG, true);
 
 	if (g->ops.clk_arb.get_arbiter_clk_domains != NULL &&
 		g->ops.clk.support_clk_freq_controller) {
-		__nvgpu_set_enabled(g, NVGPU_SUPPORT_CLOCK_CONTROLS, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_CLOCK_CONTROLS, true);
 	}
 
 	g->ops.gr.detect_sm_arch(g);
diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink.c b/drivers/gpu/nvgpu/common/nvlink/nvlink.c
index 429766ca8..4dd6bc2bf 100644
--- a/drivers/gpu/nvgpu/common/nvlink/nvlink.c
+++ b/drivers/gpu/nvgpu/common/nvlink/nvlink.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -533,7 +533,7 @@ int nvgpu_nvlink_probe(struct gk20a *g)
 	}
 
 	/* Enable NVLINK support */
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, true);
 	return 0;
 
 unregister_ndev:
@@ -561,7 +561,7 @@ int nvgpu_nvlink_remove(struct gk20a *g)
 	if (!ndev)
 		return -ENODEV;
 
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
 
 	err = nvlink_unregister_link(&ndev->link);
 	if (err != 0) {
diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c
index 6e4bc32ed..10fb86645 100644
--- a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c
+++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c
@@ -1712,7 +1712,7 @@ int gv100_nvlink_init(struct gk20a *g)
 	}
 
 	/* Set HSHUB and SG_PHY */
-	__nvgpu_set_enabled(g, NVGPU_MM_USE_PHYSICAL_SG, true);
+	nvgpu_set_enabled(g, NVGPU_MM_USE_PHYSICAL_SG, true);
 
 	err = g->ops.fb.enable_nvlink(g);
 	if (err != 0) {
@@ -1723,8 +1723,8 @@ int gv100_nvlink_init(struct gk20a *g)
 	return err;
 
 fail:
-	__nvgpu_set_enabled(g, NVGPU_MM_USE_PHYSICAL_SG, false);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
+	nvgpu_set_enabled(g, NVGPU_MM_USE_PHYSICAL_SG, false);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
 	return err;
 }
 
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c
index e5bfa3796..d593c37ba 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu.c
@@ -603,7 +603,7 @@ int nvgpu_pmu_destroy(struct gk20a *g)
 	pmu->perfmon_ready = false;
 	pmu->zbc_ready = false;
 	g->pmu_lsf_pmu_wpr_init_done = false;
-	__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
+	nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
 
 	nvgpu_log_fn(g, "done");
 	return 0;
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index 8797c9fb6..890441662 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -1153,7 +1153,7 @@ int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
 			set_perfmon_cntr_group_id_v2;
 		g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
 		g->pmu_ver_cmd_id_zbc_table_update = 16;
-		__nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
+		nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
 		g->ops.pmu_ver.get_pmu_cmdline_args_size =
 			pmu_cmdline_size_v4;
 		g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
@@ -1257,7 +1257,7 @@ int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
 			set_perfmon_cntr_group_id_v2;
 		g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
 		g->pmu_ver_cmd_id_zbc_table_update = 16;
-		__nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, false);
+		nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, false);
 		g->ops.pmu_ver.get_pmu_cmdline_args_size =
 			pmu_cmdline_size_v6;
 		g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
@@ -1404,7 +1404,7 @@ int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
 			set_perfmon_cntr_group_id_v2;
 		g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
 		g->pmu_ver_cmd_id_zbc_table_update = 16;
-		__nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
+		nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
 		g->ops.pmu_ver.get_pmu_cmdline_args_size =
 			pmu_cmdline_size_v5;
 		g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
@@ -1530,7 +1530,7 @@ int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
 			set_perfmon_cntr_group_id_v2;
 		g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
 		g->pmu_ver_cmd_id_zbc_table_update = 16;
-		__nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
+		nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
 		g->ops.pmu_ver.get_pmu_cmdline_args_size =
 			pmu_cmdline_size_v3;
 		g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
index 9f7116ee8..d9856007b 100644
--- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
@@ -422,7 +422,7 @@ int gk20a_fecs_trace_init(struct gk20a *g)
 	BUG_ON(!is_power_of_2(GK20A_FECS_TRACE_NUM_RECORDS));
 	hash_init(trace->pid_hash_table);
 
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true);
 
 	trace->init = true;
 
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index b3b004a9f..e78600676 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -814,7 +814,7 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
 
 	} else {
 		/* cold boot or rg exit */
-		__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, true);
+		nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, true);
 		if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
 			gr_gm20b_load_gpccs_with_bootloader(g);
 		} else {
@@ -1148,8 +1148,8 @@ u32 gr_gm20b_get_max_fbps_count(struct gk20a *g)
 void gr_gm20b_init_cyclestats(struct gk20a *g)
 {
 #if defined(CONFIG_GK20A_CYCLE_STATS)
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT, true);
 	g->gr.max_css_buffer_size = 0xffffffffU;
 #else
 	(void)g;
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 85afef707..f2bcbbd8e 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -825,8 +825,8 @@ int gm20b_init_hal(struct gk20a *g)
 	gops->get_litter_value = gm20b_ops.get_litter_value;
 	gops->semaphore_wakeup = gk20a_channel_semaphore_wakeup;
 
-	__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
-	__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
+	nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
+	nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
 
 	/* Read fuses to check if gpu needs to boot in secure/non-secure mode */
 	if (gops->fuse.check_priv_security(g) != 0) {
@@ -867,7 +867,7 @@ int gm20b_init_hal(struct gk20a *g)
 		gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
 	}
 
-	__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
+	nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
 	g->pmu_lsf_pmu_wpr_init_done = 0;
 
 	g->name = "gm20b";
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c
index 773fb6198..d9babc076 100644
--- a/drivers/gpu/nvgpu/gp10b/gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gp10b.c
@@ -1,7 +1,7 @@
 /*
  * GP10B Graphics
  *
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -41,10 +41,10 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g)
 
 	if (opt_feature_fuses_override_disable) {
 		if (opt_ecc_en) {
-			__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_LRF, true);
-			__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_SHM, true);
-			__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_TEX, true);
-			__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_LRF, true);
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_SHM, true);
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_TEX, true);
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
 		}
 	} else {
 		/* SM LRF */
@@ -52,12 +52,12 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g)
 					fecs_feature_override_ecc) == 1U) {
 			if (gr_fecs_feature_override_ecc_sm_lrf_v(
 					fecs_feature_override_ecc) == 1U) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_SM_LRF, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_SM_LRF, true);
 			}
 		}
@@ -67,12 +67,12 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g)
 					fecs_feature_override_ecc) == 1U) {
 			if (gr_fecs_feature_override_ecc_sm_shm_v(
 					fecs_feature_override_ecc) == 1U) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_SM_SHM, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_SM_SHM, true);
 			}
 		}
@@ -82,12 +82,12 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g)
 					fecs_feature_override_ecc) == 1U) {
 			if (gr_fecs_feature_override_ecc_tex_v(
 					fecs_feature_override_ecc) == 1U) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_TEX, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_TEX, true);
 			}
 		}
@@ -97,12 +97,12 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g)
 					fecs_feature_override_ecc) == 1U) {
 			if (gr_fecs_feature_override_ecc_ltc_v(
 					fecs_feature_override_ecc) == 1U) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_LTC, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_LTC, true);
 			}
 		}
@@ -113,6 +113,6 @@ int gp10b_init_gpu_characteristics(struct gk20a *g)
 {
 	gk20a_init_gpu_characteristics(g);
 	gp10b_detect_ecc_enabled_units(g);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true);
 	return 0;
 }
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 9127a4258..6f6b43aca 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -897,9 +897,9 @@ int gp10b_init_hal(struct gk20a *g)
 	gops->get_litter_value = gp10b_ops.get_litter_value;
 	gops->semaphore_wakeup = gk20a_channel_semaphore_wakeup;
 
-	__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
-	__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
-	__nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false);
+	nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
+	nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
+	nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false);
 
 	/* Read fuses to check if gpu needs to boot in secure/non-secure mode */
 	if (gops->fuse.check_priv_security(g) != 0) {
@@ -942,7 +942,7 @@ int gp10b_init_hal(struct gk20a *g)
 		gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
 	}
 
-	__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
+	nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
 	g->pmu_lsf_pmu_wpr_init_done = 0;
 
 	g->name = "gp10b";
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 73df2811f..3d0ee9b1e 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -289,14 +289,14 @@ int gv100_init_gpu_characteristics(struct gk20a *g)
 		return err;
 	}
 
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true);
 	if (nvgpu_has_syncpoints(g)) {
-		__nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
-		__nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
 	}
 
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
 
 	return 0;
 }
@@ -1168,15 +1168,15 @@ int gv100_init_hal(struct gk20a *g)
 	gops->get_litter_value = gv100_ops.get_litter_value;
 	gops->semaphore_wakeup = gk20a_channel_semaphore_wakeup;
 
-	__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
-	__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-	__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
-	__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);
-	__nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
+	nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
+	nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
+	nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
+	nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);
+	nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
 
 	/* for now */
-	__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
+	nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
 
 	g->pmu_lsf_pmu_wpr_init_done = 0;
 	gops->clk.split_rail_support = false;
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 38e99e07e..b517030de 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -4575,16 +4575,16 @@ static void gr_gv11b_detect_ecc_enabled_units(struct gk20a *g)
 
 	if (opt_feature_fuses_override_disable) {
 		if (opt_ecc_en) {
-			__nvgpu_set_enabled(g,
+			nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_LRF, true);
-			__nvgpu_set_enabled(g,
+			nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_L1_DATA, true);
-			__nvgpu_set_enabled(g,
+			nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_L1_TAG, true);
-			__nvgpu_set_enabled(g,
+			nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_ICACHE, true);
-			__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
-			__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true);
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
+			nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true);
 		}
 	} else {
 		/* SM LRF */
@@ -4592,12 +4592,12 @@ static void gr_gv11b_detect_ecc_enabled_units(struct gk20a *g)
 				fecs_feature_override_ecc) == 1U) {
 			if (gr_fecs_feature_override_ecc_sm_lrf_v(
 				fecs_feature_override_ecc) == 1U) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_SM_LRF, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_SM_LRF, true);
 			}
 		}
@@ -4606,12 +4606,12 @@ static void gr_gv11b_detect_ecc_enabled_units(struct gk20a *g)
 				fecs_feature_override_ecc) == 1U) {
 			if (gr_fecs_feature_override_ecc_sm_l1_data_v(
 				fecs_feature_override_ecc) == 1U) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_L1_DATA, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_L1_DATA, true);
 			}
 		}
@@ -4620,12 +4620,12 @@ static void gr_gv11b_detect_ecc_enabled_units(struct gk20a *g)
 				fecs_feature_override_ecc) == 1U) {
 			if (gr_fecs_feature_override_ecc_sm_l1_tag_v(
 				fecs_feature_override_ecc) == 1U) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_L1_TAG, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_L1_TAG, true);
 			}
 		}
@@ -4638,12 +4638,12 @@ static void gr_gv11b_detect_ecc_enabled_units(struct gk20a *g)
 					fecs_feature_override_ecc) == 1U) &&
 				(gr_fecs_feature_override_ecc_1_sm_l1_icache_v(
 					fecs_feature_override_ecc) == 1U)) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_ICACHE, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_ICACHE, true);
 			}
 		}
@@ -4652,12 +4652,12 @@ static void gr_gv11b_detect_ecc_enabled_units(struct gk20a *g)
 				fecs_feature_override_ecc) == 1U) {
 			if (gr_fecs_feature_override_ecc_ltc_v(
 				fecs_feature_override_ecc) == 1U) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_LTC, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 						NVGPU_ECC_ENABLED_LTC, true);
 			}
 		}
@@ -4666,12 +4666,12 @@ static void gr_gv11b_detect_ecc_enabled_units(struct gk20a *g)
 				fecs_feature_override_ecc) == 1U) {
 			if (gr_fecs_feature_override_ecc_sm_cbu_v(
 				fecs_feature_override_ecc) == 1U) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_CBU, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				__nvgpu_set_enabled(g,
+				nvgpu_set_enabled(g,
 					NVGPU_ECC_ENABLED_SM_CBU, true);
 			}
 		}
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c
index e7cd17c88..48d3749db 100644
--- a/drivers/gpu/nvgpu/gv11b/gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gv11b.c
@@ -1,7 +1,7 @@
 /*
  * GV11B Graphics
  *
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -30,12 +30,12 @@
 int gv11b_init_gpu_characteristics(struct gk20a *g)
 {
 	gk20a_init_gpu_characteristics(g);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
 
 	return 0;
 }
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index a98b966ae..eba6876b6 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -1030,7 +1030,7 @@ int gv11b_init_hal(struct gk20a *g)
 	gops->get_litter_value = gv11b_ops.get_litter_value;
 	gops->semaphore_wakeup = gk20a_channel_semaphore_wakeup;
 
-	__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
+	nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
 
 	/* Read fuses to check if gpu needs to boot in secure/non-secure mode */
 	if (gops->fuse.check_priv_security(g) != 0) {
@@ -1069,10 +1069,10 @@ int gv11b_init_hal(struct gk20a *g)
 		gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
 	}
 
-	__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
-	__nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
+	nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
+	nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
 
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);
 
 	g->name = "gv11b";
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index 27047ef74..6ef394c2d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -190,15 +190,21 @@ struct gk20a;
 bool nvgpu_is_enabled(struct gk20a *g, int flag);
 
 /**
- * __nvgpu_set_enabled - Set the state of a flag.
+ * nvgpu_set_enabled - Set the state of a flag.
  *
  * @g     - The GPU.
  * @flag  - Which flag to modify.
  * @state - The state to set the flag to.
  *
  * Set the state of the passed @flag to @state.
+ *
+ * This is generally a somewhat low level operation with lots of potential
+ * side effects. Be weary about where and when you use this. Typically a bunch
+ * of calls to this early in the driver boot sequence makes sense (as
+ * information is determined about the GPU at run time). Calling this in steady
+ * state operation is probably an incorrect thing to do.
  */
-void __nvgpu_set_enabled(struct gk20a *g, int flag, bool state);
+void nvgpu_set_enabled(struct gk20a *g, int flag, bool state);
 
 int nvgpu_init_enabled_flags(struct gk20a *g);
 void nvgpu_free_enabled_flags(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/libnvgpu-drv.export b/drivers/gpu/nvgpu/libnvgpu-drv.export
index 2412b9d07..8708b7039 100644
--- a/drivers/gpu/nvgpu/libnvgpu-drv.export
+++ b/drivers/gpu/nvgpu/libnvgpu-drv.export
@@ -1,4 +1,4 @@
-# Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
 __bug
 __nvgpu_get_pte
 __nvgpu_kfree
@@ -8,7 +8,6 @@ __nvgpu_log_dbg
 __nvgpu_posix_ffs
 __nvgpu_posix_fls
 __nvgpu_readl
-__nvgpu_set_enabled
 __nvgpu_set_pte
 bitmap_clear
 bitmap_find_next_zero_area_off
@@ -109,6 +108,7 @@ nvgpu_pramin_wr_n
 nvgpu_readl
 nvgpu_runlist_construct_locked
 nvgpu_rwsem_init
+nvgpu_set_enabled
 nvgpu_sgt_create_from_mem
 nvgpu_sgt_alignment
 nvgpu_sgt_free
diff --git a/drivers/gpu/nvgpu/os/linux/driver_common.c b/drivers/gpu/nvgpu/os/linux/driver_common.c
index bf1e838be..dc8f3671f 100644
--- a/drivers/gpu/nvgpu/os/linux/driver_common.c
+++ b/drivers/gpu/nvgpu/os/linux/driver_common.c
@@ -96,7 +96,7 @@ static void nvgpu_init_vars(struct gk20a *g)
 	nvgpu_init_list_node(&g->boardobj_head);
 	nvgpu_init_list_node(&g->boardobjgrp_head);
 
-	__nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, platform->has_syncpoints);
+	nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, platform->has_syncpoints);
 }
 
 static void nvgpu_init_gr_vars(struct gk20a *g)
@@ -161,11 +161,11 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
 	g->can_elpg =
 		nvgpu_platform_is_silicon(g) ? platform->can_elpg_init : false;
 
-	__nvgpu_set_enabled(g, NVGPU_GPU_CAN_ELCG,
+	nvgpu_set_enabled(g, NVGPU_GPU_CAN_ELCG,
 		nvgpu_platform_is_silicon(g) ? platform->can_elcg : false);
-	__nvgpu_set_enabled(g, NVGPU_GPU_CAN_SLCG,
+	nvgpu_set_enabled(g, NVGPU_GPU_CAN_SLCG,
 		nvgpu_platform_is_silicon(g) ? platform->can_slcg : false);
-	__nvgpu_set_enabled(g, NVGPU_GPU_CAN_BLCG,
+	nvgpu_set_enabled(g, NVGPU_GPU_CAN_BLCG,
 		nvgpu_platform_is_silicon(g) ? platform->can_blcg : false);
 
 	g->aggressive_sync_destroy = platform->aggressive_sync_destroy;
@@ -175,7 +175,7 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
 #endif
 	g->ptimer_src_freq = platform->ptimer_src_freq;
 	g->support_pmu = support_gk20a_pmu(dev_from_gk20a(g));
-	__nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, platform->can_railgate_init);
+	nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, platform->can_railgate_init);
 	g->can_tpc_powergate = platform->can_tpc_powergate;
 
 	for (i = 0; i < MAX_TPC_PG_CONFIGS; i++)
@@ -187,7 +187,7 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
 		g->railgate_delay = platform->railgate_delay_init;
 	else
 		g->railgate_delay = NVGPU_DEFAULT_RAILGATE_IDLE_TIMEOUT;
-	__nvgpu_set_enabled(g, NVGPU_PMU_PERFMON, platform->enable_perfmon);
+	nvgpu_set_enabled(g, NVGPU_PMU_PERFMON, platform->enable_perfmon);
 
 	/* set default values to aelpg parameters */
 	g->pmu.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US;
@@ -196,14 +196,14 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
 	g->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US;
 	g->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT;
 
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_ASPM, !platform->disable_aspm);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_ASPM, !platform->disable_aspm);
 }
 
 static void nvgpu_init_vbios_vars(struct gk20a *g)
 {
 	struct gk20a_platform *platform = dev_get_drvdata(dev_from_gk20a(g));
 
-	__nvgpu_set_enabled(g, NVGPU_PMU_RUN_PREOS, platform->run_preos);
+	nvgpu_set_enabled(g, NVGPU_PMU_RUN_PREOS, platform->run_preos);
 	g->vbios_min_version = platform->vbios_min_version;
 }
 
@@ -219,13 +219,13 @@ static void nvgpu_init_mm_vars(struct gk20a *g)
 	struct gk20a_platform *platform = dev_get_drvdata(dev_from_gk20a(g));
 
 	g->mm.disable_bigpage = platform->disable_bigpage;
-	__nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE,
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE,
 			    platform->honors_aperture);
-	__nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY,
+	nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY,
 			    platform->unified_memory);
-	__nvgpu_set_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES,
+	nvgpu_set_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES,
 			    platform->unify_address_spaces);
-	__nvgpu_set_enabled(g, NVGPU_MM_FORCE_128K_PMU_VM,
+	nvgpu_set_enabled(g, NVGPU_MM_FORCE_128K_PMU_VM,
 			    platform->force_128K_pmu_vm);
 
 	nvgpu_mutex_init(&g->mm.tlb_lock);
diff --git a/drivers/gpu/nvgpu/os/linux/module.c b/drivers/gpu/nvgpu/os/linux/module.c
index 37c918444..2e2a147f4 100644
--- a/drivers/gpu/nvgpu/os/linux/module.c
+++ b/drivers/gpu/nvgpu/os/linux/module.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics
  *
- * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -86,7 +86,7 @@ static int nvgpu_kernel_shutdown_notification(struct notifier_block *nb,
 						nvgpu_reboot_nb);
 	struct gk20a *g = &l->g;
 
-	__nvgpu_set_enabled(g, NVGPU_KERNEL_IS_DYING, true);
+	nvgpu_set_enabled(g, NVGPU_KERNEL_IS_DYING, true);
 	return NOTIFY_DONE;
 }
 
@@ -246,12 +246,12 @@ int nvgpu_finalize_poweron_linux(struct nvgpu_os_linux *l)
 
 void gk20a_init_linux_characteristics(struct gk20a *g)
 {
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_PARTIAL_MAPPINGS, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_DETERMINISTIC_OPTS, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_USERSPACE_MANAGED_AS, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PARTIAL_MAPPINGS, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_DETERMINISTIC_OPTS, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_USERSPACE_MANAGED_AS, true);
 
 	if (IS_ENABLED(CONFIG_SYNC)) {
-		__nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNC_FENCE_FDS, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNC_FENCE_FDS, true);
 	}
 }
 
@@ -1176,7 +1176,7 @@ int nvgpu_start_gpu_idle(struct gk20a *g)
 	 * Set NVGPU_DRIVER_IS_DYING to avoid gpu being marked
 	 * busy to submit new work to gpu.
 	 */
-	__nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
+	nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
 
 	up_write(&l->busy_lock);
 
@@ -1208,7 +1208,7 @@ void gk20a_driver_start_unload(struct gk20a *g)
 	nvgpu_log(g, gpu_dbg_shutdown, "Driver is now going down!\n");
 
 	down_write(&l->busy_lock);
-	__nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
+	nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
 	/* GR SW ready needs to be invalidated at this time with the busy lock
 	 * held to prevent a racing condition on the gr/mm code */
 	g->gr.sw_ready = false;
@@ -1326,12 +1326,12 @@ static int gk20a_probe(struct platform_device *dev)
 
 	np = nvgpu_get_node(gk20a);
 	if (of_dma_is_coherent(np)) {
-		__nvgpu_set_enabled(gk20a, NVGPU_USE_COHERENT_SYSMEM, true);
-		__nvgpu_set_enabled(gk20a, NVGPU_SUPPORT_IO_COHERENCE, true);
+		nvgpu_set_enabled(gk20a, NVGPU_USE_COHERENT_SYSMEM, true);
+		nvgpu_set_enabled(gk20a, NVGPU_SUPPORT_IO_COHERENCE, true);
 	}
 
 	if (nvgpu_platform_is_simulation(gk20a))
-		__nvgpu_set_enabled(gk20a, NVGPU_IS_FMODEL, true);
+		nvgpu_set_enabled(gk20a, NVGPU_IS_FMODEL, true);
 
 	gk20a->irq_stall = platform_get_irq(dev, 0);
 	gk20a->irq_nonstall = platform_get_irq(dev, 1);
diff --git a/drivers/gpu/nvgpu/os/linux/nvhost.c b/drivers/gpu/nvgpu/os/linux/nvhost.c
index 70f3ed5d2..ff9c3379e 100644
--- a/drivers/gpu/nvgpu/os/linux/nvhost.c
+++ b/drivers/gpu/nvgpu/os/linux/nvhost.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -48,7 +48,7 @@ int nvgpu_get_nvhost_dev(struct gk20a *g)
 	} else {
 		if (nvgpu_has_syncpoints(g)) {
 			nvgpu_warn(g, "host1x reference not found. assuming no syncpoints support");
-			__nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, false);
+			nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, false);
 		}
 		return 0;
 	}
@@ -270,7 +270,7 @@ int nvgpu_nvhost_syncpt_init(struct gk20a *g)
 	err = nvgpu_get_nvhost_dev(g);
 	if (err) {
 		nvgpu_err(g, "host1x device not available");
-		__nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, false);
+		nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, false);
 		return -ENOSYS;
 	}
 
@@ -280,7 +280,7 @@ int nvgpu_nvhost_syncpt_init(struct gk20a *g)
 			&g->syncpt_unit_size);
 	if (err) {
 		nvgpu_err(g, "Failed to get syncpt interface");
-		__nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, false);
+		nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, false);
 		return -ENOSYS;
 	}
 
diff --git a/drivers/gpu/nvgpu/os/linux/pci.c b/drivers/gpu/nvgpu/os/linux/pci.c
index 4f4425662..05bdba46e 100644
--- a/drivers/gpu/nvgpu/os/linux/pci.c
+++ b/drivers/gpu/nvgpu/os/linux/pci.c
@@ -556,8 +556,8 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
 
 	np = nvgpu_get_node(g);
 	if (of_dma_is_coherent(np)) {
-		__nvgpu_set_enabled(g, NVGPU_USE_COHERENT_SYSMEM, true);
-		__nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true);
+		nvgpu_set_enabled(g, NVGPU_USE_COHERENT_SYSMEM, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true);
 	}
 
 	err = pci_enable_device(pdev);
@@ -643,8 +643,8 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
 			goto err_free_irq;
 		}
 		/* Enable Semaphore SHIM on nvlink only for now. */
-		__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
-		__nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, false);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
+		nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, false);
 	} else {
 		err = nvgpu_nvhost_syncpt_init(g);
 		if (err) {
diff --git a/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c
index e2912b993..cb24ea5bc 100644
--- a/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c
+++ b/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Tegra Platform Interface
  *
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -646,7 +646,7 @@ int gk20a_tegra_init_secure_alloc(struct gk20a_platform *platform)
 	secure_buffer->destroy = gk20a_tegra_secure_page_destroy;
 
 	g->ops.secure_alloc = gk20a_tegra_secure_alloc;
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_VPR, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_VPR, true);
 
 	return 0;
 }
@@ -796,7 +796,7 @@ static int gk20a_tegra_probe(struct device *dev)
 
 	if (joint_xpu_rail) {
 		nvgpu_log_info(g, "XPU rails are joint\n");
-		__nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, false);
+		nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, false);
 	}
 
 	platform->g->clk.gpc_pll.id = GK20A_GPC_PLL;
diff --git a/drivers/gpu/nvgpu/os/linux/sim_pci.c b/drivers/gpu/nvgpu/os/linux/sim_pci.c
index 9a80e7e20..55d722e85 100644
--- a/drivers/gpu/nvgpu/os/linux/sim_pci.c
+++ b/drivers/gpu/nvgpu/os/linux/sim_pci.c
@@ -84,7 +84,7 @@ int nvgpu_init_sim_support_linux_pci(struct gk20a *g)
 	bool is_simulation;
 
 	is_simulation = _nvgpu_pci_is_simulation(g, sim_r());
-	__nvgpu_set_enabled(g, NVGPU_IS_FMODEL, is_simulation);
+	nvgpu_set_enabled(g, NVGPU_IS_FMODEL, is_simulation);
 
 	if (!is_simulation)
 		return 0;
diff --git a/drivers/gpu/nvgpu/os/linux/sysfs.c b/drivers/gpu/nvgpu/os/linux/sysfs.c
index 9a159640f..8c8ea7141 100644
--- a/drivers/gpu/nvgpu/os/linux/sysfs.c
+++ b/drivers/gpu/nvgpu/os/linux/sysfs.c
@@ -328,10 +328,10 @@ static ssize_t railgate_enable_store(struct device *dev,
 		return -EINVAL;
 
 	if (railgate_enable && !enabled) {
-		__nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, true);
+		nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, true);
 		pm_runtime_set_autosuspend_delay(dev, g->railgate_delay);
 	} else if (railgate_enable == 0 && enabled) {
-		__nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, false);
+		nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, false);
 		pm_runtime_set_autosuspend_delay(dev, -1);
 	}
 	/* wake-up system to make rail-gating setting effective */
diff --git a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c
index fe72a2fc1..4c5d4a50c 100644
--- a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c
+++ b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c
@@ -1,7 +1,7 @@
 /*
  * Virtualized GPU for Linux
  *
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -91,12 +91,12 @@ static void vgpu_init_vars(struct gk20a *g, struct gk20a_platform *platform)
 
 	g->aggressive_sync_destroy = platform->aggressive_sync_destroy;
 	g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh;
-	__nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, platform->has_syncpoints);
+	nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, platform->has_syncpoints);
 	g->ptimer_src_freq = platform->ptimer_src_freq;
-	__nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, platform->can_railgate_init);
+	nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, platform->can_railgate_init);
 	g->railgate_delay = platform->railgate_delay_init;
 
-	__nvgpu_set_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES,
+	nvgpu_set_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES,
 			    platform->unify_address_spaces);
 }
 
@@ -334,7 +334,7 @@ int vgpu_probe(struct platform_device *pdev)
 
 	l->dev = dev;
 	if (tegra_platform_is_vdk())
-		__nvgpu_set_enabled(gk20a, NVGPU_IS_FMODEL, true);
+		nvgpu_set_enabled(gk20a, NVGPU_IS_FMODEL, true);
 
 	gk20a->is_virtual = true;
 
diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c
index 79d11c14f..ebd5b717b 100644
--- a/drivers/gpu/nvgpu/tu104/hal_tu104.c
+++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c
@@ -305,13 +305,13 @@ static int tu104_init_gpu_characteristics(struct gk20a *g)
 		return err;
 	}
 
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true);
 	if (nvgpu_has_syncpoints(g)) {
-		__nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
-		__nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
 	}
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
 
 	return 0;
 }
@@ -1204,12 +1204,12 @@ int tu104_init_hal(struct gk20a *g)
 	gops->get_litter_value = tu104_ops.get_litter_value;
 	gops->semaphore_wakeup = gk20a_channel_semaphore_wakeup;
 
-	__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-	__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
-	__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, true);
-	__nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_RTOS, true);
+	nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
+	nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
+	nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, true);
+	nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_RTOS, true);
 
 	/* for now */
 	gops->clk.support_clk_freq_controller = false;
@@ -1235,9 +1235,9 @@ int tu104_init_hal(struct gk20a *g)
 		gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
 
 		/* Disable pmu pstate, as there is no pmu support */
-		__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
+		nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
 
-		__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP,
+		nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP,
 									false);
 		/* Disable fb mem_unlock */
 		gops->fb.mem_unlock = NULL;
@@ -1247,8 +1247,8 @@ int tu104_init_hal(struct gk20a *g)
 		gops->clk.support_clk_freq_controller = false;
 
 	} else {
-		__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
-		__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
+		nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
+		nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
 	}
 
 	g->pmu_lsf_pmu_wpr_init_done = 0;
diff --git a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c
index 77c793752..3a7374e91 100644
--- a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c
@@ -55,7 +55,7 @@ int vgpu_fecs_trace_init(struct gk20a *g)
 		nvgpu_info(g, "does not support fecs trace");
 		goto fail;
 	}
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true);
 
 	vcst->cookie = vgpu_ivm_mempool_reserve(mempool);
 	if (IS_ERR(vcst->cookie)) {
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c
index 5a24945c8..141acd1e9 100644
--- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c
+++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -33,7 +33,7 @@ void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g)
 	bool snapshots_supported = true;
 
 	/* cyclestats not supported on vgpu */
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, false);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, false);
 
 	g->gr.max_css_buffer_size = vgpu_css_get_buffer_size(g);
 
@@ -41,8 +41,7 @@ void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g)
 	if (g->gr.max_css_buffer_size == 0)
 		snapshots_supported = false;
 
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT,
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT,
 							snapshots_supported);
 #endif
 }
-
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.c
index 1f7d6c2cf..a8a5a8e1e 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,11 +28,11 @@
 int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g)
 {
 	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-		__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-		__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
+		nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
+		nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
 	} else {
-		__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-		__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
+		nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
+		nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
 	}
 
 	return 0;
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c
index 1f0f95c82..a136dba02 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -38,13 +38,13 @@ int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g)
 		return err;
 	}
 
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
-	__nvgpu_set_enabled(g, NVGPU_USE_COHERENT_SYSMEM, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
+	nvgpu_set_enabled(g, NVGPU_USE_COHERENT_SYSMEM, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
 
 	return 0;
 }
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c
index a433cc78d..8f0436f14 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -280,10 +280,10 @@ int vgpu_init_gpu_characteristics(struct gk20a *g)
 	if (err)
 		return err;
 
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, false);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, false);
 
 	/* features vgpu does not support */
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, false);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, false);
 
 	return 0;
 }
diff --git a/userspace/units/fuse/nvgpu-fuse-gm20b.c b/userspace/units/fuse/nvgpu-fuse-gm20b.c
index cea6e0314..bfb182f86 100644
--- a/userspace/units/fuse/nvgpu-fuse-gm20b.c
+++ b/userspace/units/fuse/nvgpu-fuse-gm20b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -309,7 +309,7 @@ int test_fuse_gm20b_check_fmodel(struct unit_module *m,
 	int ret = UNIT_SUCCESS;
 	int result;
 
-	__nvgpu_set_enabled(g, NVGPU_IS_FMODEL, true);
+	nvgpu_set_enabled(g, NVGPU_IS_FMODEL, true);
 
 	result = g->ops.fuse.check_priv_security(g);
 	if (result != 0) {
@@ -328,6 +328,6 @@ int test_fuse_gm20b_check_fmodel(struct unit_module *m,
 		ret = UNIT_FAIL;
 	}
 
-	__nvgpu_set_enabled(g, NVGPU_IS_FMODEL, false);
+	nvgpu_set_enabled(g, NVGPU_IS_FMODEL, false);
 	return ret;
 }
diff --git a/userspace/units/fuse/nvgpu-fuse-gp10b.c b/userspace/units/fuse/nvgpu-fuse-gp10b.c
index 8acdec081..24f4d9518 100644
--- a/userspace/units/fuse/nvgpu-fuse-gp10b.c
+++ b/userspace/units/fuse/nvgpu-fuse-gp10b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -242,7 +242,7 @@ int test_fuse_gp10b_check_fmodel(struct unit_module *m,
 	int ret = UNIT_SUCCESS;
 	int result;
 
-	__nvgpu_set_enabled(g, NVGPU_IS_FMODEL, true);
+	nvgpu_set_enabled(g, NVGPU_IS_FMODEL, true);
 
 	result = g->ops.fuse.check_priv_security(g);
 	if (result != 0) {
@@ -261,7 +261,6 @@ int test_fuse_gp10b_check_fmodel(struct unit_module *m,
 		ret = UNIT_FAIL;
 	}
 
-	__nvgpu_set_enabled(g, NVGPU_IS_FMODEL, false);
+	nvgpu_set_enabled(g, NVGPU_IS_FMODEL, false);
 	return ret;
 }
-
diff --git a/userspace/units/mm/gmmu/page_table/page_table.c b/userspace/units/mm/gmmu/page_table/page_table.c
index 9774d13d7..4d79a68be 100644
--- a/userspace/units/mm/gmmu/page_table/page_table.c
+++ b/userspace/units/mm/gmmu/page_table/page_table.c
@@ -266,12 +266,12 @@ static const struct nvgpu_sgt_ops nvgpu_sgt_posix_ops = {
 static void init_platform(struct unit_module *m, struct gk20a *g, bool is_iGPU)
 {
 	if (is_iGPU) {
-		__nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
 		/* Features below are mostly to cover corner cases */
-		__nvgpu_set_enabled(g, NVGPU_USE_COHERENT_SYSMEM, true);
-		__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, true);
+		nvgpu_set_enabled(g, NVGPU_USE_COHERENT_SYSMEM, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, true);
 	} else {
-		__nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false);
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false);
 	}
 }
 
diff --git a/userspace/units/mm/gmmu/pd_cache/pd_cache.c b/userspace/units/mm/gmmu/pd_cache/pd_cache.c
index e04ecbe1c..5d2adf97b 100644
--- a/userspace/units/mm/gmmu/pd_cache/pd_cache.c
+++ b/userspace/units/mm/gmmu/pd_cache/pd_cache.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -726,7 +726,7 @@ cleanup:
 static int test_pd_cache_env_init(struct unit_module *m,
 				  struct gk20a *g, void *args)
 {
-	__nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
+	nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
 
 	return UNIT_SUCCESS;
 }
diff --git a/userspace/units/posix/fault-injection/posix-fault-injection.c b/userspace/units/posix/fault-injection/posix-fault-injection.c
index c6ed46843..1ff8d0594 100644
--- a/userspace/units/posix/fault-injection/posix-fault-injection.c
+++ b/userspace/units/posix/fault-injection/posix-fault-injection.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -29,7 +29,7 @@
 static int test_fault_injection_init(struct unit_module *m,
 			      struct gk20a *g, void *__args)
 {
-	__nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
+	nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
 	return UNIT_SUCCESS;
 }
 
diff --git a/userspace/units/pramin/nvgpu-pramin.c b/userspace/units/pramin/nvgpu-pramin.c
index 6bb5af58f..d5391b672 100644
--- a/userspace/units/pramin/nvgpu-pramin.c
+++ b/userspace/units/pramin/nvgpu-pramin.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -483,7 +483,7 @@ static int test_pramin_nvgpu_dying(struct unit_module *m, struct gk20a *g,
 	if (init_test_env(m, g) != 0) {
 		unit_return_fail(m, "Module init failed\n");
 	}
-	__nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
+	nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
 	/*
 	 * When the GPU is dying, PRAMIN should prevent any accesses, so
 	 * pointers to nvgpu_mem and destination data don't matter and can be
@@ -493,7 +493,7 @@ static int test_pramin_nvgpu_dying(struct unit_module *m, struct gk20a *g,
 	nvgpu_pramin_rd_n(g, NULL, 0, 1, NULL);
 
 	/* Restore GPU driver state for other tests */
-	__nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, false);
+	nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, false);
 	return UNIT_SUCCESS;
 }